Method for detecting defects of power semiconductor device

Abstract

The invention provides a method for defect detection of a power semiconductor device, which belongs to the technical field of defect detection of semiconductor devices and comprises the following steps: preparing a cathode electrode on the back surface of a semiconductor layer test substrate; preparing an anode electrode on the front surface of the semiconductor layer test substrate, wherein the anode electrode comprises a transparent electrode and a metal frame; the metal frame surrounds and contacts the edge area of the transparent electrode; applying a reverse bias voltage between the cathode electrode and the transparent electrode; collecting an electroluminescent signal generated by the semiconductor layer test substrate under the reverse bias voltage through a low-light microscope located above the transparent electrode; the transparent electrode is configured to allow an electroluminescent signal to penetrate upwards; and determining the defect position of the semiconductor layer test substrate according to the electroluminescent signal. According to the method, non-destructive failure analysis can be carried out on the vertical structure device by utilizing the EMMI technology.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device defect detection technology, and more specifically, relates to a method for defect detection in power semiconductor devices. Background Technology

[0002] With the rapid development of power electronics technology and the new energy industry, the demand for high-voltage, low-loss power semiconductor devices is becoming increasingly urgent. Wide-bandgap semiconductor materials, represented by silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga2O3), have become key materials for the fabrication of next-generation high-voltage, high-power semiconductor devices due to their excellent properties such as high breakdown field strength and high electron saturation drift velocity.

[0003] However, gallium oxide materials, especially its epitaxial films, are prone to various crystal defects (such as dislocations, point defects, and impurity aggregation) during growth. These defects can become leakage paths during device operation, severely degrading the reverse blocking characteristics of the device, causing the breakdown voltage to be far lower than the theoretical value, and affecting the reliability and lifespan of the device. Therefore, accurate location and identification of defects are crucial in the device research and fabrication process.

[0004] Currently, the industry commonly uses emission microscopy (EMMI) to locate leakage points in semiconductor devices. The principle is that when a reverse bias voltage is applied to the device, weak photons are emitted at the defect site due to carrier recombination or collisional ionization. These light-emitting points can be captured by a high-sensitivity camera to locate the defect.

[0005] However, when applied to Schottky barrier diodes (SBDs) with vertical structures, traditional EMMI methods cannot receive any signal from the front of the diode. Although this can be circumvented by observing from the back or fabricating special test structures, these methods are complex to manufacture, compromise device integrity, or fail to reflect the actual failure state of the device.

[0006] Furthermore, for materials with high critical field strength such as gallium oxide, the actual breakdown voltage of its devices is often limited by the electric field concentration effect at the anode edge, making it difficult to achieve high withstand voltage while meeting the requirements for visual detection of defects. Summary of the Invention

[0007] The purpose of this invention is to provide a method for defect detection in power semiconductor devices, aiming to solve the technical problem of leakage current analysis failure of EMMI technology in vertical structure devices in the prior art.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is: to provide a method for defect detection in power semiconductor devices, comprising: A cathode electrode is fabricated on the back side of the semiconductor layer test substrate and forms an ohmic contact with the semiconductor layer test substrate. An anode electrode is fabricated on the front side of the semiconductor layer test substrate. The anode electrode includes a transparent electrode and a metal frame. The metal frame surrounds and contacts the edge region of the transparent electrode. The metal frame forms a first Schottky contact with the semiconductor layer test substrate, and the transparent electrode forms a second Schottky contact with the semiconductor layer test substrate. The Schottky barrier height of the metal frame is higher than that of the transparent electrode. A reverse bias voltage is applied between the cathode electrode and the transparent electrode; An electroluminescence signal generated by the semiconductor layer test substrate under the reverse bias voltage is acquired using a micro-microscope located above the transparent electrode; the transparent electrode is configured to allow the electroluminescence signal to penetrate upwards. The location of defects in the semiconductor layer test substrate is determined based on the electroluminescence signal.

[0009] In one possible implementation, fabricating the anode electrode on the front side of the semiconductor layer test substrate includes: A patterned metal border is formed on the front side of the semiconductor layer test substrate; The transparent electrode is formed within the area enclosed by the metal frame and on the front side of the metal frame.

[0010] In some embodiments, the metal frame surrounds the transparent electrode in a top-view orientation.

[0011] In some embodiments, the semiconductor layer test substrate, the cathode electrode, and the metal frame have a consistent outer contour in the horizontal direction.

[0012] In one possible implementation, the material of the metal frame includes at least one of Ni / Au, Pt / Au, and Pd / Au.

[0013] In one possible implementation, the transparent electrode is a conductive thin film that is transparent within the detection band of the micro-microscope; the material of the transparent electrode is at least one of indium tin oxide, tin oxide, zinc oxide, fluorine-doped tin oxide, and aluminum-doped zinc oxide.

[0014] In one possible implementation, the semiconductor layer test substrate is a wide bandgap semiconductor material, including at least one of gallium oxide, silicon carbide, and gallium nitride.

[0015] In some embodiments, the semiconductor layer test substrate includes an n-type gallium oxide single crystal substrate and an n-type gallium oxide epitaxial layer.

[0016] In some embodiments, the thickness of the n-type gallium oxide single crystal substrate is 500 nm to 500 μm; the thickness of the n-type gallium oxide epitaxial layer is 20 μm to 2000 μm; the thickness of the cathode electrode is 50 nm to 5 μm; the thickness of the transparent electrode is 50 nm to 5 μm; and the thickness of the metal frame is 1 / 5 to 1 / 3 of the thickness of the transparent electrode.

[0017] In one possible implementation, acquiring the electroluminescence signal generated by the semiconductor layer test substrate under the reverse bias voltage using a micro-microscope located above the transparent electrode includes: The semiconductor layer test substrate is placed on the sample stage of the light microscope, and the transparent electrode faces the objective lens of the light microscope; under darkroom conditions, the reverse bias voltage is applied between the cathode electrode and the transparent electrode; the electroluminescence signal transmitted from the transparent electrode is acquired and imaged by the optical imaging system of the light microscope.

[0018] The beneficial effects of the method for defect detection of power semiconductor devices provided by the present invention are as follows: Compared with the prior art, the method for defect detection of power semiconductor devices of the present invention uses a transparent electrode as the core functional area of ​​the anode electrode, so that the electroluminescent signal emitted from the defect in the semiconductor layer test substrate can directly penetrate upward and be collected by the micro-microscope above. This realizes frontal and non-destructive optical observation of defects in vertical structure power diodes. The observed defect signal directly reflects the failure behavior of the device under real working conditions, and the evaluation results are true, accurate and reliable.

[0019] The metal frame surrounding the transparent electrode has a higher Schottky barrier. Under reverse bias, the metal frame can effectively smooth the electric field peak at the anode edge and suppress premature breakdown; the increased breakdown voltage allows for the safe application of a higher reverse bias voltage during testing, thereby activating deeper or weak defects with higher breakdown thresholds. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic flowchart of a method for defect detection in power semiconductor devices provided in an embodiment of the present invention; Figure 2This is a schematic diagram of the structure of the semiconductor layer test substrate after the cathode and anode electrodes are fabricated, as provided in an embodiment of the present invention.

[0022] In the figure: 1. Semiconductor layer test substrate; 11. n-type gallium oxide single crystal substrate; 12. n-type gallium oxide epitaxial layer; 2. Cathode electrode; 3. Transparent electrode; 4. Metal frame. Detailed Implementation

[0023] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0024] It should be noted that when an element is referred to as being "set on" another element, it can be directly on or indirectly on that other element. It should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0025] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a number" means two or more, unless otherwise explicitly specified.

[0026] Please refer to the following: Figure 1 and Figure 2 The present invention will now describe a method for defect detection in power semiconductor devices. The method for defect detection in power semiconductor devices includes the following steps: S100: A cathode electrode 2 is fabricated on the back side of the semiconductor layer test substrate 1 and forms an ohmic contact with the semiconductor layer test substrate 1; S200: An anode electrode is fabricated on the front side of the semiconductor layer test substrate 1. The anode electrode includes a transparent electrode 3 and a metal frame 4. The metal frame 4 surrounds and contacts the edge region of the transparent electrode 3. The metal frame 4 forms a first Schottky contact with the semiconductor layer test substrate 1, and the transparent electrode 3 forms a second Schottky contact with the semiconductor layer test substrate 1. The Schottky barrier height of the metal frame 4 is higher than that of the transparent electrode 3. S300: Apply a reverse bias voltage between the cathode electrode 2 and the transparent electrode 3; S400: The electroluminescence signal generated by the semiconductor layer test substrate 1 under reverse bias voltage is acquired by a micro-microscope located above the transparent electrode 3; the transparent electrode 3 is configured to allow the electroluminescence signal to penetrate upward. S500: Determine the defect location of the semiconductor layer test substrate 1 based on the electroluminescence signal.

[0027] The semiconductor layer test substrate 1 is a device structure used for fabricating and testing diodes. After fabricating a cathode electrode 2 on its back side and a transparent electrode 3 on its front side, it constitutes a Schottky barrier diode for testing. The semiconductor layer test substrate 1 typically includes an epitaxial layer and a substrate. The epitaxial layer is a wide-bandgap semiconductor epitaxial film (such as gallium oxide, silicon carbide, gallium nitride, etc.) that needs to be tested. This layer is the region where electroluminescent signals are generated and where target defects exist. The epitaxial layer is usually supported by a substrate. The cathode electrode 2 is fabricated on the back side of the substrate, and the anode electrode is fabricated on the front side of the epitaxial layer.

[0028] Step S100 involves fabricating the cathode ohmic contact. Specifically, metal stacks such as Ti / Au or Ti / Pt / Au can be fabricated using methods such as electron beam evaporation or magnetron sputtering, and then a good ohmic contact can be formed with the substrate through a rapid thermal annealing process.

[0029] Step S200 involves fabricating the anode Schottky contact. To maintain semiconductor interface quality and ensure high transmittance, a transparent conductive oxide thin film can be fabricated using magnetron sputtering or chemical vapor deposition to form the transparent electrode 3; the metal frame 4 can be formed by deposition and patterning. Electron beam evaporation or magnetron sputtering is used to cover the entire working area with the metal material constituting the frame, forming a uniform, patternless metal film. Then, a lift-off process is used: first, photoresist is coated and patterned, then metal is deposited, and finally, the photoresist is dissolved to remove the metal from the non-patterned areas, forming the metal frame 4.

[0030] Steps S100 and S200 complete the fabrication of the power semiconductor device to be tested.

[0031] In step S300, the test device is placed on a probe station or a special fixture, the cathode electrode 2 is grounded, and a gradually increasing reverse bias voltage is applied to the transparent electrode 3. When the voltage rises to near or reaches the leakage or soft breakdown region of the device, the microscopic defects (such as dislocations and point defect clusters) in the semiconductor layer test substrate 1 become effective carrier tunneling or multiplication channels. When carriers undergo nonradiative recombination or impact ionization at these defects, they release weak photons of specific wavelengths.

[0032] Since the anode is transparent, the photons emitted by these defects can pass directly through the transparent electrode 3 and be captured by the high-sensitivity camera or photomultiplier tube of the optical microscopy (EMMI) configured in step S400. The optical microscopy system will generate a light emission distribution map, in which each light spot corresponds to the precise spatial location of a leakage defect.

[0033] In step S500, the current-voltage characteristic curve recorded synchronously by the micro-microscopy system can be correlated with the light emission map for analysis. By comparing the changes in luminescence intensity and distribution under different voltages, the contribution of specific defects to device leakage current can be assessed, achieving a direct correlation diagnosis from macroscopic electrical performance to the cause of microscopic defects.

[0034] The method for defect detection of power semiconductor devices provided by the present invention, compared with the prior art, prepares a transparent electrode 3 on the front side of the semiconductor layer test substrate 1 and allows the electroluminescent signal to penetrate upward, so that the micro-microscope located above the transparent electrode 3 can directly collect the luminescent signal from the internal defects of the semiconductor layer from the front side in situ, realizing top-down EMMI optical inspection of vertical structure power devices.

[0035] The anode electrode employs a composite structure of a transparent electrode 3 and a metal frame 4, with the Schottky barrier height of the metal frame 4 set higher than that of the transparent electrode 3. When a reverse bias voltage is applied, the metal frame 4 with the higher barrier will bear a larger portion of the reverse voltage, thereby effectively suppressing the peak electric field at the edge of the transparent electrode 3. This allows the entire device to avoid premature breakdown under higher reverse bias voltages, thus generating a stronger and more easily detectable electroluminescence signal, achieving compatibility between high voltage withstand design and high-sensitivity defect detection.

[0036] Because the aforementioned anode electrode structure allows the device to operate at higher reverse bias voltages, the photon emission intensity generated by impact ionization or carrier recombination at defects (such as dislocations and point defects) is significantly enhanced. Simultaneously, the transparent anode electrode provides photons with an unobstructed, low-loss vertical emission path, reducing signal attenuation. The combined effect of the metal frame 4 and the transparent electrode 3 significantly improves the signal-to-noise ratio and intensity of the signal acquired by the micro-microscope, enabling more sensitive and accurate location and identification of defects.

[0037] Moreover, defect detection is performed under the actual operating electrical conditions of the device (with reverse bias applied), observing defects that are activated by the electric field and actually cause leakage, resulting in more accurate results. No destructive treatment or special test structures are required for the device under test, preserving its integrity. After defect localization analysis, the test substrate or device under test can still undergo subsequent electrical characteristic retesting or other analyses, improving analysis efficiency and device utilization. This is suitable for material screening, process line monitoring, and failure analysis during the R&D phase.

[0038] In some embodiments, step S200 above includes the following steps: S210: A patterned metal border 4 is formed on the front side of the semiconductor layer test substrate 1; S220: A transparent electrode 3 is formed in the area enclosed by the metal frame 4 and on the front side of the metal frame 4.

[0039] Specifically, in step S210, electron beam evaporation or magnetron sputtering is used to cover the entire working area with the metal material constituting the frame, forming a uniform, patternless metal film. Then, a lift-off process is used: first, photoresist is coated and patterned, then metal is deposited, and finally, the photoresist is dissolved to remove the metal in the non-patterned areas, forming the metal frame 4. In step S220, a transparent conductive oxide film is prepared using magnetron sputtering or chemical vapor deposition to form the transparent electrode 3.

[0040] In this embodiment, the metal frame 4 is first fabricated directly on the front side of the exposed semiconductor layer test substrate 1, which ensures that a pure interface, free from interference from other materials, is formed between the metal and the semiconductor. Through rigorous surface cleaning and in-situ deposition (such as electron beam evaporation), the characteristics of this interface can be precisely controlled, thereby obtaining a stable and high Schottky barrier height.

[0041] The barrier height of a metal is primarily determined by its work function and the surface state of the semiconductor. By first fabricating the metal frame 4, its materials and processes can be independently optimized to achieve the high barrier value required by the design, without being affected by the subsequent transparent electrode 3 process.

[0042] Subsequently, a transparent conductive oxide is fabricated within the region enclosed by the metal frame 4. The work function of the transparent conductive oxide is typically lower than that of the aforementioned metal frame 4 material; therefore, the Schottky barrier height formed by it and the same semiconductor material is naturally lower than that of the metal frame 4.

[0043] If the above steps are reversed, and the transparent electrode 3 is fabricated first, followed by the metal frame 4, an annular window needs to be etched into the transparent electrode 3 to allow the metal to contact the semiconductor. This involves etching steps that could damage both the transparent electrode 3 and the underlying semiconductor, making the process complex and risky. However, the metal frame 4 itself can serve as a ready-made physical mask. During subsequent deposition of the transparent electrode 3, both the internal area and the top of the metal frame 4 can be covered in one step. No patterning etching of the transparent electrode 3 is required, simplifying the process and completely avoiding damage to the active semiconductor region caused by etching.

[0044] Moreover, the metal frame 4 typically exhibits better semiconductor adhesion than transparent oxides, serving as a good substrate for subsequent film layers. The metal frame 4 forms a certain step height, which the subsequently deposited transparent electrode 3 can effectively cover, ensuring no breakage occurs at the edge of the metal frame 4 and guaranteeing electrical continuity and structural robustness.

[0045] The transparent electrode 3 covers both the semiconductor window and the upper surface of the metal frame 4. On one hand, it electrically connects the central transparent electrode 3 to the outer metal frame 4, ensuring that their potentials are consistent and the connection resistance is low. On the other hand, the metal frame 4 is in direct contact with the semiconductor (high-barrier Schottky), and the transparent electrode 3 is in direct contact with the semiconductor (low-barrier Schottky). Both form their respective Schottky junctions with the semiconductor in a parallel arrangement in the vertical direction, resulting in a clear structure and well-defined interface characteristics.

[0046] In some embodiments, the positional relationship between the metal frame 4 and the transparent electrode 3 can be as follows: Figure 2 In the structure shown, in the top view, the metal frame 4 surrounds the transparent electrode 3, but the transparent electrode 3 does not completely cover the metal frame 4; in other words, the transparent electrode 3 does not extend to the edge of the metal frame 4.

[0047] The core function of the metal frame 4 is to act as a field plate, using its high Schottky barrier to withstand and disperse the high electric field at the edges. If the transparent electrode 3 completely covers and extends to the outer edge of the metal frame 4, then at the outer edge of the metal frame 4, the peak point of electric field concentration will be located at the transparent electrode 3 / semiconductor interface, rather than the metal frame 4 / semiconductor interface. Due to the lower barrier of the transparent electrode 3, this point will experience premature breakdown.

[0048] By ensuring that the outer edge of the metal frame 4 is not covered by the transparent electrode 3, the outer edge interface of the semiconductor device is guaranteed to be a high-barrier metal-semiconductor contact. This locks the electric field peak below the metal frame 4, which can withstand a higher electric field, thereby maximizing the actual breakdown voltage of the device and fully utilizing the protective function of the metal frame 4 as a field plate.

[0049] In addition, from the perspective of manufacturing process, if the transparent electrode 3 is required to precisely cover the outer edge of the metal frame 4, it places extremely high and unnecessary demands on the alignment accuracy and edge uniformity of the photolithography and etching processes, which will increase the difficulty of the process and the risk of failure.

[0050] In this embodiment, the transparent electrode 3 only needs to ensure complete coverage of the inner edge of the metal frame 4 (to achieve a reliable electrical connection with the frame) and fill the window area it encloses. For its outer direction, only sufficient coverage is required to provide a good electrical connection, without the need for precise alignment of the outer edge. This significantly reduces the processing difficulty and improves fabrication yield and repeatability.

[0051] In some embodiments, the semiconductor layer test substrate 1, cathode electrode 2, and metal frame 4 described above can also be employed as follows: Figure 2 The structure shown is described in the following document. Figure 2 The semiconductor layer test substrate 1, cathode electrode 2 and metal frame 4 have a consistent outer contour in the horizontal direction.

[0052] Specifically, the semiconductor layer test substrate 1 includes an epitaxial layer and a substrate. The semiconductor layer test substrate 1, cathode electrode 2, and metal frame 4 have a consistent outer contour in the horizontal direction, meaning that in the final stage of chip fabrication, the patterning of all functional layers of the entire device can be completed simultaneously through a single dicing or cutting process. In some device designs, different layers may require independent patterning processes (e.g., the epitaxial layer may require mesa etching before the substrate to form isolation, and the cathode electrode 2 may require separate photolithography to be smaller than the substrate area). This increases the steps of photolithography, etching, and cleaning, increasing process complexity, time consumption, and cost.

[0053] In this embodiment, the substrate serves as the support base, and its size determines the final chip size. The epitaxial layer 12 is epitaxially grown on it, naturally having the same contour. The cathode electrode 2 is deposited using full-area deposition (such as evaporation or sputtering) and is finally diced together with the substrate. By defining the structure described above, the process flow can be simplified, the use of photomasks can be reduced, and testing costs can be lowered.

[0054] Furthermore, the alignment of the outer contours of the four layers creates a completely consistent support structure from top to bottom. This avoids problems such as weak mechanical strength, fragility, or internal stress concentration caused by excessive cutting of a layer or the presence of overhanging or protruding parts in a particular layer.

[0055] Device breakdown first occurs at the edges. Once the edges of all critical layers are aligned, the entire device has only a single, uniform physical edge. The high-barrier metal frame 4 acts as a field plate, and its protective effect can be most effectively and uniformly applied to this entire uniform edge perimeter. Electric field simulation and design become simpler and more controllable.

[0056] In some embodiments, the material of the metal frame 4 includes at least one of Ni / Au, Pt / Au, and Pd / Au.

[0057] Ni, Pt, and Pd are all high work function metals. When they come into contact with wide bandgap semiconductors such as gallium oxide, they naturally form a high Schottky barrier height, ensuring that the Schottky barrier of the metal frame 4 is higher than that of the transparent electrode 3. The high barrier allows the metal frame 4 to withstand a higher electric field, thereby effectively suppressing the electric field concentration at the edge of the transparent electrode 3 and improving the overall breakdown voltage.

[0058] Au is an inert metal that, when used as a coating on Ni, Pt, or Pd, effectively prevents them from oxidizing in air or during subsequent processes, thus maintaining long-term stability of contact resistance and interface properties. Au also has good electrical conductivity, providing an excellent low-resistance contact surface for external probe testing or wire bonding.

[0059] Ni, Pt, Pd, and Au are all extremely mature and widely used thin-film materials in semiconductor processes. They are easily deposited with high purity and in a controlled manner through electron beam evaporation or magnetron sputtering. They are suitable for combination with lift-off processes to form precise metal border patterns.

[0060] In some embodiments, the transparent electrode 3 is a conductive thin film that is transparent within the detection wavelength range of a micro-microscope.

[0061] The EMMI system detects electroluminescence generated by semiconductor defects under an electric field, with a spectral range typically covering the visible to near-infrared band. The transparent electrode 3 is transparent within the detection band of the microscopy, meaning that the optical bandgap and thin-film properties of the selected material must have high transmittance for this specific spectral window. This ensures that the vast majority of photons emitted from the defects can pass through the electrode without loss or with low loss and be effectively captured by the detector above, avoiding signal attenuation due to absorption or strong reflection by the electrode itself.

[0062] High light transmittance directly translates into high signal intensity. A stronger transmitted light signal means a shorter imaging integration time and a clearer outline of the luminescent point, thereby improving detection efficiency and enabling the observation of even the faintest defect luminescence. The uniform light transmittance of the material avoids image distortion or uneven signal intensity caused by uneven electrode film layers, ensuring that the formed photon image accurately reflects the distribution and intensity of the underlying defects, resulting in accurate and reliable localization results.

[0063] Preferably, the material of the transparent electrode 3 is at least one of indium tin oxide, tin oxide, zinc oxide, fluorine-doped tin oxide, and aluminum-doped zinc oxide.

[0064] The aforementioned materials possess an appropriate work function, enabling them to form a stable and repeatable Schottky barrier with the epitaxial layer. This forms the basis for constructing a functional Schottky diode under test, ensuring that the test is performed under the actual operating conditions of a standard device, rather than a non-functional structure used only for light transmission.

[0065] In some embodiments, the semiconductor layer test substrate 1 is a wide bandgap semiconductor material, including at least one of gallium oxide, silicon carbide, and gallium nitride. Preferably, the semiconductor layer test substrate 1 includes an n-type gallium oxide single crystal substrate 11 and an n-type gallium oxide epitaxial layer 12.

[0066] The n-type gallium oxide single crystal substrate 11 is the physical foundation of the device. As a high-quality single crystal material, it provides a perfect crystallographic template for the subsequent homoepitaxial growth of the n-type gallium oxide epitaxial layer 12, ensuring the crystal quality of the epitaxial layer. The heavy doping of the n-type gallium oxide single crystal substrate 11 gives it extremely low resistivity. In a vertically conductive diode structure, it acts as a highly efficient vertical current channel, uniformly conducting the cathode current to the entire epitaxial layer while minimizing its own on-resistance and voltage drop.

[0067] The n-type gallium oxide epitaxial layer 12 is the functional core of the device. During the growth of the epitaxial layer, various microscopic defects (such as dislocations and point defect clusters) are introduced. These defects are the source of leakage current and ultimately light emission under an electric field. The light doping of the n-type gallium oxide epitaxial layer 12 enables it to withstand high reverse voltage. By controlling its thickness and doping concentration, the theoretical breakdown voltage of the device can be precisely designed.

[0068] The n-type gallium oxide single crystal substrate 11 has a thickness of 500 nm to 500 μm; the n-type gallium oxide epitaxial layer 12 has a thickness of 20 μm to 2000 μm; the cathode electrode 2 has a thickness of 50 nm to 5 μm; the transparent electrode 3 has a thickness of 50 nm to 5 μm; and the metal frame 4 has a thickness of 1 / 5 to 1 / 3 of the thickness of the transparent electrode 3.

[0069] In some embodiments, step S400 may include: placing the semiconductor layer test substrate 1 on the sample stage of a light microscope, with the transparent electrode 3 facing the objective lens of the light microscope; applying a reverse bias voltage between the cathode electrode 2 and the transparent electrode 3 under darkroom conditions; and acquiring and imaging the electroluminescence signal transmitted from the transparent electrode 3 through the optical imaging system of the light microscope.

[0070] Specifically, the low-light microscope is an EMMI system, which includes a liquid nitrogen-cooled silicon-based CCD or InGaAs array detector, a long working distance optical objective, and an electromagnetically shielded dark chamber. During testing, the test substrate is fixed on the sample stage, with the transparent electrode 3 facing the objective. After applying a bias voltage, the light signal emitted by the defect is collected by the objective, integrated by the detector for several seconds to tens of minutes, and a photon emission localization map superimposed on the device morphology is generated.

[0071] Liquid nitrogen-cooled silicon-based CCDs or InGaAs detectors effectively suppress thermal noise and exhibit extremely high detection efficiency for very weak photon signals in the near-infrared to visible light bands. This ensures effective capture of the typically very low-intensity luminescence signals emitted by gallium oxide defects. Furthermore, its location above the transparent electrode 3 allows for capture of electroluminescent signals from above without altering the overall structure of the test device.

[0072] Long working distance objectives allow for a safe distance between the objective and the test device (especially the electrodes that connect to the probe), avoiding physical collisions and ensuring operational safety and stability when high voltage is applied.

[0073] Electromagnetic shielding darkrooms, combined with electromagnetic shielding under darkroom conditions, can isolate ambient light and external electromagnetic field interference to the greatest extent, ensuring that the collected light signals originate purely from the electroluminescence inside the device, thus improving the accuracy and reliability of detection.

[0074] In addition, by integrating the signal over several seconds to tens of minutes, intermittent and weak single-photon events can be accumulated into a stable and clear image signal, thereby significantly improving the signal-to-noise ratio and making even very weak defects and leakage currents visible.

[0075] Using the aforementioned low-light microscopy system, each light spot in the image directly corresponds to an active leakage defect point, and its brightness roughly reflects the strength of the leakage at that point, enabling rapid and visual screening of defects. By precisely overlaying the image with the device morphology (such as the boundary of transparent electrode 3 and the edge of the mesa), the specific coordinates of the defect in the active region can be determined, providing precise guidance for subsequent physical failure analyses such as focused ion beam cutting and transmission electron microscopy. By changing the bias voltage and observing the evolution of the emission patterns under different voltages, the activation characteristics of the defects can be studied. Statistical analysis of the emission patterns of multiple devices from the same batch allows for quantitative evaluation of the epitaxial material quality or process stability.

[0076] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for defect detection in power semiconductor devices, characterized in that, include: A cathode electrode (2) is fabricated on the back side of the semiconductor layer test substrate (1) and forms an ohmic contact with the semiconductor layer test substrate (1); An anode electrode is fabricated on the front side of the semiconductor layer test substrate (1). The anode electrode includes a transparent electrode (3) and a metal frame (4). The metal frame (4) surrounds and contacts the edge region of the transparent electrode (3). The metal frame (4) forms a first Schottky contact with the semiconductor layer test substrate (1), and the transparent electrode (3) forms a second Schottky contact with the semiconductor layer test substrate (1). The Schottky barrier height of the metal frame (4) is higher than that of the transparent electrode (3). A reverse bias voltage is applied between the cathode electrode (2) and the transparent electrode (3); The electroluminescence signal generated by the semiconductor layer test substrate (1) under the reverse bias voltage is acquired by a micro-microscope located above the transparent electrode (3); the transparent electrode (3) is configured to allow the electroluminescence signal to penetrate upward. The defect location of the semiconductor layer test substrate (1) is determined based on the electroluminescent signal.

2. The method for defect detection in power semiconductor devices as described in claim 1, characterized in that, The fabrication of the anode electrode on the front side of the semiconductor layer test substrate (1) includes: A patterned metal border (4) is formed on the front side of the semiconductor layer test substrate (1); The transparent electrode (3) is formed in the area enclosed by the metal frame (4) and on the front side of the metal frame (4).

3. The method for defect detection in power semiconductor devices as described in claim 2, characterized in that, In a top view, the metal frame (4) surrounds the transparent electrode (3).

4. The method for defect detection in power semiconductor devices as described in claim 3, characterized in that, The semiconductor layer test substrate (1), the cathode electrode (2), and the metal frame (4) have a consistent outer contour in the horizontal direction.

5. The method for defect detection in power semiconductor devices as described in claim 1, characterized in that, The material of the metal frame (4) includes at least one of Ni / Au, Pt / Au, and Pd / Au.

6. The method for defect detection in power semiconductor devices as described in claim 1, characterized in that, The transparent electrode (3) is a conductive thin film that is transparent within the detection band of the micro-microscope; the material of the transparent electrode (3) is at least one of indium tin oxide, tin oxide, zinc oxide, fluorine-doped tin oxide, and aluminum-doped zinc oxide.

7. The method for defect detection in power semiconductor devices as described in claim 1, characterized in that, The semiconductor layer test substrate (1) is a wide bandgap semiconductor material, including at least one of gallium oxide, silicon carbide, and gallium nitride.

8. The method for defect detection in power semiconductor devices as described in claim 7, characterized in that, The semiconductor layer test substrate (1) includes an n-type gallium oxide single crystal substrate (11) and an n-type gallium oxide epitaxial layer (12).

9. The method for defect detection in power semiconductor devices as described in claim 8, characterized in that, The thickness of the n-type gallium oxide single crystal substrate (11) is 500 nm to 500 μm; the thickness of the n-type gallium oxide epitaxial layer (12) is 20 μm to 2000 μm; the thickness of the cathode electrode (2) is 50 nm to 5 μm; the thickness of the transparent electrode (3) is 50 nm to 5 μm; and the thickness of the metal frame (4) is 1 / 5 to 1 / 3 of the thickness of the transparent electrode (3).

10. The method for defect detection in power semiconductor devices as described in claim 1, characterized in that, The acquisition of the electroluminescence signal generated by the semiconductor layer test substrate (1) under the reverse bias voltage using a micro-microscope located above the transparent electrode (3) includes: The semiconductor layer test substrate (1) is placed on the sample stage of the light microscope, and the transparent electrode (3) faces the objective lens of the light microscope; under darkroom conditions, the reverse bias voltage is applied between the cathode electrode (2) and the transparent electrode (3); the electroluminescence signal transmitted from the transparent electrode (3) is collected and imaged by the optical imaging system of the light microscope.

Images