Epitaxial structure of heterojunction bipolar transistor and method for manufacturing the same
By using GaN-based materials as the collector layer in the epitaxial structure of GaAs heterojunction bipolar transistors, the power limitation problem of GaAs HBT devices in high-frequency and high-power applications has been solved, achieving higher operating voltage and output power, thus meeting the requirements of 5G communication.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-03-25
- Publication Date
- 2026-03-24
AI Technical Summary
Existing GaAs heterojunction bipolar transistors have power limitations in high-frequency and high-power applications, making it difficult to meet the requirements of 5G communication.
Using GaN-based materials as the collector layer of a heterojunction bipolar transistor, combined with specific epitaxial structures and fabrication processes, the process involves epitaxially forming an n-type doped AlGaAs emitter layer, a p-type doped GaAs base layer, and an n-type doped GaN-based collector layer on a GaAs substrate.
The operating voltage of the device was increased, the output power was increased, the power limitation of GaAs HBT devices was overcome, and the high frequency and high power requirements of 5G communication were met.
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Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor device process, in particular to an epitaxial structure of a heterojunction bipolar transistor and a preparation method thereof. BACKGROUND
[0002] The development of wireless communication technology puts forward higher requirements for the performance of radio frequency devices, such as higher frequency range, higher power, higher efficiency, higher operating voltage, etc. Therefore, compound semiconductor material-based radio frequency devices are more and more widely used in the field of wireless communication.
[0003] Gallium arsenide (GaAs) compound semiconductor is one of the main materials of radio frequency power amplifiers in wireless communication systems, and is important in the preparation of radio frequency, microwave devices and high-speed digital circuits due to its high electron mobility. GaAs semiconductor devices have the advantages of high frequency, good temperature performance, small noise, strong anti-radiation ability, etc.
[0004] At present, GaAs material-based semiconductor devices mainly include GaAs heterojunction bipolar transistors (GaAs HBT) and GaAs high electron mobility transistors (GaAs HEMT). Among them, GaAs HBT is widely used in mobile phones, optical communication systems, radar systems and other equipment systems due to its high power density, high gain, low phase noise, good linearity, small chip area and low manufacturing cost. SUMMARY
[0005] In a first aspect, a method for preparing an epitaxial structure of a heterojunction bipolar transistor is provided, comprising:
[0006] forming an n-type doped aluminum gallium arsenide (AlGaAs) emitter layer on a gallium arsenide (GaAs) substrate by epitaxy;
[0007] forming a p-type doped gallium arsenide (GaAs) base layer on the emitter layer by epitaxy;
[0008] forming an n-type doped gallium nitride (GaN) collector layer on the base layer by epitaxy.
[0009] In a second aspect, an epitaxial structure of a heterojunction bipolar transistor is provided, comprising a gallium arsenide (GaAs) substrate, an n-type doped aluminum gallium arsenide (AlGaAs) emitter layer, a p-type doped gallium arsenide (GaAs) base layer, and an n-type doped gallium nitride (GaN) collector layer.
[0010] The emitter layer, the base layer and the collector layer are sequentially arranged on the upper surface of the substrate from bottom to top.
[0011] It can be seen that in the practical application of the HBT device with the new epitaxial structure of the HBT, since the GaN-based material is used as the collector layer, a higher working voltage can be used, thereby being beneficial to increase the output power of the HBT device, overcome the power limitation of the GaAs HBT device, and better meet the requirements of high frequency and high power of 5G communication. BRIEF DESCRIPTION OF DRAWINGS
[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.
[0013] Figure 1 is a structure schematic diagram of an epitaxial structure of a GaAs HBT according to an embodiment of the present application;
[0014] Figure 2 is a structure schematic diagram of an epitaxial structure of a HBT according to an embodiment of the present application;
[0015] Figure 3 is a flowchart of a preparation method of an epitaxial structure of a heterojunction bipolar transistor according to an embodiment of the present application;
[0016] Figure 4 is a flowchart of a preparation of a collector of a HBT device according to an embodiment of the present application;
[0017] Figure 5 is a flowchart of a preparation of a base of a HBT device according to an embodiment of the present application;
[0018] Figure 6 is a flowchart of a preparation of an emitter of a HBT device according to an embodiment of the present application;
[0019] Figure 7 is a structure schematic diagram of a HBT device according to an embodiment of the present application;
[0020] Figure 8 is a structure schematic diagram of another HBT device according to an embodiment of the present application;
[0021] Figure 9 is a structure schematic diagram of another HBT device according to an embodiment of the present application;
[0022] Figure 10This is a schematic diagram of a power amplifier circuit based on an HBT device according to an embodiment of this application. Detailed Implementation
[0023] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0024] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. The reference to "embodiment" herein means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments. Furthermore, the terms "placed on," "placed," or "placed in" in the embodiments of this application are equivalent to "deposited," referring to a layer structure deposited using thin-film deposition techniques in semiconductor manufacturing processes.
[0025] In the accompanying drawings provided in this application, the cross-sectional views of the device structure shown may not be scaled up, and the schematic diagrams are merely illustrative and should not limit the scope of protection claimed in this application. Furthermore, the thickness of each layer in the cross-sectional views of the device structure is only schematic and needs to be determined based on the specific semiconductor process, and does not constitute a limitation on the embodiments of this application. Additionally, the radio frequency semiconductor device fabricated in the actual fabrication process should include three-dimensional spatial dimensions of length, width, and depth.
[0026] In the embodiments of this application, "at least one item" or its similar expression refers to any combination of these items, including any combination of a single item or a plurality of items. "One or more" means one or more, while "multiple" means two or more. For example, "at least one item" of a, b, or c can represent the following seven cases: a, b, c; a and b; a and c; b and c; a, b, and c. Each of a, b, and c can be an element or a set containing one or more elements.
[0027] In this embodiment, the epitaxial structure of GaAs HBT can be prepared using the following method:
[0028] On a GaAs substrate, an n-type doped GaAs (n-GaAs) collector layer, a p-type doped GaAs (p-GaAs) base layer, and an n-type doped AlGaAs (n-AlGaAs) emitter layer are epitaxially grown sequentially. Figure 1 As shown.
[0029] The current collector material can be GaAs, with a bandgap of 1.4 eV and a breakdown electric field strength of 0.4 MV / cm.
[0030] In addition, unlike the epitaxial structures of GaAs HBTs described above, a novel epitaxial structure of HBT according to embodiments of this application can be fabricated using the following method:
[0031] On a GaAs substrate, an n-type doped aluminum gallium arsenide (n-AlGaAs) emitter layer, a p-type doped GaAs (p-GaAs) base layer, and an n-type doped gallium nitride (n-GaN) collector layer are sequentially epitaxially formed, such as... Figure 2 As shown.
[0032] Specifically, GaN-based materials may include at least one of GaN, aluminum gallium nitride (AlGaN), and indium gallium nitride (InGaN).
[0033] It should be noted that using GaN-based materials as the current collector layer of the HBT in this embodiment of the application has the following advantages:
[0034] 1) The bandgap of GaN-based materials can be 3.4 eV;
[0035] Therefore, GaN-based materials have a larger bandgap compared to GaAs.
[0036] 2) The breakdown electric field strength of GaN-based materials can be 3.3 MV / cm.
[0037] Therefore, GaN-based materials have a larger breakdown voltage compared to GaAs.
[0038] In summary, in practical applications of HBT devices with the epitaxial structure of the novel HBT of this application, the use of GaN-based materials as the collector layer allows for the use of higher operating voltages, thereby increasing the output power of the HBT device, overcoming the power limitations of GaAs HBT devices, and better meeting the high-frequency and high-power requirements of 5G communication.
[0039] In some possible implementations, the HBT epitaxial structure of the embodiments of this application, in addition to the above-described... Figure 2As shown, there may also be several variant structures, where the various epitaxially grown thin film layers (such as the emitter layer, base layer, and current collector layer) are made of different materials than those described above, as follows:
[0040] 1) In addition to AlGaAs, other single materials such as InGaAs and InGaP can also be used when preparing the emitter layer.
[0041] For example, on a GaAs substrate, an n-type doped InGaAs (or n-type doped InGaP) emitter layer, a p-type doped GaAs base layer, and an n-type doped GaN-based current collector layer are epitaxially grown sequentially.
[0042] 2) Two or more materials can be used when preparing the emitter layer.
[0043] For example, at least two of AlGaAs, InGaAs, and InGaP can be used to prepare the emitter layer.
[0044] In some possible implementations, the extensional structure of the novel HBT in this application embodiment, in addition to the above-described... Figure 2 As shown, there may be other structures used to enhance device performance, yield and reliability, such as buffer layers, sub-collectors, grading layers, spacers, cap layers, etc.
[0045] For simplicity, the following introduction to the fabrication of HBT epitaxial structures and HBT device fabrication methods will focus on... Figure 2 Taking the shown epitaxial structure as an example, the other various variant structures can be understood in the same way, and all of them are within the scope of protection claimed in this application, so they will not be described in detail here.
[0046] I. Epitaxial Structure Preparation Method of HBT
[0047] Please see Figure 3 , Figure 3 This is a schematic flowchart illustrating a method for fabricating an epitaxial structure of a heterojunction bipolar transistor according to an embodiment of this application. The specific steps are as follows:
[0048] S310. An n-type doped aluminum gallium arsenide (AlGaAs) emitter layer is epitaxially formed on a GaAs substrate.
[0049] It should be noted that n-type doped AlGaAs (n-AlGaAs) emitter layers can be prepared in various ways, such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), and hydride vapor phase epitaxy (HVPE).
[0050] Trimethylgallium (TMG) can be the source of Ga, trimethylaluminium (TMA) can be the source of Al, and arsenic (AsH3) can be the source of As. The reaction temperature can be between 600℃ and 800℃, and the growth rate can be between 400A / min and 1000A / min.
[0051] Specifically, the thickness of the AlGaAs emitter layer can be 50-500 nm.
[0052] In addition, in order to form n-type doping, the doping element used can be at least one of O, S, Se, Te, etc., or at least one of C, Si, Ge, Sn, etc., and the doping concentration can be between 1E17 cm⁻³ and 1E20 cm⁻³.
[0053] S320. A p-type doped gallium arsenide (GaAs) base layer is epitaxially formed on the emitter layer.
[0054] It should be noted that p-type doped GaAs (p-GaAs) base layers can be prepared using various methods, such as MBE or MOCVD.
[0055] Specifically, the thickness of the p-type doped GaAs base layer can be 50-150 nm.
[0056] In addition, in order to form p-type doping, the doping element used can be at least one of Be, Mg, Zn, Cd, Hg, etc., or at least one of C, Si, Ge, Sn, etc., and the doping concentration can be between 1E18 cm⁻³ and 1E20 cm⁻³.
[0057] S330, An n-type doped gallium nitride (GaN) collector layer is epitaxially formed on the base layer.
[0058] It should be noted that growing the current collector layer of n-type doped GaN-based material on the upper surface of the p-GaAs base layer can be achieved using gas-source molecular beam epitaxy (GSMBE) with dimethylhydrazine as the nitrogen (N) source.
[0059] For example, taking GaN as an example, dimethylhydrazine is introduced into a vacuum chamber with a pressure between 10 Torr and 9 Torr via a flow controller, while solid potassium (Ga) can come from an evaporation source. By simultaneously supplying dimethylhydrazine and potassium into the reaction chamber, the reaction temperature can be between 600°C and 800°C, and the growth rate can be 150 nm / hr, thereby generating GaN.
[0060] In addition, the upper surface of the p-GaAs base layer also needs to be thermally cleaned.
[0061] For example, before introducing dimethylhydrazine and potassium as described above, thermal cleaning can be achieved by injecting diethylarsine (DEA) or triethylarsine (TEA) at a temperature of 660°C.
[0062] II. Fabrication method of the HBT device of this application
[0063] 1. Fabrication of the collector
[0064] a) Photolithography process
[0065] It should be noted that the photolithography process can include coating, alignment, and development. For example... Figure 4 As shown in (a), photoresist is prepared on the upper surface of the current collector layer of GaN-based material.
[0066] b) Fabrication of the current collector metal layer
[0067] It should be noted that the collector metal layer can be prepared by sputtering and evaporation.
[0068] For example, such as Figure 4 As shown in (b), the collector metal layer is prepared in the photoresist by sputtering and evaporation.
[0069] Specifically, the collector metal layer can be composed of two or more metals, such as Ti / Al / Ti / Au, and the thickness can be 10-40nm for Ti, 100-300nm for Al, and 100-300nm for Au.
[0070] c) Degumming and Cleaning
[0071] For example, such as Figure 4 As shown in (c), a current collector is prepared on the upper surface of the current collector layer of the GaN-based material by removing the adhesive and cleaning.
[0072] d) Optionally, prepare a first passivation layer.
[0073] It should be noted that a first passivation layer can also be fabricated to protect the collector. This first passivation layer is essentially a passivation layer used to protect the collector; other terms can also be used to describe it, and no specific limitation is made.
[0074] For example, such as Figure 4 As shown in (d), a first passivation layer is deposited on the upper surface of the current collector layer and on the current collector electrode of the GaN-based material.
[0075] Specifically, the first passivation layer can be SiN. x , SiO2, Al2O3, AlN, AlON, SiO x N y A single-layer or multi-layer structure composed of at least one of the following materials: HfO2 and Ga2O3.
[0076] Specifically, the thickness of the first passivation layer can be 100-200 nm.
[0077] 2. Base fabrication
[0078] a) Photolithography process
[0079] It should be noted that the photolithography process can include coating, alignment, and development. For example... Figure 5 As shown in (a), photoresist is prepared on the upper surface of the first passivation layer.
[0080] b) Etching process
[0081] It should be noted that the etching process can be applied to both the first passivation layer and the current collector layer of the n-type doped GaN-based material. For example... Figure 5 As shown in (b), the first passivation layer and the current collector layer of n-type doped GaN material are etched using photoresist as a mask.
[0082] Specifically, etching can be dry etching.
[0083] Specifically, the first passivation layer can be etched using various gases, such as CF4, CHF3, and SF6.
[0084] Specifically, the gases used to etch the current collector layer can also be in various combinations, such as SF6 / BCl3 / He, Cl2 / O2 / N2, Cl2 / BCl3, etc.
[0085] In addition, to reduce damage to the current collector layer, atomic layer etching (ALE) can be used when etching the current collector layer, or an endpoint detector (EPD) can be used to precisely control the etching of the current collector layer to reduce or prevent the etching of the current collector layer.
[0086] After etching is complete, resist removal and wafer cleaning can be performed.
[0087] c) Base metal layer fabrication
[0088] It should be noted that the base metal layer can be prepared by sputtering and evaporation.
[0089] For example, such as Figure 5 As shown in (c), the base metal layer is prepared by sputtering and evaporation.
[0090] Specifically, the base metal layer can be composed of two or more metals, such as Ti / Au, Ti / Pt / Ti / Au, and the thickness can be 10-40nm for Ti, 50-200nm for Pt, and 100-300nm for Au.
[0091] d) De-adhesive removal and cleaning.
[0092] e) Optionally, a second passivation layer is prepared.
[0093] It should be noted that a second passivation layer can also be fabricated to protect the base. This second passivation layer is essentially a passivation layer used to protect the base, but other terms can be used to describe it; no specific restrictions are placed on this.
[0094] For example, such as Figure 5 As shown in (d), a second passivation layer is deposited on the upper surface of the base, the upper surface of the first passivation layer, and the upper surface of the p-type doped gallium arsenide (GaAs) base layer.
[0095] Specifically, the second passivation layer can be SiN. x , SiO2, Al2O3, AlN, AlON, SiO x N y A single-layer or multi-layer structure composed of at least one of the following materials: HfO2 and Ga2O3.
[0096] Specifically, the thickness of the second passivation layer can be 100-200 nm.
[0097] 3. Fabrication of the emitter:
[0098] a) Photolithography process
[0099] It should be noted that the photolithography process can include coating, alignment, and development.
[0100] For example, such as Figure 6 As shown in (a), photoresist is prepared on the upper surface of the second passivation layer.
[0101] b) Etching process
[0102] It should be noted that the etching process can be used to etch the second passivation layer and the p-GaAs base layer.
[0103] For example, such as Figure 6 As shown in (b), the second passivation layer and the p-GaAs base layer are etched using photoresist as a mask.
[0104] Specifically, dry etching.
[0105] Specifically, various gases can be used to etch the second passivation layer, such as CF4, CHF3, SF6, etc.
[0106] Specifically, the p-GaAs base layer can be etched using either wet or dry etching processes. Wet etching is performed in an aqueous solution of phosphoric acid (H3PO4) and acidic oxygen water (H2O2). Dry etching employs plasma etching, using gases such as Cl2, BCl3, SiCl4, CF4, and CCl2F2. The desired etching result is achieved by controlling the microwave power, internal pressure, gas type, and flow rate within the reaction chamber.
[0107] In addition, to reduce damage to the p-GaAs base layer, atomic layer etching (ALE) can be used when etching the p-GaAs base layer, or the etching rate can be reduced by adjusting the process parameters.
[0108] After etching is completed, resist removal and wafer cleaning can also be performed.
[0109] c) Fabrication of emitter metal layer
[0110] It should be noted that the emitter metal layer can be prepared by sputtering or evaporation.
[0111] Specifically, the emitter metal layer can be composed of two or more metals, such as Ni / Au, AuGe / Ti / Au, Ti / Pt / Au, and the thickness can be 10-40nm for Ti, 50-200nm for Pt, and 100-300nm for Au.
[0112] d) De-adhesive removal and cleaning.
[0113] e) Optionally, a third passivation layer is prepared.
[0114] It should be noted that a third passivation layer can also be fabricated to protect the emitter. This third passivation layer is essentially a passivation layer used to protect the emitter, but other terms can be used to describe it; no specific restrictions are placed on this.
[0115] For example, such as Figure 6 As shown in (c), a third passivation layer is deposited on the upper surface of the emitter and the upper surface of the second passivation layer.
[0116] Specifically, the third passivation layer can be SiN. x, SiO2, Al2O3, AlN, AlON, SiO x N y A single-layer or multi-layer structure composed of at least one of the following materials: HfO2 and Ga2O3.
[0117] Specifically, the thickness of the third passivation layer can be 100-200 nm.
[0118] 4. Other frontside processes
[0119] For the front-side fabrication of GaAs HBT devices, in addition to the fabrication of the emitter, base, and collector, other processes may also be included, such as intermetallic dielectric layers, via etching, and metal interconnects. Figure 7 As shown.
[0120] Specifically, the intermetallic dielectric layer can be silicon oxide, silicon nitride, or polyimide, etc.
[0121] Specifically, the metal interconnects can be Au, Cu, Al, etc.
[0122] Finally, a passivation layer (Final Passivation), also known as the fourth passivation layer, is created. While the fourth passivation layer is essentially a passivation layer, other terms can also be used to describe it; no specific restrictions are placed on this.
[0123] Specifically, the fourth passivation layer can be silicon oxide, silicon nitride, polyimide, benzocyclobutene (BCB), etc.
[0124] For example, a schematic diagram of an HBT device after the front-side process is completed, such as... Figure 7 As shown.
[0125] 5. Optionally, capacitors, resistors, and inductors can be fabricated.
[0126] It should be noted that, in the embodiments of this application, while fabricating the HBT device, capacitors, resistors, and inductors can also be fabricated to form a monolithic microwave integrated circuit (MMIC) circuit, which can be used as an internal matching circuit, an input / output matching circuit, or an LC filter, such as... Figure 8 As shown.
[0127] In addition, Figure 8 In the devices shown, the number of capacitors, resistors, and inductors in this application embodiment is not limited.
[0128] Specifically, an inductor can be made of a metal coil, which can be a square winding, a round winding, or other shapes. The metal electrode material of the inductor can be made of at least one of Au, Al, Cu, Fe, Ni, or an alloy thereof.
[0129] Specifically, the capacitor can adopt a MIM (metal-dielectric-metal) structure. The capacitor can also have various shapes, such as square and rectangular. The capacitor dielectric can be silicon nitride, silicon oxide, or other dielectric materials. The metal electrode material of the capacitor can be at least one of Au, Al, and Cu, or other metals or alloys. The thickness of the capacitor dielectric and metal, as well as the size and shape of the capacitor, can be determined by the specific application and design.
[0130] Specifically, the resistor can be a thin film resistor (TFR). There are various methods for its fabrication, such as etching and metal stripping. The etching method is explained below:
[0131] 1) Fabrication of thin film resistive layer
[0132] It should be noted that the embodiments of this application can be prepared by vacuum evaporation, sputtering or chemical deposition.
[0133] 2) Perform adhesive application, alignment, exposure, and development.
[0134] 3) Thin-film resistive etching
[0135] It should be noted that the materials used for thin-film resistors include Ni-Co, Ta, Si, cermet, and Au-Cr and Ni-P resistive films. For example, NiCr and TaN are also possible materials.
[0136] 4) Remove glue and clean
[0137] 6. Backside Process:
[0138] It should be noted that after the front-side process of the GaAs HBT device is completed, the back-side process can be performed in this embodiment. The back-side process may include the following steps:
[0139] 1) Bond the wafer to a carrier, such as a sapphire or silicon wafer.
[0140] It should be noted that wafer bonding technology refers to the physical bonding of a device wafer onto a carrier for the implementation of back-side wafer processing.
[0141] 2) Thinning and polishing
[0142] It should be noted that the thickness of the thinned wafer can be 50-150um.
[0143] 3) Backside via photolithography
[0144] It should be noted that back-hole photolithography can include processes such as coating, alignment, exposure, and development.
[0145] 4) Back hole etching
[0146] It should be noted that back hole etching can be performed using plasma etching technology, and commonly used gases include Cl2, BCl3, SiCl4, CF4, CCl2F2, etc.
[0147] To obtain vias with good morphology, the Bosch etching method can be used, in which the entire etching process involves alternating etching and deposition steps. The etching step uses SF6 as the etching gas, and the deposition step uses C4F8 as the deposition gas, which deposits a polymer protective film on the silicon via sidewalls to protect them from etching.
[0148] 5) Back hole metallization
[0149] It should be noted that the metallization process may include the sputtering of a seed layer, typically Ti or TiW, with a thickness of 5-50 nm.
[0150] When making metallic conductors, metals such as Al, Cu, and Au can be used, and processes such as vapor deposition or electroplating can be employed, with a thickness ranging from 2 to 10 μm.
[0151] 6) Wafer debonding, cleaning, and testing.
[0152] For example, HBT devices after back-side processing, such as Figure 9 As shown. The GaAs substrate needs to be thinned, and back vias are made on the thinned GaAs substrate and emitter layer, as well as a back metal layer is deposited.
[0153] It should be noted that the HBT device in this application embodiment can be used to design and manufacture a radio frequency power amplifier (PA). In addition to having excellent frequency performance, the radio frequency power amplifier can be used at higher operating voltages to meet higher power requirements.
[0154] For example, such as Figure 10 As shown, the RF power amplifier may include an input matching module for the input signal, an HBT transistor module, a bias and stabilization circuit module, and an output matching module for the output signal. The input matching module, HBT transistor module, and output matching module are connected in sequence, and the stabilization circuit module is connected to the HBT transistor module.
[0155] Furthermore, it should be noted that, for the sake of simplicity, the above-described method embodiments are all presented as a series of actions. Those skilled in the art should understand that this application is not limited to the described order of actions, as some steps in the embodiments of this application can be performed in other orders or simultaneously. In addition, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of this application.
[0156] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0157] The embodiments of this application have been described in detail above. The descriptions in the embodiments of this application are only for the purpose of helping to understand the method and core ideas of this application. Those skilled in the art should know that there may be changes in the specific implementation methods and application scope of the embodiments of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A method for fabricating an epitaxial structure of a heterojunction bipolar transistor, characterized in that, include: An n-type doped aluminum gallium arsenide (AlGaAs) emitter layer is epitaxially formed on a gallium arsenide (GaAs) substrate; A p-type doped gallium arsenide (GaAs) base layer is epitaxially formed on the emitter layer; An n-type doped gallium nitride (GaN) current collector layer is epitaxially formed on the base layer; A first photoresist is prepared on the upper surface of the current collector layer, a current collector metal layer is prepared in the first photoresist, the first photoresist is removed to obtain a current collector, the current collector is located on the upper surface of the current collector layer, and a first passivation layer is deposited on the upper surface of the current collector layer and the current collector. A second photoresist is prepared on the upper surface of the first passivation layer, and the second photoresist covers the collector electrode. Using the second photoresist as a mask, the first passivation layer and the collector layer are etched to expose the base layer. The second photoresist is removed, and a third photoresist is prepared on the upper surface of the exposed base layer. A base metal layer is prepared in the third photoresist, and the third photoresist is removed to obtain the base electrode. The base electrode is located on the upper surface of the exposed base layer. A second passivation layer is deposited on the upper surface of the base electrode, the upper surface of the first passivation layer, and the upper surface of the base layer. A fourth photoresist is prepared on the upper surface of the second passivation layer, the fourth photoresist covering the base electrode. Using the fourth photoresist as a mask, the second passivation layer and the base electrode layer are etched to expose the emitter layer. The fourth photoresist is removed, and a fifth photoresist is prepared on the upper surface of the exposed emitter layer. An emitter metal layer is prepared in the fifth photoresist, and the fifth photoresist is removed to obtain the emitter. The emitter is located on the upper surface of the exposed emitter layer. A third passivation layer is deposited on the upper surface of the emitter and the upper surface of the second passivation layer. An intermetallic dielectric layer is prepared on the upper surface of the third passivation layer, and a fourth passivation layer is prepared on the upper surface of the intermetallic dielectric layer to obtain a heterojunction bipolar transistor device.
2. The method according to claim 1, characterized in that, The bandgap of the GaN-based material is 3.4e; the electric field strength of the GaN-based material is 3.3 MV / cm.
3. The method according to claim 1, characterized in that, The GaN-based material includes at least one of GaN, aluminum gallium nitride (AlGaN), and indium gallium nitride (InGaN).
4. The method according to claim 1, characterized in that, The doping element used to epitaxially form the current collector layer is at least one of Si, C, and Ge; The doping concentration used to epitaxially form the current collector layer is between 1E17 cm⁻³ and 1E19 cm⁻³.
5. The method according to claim 1, characterized in that, The Al in the AlGaAs used to epitaxially form the emitter layer is provided by trimethylaluminum; The Ga in the AlGaAs used to epitaxially form the emitter layer is provided by trimethylgallium; The As in the AlGaAs used to epitaxially form the emitter layer is provided by arsine; The reaction temperature used to epitaxially form the emitter layer is between 600°C and 800°C; The growth rate used to epitaxially form the emitter layer is between 400 A / min and 1000 A / min; The doping element used to epitaxially form the emitter layer is at least one of O, S, Se, and Te, or the doping element used to epitaxially form the emitter layer is at least one of C, Si, Ge, and Sn; The doping concentration used to epitaxially form the emitter layer is between 1E17 cm⁻³ and 1E20 cm⁻³.
6. The method according to claim 1, characterized in that, The Al in the GaAs used to epitaxially form the base layer is provided by trimethylaluminum; The doping element used to epitaxially form the base layer is at least one of Be, Mg, Zn, Cd, and Hg, or the doping element used to epitaxially form the base layer is at least one of C, Si, Ge, and Sn. The doping concentration used to epitaxially form the base layer is between 1E18 cm⁻³ and 1E20 cm⁻³.
7. The method according to claim 1, characterized in that, The thickness of the current collector layer is 500nm-2000nm; The thickness of the base layer is 50-150 nm; The thickness of the emission layer is 50-500 nm.
8. The method according to claim 1, characterized in that, Also includes: The heterojunction bipolar transistor device is subjected to back-side processing.
9. An epitaxial structure for a compound semiconductor device, characterized in that, include: The structure comprises a silicon (Si) substrate, an n-type doped gallium nitride (GaN) current collector layer, a p-type doped gallium arsenide (GaAs) base layer, and an n-type doped aluminum gallium arsenide (AlGaAs) emitter layer; among which, The current collector layer, the base layer, and the emitter layer are arranged sequentially from bottom to top on the upper surface of the substrate; The epitaxial structure is used to fabricate a heterojunction bipolar transistor device, and the fabrication method of the heterojunction bipolar transistor device includes: A first photoresist is prepared on the upper surface of the current collector layer, a current collector metal layer is prepared in the first photoresist, the first photoresist is removed to obtain a current collector, the current collector is located on the upper surface of the current collector layer, and a first passivation layer is deposited on the upper surface of the current collector layer and the current collector. A second photoresist is prepared on the upper surface of the first passivation layer, and the second photoresist covers the collector electrode. Using the second photoresist as a mask, the first passivation layer and the collector layer are etched to expose the base layer. The second photoresist is removed, and a third photoresist is prepared on the upper surface of the exposed base layer. A base metal layer is prepared in the third photoresist, and the third photoresist is removed to obtain the base electrode. The base electrode is located on the upper surface of the exposed base layer. A second passivation layer is deposited on the upper surface of the base electrode, the upper surface of the first passivation layer, and the upper surface of the base layer. A fourth photoresist is prepared on the upper surface of the second passivation layer, the fourth photoresist covering the base electrode. Using the fourth photoresist as a mask, the second passivation layer and the base electrode layer are etched to expose the emitter layer. The fourth photoresist is removed, and a fifth photoresist is prepared on the upper surface of the exposed emitter layer. An emitter metal layer is prepared in the fifth photoresist, and the fifth photoresist is removed to obtain the emitter. The emitter is located on the upper surface of the exposed emitter layer. A third passivation layer is deposited on the upper surface of the emitter and the upper surface of the second passivation layer. An intermetallic dielectric layer is prepared on the upper surface of the third passivation layer, and a fourth passivation layer is prepared on the upper surface of the intermetallic dielectric layer to obtain a heterojunction bipolar transistor device.