Semiconductor device and method of manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate and a capacitor. The substrate includes a memory array region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is located on the substrate. The second electrode includes a first conductor layer and a metal layer. The first conductor layer is located on the first electrode. The metal layer is located on the first conductor layer. The metal layer exposes a portion of the first conductor layer. The insulating layer is located between the first electrode and the second electrode. The above semiconductor device can improve the electrical performance of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a capacitor and a method for manufacturing the same. Background Art

[0002] Currently, in the process of semiconductor devices, hydrogen sintering treatment is performed to reduce dangling bonds and improve the electrical performance of semiconductor devices. In some semiconductor devices (such as dynamic random access memory (DRAM)), the upper electrode of the capacitor includes a boron-doped silicon germanium layer (B-doped SiGe layer) and a tungsten layer, and the tungsten layer can also be used as an etch stop layer during the formation of contact windows. However, during the hydrogen sintering treatment, the tungsten layer forms a strong barrier for hydrogen to penetrate into the silicon substrate, which hinders the progress of the hydrogen sintering treatment and reduces the electrical performance of the semiconductor device.

[0003] The current solution is to omit the tungsten layer in the upper electrode so that the hydrogen sintering treatment can proceed smoothly. In this way, since there is no tungsten layer as an etch stop layer during the formation of contact windows, the thickness of the boron-doped silicon germanium layer must be increased. However, due to the poor uniformity of the thicker boron-doped silicon germanium layer between different memory array regions, the electrical performance of the semiconductor device is reduced. In addition, if the tungsten layer in the upper electrode is omitted, the resistance between the contact window and the upper electrode will increase, and the non-uniformity during the etching of contact holes will increase, reducing the electrical performance of the semiconductor device. Summary of the Invention

[0004] The present invention provides a semiconductor device and a method for manufacturing the same, which can improve the electrical performance of the semiconductor device.

[0005] The present invention provides a semiconductor device, including a substrate and a capacitor. The substrate includes a memory array region. The capacitor is located in the memory array region. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is located on the substrate. The second electrode includes a first conductor layer and a metal layer. The first conductor layer is located on the first electrode. The metal layer is located on the first conductor layer. The metal layer exposes a part of the first conductor layer. The insulating layer is located between the first electrode and the second electrode.

[0006] The present invention provides a method for manufacturing a semiconductor device, comprising the following steps. Provide a substrate. The substrate includes a memory array region. Form a capacitor in the memory array region. The method for forming the capacitor includes the following steps. Form a first electrode on the substrate in the memory array region. Form an insulating layer on the first electrode. Form a second electrode on the insulating layer. The method for forming the second electrode includes the following steps. Form a first conductor layer on the insulating layer. Form a metal layer on the first conductor layer. The metal layer exposes a part of the first conductor layer.

[0007] Based on the above, in the semiconductor device and the method for manufacturing the same according to the present invention, since the metal layer exposes the first conductor layer, that is, the metal layer does not completely cover the first conductor layer, the subsequent hydrogen sintering process can be smoothly carried out to improve the electrical performance of the semiconductor device. In addition, since the metal layer can be used as an etch stop layer in the subsequent process of forming a contact window, there is no need to increase the thickness of the first conductor layer. In this way, the first conductor layer can have better uniformity between different memory array regions, and thus the electrical performance of the semiconductor device can be effectively improved. In addition, the subsequently formed contact window can be electrically connected to the metal layer in the second electrode, thereby reducing the resistance value between the contact window and the second electrode, and further improving the electrical performance of the semiconductor device.

[0008] In order to make the above features and advantages of the present invention more obvious and understandable, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0009] Figure 1 A perspective view of a semiconductor device according to an embodiment of the present invention;

[0010] Figures 2A to 2G Along Figure 1 A cross-sectional view of the manufacturing process of the semiconductor device along the I-I' cross-sectional line in

[0011] Figure 3A For Figure 2G A top view of the metal layer, the contact window and the conductor layer in

[0012] Figures 3B to 3G A top view of the metal layer, the contact window and the conductor layer according to other embodiments of the present invention;

[0013] Figure 4 A perspective view of a semiconductor device according to another embodiment of the present invention;

[0014] Figures 5A to 5H Along Figure 4 A cross-sectional view of the manufacturing process of the semiconductor device along the II-II' cross-sectional line in

[0015] Figure 6 A perspective view of a semiconductor device according to another embodiment of the present invention;

[0016] Figures 7A to 7E A cross-sectional view of the manufacturing process of a semiconductor device along the III-II' cross-sectional line in Figure 6 .

[0017] Explanation of the reference numerals in the figure:

[0018] 10, 20, 30: Semiconductor devices

[0019] 100: Substrate

[0020] 102: Interconnection structure

[0021] 104, 126, 210, 314: Electrodes

[0022] 106, 108, 118, 130, 200, 202, 214, 306, 318: Dielectric layers

[0023] 110: Insulating material layer

[0024] 110a: Insulating layer

[0025] 112, 114: Conductor material layers

[0026] 112a, 114a: Conductor layers

[0027] 116, 116a, 208, 304, 304a: Metal material layers

[0028] 116b, 208a, 304b: Metal layers

[0029] 120, 122, 204, 300, 308, 310: Patterened photoresist layers

[0030] 124, 132, 134, 216, 218, 230, 312, 320, 322: Openings

[0031] 128, 212, 316: Capacitors

[0032] 130, 200, 202, 306, 318: Dielectric layers

[0033] 136, 140, 220, 224, 324, 328: Barrier layers

[0034] 138, 142, 222, 226, 326, 330: Contact windows

[0035] 144, 228, 332: Hydrogen sintering treatment

[0036] 206, 302: Groove

[0037] R1: Memory array region

[0038] R2: Peripheral circuit region Detailed implementation manner

[0039] Figure 1 FIG. is a perspective view of a semiconductor device according to an embodiment of the present invention. Figures 2A to 2G is along Figure 1 The cross-sectional view of the manufacturing process of the semiconductor device along the I-I' cross-sectional line in. In Figure 1 Some components in are omitted Figures 2A to 2G in to clearly show Figure 1 The configuration relationship between the components in.

[0040] Please refer to Figure 2A , a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. The substrate 100 may include a memory array region R1 and a peripheral circuit region R2. In addition, according to the type of the semiconductor device, corresponding components may be provided on the substrate 100. In this embodiment, the semiconductor device is taken as an example of a dynamic random access memory (DRAM). In this case, corresponding transistors (not shown) may be provided on the substrate 100 in the memory array region R1, and corresponding active devices (such as, sense amplifiers) (not shown) and an interconnect structure 102 electrically connected to the active devices may be provided on the substrate 100 in the peripheral circuit region R2. In some embodiments, an etch stop layer (not shown) may be provided on the interconnect structure 102. In addition, required dielectric layers (not shown) and other interconnect structures (not shown) etc. may also be provided on the substrate 100, and required components (such as, isolation structures or doped regions etc.) may also be provided in the substrate 100, and their descriptions are omitted here.

[0041] Next, an electrode 104 is formed on the substrate 100 of the memory array region R1. The electrode 104 can be electrically connected to the corresponding transistor on the substrate 100. The material of the electrode 104 is, for example, titanium, titanium nitride, or a combination thereof. In some embodiments, after the electrode 104 is formed, dielectric layers 106 and 108 are left. The materials of the dielectric layers 106 and 108 are, for example, silicon nitride. Then, an insulating material layer 110 can be conformally formed on the electrode 104. The material of the insulating material layer 110 can be a dielectric material, such as a high-k material. Next, a conductor material layer 112 can be conformally formed on the insulating material layer 110. The material of the conductor material layer 112 is, for example, titanium, titanium nitride, or a combination thereof. After that, a conductor material layer 114 can be formed on the conductor material layer 112. The material of the conductor material layer 114 is, for example, a doped semiconductor material, such as a boron-doped silicon germanium layer (BSiGe) or doped polysilicon.

[0042] Please refer to Figure 2B , a metal material layer 116 can be directly formed on the conductor material layer 114. The material of the metal material layer 116 is, for example, a metal such as tungsten. Next, a dielectric layer 118 can be formed on the metal material layer 116. The material of the dielectric layer 118 is, for example, silicon oxide, such as tetraethyl orthosilicate (TEOS) silicon oxide. Then, a patterned photoresist layer 120 can be formed on the dielectric layer 118. The patterned photoresist layer 120 can expose a part of the dielectric layer 118 located in the peripheral circuit region R2.

[0043] Please refer to Figure 2C , the patterned photoresist layer 120 can be used as a mask to remove a part of the dielectric layer 118, a part of the metal material layer 116, a part of the conductor material layer 114, a part of the conductor material layer 112, and a part of the insulating material layer 110 located in the peripheral circuit region R2, so as to form an insulating layer 110a on the electrode 104, a conductor layer 112a on the insulating layer 110a, a conductor layer 114a on the conductor layer 112a, and a metal material layer 116a on the conductor layer 114a. Next, the patterned photoresist layer 120 is removed.

[0044] Please refer to Figure 2D , a patterned photoresist layer 122 can be formed. Next, the patterned photoresist layer 122 can be used as a mask to remove a part of the dielectric layer 118 and a part of the metal material layer 116a. Thus, a patterning process can be performed on the metal material layer 116a to form a metal layer 116b that exposes a part of the conductor layer 114a. In this way, the metal layer 116b can be formed on the conductor layer 114a. For example, after the above process is performed, the metal layer 116b can have at least one opening 124, and the opening 124 exposes a part of the conductor layer 114a.

[0045] Through the above process, the electrode 126 can be formed on the insulating layer 110a, and the capacitor 128 can be formed in the memory array region R1. However, the manufacturing method of the capacitor 128 of the present invention is not limited thereto. The capacitor 128 can be a cylinder capacitor, but the present invention is not limited thereto. The electrode 126 can include a conductor layer 114a, a metal layer 116b, and a conductor layer 112a. The capacitor 128 can include an electrode 104, an electrode 126, and an insulating layer 110a.

[0046] Please refer to Figure 2E , the patterned photoresist layer 122 can be removed. Then, a dielectric layer 130 can be formed in the memory array region R1 and the peripheral circuit region R2, and the dielectric layer 130 can fill the opening 124. The dielectric layer 130 can have a flat upper surface. The material of the dielectric layer 130 is, for example, silicon oxide, such as tetraethoxysilane (TEOS) silicon oxide. The method for forming the dielectric layer 130 is, for example, depositing a dielectric material layer first, and then planarizing the dielectric material layer by an etching process and / or a chemical mechanical polishing process. However, the present invention is not limited thereto.

[0047] Please refer to Figure 2F , an opening 132 exposing the capacitor 128 can be formed in the dielectric layer 130 and the dielectric layer 118 in the memory array region R1, and an opening 134 exposing the interconnect structure 102 can be formed in the dielectric layer 130 in the peripheral circuit region R2. For example, the opening 132 can expose the metal layer 116b in the capacitor 128. The method for forming the opening 132 and the opening 134 is, for example, patterning the dielectric layer 130 and the dielectric layer 118 by a lithography process and an etching process. In some embodiments, a patterned hard mask layer (not shown) can also be used as a mask for forming the opening 132 and the opening 134. In the etching process for forming the opening 132 and the opening 134, since the etching rate of the etching process for the metal layer 116b is much smaller than the etching rate for the dielectric layer 130, the opening 132 and the opening 134 can be sequentially formed by the etching process, and the etching process can smoothly stop on the metal layer 116b exposed by the opening 132 and the interconnect structure 102 exposed by the opening 134. In addition, the interconnect structure 102 and the metal layer 116b can be of the same material. Additionally, in the etching process for forming the opening 132 and the opening 134, part of the interconnect structure 102 and part of the metal layer 116b may be removed.

[0048] Please refer to Figure 2G, a barrier layer 136 and a contact window 138 electrically connected to the metal layer 116b can be formed in the opening 132, and a barrier layer 140 and a contact window 142 electrically connected to the interconnect structure 102 can be formed in the opening 134. The materials of the barrier layer 136 and the barrier layer 140 are, for example, titanium, titanium nitride, or a combination thereof. The materials of the contact window 138 and the contact window 142 are, for example, tungsten. In some other embodiments, the barrier layer 136 and the barrier layer 140 can be omitted.

[0049] Next, a hydrogen sintering process 144 can be performed, whereby the dangling bonds on the substrate 100 can be reduced, and thus the electrical performance of the semiconductor device can be improved. In some embodiments, the hydrogen sintering process 144 can be performed after the back-end-of-line (BEOL) process.

[0050] Hereinafter, Figure 1 and Figure 2G will be used to illustrate the semiconductor device 10 of the above embodiments. In addition, although the formation method of the semiconductor device 10 is illustrated by taking the above method as an example, the present invention is not limited thereto.

[0051] Please refer to Figure 1 and Figure 2G , the semiconductor device 10 includes a substrate 100 and a capacitor 128. The substrate 100 may include a memory array region R1 and a peripheral circuit region R2. An interconnect structure 102 may be provided in the peripheral circuit region R2. The capacitor 128 is located in the memory array region R1 and includes an electrode 104, an electrode 126, and an insulating layer 110a. The electrode 104 is located on the substrate 100. The electrode 126 includes a conductor layer 114a and a metal layer 116b. The conductor layer 114a is located on the electrode 104. The metal layer 116b is located on the conductor layer 114a. The metal layer 116b and the conductor layer 114a may be in direct contact. The metal layer 116b exposes a part of the conductor layer 114a. For example, the metal layer 116b may expose a part of the top surface of the conductor layer 114a. In addition, the metal layer 116b may be located on the top surface and the side surface of the conductor layer 114a. The insulating layer 110a is located between the electrode 104 and the electrode 126. In addition, the electrode 126 may further include a conductor layer 112a. The conductor layer 112a is located between the conductor layer 114a and the insulating layer 110a.

[0052] In addition, the semiconductor element 10 may further include at least one of a dielectric layer 118, a dielectric layer 130, a barrier layer 136, a contact window 138, a barrier layer 140, and a contact window 142. The dielectric layer 118 is located on the metal layer 116b. The dielectric layer 130 covers the capacitor 128 and the interconnect structure 102. The barrier layer 136 and the contact window 138 are located in the memory array region R1 and are electrically connected to the metal layer 116b. The barrier layer 136 may be located in the opening 132, and the contact window 138 may be located on the barrier layer 136 in the opening 132. The barrier layer 140 and the contact window 142 are located in the peripheral circuit region R2 and are electrically connected to the interconnect structure 102. The barrier layer 140 may be located in the opening 134, and the contact window 142 may be located on the barrier layer 140 in the opening 134. The top view shapes of the contact window 138 and the contact window 142 may be polygonal (e.g., rectangular), elliptical, circular, or a combination thereof.

[0053] Figure 3A is Figure 2G a top view of the metal layer, the contact window, and the conductor layer in Figures 3B to 3G is a top view of the metal layer, the contact window, and the conductor layer according to some other embodiments of the present invention.

[0054] Please refer to Figures 3A to 3G , where the metal layer 116b exposes a part of the conductor layer 114a. The metal layer 116b may have at least one opening 124, and the opening 124 exposes a part of the conductor layer 114a. The shape of the opening 124 may be rectangular ( Figure 3A , Figure 3D and Figure 3E ), elliptical ( Figure 3B ), circular ( Figure 3C ), or a combination thereof, but the present invention is not limited thereto. As long as the metal layer 116b exposes a part of the conductor layer 114a and the contact window 138 can be located directly above the metal layer 116b, it falls within the scope of the present invention.

[0055] Figure 4 is a perspective view of a semiconductor element according to another embodiment of the present invention. Figures 5A to 5H is a cross-sectional manufacturing flow diagram of the semiconductor element along the II-II' cross-sectional line in Figure 4 . Some components in Figure 4 are omitted to clearly show the configuration relationship between the components in Figures 5A to 5H . Figure 4 is a cross-sectional manufacturing flow diagram following the steps in Figures 5A to 5H continuing Figure 2A .

[0056] Please refer to Figure 5A, a dielectric layer 200 can be formed on the conductor material layer 114. The dielectric layer 200 can expose a part of the conductor material layer 114 and can serve as a hard mask layer. The material of the dielectric layer 200 is, for example, silicon oxide, such as tetraethyl orthosilicate (TEOS) silicon oxide.

[0057] Please refer to Figure 5B , the dielectric layer 200 can be used as a mask to remove a part of the conductor material layer 114, a part of the conductor material layer 112, and a part of the insulating material layer 110 in the peripheral circuit region R2, so as to form an insulating layer 110a on the electrode 104, form a conductor layer 112a on the insulating layer 110a, and form a conductor layer 114a on the conductor layer 112a.

[0058] Please refer to Figure 5C , a dielectric layer 202 covering the dielectric layer 200 and the interconnect structure 102 can be formed. The material of the dielectric layer 202 is, for example, silicon oxide, such as tetraethyl orthosilicate (TEOS) silicon oxide.

[0059] Please refer to Figure 5D , a part of the dielectric layer 202 and a part of the dielectric layer 200 can be removed to expose the conductor layer 114a. The method for removing the part of the dielectric layer 202 and the part of the dielectric layer 200 is, for example, planarization by an etching process and / or a chemical mechanical polishing process, but the present invention is not limited thereto.

[0060] Please refer to Figure 5E , a patterned photoresist layer 204 can be formed. Then, the patterned photoresist layer 204 can be used as a mask to remove a part of the conductor layer 114a to form a groove 206 in the conductor layer 114a.

[0061] Please refer to Figure 5F , the patterned photoresist layer 204 can be removed. Then, a metal material layer 208 filling the groove 206 can be directly formed on the conductor layer 114a. The material of the metal material layer 208 is, for example, a metal such as tungsten.

[0062] Please refer to Figure 5G , the metal material layer 208 located outside the groove 206 is removed to form a metal layer 208a in the groove 206, and the metal layer 208a exposes a part of the conductor layer 114a. In this way, a metal layer 208a can be formed on the conductor layer 114a. The method for removing the metal material layer 208 located outside the groove 206 is, for example, a re-etching method, a chemical mechanical polishing method, or a combination thereof.

[0063] Through the above process, the electrode 210 can be formed on the insulating layer 110a, and the capacitor 212 can be formed in the memory array region R1. However, the manufacturing method of the capacitor 212 of the present invention is not limited thereto. The electrode 210 may include a conductor layer 114a, a metal layer 208a, and a conductor layer 112a. The capacitor 212 may include an electrode 104, an electrode 210, and an insulating layer 110a. The capacitor 212 may be a columnar capacitor, but the present invention is not limited thereto.

[0064] Please refer to Figure 5H , a dielectric layer 214 can be formed in the memory array region R1 and the peripheral circuit region R2. The material of the dielectric layer 214 is, for example, silicon oxide. Then, an opening 216 exposing the capacitor 212 can be formed in the dielectric layer 214 of the memory array region R1, and an opening 218 exposing the internal wiring structure 102 can be formed in the dielectric layer 214 and the dielectric layer 202 of the peripheral circuit region R2. For example, the opening 216 may expose the metal layer 208a in the capacitor 212. Then, a barrier layer 220 and a contact window 222 electrically connected to the metal layer 208a are formed in the opening 216, and a barrier layer 224 and a contact window 226 electrically connected to the internal wiring structure 102 are formed in the opening 218. The formation methods of the opening 216, the opening 218, the barrier layer 220, the contact window 222, the barrier layer 224, and the contact window 226 can refer to Figure 2F and Figure 2G the formation methods of the opening 132, the opening 134, the barrier layer 136, the contact window 138, the barrier layer 140, and the contact window 142 in, which will not be described herein.

[0065] Next, a hydrogen sintering process 228 can be performed, thereby reducing the dangling bonds on the substrate 100, and further improving the electrical performance of the semiconductor device. In some embodiments, the hydrogen sintering process 228 can be performed after the back-end-of-line (BEOL) process.

[0066] Hereinafter, the semiconductor device 20 of the above embodiment will be described through Figure 4 and Figure 5H . In addition, although the formation method of the semiconductor device 20 is described by taking the above method as an example, the present invention is not limited thereto.

[0067] Please refer to Figure 4 and Figure 5H, the semiconductor device 20 includes a substrate 100 and a capacitor 212. The substrate 100 may include a memory array region R1 and a peripheral circuit region R2. An interconnection structure 102 may be provided in the peripheral circuit region R2. The capacitor 212 is located in the memory array region R1 and includes an electrode 104, an electrode 210, and an insulating layer 110a. The electrode 104 is located on the substrate 100. The electrode 210 includes a conductor layer 114a and a metal layer 208a. The conductor layer 114a is located on the electrode 104. The metal layer 208a is located on the conductor layer 114a and may be located in a groove 206. The metal layer 208a and the conductor layer 114a may be in direct contact. The metal layer 208a exposes a portion of the conductor layer 114a. For example, the metal layer 208a may expose a portion of the top surface of the conductor layer 114a. The insulating layer 110a is located between the electrode 104 and the electrode 210. In addition, the electrode 210 may further include a conductor layer 112a. The conductor layer 112a is located between the conductor layer 114a and the insulating layer 110a.

[0068] In addition, the semiconductor device 20 may further include at least one of a dielectric layer 200, a dielectric layer 202, a dielectric layer 214, a barrier layer 220, a contact window 222, a barrier layer 224, and a contact window 226. The dielectric layer 200 is located on the sidewalls of the capacitor 212. The dielectric layer 202 covers the interconnection structure 102. The dielectric layer 214 covers the capacitor 212 and the dielectric layer 202. The barrier layer 220 and the contact window 222 are located in the memory array region R1 and are electrically connected to the metal layer 208a. The barrier layer 220 may be located in an opening 216, and the contact window 222 may be located on the barrier layer 220 in the opening 216. The barrier layer 224 and the contact window 226 are located in the peripheral circuit region R2 and are electrically connected to the interconnection structure 102. The barrier layer 224 may be located in an opening 218, and the contact window 226 may be located on the barrier layer 224 in the opening 218.

[0069] In addition, the metal layer 208a may have at least one opening 230, and the opening 230 exposes a portion of the conductor layer 114a. The number of the openings 230 may be adjusted according to requirements and is not limited to Figure 5H the number in. The shapes and arrangements of the metal layer 208a and the opening 230 may refer to Figures 3A to 3G the shapes and arrangements of the metal layer 116b and the opening 124 in, and will not be described herein again.

[0070] Figure 6 is a perspective view of a semiconductor device according to another embodiment of the present invention. Figures 7A to 7E is a cross-sectional manufacturing flow diagram of the semiconductor device along the III-II' cross-sectional line in Figure 6 . Some components in Figure 6 are omitted Figures 7A to 7E to clearly show Figure 6The configuration relationships among the components. Figures 7A to 7E For continuation Figure 2A A cross-sectional view of the manufacturing process after the steps of

[0071] Please refer to Figure 7A , a patterned photoresist layer 300 can be formed on the conductor material layer 114. Then, using the patterned photoresist layer 300 as a mask, part of the conductor material layer 114 can be removed, and a groove 302 can be formed in the conductor material layer 114.

[0072] Please refer to Figure 7B , the patterned photoresist layer 300 can be removed. Then, a metal material layer 304 filling the groove 302 can be directly formed on the conductor material layer 114. The material of the metal material layer 304 is, for example, a metal such as tungsten. Then, a dielectric layer 306 can be formed on the metal material layer 304. The material of the dielectric layer 306 is, for example, silicon oxide, such as tetraethoxysilane (TEOS) silicon oxide. Next, a patterned photoresist layer 308 can be formed on the dielectric layer 306. The patterned photoresist layer 308 exposes part of the dielectric layer 306.

[0073] Please refer to Figure 7C , using the patterned photoresist layer 308 as a mask, a patterning process can be performed on the dielectric layer 306, the metal material layer 304, the conductor material layer 114, the conductor material layer 112, and the insulating material layer 110 to remove part of the dielectric layer 306, part of the metal material layer 304, part of the conductor material layer 114, part of the conductor material layer 112, and part of the insulating material layer 110 located in the peripheral circuit region R2, and an insulating layer 110a can be formed on the electrode 104, a conductor layer 112a can be formed on the insulating layer 110a, a conductor layer 114a can be formed on the conductor layer 112a, and a metal material layer 304a can be formed on the conductor layer 114a.

[0074] Please refer to Figure 7D , the patterned photoresist layer 308 can be removed. Then, a patterned photoresist layer 310 can be formed. Then, using the patterned photoresist layer 310 as a mask, part of the dielectric layer 306 and part of the metal material layer 304a can be removed. Thus, a patterning process can be performed on the metal material layer 304a to form a metal layer 304b exposing part of the conductor layer 114a. In this way, the metal layer 304b can be formed on the conductor layer 114a. For example, after performing the above process, the metal layer 304b can have at least one opening 312, and the opening 312 exposes part of the conductor layer 114a.

[0075] Through the above process, the electrode 314 can be formed on the insulating layer 110a, and the capacitor 316 can be formed in the memory array region R1. However, the manufacturing method of the capacitor 316 of the present invention is not limited thereto. The electrode 314 includes a conductor layer 114a, a metal layer 304b, and a conductor layer 112a. The capacitor 316 includes an electrode 104, an electrode 314, and an insulating layer 110a. The capacitor 316 can be a columnar capacitor, but the present invention is not limited thereto.

[0076] Please refer to Figure 7E , the patterned photoresist layer 310 can be removed. Then, a dielectric layer 318 can be formed in the memory array region R1 and the peripheral circuit region R2, and the dielectric layer 318 can fill the opening 312. Then, an opening 320 exposing the capacitor 316 can be formed in the dielectric layer 318 in the memory array region R1 and the dielectric layer 306, and an opening 322 exposing the interconnect structure 102 can be formed in the dielectric layer 318 in the peripheral circuit region R2. For example, the opening 320 can expose the metal layer 304b in the capacitor 316. Next, a barrier layer 324 and a contact window 326 electrically connected to the metal layer 304b can be formed in the opening 320, and a barrier layer 328 and a contact window 330 electrically connected to the interconnect structure 102 can be formed in the opening 322. The formation methods of the dielectric layer 318, the opening 320, the opening 322, the barrier layer 324, the contact window 326, the barrier layer 328, and the contact window 330 can refer to Figures 2E to 2G the formation methods of the dielectric layer 130, the opening 132, the opening 134, the barrier layer 136, the contact window 138, the barrier layer 140, and the contact window 142 in

[0077] Next, a hydrogen sintering process 332 can be performed, thereby reducing the dangling bonds on the substrate 100 and further improving the electrical performance of the semiconductor device. In some embodiments, the hydrogen sintering process 332 can be performed after the back-end-of-line (BEOL) process.

[0078] Hereinafter, through Figure 6 and Figure 7E the semiconductor device 30 of the above embodiment will be described. In addition, although the formation method of the semiconductor device 30 is described by taking the above method as an example, the present invention is not limited thereto.

[0079] Please refer to Figure 6 and Figure 7E, the semiconductor element 30 includes a substrate 100 and a capacitor 316. The substrate 100 may include a memory array region R1 and a peripheral circuit region R2. An interconnect structure 102 may be provided in the peripheral circuit region R2. The capacitor 316 is located in the memory array region R1 and includes an electrode 104, an electrode 314, and an insulating layer 110a. The electrode 104 is located on the substrate 100. The electrode 314 includes a conductor layer 114a and a metal layer 304b. The conductor layer 114a is located on the electrode 104. The metal layer 304b is located on the conductor layer 114a. The metal layer 304b and the conductor layer 114a may be in direct contact. The metal layer 304b exposes a portion of the conductor layer 114a. For example, the metal layer 304b may expose a portion of the top surface of the conductor layer 114a. In addition, a portion of the metal layer 304b may be located in the conductor layer 114a. The metal layer 304b may be located on the top surface and the side surface of the conductor layer 114a. The insulating layer 110a is located between the electrode 104 and the electrode 314. In addition, the electrode 314 may further include a conductor layer 112a. The conductor layer 112a is located between the conductor layer 114a and the insulating layer 110a.

[0080] In addition, the semiconductor element 30 may further include at least one of a dielectric layer 306, a dielectric layer 318, a barrier layer 324, a contact window 326, a barrier layer 328, and a contact window 330. The dielectric layer 306 is located on the metal layer 304b. The dielectric layer 318 covers the capacitor 316 and the interconnect structure 102. The barrier layer 324 and the contact window 326 are located in the memory array region R1 and are electrically connected to the metal layer 304b. The barrier layer 324 may be located in the opening 320, and the contact window 326 may be located on the barrier layer 324 in the opening 320. The barrier layer 328 and the contact window 330 are located in the peripheral circuit region R2 and are electrically connected to the interconnect structure 102. The barrier layer 328 may be located in the opening 322, and the contact window 330 may be located on the barrier layer 328 in the opening 322.

[0081] In addition, the metal layer 304b may have at least one opening 312, and the opening 312 exposes a portion of the conductor layer 114a. The number of the openings 312 can be adjusted according to requirements and is not limited to Figure 7E the number in Figures 3A to 3G . The shapes and arrangements of the metal layer 304b and the opening 312 may refer to the shapes and arrangements of the metal layer 116b and the opening 124 in

[0082] Based on the above embodiments, it can be seen that in the semiconductor device (10, 20, or 30) and its manufacturing method, since the metal layer (116b, 208a, or 304b) exposes the conductive layer (114a), that is, the metal layer (116b, 208a, or 304b) does not completely cover the conductive layer (114a), the subsequent hydrogen sintering process (144, 228, or 332) can be smoothly performed to improve the electrical performance of the semiconductor device (10, 20, or 30). In addition, since the metal layer (116b, 208a, or 304b) can serve as an etch stop layer in the subsequent process of forming the contact window (138, 222, or 326), it is not necessary to increase the thickness of the conductive layer (114a). As a result, the conductive layer (114a) can have better uniformity between different memory array regions (R1), thereby effectively improving the electrical performance of the semiconductor device (10, 20, or 30). In addition, the subsequently formed contact window (138, 222 or 326) can be electrically connected to the metal layer (116b, 208a or 304b) in the electrode (126, 210 or 314), thereby reducing the resistance between the contact window (138, 222 or 326) and the electrode (126, 210 or 314), thereby improving the electrical performance of the semiconductor element (10, 20 or 30).

[0083] Although the present invention has been disclosed above by way of embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A semiconductor device, characterized in that, Comprising: a substrate, including a memory array region; and a capacitor, located in the memory array region, and comprising: a first electrode, located on the substrate; a second electrode, comprising: a first conductor layer, located on the first electrode; and a metal layer, located on the first conductor layer, wherein the metal layer exposes a part of the first conductor layer; and an insulating layer, located between the first electrode and the second electrode, wherein the substrate further includes a peripheral circuit region having an interconnection structure therein, and the semiconductor device further comprises: a first contact window, located in the memory array region and electrically connected to the metal layer; and a second contact window, located in the peripheral circuit region and electrically connected to the interconnection structure.

2. The semiconductor device according to claim 1, wherein, The material of the first conductor layer includes a doped semiconductor material.

3. The semiconductor element according to claim 1, wherein The metal layer is in direct contact with the first conductor layer.

4. The semiconductor device according to claim 1, wherein, The metal layer has at least one opening, and the at least one opening exposes a part of the first conductor layer.

5. The semiconductor device according to claim 4, wherein The shape of the at least one opening includes a polygon, an ellipse, a circle, or a combination thereof.

6. The semiconductor element according to claim 1, wherein The first conductor layer has a groove, and the metal layer is located in the groove.

7. The semiconductor device according to claim 1, wherein The metal layer is located on the top surface and the side surface of the first conductor layer.

8. The semiconductor device according to claim 1, wherein The second electrode further comprises: a second conductor layer, located between the first conductor layer and the insulating layer.

9. A method for manufacturing a semiconductor device, characterized in that, Comprising: providing a substrate, wherein the substrate includes a memory array region; and forming a capacitor in the memory array region, wherein the method for forming the capacitor includes: forming a first electrode on the substrate in the memory array region; forming an insulating layer on the first electrode; and forming a second electrode on the insulating layer, wherein the method for forming the second electrode includes: forming a first conductor layer on the insulating layer; and forming a metal layer on the first conductor layer, wherein the metal layer exposes a part of the first conductor layer, wherein the substrate further includes a peripheral circuit region having an interconnection structure therein, and the method for manufacturing the semiconductor device further includes: forming a dielectric layer in the memory array region and the peripheral circuit region; forming a first opening exposing the capacitor in the dielectric layer of the memory array region and forming a second opening exposing the interconnection structure in the dielectric layer of the peripheral circuit region; and forming a first contact window electrically connected to the metal layer in the first opening and forming a second contact window electrically connected to the interconnection structure in the second opening.

10. The manufacturing method of the semiconductor device according to claim 9, characterized in that, The method for forming the metal layer includes: forming a metal material layer on the first conductor layer; and performing a patterning process on the metal material layer to form the metal layer exposing a part of the first conductor layer, wherein the metal layer has at least one opening, and the at least one opening exposes a part of the first conductor layer.

11. The manufacturing method of the semiconductor device according to claim 9, characterized in that, The method for forming the metal layer includes: forming a groove in the first conductor layer; forming a metal material layer filling the groove on the first conductor layer; and removing the metal material layer located outside the groove to form the metal layer in the groove.

12. The manufacturing method of the semiconductor element according to claim 9, characterized in that, The forming method of the first conductor layer and the metal layer includes: Forming a conductor material layer; Forming a groove in the conductor material layer; Forming a metal material layer on the conductor material layer to fill the groove; Performing a first patterning process on the conductor material layer to form the first conductor layer; and Performing a second patterning process on the metal material layer to form the metal layer that exposes part of the first conductor layer.

13. The manufacturing method of the semiconductor device according to claim 12, characterized in that, The metal layer is located on the top surface and the side surface of the first conductor layer, and part of the metal layer is located in the first conductor layer.

14. The manufacturing method of the semiconductor device according to claim 9, characterized in that, It further includes: After forming the first contact window and the second contact window, performing a hydrogen sintering treatment.

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