Dead time processing method and device for converter and converter

Abstract

The application discloses a dead time processing method and device of a converter and the converter. The method comprises the following steps: obtaining a change slope of a secondary side current for the first time after a main switch tube of the converter is turned off; obtaining a zero-crossing point moment of an excitation inductance current of a primary side of the converter based on the change slope of the secondary side current; obtaining a time difference between the zero-crossing point moment and a turn-off moment of a clamping tube of the converter; and determining a dead time of the primary side of the converter based on the time difference, wherein the dead time is a time period from the turn-off moment of the clamping tube to a turn-on moment of the main switch tube of the converter. The application solves the technical problems of poor loop stability of the converter caused by sudden change of the dead time when the converter is converted from a DCM mode to a CCM mode and the main switch tube failing to be turned on when the voltage at a switching node is at a lowest point.

Description

Technical Field

[0001] This invention relates to the field of electronic circuits, and more specifically, to a method, apparatus, and converter for processing the dead time of a converter. Background Technology

[0002] In an active clamp flyback converter, the primary winding and the main switch are connected in series, while the primary winding and the clamping transistor are connected in parallel. The converter utilizes the clamping branch to recover leakage inductance energy in the power circuit and uses the reverse excitation of the magnetizing inductor to create conditions for the main switch to achieve ZVS (Zero Voltage Switch). When the clamping transistor is turned on, the voltage across the clamping capacitor connected in series with it is applied to the primary winding of the transformer. The magnetizing inductor carries a negative current. After the clamping transistor is turned off, the current in the magnetizing inductor cannot change abruptly; the negative current discharges the charge on the parasitic capacitance of the switching node. After the dead time, the voltage at the switching node discharges to zero. At this point, turning on the main switch achieves ZVS, eliminates turn-on losses and parasitic capacitance charging and discharging losses, and recovers leakage inductance energy. Therefore, the dead time and the negative current of the magnetizing inductor have a significant impact on whether the main switch can achieve ZVS. When the input voltage of the active clamp flyback converter decreases, in order to ensure the efficiency of the converter, the converter switches from DCM mode (discontinuous Conduction Mode) to CCM mode (continuous Conduction Mode).

[0003] In related technologies, to adapt to the converter mode change when the input voltage decreases, a larger dead time is set when the converter is in DCM mode and a smaller dead time is set in CCM mode. When the converter switches from DCM mode to CCM mode, the dead time jumps directly from the larger value to the smaller value. This will cause the following problems: On the one hand, the sudden change in dead time will lead to a sudden change in energy, resulting in poor converter loop stability under critical operating conditions; on the other hand, during the transition from DCM mode to CCM mode, there is still some negative current that is beneficial to achieving ZVS of the main switch. The sudden decrease in dead time will cause the main switch to turn on before the switching node voltage reaches its lowest point.

[0004] In summary, in related technologies, when a converter transitions from DCM mode to CCM mode, there are issues such as poor converter loop stability caused by sudden changes in dead time, and the main switch failing to turn on when the switching node voltage drops to its lowest point. Summary of the Invention

[0005] This invention provides a method, apparatus, and converter for handling dead time in a converter, to at least solve the technical problems in the related art, such as poor converter loop stability caused by sudden changes in dead time when the converter transitions from DCM mode to CCM mode, and the inability of the main switch to turn on when the switching node voltage drops to the lowest point.

[0006] According to one aspect of the present invention, a method for processing the dead time of a converter is provided, comprising: obtaining the slope of the first decrease in the secondary current after the main switch of the converter is turned off; obtaining the zero-crossing time of the magnetizing inductor current on the primary side of the converter based on the slope of the secondary current change, wherein the zero-crossing time is the time when the magnetizing inductor current decreases to zero after the main switch is turned off; obtaining the time difference between the zero-crossing time and the turn-off time of the clamping transistor of the converter; and determining the dead time of the primary side of the converter based on the time difference, wherein the dead time is the time period from the turn-off time of the clamping transistor to the turn-on time of the main switch of the converter.

[0007] As an optional embodiment, obtaining the slope of the first decrease in secondary current after the main switch of the converter is turned off includes: obtaining a first voltage threshold and a second voltage threshold; obtaining a first moment when the secondary voltage is the first voltage threshold and a second moment when the secondary voltage is the second voltage threshold after the main switch of the converter is turned off; and determining the slope of the first decrease in secondary current after the main switch of the converter is turned off based on the first voltage threshold and the second voltage threshold, as well as the first moment and the second moment.

[0008] As an optional embodiment, the zero-crossing time of the primary-side magnetizing inductor current of the converter is obtained based on the slope of the change of the secondary-side current, including: determining the transformation relationship between the secondary-side current and time based on the slope of the change; and determining the zero-crossing time corresponding to the primary-side magnetizing inductor current of the converter being zero based on the transformation relationship.

[0009] As an optional embodiment, determining the dead time of the primary side of the converter based on the time difference includes: converting the time difference into a voltage signal; determining a voltage divider signal of the voltage signal based on a predetermined ratio; and determining the dead time of the primary side of the converter based on the voltage divider signal.

[0010] As an optional embodiment, determining the dead time of the primary side of the converter based on the voltage divider signal includes: determining a first dead time based on the voltage divider signal; obtaining the difference between the first dead time and a predetermined dead time; determining the first dead time as the dead time of the primary side of the converter if the difference is greater than the predetermined difference; or determining the predetermined dead time as the dead time of the primary side of the converter if the difference is less than or equal to the predetermined difference.

[0011] As an optional embodiment, after determining the dead time of the primary side of the converter based on the time difference, the method further includes: feeding back the determined dead time to the primary side controller of the converter, so that the primary side controller can control the clamping transistor and the main switching transistor based on the dead time.

[0012] According to another aspect of the present invention, a dead-time processing device for a converter is also provided, comprising: a slope detection unit, configured to acquire the slope of the first decrease in secondary current after the main switch of the converter is turned off; a zero-crossing calculation unit, configured to acquire the zero-crossing time of the magnetizing inductor current on the primary side of the converter based on the slope of the secondary current change, wherein the zero-crossing time is the time when the magnetizing inductor current decreases to zero after the main switch is turned off; and a dead-time processing unit, configured to acquire the time difference between the zero-crossing time and the turn-off time of the clamping transistor of the converter, and to determine the dead time of the primary side of the converter based on the time difference, wherein the dead time is the time period from the turn-off time of the clamping transistor to the turn-on time of the main switch of the converter.

[0013] As an optional embodiment, the device further includes: a differential amplifier circuit, used to differentially amplify the voltage signal acquired from the secondary side after the main switch of the converter is turned off, to obtain a differentially amplified signal, and output the differentially amplified signal to the slope detection unit.

[0014] As an optional embodiment, the dead time processing unit includes: a voltage conversion and scaling unit for converting the time difference into a voltage signal and setting a predetermined scaling ratio; and a dead time adjustment unit for determining a voltage divider signal based on the predetermined scaling ratio and determining the dead time of the primary side of the converter based on the voltage divider signal.

[0015] According to another aspect of the present invention, a converter is also provided, including: a primary winding, a primary controller, a secondary winding and a secondary controller, a main switch, a clamping transistor, and a rectifier. The primary controller controls the output of the primary winding through the main switch and the clamping transistor. The secondary controller is connected to the secondary winding through the rectifier. The secondary controller includes a dead-time processing device for the converter as described above. The secondary controller is further configured to feed back the dead-time obtained by the dead-time processing device to the primary controller, so that the primary controller can control the clamping transistor and the main switch based on the dead-time.

[0016] In this embodiment of the invention, by obtaining the slope of the first decrease in the secondary current after the main switch of the converter is turned off, the zero-crossing time of the primary-side magnetizing inductor current of the converter is obtained based on the slope of the secondary current change. The time difference between the zero-crossing time and the turn-off time of the clamping transistor of the converter is obtained, and the dead time of the primary side of the converter is determined based on the time difference. The zero-crossing time of the secondary-side magnetizing current of the converter can be obtained based on the slope of the secondary current change, and the zero-crossing time of the primary-side magnetizing inductor current can be determined based on the zero-crossing time of the secondary-side magnetizing current. As the input voltage of the converter decreases, the zero-crossing time of the primary-side magnetizing inductor current gets closer and closer to the turn-off time of the clamping transistor. Therefore, as the input voltage of the converter decreases, the time difference between the zero-crossing time and the turn-off time of the clamping transistor also decreases, and the dead time determined based on this time difference also decreases. The dead time of the converter is determined based on the time difference between the zero point and the turn-off time of the clamping transistor of the converter. As the converter voltage decreases, the dead time will gradually decrease instead of abruptly. This solves the technical problems in related technologies, such as poor converter loop stability caused by abrupt changes in dead time when the converter transitions from DCM mode to CCM mode, and the technical problem that the main switching transistor cannot be turned on when the switching node voltage drops to the lowest point. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0018] Figure 1 This is a flowchart of an optional converter dead time processing method according to an embodiment of the present invention;

[0019] Figure 2 This is a framework diagram of an optional converter dead time processing device according to an embodiment of the present invention;

[0020] Figure 3 This is a topology diagram of an active clamp flyback converter in related technologies;

[0021] Figure 4 This is a timing diagram of key signals in an active clamp flyback converter in related technologies;

[0022] Figure 5 This is a framework diagram of another optional converter dead time processing device according to an embodiment of the present invention;

[0023] Figure 6 This is an optional timing diagram of key converter signals according to an embodiment of the present invention;

[0024] Figure 7This is a circuit diagram of an optional converter slope detection unit according to an embodiment of the present invention;

[0025] Figure 8 This is a circuit diagram of an optional converter zero-crossing calculation unit according to an embodiment of the present invention;

[0026] Figure 9 This is a circuit diagram of an optional converter voltage conversion and scaling unit according to an embodiment of the present invention.

[0027] Figure 10 This is a circuit diagram of an optional converter dead time processing unit according to an embodiment of the present invention. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] According to an embodiment of the present invention, a method embodiment for processing converter dead time is provided. It should be noted that, in some cases, the steps shown or described may be performed in a different order than that shown here.

[0031] Figure 1 This is a flowchart of an optional converter dead time processing method according to an embodiment of the present invention, such as... Figure 1 As shown, the method includes the following steps:

[0032] Step S101: Obtain the slope of the first decrease in secondary current after the main switch of the converter is turned off.

[0033] It's important to understand that after the main switch is turned off, the secondary current of the converter first increases and then decreases. After the clamping transistor is turned on, the secondary current increases again and then decreases after the clamping transistor is turned off. Therefore, the range during which the secondary current first decreases after the main switch is turned off refers to the range during which the secondary current decreases over time from the time the main switch is turned off to the time the clamping transistor is turned on.

[0034] Step S102: Based on the slope of the change in the secondary current, obtain the zero-crossing moment of the magnetizing inductor current on the primary side of the converter, wherein the zero-crossing moment is the moment when the magnetizing inductor current decreases to zero after the main switch is turned off.

[0035] It's important to understand that the secondary current changes linearly with time. The zero-crossing point of the secondary current can be determined by the slope of its change. This zero-crossing point is not the actual moment the secondary current decreases to zero, but rather the moment calculated from the slope of its change. The zero-crossing point of the secondary current corresponds to the zero-crossing point of the magnetizing inductor current; therefore, the zero-crossing point of the magnetizing inductor current can be determined based on the zero-crossing point of the secondary current.

[0036] Step S103: Obtain the time difference between the zero-crossing moment and the turn-off moment of the converter's clamping transistor.

[0037] Step S104: Determine the dead time of the primary side of the converter based on the time difference, wherein the dead time is the time interval from the turn-off time of the clamping transistor to the turn-on time of the main switch transistor of the converter.

[0038] In this optional embodiment, the slope of the first decrease in secondary current after the main switch of the converter is turned off is obtained. Based on the slope of the secondary current change, the zero-crossing time of the primary-side magnetizing inductor current of the converter is obtained. The time difference between the zero-crossing time and the turn-off time of the clamping transistor of the converter is obtained. The dead time of the primary side of the converter is determined based on the time difference. The zero-crossing time of the secondary-side magnetizing current can be obtained based on the slope of the secondary-side current change, and the zero-crossing time of the primary-side magnetizing inductor current can be determined based on the zero-crossing time of the secondary-side magnetizing current. As the input voltage of the converter decreases, the zero-crossing time of the primary-side magnetizing inductor current gets closer and closer to the turn-off time of the clamping transistor. Therefore, as the input voltage of the converter decreases, the time difference between the zero-crossing time and the turn-off time of the clamping transistor also decreases, and the dead time determined based on this time difference also decreases. The dead time of the converter is determined based on the time difference between the zero-point moment and the turn-off moment of the converter's clamping transistor. This ensures that the dead time decreases slowly as the converter voltage decreases, rather than abruptly. This solves the technical problems in related technologies, such as poor converter loop stability caused by abrupt dead time changes during the transition from DCM mode to CCM mode, and the inability of the main switch to turn on when the switching node voltage drops to its minimum. In other words, the method provided in this optional embodiment ensures a smooth change in dead time during the transition from discontinuous magnetizing inductor current mode (DCM) to continuous magnetizing inductor current mode (CCM), eliminating the impact on the stability of the converter control loop. Furthermore, the control of the dead time by this method allows the main switch to turn on at the minimum value of the switching node voltage when the converter is in the critical state between discontinuous magnetizing inductor current mode and continuous mode, improving converter efficiency.

[0039] As an optional embodiment, the method for obtaining the slope of the first decrease in secondary current after the main switch of the converter is turned off may include: obtaining a first voltage threshold and a second voltage threshold, and a first moment when the secondary voltage is the first voltage threshold and a second moment when the secondary voltage is the second voltage threshold after the main switch of the converter is turned off; and obtaining the slope of the first decrease in secondary current after the main switch of the converter is turned off based on the first voltage threshold and the second voltage threshold, as well as the first moment and the second moment.

[0040] It's important to understand that after the main switch is turned off, the secondary current of the converter first increases and then decreases. After the clamping transistor is turned on, the secondary current increases again and decreases after the clamping transistor is turned off. The slope of the first decrease in secondary current after the main switch is turned off is the slope of the decrease in secondary current over time when the main switch is off and the clamping transistor is not on. This slope is equal to the ratio of the difference between the first and second voltage thresholds to the difference between the first and second time points. Determining the slope based on the first and second thresholds, as well as the first and second time points, is a simple method with high accuracy.

[0041] As an optional embodiment, the method for obtaining the zero-crossing time of the primary-side magnetizing inductor current of the converter based on the slope of the change of the secondary-side current may include: determining the transformation relationship between the secondary-side current and time based on the slope of the change; and determining the zero-crossing time corresponding to when the primary-side magnetizing inductor current of the converter is zero based on the transformation relationship.

[0042] In this optional embodiment, the zero-crossing time of the secondary current can be obtained based on the transformation relationship between the secondary current and time. The zero-crossing time of the secondary current of the converter is the same as the zero-crossing time of the magnetizing inductor current on the primary side of the converter. Therefore, the zero-crossing time of the magnetizing inductor current on the primary side of the converter can be accurately obtained based on the zero-crossing time of the secondary current. It should be understood that the secondary current increases after the clamping transistor is turned on, and the clamping transistor turns on ahead of the zero-crossing time of the magnetizing inductor current. That is, the clamping transistor turns on ahead of the zero-crossing time of the secondary current. After the clamping transistor is turned on, the secondary current increases. Therefore, the secondary current does not actually decrease to zero. The zero-crossing time of the secondary current obtained based on the transformation relationship between the secondary current and time is not the time when the secondary current actually decreases to zero, but a calculated value obtained based on the transformation relationship between the secondary current and time.

[0043] As an optional embodiment, the method for determining the dead time of the primary side of the converter based on the time difference may include: converting the time difference into a voltage signal; determining a voltage divider signal based on a predetermined ratio; and determining the dead time of the primary side of the converter based on the voltage divider signal.

[0044] In this optional embodiment, the voltage signal converted from the time difference is divided by a predetermined ratio, the dead time is determined based on the divided voltage signal, and the turn-on of the main switch is controlled using the dead time obtained based on this method, so that the main switch can be turned on when the node voltage is about to reach the lowest point.

[0045] In one optional embodiment, a proportional value for the conversion voltage is reasonably set according to the relationship between the dead time and the time difference. This proportional value is used as a predetermined ratio to divide the voltage signal converted by the time difference, obtaining a divided voltage signal, and the dead time is determined based on this divided voltage signal. The dead time obtained by this method is more reasonable. By controlling the turn-on of the main switch according to this dead time, the main switch can be turned on when the node voltage is about to reach its lowest point.

[0046] As an optional embodiment, the method for determining the dead time of the primary side of the converter based on the voltage divider signal may include: determining a first dead time based on the voltage divider signal; obtaining the difference between the first dead time and a predetermined dead time; determining the first dead time as the dead time of the primary side of the converter if the difference is greater than the predetermined difference; or determining the predetermined dead time as the dead time of the primary side of the converter if the difference is less than or equal to the predetermined difference.

[0047] As an optional implementation, the method for determining the dead time of the primary side of the converter based on the voltage divider signal may include: determining a first dead time based on the voltage divider signal; if the first dead time is greater than a predetermined dead time threshold, determining the first dead time as the dead time of the primary side of the converter; or, if the difference is less than or equal to the predetermined dead time threshold, determining the predetermined dead time as the dead time of the primary side of the converter.

[0048] In this optional embodiment, the predetermined dead time is less than or equal to a predetermined dead time threshold. When the first dead time is less than or equal to the dead time threshold, it indicates that the first dead time is sufficiently small. In this case, using the predetermined dead time as the dead time of the primary side of the converter is equivalent to directly changing the dead time from the first dead time to the predetermined dead time when the first dead time is less than or equal to the predetermined dead time threshold. Because the difference between the two is small, this change is smooth and slow. Therefore, while improving processing efficiency, the stability of the converter loop is ensured, and the main switch is turned on when the switching node voltage reaches its lowest point.

[0049] In some alternative embodiments, after determining the dead time of the primary side of the converter based on the time difference, the determined dead time is fed back to the primary side controller of the converter, which then controls the clamping transistor and the main switch based on the dead time. By using a dead time that varies slowly with the converter input voltage to control the turn-on of the main switch, it is possible to enable the main switch to turn on when the switching node voltage is about to reach its lowest point.

[0050] Figure 2 This is a framework diagram of an optional converter dead-time processing device according to an embodiment of the present invention, with reference to... Figure 2As shown, the dead time processing device of the converter includes a slope detection unit 201, a zero-crossing calculation unit 202, and a dead time processing unit 203. These will be described below.

[0051] The slope detection unit 201 is used to acquire the slope of the first decrease in the secondary current after the main switch of the converter is turned off; the zero-crossing calculation unit 202, connected to the slope detection unit 201, is used to acquire the zero-crossing time of the magnetizing inductor current on the primary side of the converter based on the slope of the secondary current change, wherein the zero-crossing time is the moment when the magnetizing inductor current decreases to zero after the main switch is turned off; the dead time processing unit 203, connected to the zero-crossing calculation unit 202, is used to acquire the time difference between the zero-crossing time and the turn-off time of the clamping transistor of the converter, and to determine the dead time of the primary side of the converter based on the time difference, wherein the dead time is the time period from the turn-off time of the clamping transistor to the turn-on time of the main switch of the converter.

[0052] It should be noted that the slope detection unit 201 and the zero-crossing calculation unit 202 mentioned above correspond to steps S101 and S102 in the aforementioned embodiments, and the dead time processing unit 203 corresponds to steps S103 and S104 in the aforementioned embodiments.

[0053] As an optional embodiment, the device further includes: a differential amplifier circuit, used to differentially amplify the voltage signal acquired from the secondary side after the main switch of the converter is turned off, to obtain a differentially amplified signal, and output the differentially amplified signal to the slope detection unit.

[0054] As an optional embodiment, the dead time processing unit includes: a voltage conversion and scaling unit for converting the time difference into a voltage signal and setting a predetermined scaling ratio; and a dead time adjustment unit for determining a voltage divider signal based on the predetermined scaling ratio and determining the dead time of the primary side of the converter based on the voltage divider signal.

[0055] The present invention also provides a converter, comprising: a primary winding, a primary controller, a secondary winding and a secondary controller, a main switch, a clamping transistor, and a rectifier, wherein the primary controller controls the output of the primary winding through the main switch and the clamping transistor, the secondary controller is connected to the secondary winding through the rectifier, the secondary controller includes a dead-time processing device of the converter as described above, and the secondary controller is further used to feed back the dead time obtained by the dead-time processing device to the primary controller, so that the primary controller can control the clamping transistor and the main switch based on the dead time.

[0056] Based on the above embodiments and optional embodiments, an optional implementation method is provided, which is described in detail below.

[0057] In related technologies, the topology of an active clamp flyback converter is as follows: Figure 3 As shown. (Refer to...) Figure 3 The primary winding N of the converter P One end and leakage inductance L k One end is connected, and the other end is connected to the clamping tube M. A The source and main switch M P The drain and switching node parasitic capacitance C PAR Four points are connected at one end, clamp tube M A Drain and clamping capacitor C A One end is connected to the clamping capacitor C. A The other end and leakage inductance L k The other end is connected to the main switch transistor M. P The source is grounded through a resistor, and the parasitic capacitance C of the switching node... PAR The other end is grounded; clamping tube M A Gate and main switch M P Gate and main switch M P The source terminals are respectively connected to the input terminals of the primary-side controller. Figure 4 This is a timing diagram of key signals for an active clamp flyback converter. (Refer to...) Figure 4 As shown, clamping tube M A and main switch M P Alternating activation, the converter is in a complementary alternating mode. Figure 4 In the middle, G_M P The gate drive voltage waveform of the main switch transistor, G_M A For clamping tube M A Gate drive voltage waveform, DS_M P Main switch transistor M P The drain voltage waveform, i.e., the voltage waveform at the switching node, I LM For the magnetizing inductor L M Current waveform, I LK For leakage inductance L k Current waveform, T DAP For clamping tube M A Turn off to main switch M P Dead time of activation, T ON_A For the excitation current to cross zero to the clamping transistor M A Delay of shutdown, I PKP For the magnetizing inductor L M Forward current peak, I PKN For the magnetizing inductor L M Peak negative current.

[0058] The converter recovers energy from the leakage inductance in the power circuit using a clamping branch and utilizes the magnetizing inductance L M Reverse excitation creates conditions for ZVS of the main switching transistor. Clamping transistor MA The conduction of the clamping capacitor C A The voltage is applied to the primary winding N of the transformer. P Above, magnetizing inductor L M Possesses negative current; clamping transistor M A After being turned off, the magnetizing inductor L M The current cannot change abruptly; a negative current will cause the parasitic capacitance C of the switching node to change. PAR The charge on the transistor is discharged; after the dead time, the main switch M... P When the voltage at the switching node is discharged to zero, the main switch M is turned on. P This enables ZVS, eliminating turn-on losses and parasitic capacitance charging and discharging losses, and recovering leakage inductance energy.

[0059] Based on the working principle of the active clamp flyback converter described above, it can be concluded that the two key parameters for achieving ZVS of the main switch are the negative current of the magnetizing inductor and the dead time. Magnetizing inductor L M The negative current is generated by the clamping transistor M A The conduction time is determined, specifically N. PS *V OUT / L M *T ON_A , where N PS V is the turns ratio of the primary and secondary windings of the transformer. OUT This refers to the output voltage of the converter. Because converters come in various power ratings, and the operating conditions of the same converter change constantly with the input voltage and load, in order to achieve the desired output voltage for the main switching transistor M under various conditions... P ZVS often requires clamping tube M A The on-time and dead time are adaptively adjusted to optimize efficiency.

[0060] However, in higher power applications, under full load conditions, as the input voltage decreases, the system operating frequency is further reduced to ensure a certain negative current in the magnetizing inductor. At this time, the peak current of the magnetizing inductor (I0)... PKP -I PKN The main switch transistor M is relatively large. P Significant conduction losses, transformer winding losses, and core losses lead to a decrease in converter efficiency, which limits the converter's input voltage range. To improve efficiency at low input voltages, the converter can be configured to operate in CCM mode with decreasing magnetizing current as the input voltage decreases, and the energy of the leakage inductance can be utilized to achieve ZVS (Zero-Voltage Switching) of the main switching transistors as much as possible. Although the leakage inductance energy is insufficient to completely discharge the charge at the switching nodes, the peak value of the magnetizing inductor current is reduced due to the system operating frequency being limited to a fixed frequency. This reduces the conduction losses of the power transistors and transformer losses, thereby improving the overall efficiency of the converter.

[0061] As the input voltage decreases, the converter gradually transitions from DCM mode to CCM mode, and the negative current of the magnetizing inductor gradually decreases to zero. In DCM mode, the converter has a negative current, and during adaptive adjustment, the dead time is related to the resonant period of the magnetizing inductor and the parasitic capacitance of the switching node. In CCM mode, the converter does not have a negative current, and the dead time is related to the resonant period of the leakage inductance and the parasitic capacitance of the switching node.

[0062] In related technologies, a larger dead time is set in DCM mode and a smaller dead time is set in CCM mode. The input voltage level is then determined by detecting the bus voltage, and the dead time is switched accordingly. This dead time control method has two drawbacks: first, the abrupt change in dead time leads to a sudden change in energy, which can easily cause loop stability problems under critical operating conditions; second, during the transition from DCM to CCM, the magnetizing inductance L... M There is still some negative current, which is beneficial for achieving ZVS of the main switch. If the dead time remains unchanged, the main switch will be turned on only after the switching node voltage has fallen back. If the dead time suddenly decreases, the main switch will be turned on before the switching node voltage has dropped to its lowest point.

[0063] In view of this, this disclosure provides a converter dead time processing device. It obtains the slope of the first decrease in secondary current after the main switch of the converter is turned off. Based on the slope of the secondary current change, it obtains the zero-crossing moment of the primary side magnetizing inductor current of the converter. It then obtains the time difference between the zero-crossing moment and the turn-off moment of the converter's clamping transistor, and determines the primary side dead time of the converter based on this time difference. By determining the converter dead time based on the time difference between the zero-crossing moment and the turn-off moment of the converter's clamping transistor, the dead time decreases slowly rather than abruptly when the converter voltage decreases. This solves the technical problems in related technologies, such as poor converter loop stability caused by abrupt dead time changes when the converter transitions from DCM mode to CCM mode, and the inability of the main switch to turn on when the switching node voltage drops to its lowest point.

[0064] Figure 5 This is a framework diagram of another optional converter dead-time processing device according to an embodiment of the present invention. (Refer to...) Figure 5 As shown, the device includes a differential amplifier (equivalent to the aforementioned differential amplifier circuit), a slope detection unit, a zero-crossing calculation unit, a voltage conversion and proportional setting unit, and a dead-time adjustment unit. The device is implemented on the secondary side of the converter, and a synchronous rectifier diode is connected in series in the secondary winding of the converter.

[0065] The differential amplifier's positive and negative input terminals are connected to the source and drain of the synchronous rectifier, respectively. The differential amplifier's output terminal is connected to the first and second input terminals of the slope detection unit, respectively. The first and second output terminals of the slope detection unit are connected to the first and second input terminals of the zero-crossing calculation unit, respectively. The output terminal of the zero-crossing calculation unit is connected to the input terminal of the voltage conversion and proportional setting unit. The output terminal of the voltage conversion and proportional setting unit is connected to the input terminal of the dead time adjustment unit. The dead time adjustment unit outputs the dead time.

[0066] The working principle of each unit is explained below.

[0067] The differential amplifier is used to acquire the voltage difference between the source and drain of the synchronous rectifier, amplify the voltage difference, convert it into a voltage with a larger amplitude that is easy to process, and output the voltage signal to the slope detection unit.

[0068] The slope detection unit compares the amplified voltage signal with a preset first voltage threshold and a preset second voltage threshold to obtain the time difference signal of the amplified signal passing through the two preset voltage thresholds, and inputs the time difference signal as a control signal to the zero-crossing calculation unit.

[0069] The zero-crossing calculation unit calculates the time of the secondary current's zero-crossing based on the received time difference signal, and thus determines the zero-crossing time of the magnetizing inductor current. Based on the zero-crossing time of the magnetizing inductor and the turn-off time of the clamping transistor, the time difference between the zero-crossing time of the magnetizing inductor current and the turn-off time of the clamping transistor can be obtained. After obtaining this time difference, it is input to the voltage conversion and proportional setting unit. The turn-off time of the clamping transistor is the falling edge of the clamping transistor drive signal. The first voltage threshold is greater than the second voltage threshold. Comparing the difference between the first and second voltage thresholds with the time difference of the amplified signal passing through two preset voltage thresholds yields the slope of the secondary current's change with time after the main switching transistor segment. Using either the first or second threshold as the starting point and combining it with the slope of the secondary current's change with time, the zero-crossing time of the secondary current can be obtained.

[0070] The voltage conversion and proportional setting unit converts the time difference between the zero-crossing point of the excitation inductor current and the turn-off time of the clamping transistor into a voltage signal, divides the voltage signal according to a preset ratio, and then inputs the divided voltage signal to the dead time adjustment unit.

[0071] The dead time adjustment unit linearly adjusts the dead time according to the voltage divider signal and limits the dead time to a minimum value. This minimum value (equivalent to the predetermined dead time in the aforementioned embodiment) is half a cycle of the resonant voltage of the leakage inductance and the switching node capacitor.

[0072] Figure 6This is an optional timing diagram of key converter signals according to an embodiment of the present invention. (Refer to...) Figure 6 As shown, G_M P G_M represents the gate drive voltage waveform of the main switch transistor in the converter. A The gate drive voltage waveform of the clamping transistor, DS_M P For the switching node voltage waveform, I LM The waveform of the magnetizing inductor current, I LK The leakage inductance current waveform, I SEC The waveform of the secondary current of the converter, I PKN T is the peak value of the negative current of the magnetizing inductor. ON_A T is the conduction time of the clamping transistor. DAP T is the dead time from the clamping transistor being turned off to the main switch being turned on. ON_ACT From the zero-crossing point of the excitation current to I PKN The time after the clamping transistor is turned off, the switching node voltage of the main switching transistor. The waveform follows the following formula:

[0073]

[0074]

[0075] Among them, V IN L is the input voltage of the converter. M For the magnetizing inductor, C PAR ω is the capacitance value of the parasitic capacitance of the switching node, t is the period parameter, and N is the time. PS V is the turns ratio of the primary winding to the secondary winding. OUT This is the output voltage on the secondary side of the converter.

[0076] The above formula can be approximated by the series expansion of the sine and cosine functions as follows:

[0077]

[0078] Relative to the magnetizing inductance L M With the switching node capacitor C PAR The resonant period of the converter means that the dead time from the clamp transistor turning off to the main switch turning on is relatively small. As long as ωt≦1, the switching node voltage... This can be represented as:

[0079]

[0080] After the clamping transistor is turned off, the main switch must be turned on before the magnetizing current changes from negative to positive; otherwise, the voltage of DS_MP will reverse. The optimal turn-on point is the moment when the magnetizing current changes from negative to positive. This moment is advanced as the absolute value of the negative peak current of the magnetizing inductor decreases, and delayed as the negative peak current increases. After the clamping transistor is turned off, the transient value I(t) of the magnetizing current can be expressed as:

[0081]

[0082] Therefore, the moment when the excitation current changes from negative to positive (with the clamping transistor turning off as the zero moment) t can be calculated. N→P for:

[0083]

[0084] Negative peak current I of the magnetizing inductor PKN for:

[0085]

[0086] Among them, T ON_ACT It is the time difference between the moment when the excitation inductor current crosses zero and the moment when the clamping transistor turns off.

[0087] Therefore, T can be used ON_ACT Substituting the value of T into the above formula yields the moment when the excitation current changes from negative to positive; this moment corresponds to the optimal dead time. However, calculating the formula is very difficult for analog control circuits. Therefore, based on the functional relationship expressed in the formula, a reasonable approximation can be used. The approximate dead time T is... DAP With T ON_ACT The relationship is:

[0088] T DAP =K*T ON_ACT

[0089] Where K is the proportionality coefficient.

[0090] The working principle of the dead-time processing device will be explained below by referring to each unit in the time processing device.

[0091] The positive and negative input terminals of the differential amplifier are connected across the source and drain of the synchronous rectifier, respectively. The voltage difference V between the source and drain of the synchronous rectifier is... DSON After amplification, the amplified signal AMP is obtained. _OUT As shown in the following formula:

[0092] AMP _OUT =A×V _DSON

[0093] Where A is the amplification factor of the differential amplifier.

[0094] The slope detection unit is set with a first voltage threshold V. TH_H Second voltage threshold V TH_L The differential amplifier amplifies the signal AMP. _OUT After comparing with these two thresholds, the time difference signal between the two thresholds is output, and the corresponding control signal is output to the zero-crossing calculation unit. The control signal controls different constant current sources in the zero-crossing calculation unit to charge the two capacitors in the zero-crossing calculation unit, and compares the voltages of the two capacitors. Based on the capacitance values ​​of the two capacitors and the current settings of the two constant current sources, the zero-crossing time of the secondary current is calculated. Then, combined with the clamping transistor drive signal received by the zero-crossing calculation unit, the time difference T between the zero-crossing time of the excitation inductor current and the turn-off time of the clamping transistor is obtained. ON_ACT Time difference T ON_ACT The input is sent to the voltage conversion and proportional setting unit, which then converts the time difference T. ON_ACT The signal is converted into a voltage signal through capacitor charging and sample-and-hold, and then calculated based on the dead time and time difference T. ON_ACT The voltage conversion ratio is set reasonably according to the relationship, and the voltage is divided according to the ratio. Then the voltage division signal is input to the dead time adjustment unit, and the dead time adjustment unit adjusts the dead time cycle by cycle according to the voltage division signal.

[0095] In this optional embodiment, a non-complementary control mode is adopted, where the main switch is turned off for a certain period of time before the clamping transistor is turned on, and the clamping transistor is turned on for a short period of time before the main switch is turned on. This differs from the complementary control mode in related technologies, where the clamping transistor and the main switch are alternately turned on. In the non-complementary control mode, the secondary current of the converter changes linearly with time. The zero-crossing time of the excitation inductor current can be obtained by detecting the zero-crossing time of the secondary current. Based on the time difference between the zero-crossing time and the turn-off time of the clamping transistor, the initially set dead time is adjusted so that the dead time can smoothly transition to a minimum value during the transition of the converter from DCM mode to CCM mode, while simultaneously enabling the main switch to turn on at the valley of the resonant voltage at the switching node.

[0096] The clamping transistor turns on at the zero-crossing moment of the magnetizing inductor current, and its conduction time determines the peak value of the negative current of the magnetizing inductor. By setting an appropriate dead time and adjusting the conduction time of the clamping transistor in real time using an adaptive adjustment method, the peak value of the negative current of the magnetizing inductor can be adjusted, enabling the main switching transistor to achieve ZVS under different operating conditions. As the input voltage decreases, the converter enters CCM mode, and the clamping transistor turns on ahead of the zero-crossing moment of the magnetizing inductor current. The secondary current increases during the conduction period of the clamping transistor. At this time, it is difficult to directly detect the zero-crossing moment of the secondary current and the magnetizing inductor current.

[0097] This optional implementation sets two different thresholds and detects the time difference between the secondary current crossing these two thresholds. Based on the time difference and the two thresholds, the slope of the secondary current change is obtained. Then, the zero-crossing moment of the magnetizing inductor current can be calculated based on the slope of the current change. The calculated zero-crossing moment and the actual clamping transistor turn-off time difference T... ON_ACT The voltage drop is proportional to the negative peak value of the magnetizing inductor current, because the negative peak value directly determines the magnitude of the voltage drop at the switching node. Therefore, it can be determined based on the time difference T. ON_ACT The decrease gradually reduces the dead time from the clamping transistor's turn-off to the main switch's turn-on. At T... ON_ACT Once the dead time falls below a certain threshold, the dead time is switched to a minimum value, which corresponds to half a cycle of the resonant voltage of the leakage inductance and the parasitic capacitance of the switching node.

[0098] The circuit connections of each unit are explained below.

[0099] Figure 7 This is a circuit diagram of an optional converter slope detection unit according to an embodiment of the present invention. (Refer to...) Figure 7 As shown, the slope detection unit includes a first comparator U1, a second comparator U2, a first D flip-flop D1, and a first NOT gate B1.

[0100] The positive input terminals of the first comparator U1 and the second comparator U2 respectively constitute the first and second input terminals of the slope detection unit. That is, the output terminal of the differential amplifier is connected to the positive input terminals of the first comparator U1 and the second comparator U2, respectively. The negative input terminal of the first comparator U1 is connected to the first voltage threshold V. TH_H The negative input terminal of the second comparator U2 is connected to the second voltage threshold V. TH_L The output of the first comparator U1 is connected to the trigger terminal of the first D flip-flop D1, and the output of the second comparator U2 is connected to the reset terminal of the first D flip-flop D1 and the input terminal of the first NOT gate B1, respectively. The D input terminal of the first D flip-flop D1 is connected to a high potential; the Q output terminal of the first D flip-flop D1 and the output terminal of the first NOT gate B1 constitute the first and second output terminals of the control signal generation unit, respectively; the Q output terminal of the first D flip-flop D1 outputs the first control signal T. CH1 The output of the first NOT gate B1 outputs the second control signal T. CH2 First control signal T CH1 The magnitude is equal to the second time, the second control signal T CH2 The first control signal T CH1 The inverted signal.

[0101] Combination Figure 6 The first control signal T is output at the Q output terminal of the first D flip-flop D1. CH1 for:

[0102]

[0103] Among them, R DSON is the impedance between the drain and source of the synchronous rectifier, and m is the slope of the secondary current change.

[0104] Figure 8 This is a circuit diagram of an optional converter zero-crossing calculation unit according to an embodiment of the present invention. (Refer to...) Figure 8 As shown, the zero-crossing calculation unit includes a first current source I1, a second current source I2, a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a first capacitor C1, a second capacitor C2, a third comparator U3, a second D flip-flop D2, and a pulse generator S1.

[0105] In this circuit, both the first current source I1 and the second current source I2 are connected to a high potential. The output terminals of the first current source I1 and the second current source I2 are connected to one end of the first switch K1 and one end of the second switch K2, respectively. The control terminals of the first switch K1 and the second switch K2 are connected to the first and second output terminals of the control signal generation unit, respectively. The other end of the first switch K1 is connected to one end of the first capacitor C1, one end of the third switch K3, and the positive input terminal of the third comparator U3. The other end of the first capacitor C1 is connected to the other end of the third switch K3 and grounded. The other end of the second switch K2, one end of the second capacitor C2, and the fourth... One end of switch K4, the negative input of the third comparator U3, and the other end of the second capacitor C2 are connected together and grounded. The control terminals of the third switch K3 and the fourth switch K4, the reset terminal of the second D flip-flop D2, and the output terminal of the pulse generator S1 are connected together. The output terminal of the third comparator U3 is connected to the trigger terminal of the second D flip-flop D2. The D input terminal of the second D flip-flop D2 is connected to a high potential. The Q output terminal of the second D flip-flop D2 outputs the first time signal. The Q output terminal of the second D flip-flop D2 constitutes the output terminal of the time acquisition unit. The input terminal of the pulse generator S1 is connected to the drive signal of the clamping transistor.

[0106] In this circuit, pulse generator S1 generates a narrow high-level pulse on the falling edge of the clamping transistor drive signal to reset the second D flip-flop D2, as well as the first capacitor C1 and the second capacitor C2. The control terminals of the first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 are all active high. The first switch K1 is turned on by a first control signal and charges the first capacitor C1 through the first current source I1. At the end of charging, the voltage V of the first capacitor C1... C1 for:

[0107]

[0108] The voltage of the first capacitor C1 is maintained until the falling edge of the clamping transistor drive signal of the current cycle arrives. Before the falling edge of the clamping transistor drive signal arrives, the second control limit T... CH2 This causes K2 to conduct, and current source I2 charges capacitor C2. The voltage across C2 reaches the voltage held by C1, causing the third comparator U3 to flip. The second D flip-flop D2 is then triggered by the output signal of the third comparator U3, and the Q output signal T of the second D flip-flop D2 is generated. ON_ACT The value is toggled to a high level. ON_ACT Flip to high level relative to T CH2 The time difference T between the flipping to high level ON_ACT_LH It can be calculated using the following formula:

[0109]

[0110] By properly setting the parameters in the formula, T can be... ON_ACT The moment the voltage flips to high corresponds to the moment the magnetizing inductor current crosses zero. For example, V TH_H / (A*R DSON ) = 4A, V TH_L / (A*R DSON Given I1 = I2, C1 = C2, and the slope of the excitation current remains constant, the time it takes for the current to drop from 4A to 2A is the same as the time it takes for it to drop from 2A to 0A. Therefore, the charging time for capacitors C1 and C2 is the same. The moment C2 charges to the voltage of C1, which corresponds to the excitation current crossing zero, is when the second D flip-flop D2 is triggered. The second D flip-flop D2 resets at the moment the clamping transistor is turned off. Therefore, T... ON_ACT The high-level width represents the peak value of the negative magnetizing inductor current.

[0111] Figure 9 This is a circuit diagram of an optional converter voltage conversion and scaling unit according to an embodiment of the present invention. (Refer to...) Figure 9 As shown, the voltage conversion and proportional setting unit includes a fifth switch K5, a sixth switch K6, a seventh switch K7, a third current source I3, a first buffer F1, a second buffer F2, a third capacitor C3, a fourth capacitor C4, a first resistor R1, a second resistor R2, and a control signal generation circuit.

[0112] The input terminal of the third current source I3 is connected to a high potential, and the output terminal of the third current source I3 is connected to one end of the fifth switch K5. The control terminal of the fifth switch K5 is connected to the output terminal of the time acquisition unit. The other end of the fifth switch K5 is connected to one end of the third capacitor C3, one end of the sixth switch K7, and the positive input terminal of the first buffer F1. The other end of the third capacitor C3 and the other end of the sixth switch K7 are connected to ground. The control terminal of the sixth switch K7 is connected to the first output terminal of the control signal generation circuit. The negative input terminal of the first buffer F1 and the positive input terminal of the first buffer F1, and one end of the sixth switch K5 are connected to the first output terminal of the control signal generation circuit. The three terminals are connected together; the other end of the sixth switch K6 is connected to one end of the fourth capacitor C4 and the positive input terminal of the second buffer F2. The control terminal of the sixth switch K6 is connected to the other output terminal of the control signal generation circuit. The input terminal of the control signal generation circuit is connected to the output terminal of the time acquisition unit. The other end of the fourth capacitor C4 is grounded. The negative input terminal of the second buffer F2 and the output terminal of the second buffer F2 are connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to one end of the second resistor R2. The connection point constitutes the output terminal of the voltage conversion and proportional setting unit. The other end of the second resistor R2 is grounded.

[0113] The control signal generation circuit inputs the time difference signal T between the zero-crossing point of the excitation inductor current and the turn-off of the clamping transistor. ON_ACT Signals, and respectively generate hysteresis T ON_ACT Control signals 1 and 2 are used, with control signal 2 lagging behind control signal 1. Control signal 1 turns on K6 to sample the voltage of the third capacitor C3, and control signal 2 turns on the seventh switch K7 to reset the third capacitor C3. When the seventh switch K7 is on, the sixth switch K6 is already off. The first buffer F1 and the second buffer F2 have unity gain, and the peak charging voltage V of the third capacitor C3 is... C3 for:

[0114]

[0115] The dead-time adjustment voltage signal V output by the voltage conversion and proportional setting circuit D_CTRL The voltage division value of the sampled and held voltage across capacitor C4 is as follows:

[0116]

[0117] Figure 10 This is a circuit diagram of an optional converter dead-time processing unit according to an embodiment of the present invention. (Refer to...) Figure 10 As shown, the converter dead time processing unit includes: a fourth current source I4, a fifth capacitor C5, an eighth switch K8, a fourth comparator U4, a superimposed voltage V1, a third D flip-flop U3, a first OR gate H1, and a minimum dead time setting circuit.

[0118] The fourth current source I4 has its input terminal connected to a high potential. The output terminal of the fourth current source I4 is connected to one end of the fifth capacitor C5, one end of the eighth switch K8, and the negative input terminal of the fourth comparator U4. The other end of the fifth capacitor C5 and the other end of the eighth switch K8 are connected and grounded. The positive input terminal of the fourth comparator U4 is connected to the output terminal of the voltage conversion and proportional setting unit. The output terminal of the fourth comparator U4 is connected to the reset terminal of the third D flip-flop U3. The D input terminal of the third D flip-flop U3 is connected to a high potential. The trigger terminal of the third D flip-flop U3 is connected to the clamping transistor drive signal. The Q output terminal of the third D flip-flop U3 is connected to one input terminal of the first OR gate and the control terminal of the eighth switch K8. The other input terminal of the first OR gate is connected to the output terminal of the minimum dead time setting circuit. The output terminal of the first OR gate outputs the dead time adjustment signal.

[0119] Wherein, the superimposed voltage V1 is a DC voltage, and the superimposed voltage V1 is superimposed on V D_CTRL On the voltage signal, the initial dead time is set. The minimum dead time setting circuit is used to set the minimum dead time based on the leakage inductance and the resonant period of the switching node capacitor, so as to enable the main switch to turn on at the valley of the resonant voltage of the switching node in the magnetizing inductor current CCM mode.

[0120] Dead time T during the transition from DCM mode to CCM mode DAP for:

[0121]

[0122] Among them, V801 is superimposed on the amplitude of voltage V1.

[0123] By properly setting the parameters in the formula, the dead time and T can be adjusted. ON_ACT The relationship between them is a linear relationship with a fixed slope, and the dead time is then controlled based on this linear relationship.

[0124] The dead time processing device provided in this optional embodiment has the following advantages: on the one hand, during the transition of the converter from the discontinuous mode of the excitation inductor current to the continuous mode, the dead time changes smoothly, eliminating the impact on the stability of the control loop; on the other hand, by controlling the dead time, when the converter is in the critical state between the discontinuous mode and the continuous mode of the excitation inductor current, the main switch can be turned on at the lowest value of the switching node voltage, thereby improving efficiency.

[0125] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0126] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0127] The above embodiments, based on the functional relationship between dead time and the negative peak current of the magnetizing inductor, provide a specific implementation circuit after a certain degree of linear simplification of the function. It should be understood that the technical content disclosed in the above embodiments can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they can be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0128] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0129] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0130] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for handling the dead time of a converter, characterized in that it includes: Obtain the slope of the first decrease in secondary current after the main switch of the converter is turned off. Based on the slope of the change of the secondary current, the zero-crossing time of the magnetizing inductor current on the primary side of the converter is obtained, wherein the zero-crossing time is the moment when the magnetizing inductor current decreases to zero after the main switch is turned off. Obtain the time difference between the zero-crossing moment and the turn-off moment of the clamping transistor of the converter; Determining the dead time of the primary side of the converter based on the time difference includes: converting the time difference into a voltage signal; determining a voltage divider signal based on a predetermined ratio; and determining the dead time of the primary side of the converter based on the voltage divider signal. The dead time is the time interval from the turn-off time of the clamping transistor to the turn-on time of the main switch transistor of the converter. Determining the dead time of the primary side of the converter based on the voltage divider signal includes: determining a first dead time based on the voltage divider signal; obtaining the difference between the first dead time and a predetermined dead time; determining the first dead time as the dead time of the primary side of the converter if the difference is greater than the predetermined difference; or determining the predetermined dead time as the dead time of the primary side of the converter if the difference is less than or equal to the predetermined difference.

2. The method according to claim 1, characterized in that, The step of obtaining the slope of the first decrease in secondary current after the main switch of the converter is turned off includes: Obtain the first voltage threshold and the second voltage threshold; The first moment when the secondary voltage is the first voltage threshold after the main switch of the converter is turned off, and the second moment when the secondary voltage is the second voltage threshold are obtained; Based on the first voltage threshold and the second voltage threshold, as well as the first time and the second time, determine the slope of the first decrease in secondary current after the main switch of the converter is turned off.

3. The method according to claim 1, characterized in that, Based on the slope of the secondary current change, the zero-crossing time of the primary-side magnetizing inductor current of the converter is obtained, including: Based on the slope of change, the transformation relationship between the secondary current and time is determined; Based on the transformation relationship, the zero-crossing point time corresponding to the zero-crossing point when the excitation inductance current on the primary side of the converter is zero is determined.

4. The method according to any one of claims 1 to 3, characterized in that, After determining the dead time of the primary side of the converter based on the time difference, the method further includes: The determined dead time is fed back to the primary-side controller of the converter, so that the primary-side controller can control the clamping transistor and the main switching transistor based on the dead time.

5. A dead-time processing device for a converter, characterized in that it comprises: The slope detection unit is used to obtain the slope of the first decrease in the secondary current after the main switch of the converter is turned off. The zero-crossing calculation unit is used to obtain the zero-crossing time of the magnetizing inductor current on the primary side of the converter based on the slope of the change of the secondary side current, wherein the zero-crossing time is the moment when the magnetizing inductor current decreases to zero after the main switch is turned off. The dead time processing unit is used to obtain the time difference between the zero-crossing time and the turn-off time of the clamping transistor of the converter, and to determine the dead time of the primary side of the converter based on the time difference, wherein the dead time is the time period from the turn-off time of the clamping transistor to the turn-on time of the main switch of the converter. The step of determining the dead time of the primary side of the converter based on the time difference includes: converting the time difference into a voltage signal; determining a voltage divider signal of the voltage signal based on a predetermined ratio; and determining the dead time of the primary side of the converter based on the voltage divider signal. Determining the dead time of the primary side of the converter based on the voltage divider signal includes: determining a first dead time based on the voltage divider signal; obtaining the difference between the first dead time and a predetermined dead time; determining the first dead time as the dead time of the primary side of the converter if the difference is greater than the predetermined difference; or determining the predetermined dead time as the dead time of the primary side of the converter if the difference is less than or equal to the predetermined difference.

6. The apparatus according to claim 5, characterized in that, The device further includes: The differential amplifier circuit is used to differentially amplify the voltage signal acquired from the secondary side after the main switch of the converter is turned off, to obtain a differentially amplified signal, and output the differentially amplified signal to the slope detection unit.

7. The apparatus according to claim 5, characterized in that, The dead-time processing unit includes: A voltage conversion and ratio setting unit is used to convert the time difference into a voltage signal and set a predetermined ratio; The dead time adjustment unit is used to determine the voltage divider signal of the voltage signal based on the predetermined ratio, and to determine the dead time of the primary side of the converter based on the voltage divider signal.

8. A converter, characterized in that, include: The converter comprises a primary winding, a primary controller, a secondary winding and a secondary controller, a main switch, a clamping transistor, and a rectifier transistor. The primary controller controls the output of the primary winding via the main switch and the clamping transistor. The secondary controller is connected to the secondary winding via the rectifier transistor. The secondary controller includes a dead-time processing device for the converter as described in any one of claims 5 to 7. The secondary controller is further configured to feed back the dead-time obtained by the dead-time processing device to the primary controller, so that the primary controller can control the clamping transistor and the main switch based on the dead-time.

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