An aperiodic sampling low pass filter

Abstract

The application discloses an indefinite frequency sampling low-pass filter, and relates to the field of filters.The indefinite frequency sampling low-pass filter comprises a switched capacitor sampling filter circuit and an indefinite frequency signal generating circuit; the output end of the indefinite frequency signal generating circuit is connected with the switched capacitor sampling filter circuit; and the indefinite frequency signal generating circuit is used for providing an indefinite frequency control clock signal for the switched capacitor sampling filter circuit.The application can reduce the capacitor area, save the chip cost, and avoid generating a dislocation voltage.

Description

Technical Field

[0001] This invention relates to the field of filters, and in particular to a variable frequency sampling low-pass filter. Background Technology

[0002] Ordinary RC filters, such as Figure 1 As shown, a typical RC filter consists of resistors and capacitors, and its cutoff frequency f 3db It is determined by the reciprocal of the product of resistance R and capacitance C. To achieve an extremely low cutoff frequency, a large RC constant is required. In semiconductor chips, capacitor density is generally low; to achieve a large capacitance value, a large chip area is needed, increasing chip cost. On the other hand, although resistor density is high, the resistance value cannot be increased indiscriminately, because excessively large resistors will increase sensitivity to leakage current in the circuit, increasing the voltage error of the filter.

[0003] To address the aforementioned issues, a switched-capacitor sampling filter is provided, such as... Figure 2 As shown, a sampling switch CLK is added before a standard RC filter. Its switching frequency is Fsw, and its duty cycle is D. This switched-capacitor sampling filter utilizes the sample-and-hold principle, sampling the input signal only for a small portion of the time within a cycle, while keeping the charge on the capacitor constant for the rest of the time. Assuming a sampling duty cycle of 1 / 10, a 10-fold capacitance multiplication effect can be achieved, significantly reducing capacitor area and saving chip cost. However, current switched-capacitor sampling filters typically use a fixed-frequency clock for sampling. When the sampling clock frequency is related to the input signal frequency, such as for a sinusoidal input, if the input signal is an integer multiple of the sampling clock frequency, sampling errors will be introduced, resulting in offset voltage. For example, as... Figure 3 As shown, VSIN is the input sine wave signal, VSAMPLE is the 1 / 10 duty cycle sampled signal, V_RC is the output signal of VSIN after passing through an ideal RC filter, and V_DUTY_RC is the output signal of VSIN after small duty cycle sampling. The frequency of the input sine wave signal is twice the sampling frequency. Figure 3 As can be seen, since VSIN is twice the sampling frequency, each sampling point is at the same position of the input signal. This results in a fixed offset voltage in the output signal of the small duty cycle sampling compared to the output of an ideal RC filter. The magnitude of this offset voltage is related to the amplitude of the input signal and the phase difference between the input signal and the sampled signal. Figure 3 As can be seen, the offset voltage is 68mV. Summary of the Invention

[0004] Based on this, embodiments of the present invention provide a variable frequency sampling low-pass filter that reduces capacitor area and saves chip cost while avoiding the generation of offset voltage.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] A variable-frequency sampling low-pass filter includes: a switched-capacitor sampling filter circuit and a variable-frequency signal generation circuit;

[0007] The output of the variable frequency signal generation circuit is connected to the switched capacitor sampling and filtering circuit; the variable frequency signal generation circuit is used to provide a variable frequency control clock signal for the switched capacitor sampling and filtering circuit.

[0008] Optionally, the variable frequency signal generation circuit includes a multiplexer, a first inverter, and a second inverter connected in sequence.

[0009] The input terminal of the multiplexer is connected to multiple clock signals, which are fixed-frequency signals in the same period and have a phase difference between them. The control terminal of the multiplexer is used to input a random control signal to randomly select from the multiple clock signals. The output terminals of the first inverter and the second inverter are both connected to the switched-capacitor sampling and filtering circuit. The output terminal of the first inverter is used to output a first variable-frequency control clock signal, and the output terminal of the second inverter is used to output a second variable-frequency control clock signal.

[0010] Optionally, the variable frequency sampling low-pass filter further includes: a pseudo-random sequence generator;

[0011] The input terminal of the pseudo-random sequence generator is connected to the output terminal of the first inverter; the output terminal of the pseudo-random sequence generator is connected to the control terminal of the multiplexer; the pseudo-random sequence generator is used to provide a random control signal to the multiplexer.

[0012] Optionally, the multiplexer includes four input ports; one input port is connected to one clock signal; the four clock signals are in the same period and have a phase difference of . A fixed-frequency signal, where T represents the period.

[0013] Optionally, the pseudo-random sequence generator includes an XOR gate and a first register, a second register, a third register, a fourth register, a fifth register, and a sixth register connected in sequence;

[0014] The clock terminals of the first register, the second register, the third register, the fourth register, the fifth register, and the sixth register are all connected to the output terminal of the first inverter; the output terminals of the fifth register and the sixth register are both connected to the input terminal of the XOR gate; the output terminal of the XOR gate is connected to the input terminal of the first register; the output terminal of the fifth register is connected to the first control terminal of the multiplexer; and the output terminal of the sixth register is connected to the second control terminal of the multiplexer.

[0015] Optionally, the switched capacitor sampling and filtering circuit includes a sampling switch and an RC filter circuit connected in sequence; the sampling switch is connected to the output terminal of the variable frequency signal generation circuit.

[0016] Optionally, the sampling switch includes a first switching transistor and a second switching transistor;

[0017] The source of the first switch and the source of the second switch are both connected to the filter input terminal, the drain of the first switch and the drain of the second switch are both connected to the RC filter circuit, the gate of the first switch is connected to the output terminal of the first inverter, and the gate of the second switch is connected to the output terminal of the second inverter.

[0018] Optionally, the RC filter circuit includes a resistor and a capacitor connected in sequence;

[0019] One end of the sampling switch is connected to the filter input terminal; the other end of the sampling switch is grounded after passing through the resistor and the capacitor in sequence; the connection point of the resistor and the capacitor is the filter output terminal.

[0020] Optionally, the duty cycle of the variable frequency control clock signal is less than 1.

[0021] Optionally, the first switch is an NMOS transistor; the second switch is a PMOS transistor.

[0022] Compared with the prior art, the beneficial effects of the present invention are:

[0023] This invention proposes a variable-frequency sampling low-pass filter, comprising: a switched-capacitor sampling filter circuit and a variable-frequency signal generation circuit; the output of the variable-frequency signal generation circuit is connected to the switched-capacitor sampling filter circuit; the variable-frequency signal generation circuit provides a variable-frequency control clock signal to the switched-capacitor sampling filter circuit. This embodiment provides a variable-frequency control clock signal to the switched-capacitor sampling filter circuit through the variable-frequency signal generation circuit. Under the control of the variable-frequency control clock signal, the switched-capacitor sampling filter circuit achieves non-fixed-frequency clock sampling, avoiding correlation between the sampling clock frequency and the input signal frequency, avoiding the introduction of sampling errors, and thus avoiding offset voltage. Furthermore, the switching-capacitor sampling filter circuit reduces the capacitor area and saves chip cost. Therefore, this invention can reduce the capacitor area and save chip cost while avoiding offset voltage. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of a typical RC filter.

[0026] Figure 2 This is a schematic diagram of the structure of a switched-capacitor sampling filter;

[0027] Figure 3 The waveform of the offset voltage generated by the switched capacitor filter;

[0028] Figure 4 This is a schematic diagram of the structure of the variable frequency sampling low-pass filter provided in Embodiment 1 of the present invention;

[0029] Figure 5 This is a structural diagram of the variable frequency signal generation circuit provided in Embodiment 2 of the present invention;

[0030] Figure 6 This is a structural diagram of the pseudo-random sequence generator provided in Embodiment 3 of the present invention;

[0031] Figure 7 The timing diagram for the joint simulation of the pseudo-random sequence generator and the variable frequency signal generation circuit provided in Embodiment 3 of the present invention;

[0032] Figure 8 This is a structural diagram of the switched capacitor sampling filter circuit provided in Embodiment 4 of the present invention;

[0033] Figure 9 This is a comparison chart of the filtering effects of different low-pass filters. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] Example 1

[0037] Figure 4 This is a schematic diagram of the structure of the variable-frequency sampling low-pass filter provided in Embodiment 1 of the present invention. See also... Figure 4 The variable-frequency sampling low-pass filter includes a switched-capacitor sampling filter circuit and a variable-frequency signal generation circuit. The output terminal of the variable-frequency signal generation circuit is connected to the switched-capacitor sampling filter circuit; the variable-frequency signal generation circuit is used to provide a variable-frequency control clock signal for the switched-capacitor sampling filter circuit.

[0038] Those skilled in the art can select a variable frequency signal generation circuit as needed. The specific structure of the variable frequency signal generation circuit is not limited here, as long as it can at least achieve the function of generating a variable frequency control clock signal.

[0039] In one example, the duty cycle of the variable frequency control clock signal can be flexibly designed according to requirements. For example, the duty cycle of the variable frequency control clock signal can be set to be less than 1.

[0040] In this embodiment, an indeterminate frequency signal generation circuit provides an indeterminate frequency control clock signal to the switched capacitor sampling and filtering circuit. Under the control of the indeterminate frequency control clock signal, the switched capacitor sampling and filtering circuit realizes non-fixed frequency clock sampling, avoids the correlation between the sampling clock frequency and the input signal frequency, avoids the introduction of sampling errors, and thus avoids the generation of offset voltage.

[0041] Example 2

[0042] The difference from the above embodiments is that this embodiment provides a specific structure for a variable frequency signal generation circuit.

[0043] See Figure 5The variable-frequency signal generation circuit includes a multiplexer 1, a first inverter 2, and a second inverter 3 connected in sequence. The input of the multiplexer is connected to multiple clock signals, which are fixed-frequency signals within the same period and have a phase difference. The control terminal of the multiplexer is used to input a random control signal to randomly select from the multiple clock signals. The outputs of both the first and second inverters are connected to the switched-capacitor sampling and filtering circuit. The output of the first inverter outputs a first variable-frequency control clock signal CLK_I, and the output of the second inverter outputs a second variable-frequency control clock signal CLK_F. The duty cycles of the first and second variable-frequency control clock signals CLK_I and CLK_F are less than a set value, enabling the low-pass filter to achieve variable-frequency, small-duty-cycle sampling, further reducing capacitor area and saving chip cost. It is understandable that the duty cycles of the first variable frequency control clock signal CLK_I and the second variable frequency control clock signal CLK_F can be flexibly designed according to requirements. For example, the duty cycles of the first variable frequency control clock signal CLK_I and the second variable frequency control clock signal CLK_F can both be set to be less than 1.

[0044] An inverter is an output circuit where the input and output levels are opposite; that is, when the input is low, the output is high, and when the input is high, the output is low.

[0045] In one example, the multiplexer includes four input ports; each input port is connected to one clock signal (input ports A, B, C, and D correspond to clock signals CLK1, CLK2, CLK3, and CLK4, respectively); the four clock signals are in the same period and have a phase difference of . A fixed-frequency signal, where T represents the period. For example, the initial phase of CLK1 is 0, and the initial phase of CLK1 is... And so on.

[0046] It is understood that those skilled in the art can flexibly design the number of input ports of the multiplexer and the phase difference of the multiple clock signals as needed, which will not be elaborated here.

[0047] Example 3

[0048] The difference from the above embodiments lies in that this embodiment uses a pseudo-random sequence generator to provide a randomized control signal to the control terminal of the multiplexer. The input terminal of the pseudo-random sequence generator is connected to the output terminal of the first inverter; the output terminal of the pseudo-random sequence generator is connected to the control terminal of the multiplexer; the pseudo-random sequence generator provides a randomized control signal to the multiplexer; a variable-frequency signal generation circuit, under the control of the randomized control signal, randomly selects from the input multiple clock signals to output two complementary variable-frequency control clock signals; the switched-capacitor sampling filter circuit, under the control of the two variable-frequency control clock signals, achieves non-fixed-frequency clock sampling, avoiding the introduction of sampling errors during the filtering process, thereby preventing offset voltage. Furthermore, compared to a conventional RC filter, the switched-capacitor sampling filter circuit reduces the capacitor area and saves chip cost.

[0049] A pseudo-random sequence generator can be flexibly designed according to the number of control signals (random signals) required for the desired randomness. For example, if you want to achieve random selection of four clock signals input to the four input ports of a multiplexer, you need to design a pseudo-random sequence generator that outputs two random signals, that is, design a 6-bit pseudo-random sequence generator.

[0050] See Figure 6 The pseudo-random sequence generator includes an XOR gate and a first register, a second register, a third register, a fourth register, a fifth register, and a sixth register connected in sequence. The output bits of all six registers are incremented by 2. 6 -1 is a periodic pseudo-random sequence, where D0 to D5 are the output signals of each register.

[0051] The clock terminals of the first register, the second register, the third register, the fourth register, the fifth register, and the sixth register are all connected to the output terminal of the first inverter; the output terminals of the fifth register and the sixth register are both connected to the input terminal of the XOR gate; the output terminal of the XOR gate is connected to the input terminal of the first register. Figure 5 and Figure 6 As shown, the output terminal D4 of the fifth register is connected to the first control terminal S0 of the multiplexer; the output terminal D5 of the sixth register is connected to the second control terminal S1 of the multiplexer. When S0S1 = 00 / 01 / 10 / 11, the output terminal OUT of the multiplexer outputs the clock signals connected to terminals A / B / C / D respectively. The two random signals output by the fifth and sixth registers enable random selection of the four clock signals, causing the variable frequency signal generation circuit to output a control signal with an uncertain frequency (variable frequency control clock signal).

[0052] The operation of the pseudo-random sequence generator and the variable frequency signal generation circuit is as follows: Initially, the outputs of all six registers are set to 0, at which point D4 = 0, D5 = 0, and the four-input multiplexer selects CLK1. At this time, CLK_I = CLK1!. As CLK_I continuously flips, the pseudo-random sequence generated by the six registers will be shifted at the rising edge of the input CLK_I, i.e., D1 = D0, D2 = D1, D3 = D2, D4 = D3, D5 = D4, D0 = D4⊕D5 (D4 XOR D5). Among them, D0 to D5 are all shifted by 2... 6 The sequence has a period of -1 = 31, and it cycles continuously, so it is called a pseudo-random sequence.

[0053] D4 and D5 are selected as random control signals to control the four-input multiplexer. Due to the random nature of D4 and D5, the output of the first inverter outputs a first variable-frequency control clock signal CLK_I, and the outputs of the second inverter output a second variable-frequency control clock signal CLK_F. CLK_F is also a randomly selected signal from CLK1 to CLK4, resulting in unstable frequencies for CLK_I and CLK_F. The timing diagram for the joint simulation of the pseudo-random sequence generator and the variable-frequency signal generation circuit is shown below. Figure 7 As shown. By Figure 7 As can be seen, CLK1 to CLK4 are four fixed-frequency signals with a phase difference of 1 / 4 cycle. D4 and D5 have irregular waveforms. CLK_F is controlled by D4 and D5 to select CLK1 to CLK4, so its signal frequency is unstable.

[0054] Example 4

[0055] The difference from the above embodiments is that this embodiment provides a detailed description of the switched capacitor sampling and filtering circuit.

[0056] See Figure 8 The switched capacitor sampling and filtering circuit includes a sampling switch and an RC filter circuit connected in sequence; the sampling switch is connected to the output terminal of the first inverter and the output terminal of the second inverter, respectively.

[0057] In one example, to reduce the effects of channel charge injection and capacitor feedthrough, the sampling switch includes a first switching transistor 4 and a second switching transistor 5; the source of the first switching transistor 4 and the source of the second switching transistor 5 are both connected to the filter input terminal, the drain of the first switching transistor 4 and the drain of the second switching transistor 5 are both connected to the RC filter circuit, the gate of the first switching transistor 4 is connected to the output terminal of the first inverter, and the gate of the second switching transistor 5 is connected to the output terminal of the second inverter.

[0058] Those skilled in the art can select the model or type of the first switching transistor 4 and the second switching transistor 5 as needed. For example, the first switching transistor 4 can be an NMOS transistor; the second switching transistor 5 can be a PMOS transistor, as long as it can at least achieve the on and off function.

[0059] In one example, the RC filter circuit includes a resistor and a capacitor connected in sequence; one end of the sampling switch is connected to the filter input terminal; the other end of the sampling switch is grounded after passing through the resistor and the capacitor in sequence; the connection point of the resistor and the capacitor is the filter output terminal.

[0060] The operation process of the variable-frequency sampling low-pass filter in this embodiment is as follows:

[0061] The input signals CLK1 to CLK4 of the four-input multiplexer are periodic signals, with their initial phases differing by 1 / 4 period. D4 and D5 come from the outputs of the fifth and sixth registers in the pseudo-random sequence generator. CLK_I is used as... Figure 4 The clock input, CLK_F as Figure 2 The switching signal in the middle.

[0062] The variable frequency signal generation circuit serves as the initial input unit. The four clock signals first pass through a multiplexer, and the S0 and S1 control ports of the multiplexer select the four signals. After a signal is selected, the first variable frequency control clock signal CLK_I is output through the first inverter. At the same time, the output of the first inverter is connected to the input of the random sequence generator and the gate of the first switch transistor 4 in the switched capacitor sampling filter circuit (CLK_I provides a control signal for the first switch transistor 4). The first variable frequency control clock signal CLK_I passes through the second inverter again to obtain the second variable frequency control clock signal CLK_F. At the same time, the output of the second inverter is connected to the gate of the second switch transistor 5 in the switched capacitor sampling filter circuit (CLK_F provides a control signal for the second switch transistor 5). CLK_F and CLK_I cooperate with each other to further control the on / off state of the two switches.

[0063] Furthermore, the obtained CLK_I signal needs to pass through a random sequence generator, which generates random control signals for D4 and D5, and further controls the multiplexer in the variable frequency signal generation circuit. The multiplexer then selects the corresponding input signal to obtain the subsequent CLK_I and CLK-F signals, which better control the switching transistors in the switched capacitor sampling filter circuit.

[0064] Figure 9This is a comparison chart of the filtering effects of different low-pass filters. V_RC represents the output of the ideal RC filter, V_DUTY_RC represents the output of the switched-capacitor sampling filter (a fixed-frequency, small duty cycle filter), and V_SCRAMBLE represents the output of the variable-frequency sampling low-pass filter (a non-fixed-frequency, small duty cycle filter) in this embodiment. It can be seen that the offset between V_SCRAMBLE and V_RC is very small, approximately only 2mV, far less than the 68mV of V_DUTY_RC.

[0065] The variable-frequency sampling low-pass filter provided in the above embodiments of the present invention has the following advantages:

[0066] 1) To achieve a low low-pass cutoff frequency, conventional RC filters require large resistors and capacitors, which occupies a significant chip area and increases chip cost. In contrast, variable-frequency sampling low-pass filters employ switched-capacitor sampling circuits, reducing capacitor area and saving chip cost.

[0067] 2) The switching capacitor sampling filter circuit uses a small duty cycle switching clock sampling, which can greatly reduce the resistance and capacitance, but there is a possibility of generating offset voltage. The variable frequency sampling low-pass filter in this embodiment uses a pseudo-random sequence generator and a variable frequency signal generation circuit to provide a variable frequency control clock signal for the switching capacitor sampling filter circuit, realizing non-fixed frequency clock sampling, avoiding the introduction of sampling error, and thus avoiding the generation of offset voltage.

[0068] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0069] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An aperiodic frequency sampling low pass filter characterized by, The application relates to a switch capacitor sampling filter circuit and an uncertain frequency signal generating circuit. An output end of the uncertain frequency signal generating circuit is connected with the switch capacitor sampling filter circuit. The uncertain frequency signal generating circuit is used for providing an uncertain frequency control clock signal for the switch capacitor sampling filter circuit. The uncertain frequency signal generating circuit comprises a multiplexer, a first inverter and a second inverter which are connected in sequence. The multiplexer is connected with a plurality of clock signals, the plurality of clock signals are fixed frequency signals in a same period and have a phase difference between the signals. The control end of the multiplexer is used for inputting a control signal with randomness to randomly select the plurality of clock signals. The output end of the first inverter and the output end of the second inverter are connected with the switch capacitor sampling filter circuit. The output end of the first inverter is used for outputting a first uncertain frequency control clock signal, and the output end of the second inverter is used for outputting a second uncertain frequency control clock signal.

2. The variable frequency sampling low-pass filter of claim 1, wherein, The multiplexer comprises four input ports; one of the input ports is connected with one clock signal; the four clock signals are in the same period and have a phase difference of , wherein, T represents the period.

3. The variable frequency sampling low-pass filter of claim 1, wherein, The uncertain frequency sampling low-pass filter further comprises a pseudo-random sequence generator which is used for providing the control signal with randomness for the multiplexer.

4. A variable frequency sampling low pass filter according to claim 3, wherein, The pseudo-random sequence generator comprises an XOR gate and a first register, a second register, a third register, a fourth register, a fifth register and a sixth register which are connected in sequence. The clock end of the first register, the second register, the third register, the fourth register, the fifth register and the sixth register is connected with the output end of the first inverter.

5. A variable frequency sampling low pass filter according to claim 4, wherein, The output end of the fifth register and the output end of the sixth register are connected with the input end of the XOR gate. The output end of the XOR gate is connected with the input end of the first register.

6. The variable frequency sampling low-pass filter of claim 1, wherein, The output end of the fifth register is connected with the first control end of the multiplexer.

7. The variable frequency sampling low-pass filter of claim 4, wherein, The output end of the sixth register is connected with the second control end of the multiplexer. The switch capacitor sampling filter circuit comprises a sampling switch and an RC filter circuit which are connected in sequence. The sampling switch is connected with the output end of the uncertain frequency signal generating circuit. The sampling switch comprises a first switch tube and a second switch tube. The source of the first switch tube and the source of the second switch tube are connected with a filter input end. The drain of the first switch tube and the drain of the second switch tube are connected with the RC filter circuit. The gate of the first switch tube is connected with the output end of the first inverter. The gate of the second switch tube is connected with the output end of the second inverter. The RC filter circuit comprises a resistor and a capacitor which are connected in sequence. One end of the sampling switch is connected with the filter input end. The other end of the sampling switch is connected with the ground through the resistor and the capacitor in sequence. The connection point of the resistor and the capacitor is a filter output end. The duty cycle of the uncertain frequency control clock signal is less than 1. The first switch tube is an NMOS tube, and the second switch tube is a PMOS tube.

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