Solid-state drives that support both byte-addressable and block-addressable protocols

Abstract

A solid-state drive (SSD) enabled to process and store block-addressable and byte-addressable data includes: a first storage area for storing byte-addressable data; a second storage area for storing block-addressable data; and an SSD controller coupled to the first storage area and the second storage area via a bus. The SSD controller includes a processor and an interface for receiving data packets from a host. The SSD controller receives a data packet from the host at the interface, determines at the processor whether the data packet contains byte-addressable data or block-addressable data, selects the first storage area or the second storage area based on the determination, and stores the data associated with the data packet in the selected storage area.

Description

Technical Field

[0001] The present invention generally relates to systems and methods for processing command packets utilizing a byte-addressable protocol or a block-addressable protocol. Background Art

[0002] A solid-state drive (SSD) includes a controller that allows the SSD to receive and process command packets from a central processing unit (CPU). The controller includes logic that allows the controller to decode and process received data packets. Typically, the logic allows the controller to process a specific type of command packet based on the available memory type and the internal hardware of the controller, SSD, and storage area.

[0003] Typically, SSDs use a storage protocol that is a block-addressable protocol. Block-addressable transfer protocols enable SSDs to read and write fixed data blocks, which were originally associated with hard disk protocols that stored fixed-size data blocks in sectors of hard disk platters addressed using logical block addresses (LBAs). Example protocols include Small Computer System Interface (SCSI) and Advanced Technology Attachment / Serial Advanced Technology Attachment (ATA / SATA). Later, specific protocols were introduced for SSDs that consist of non-volatile memory (NVM) but still retain the concept of transferring data in fixed-size blocks addressable by LBAs. Examples of NVM storage protocols include the Non-Volatile Memory Express (NVMe) protocol, which is a block-addressable protocol. In contrast, according to protocol standards such as Double Data Rate 3 (DDR3), Double Data Rate 4 (DDR4), etc., memory devices are attached to the CPU via a memory bus that uses a byte-level transfer protocol. Before the development of NVM technologies such as NAND flash memory, these devices were volatile, with examples including dual inline modules (DIMMs) consisting of dynamic random access memory devices (DRAM). More recently, persistent memory devices such as NVDIMMs (non-volatile DIMMs) have been developed that consist of both DRAM and NAND flash memory devices, but still employ a DDR-type byte-level protocol. Currently, SSDs are designed to process data according to only block-level transfer protocols, and memory devices are designed to process data according to only byte-level protocols.

[0004] Therefore, there has long been a need for an SSD that can efficiently process data packets using both byte-addressable and block-addressable protocols. Summary of the Invention

[0005] In one aspect, an SSD enabled to process and store block- and byte-addressable data includes a first storage area configured to store addressable data; a second storage area configured to store block-addressable data; and a controller communicatively coupled to the first and second storage areas via a bus. The controller includes a processor and an interface configured to receive a data packet from a host. The controller receives a data packet from the host at the interface, determines whether the data packet includes byte-addressable data or block-addressable data, and selects the first or second storage area based on the determination. The controller stores the data associated with the data packet in the selected storage area.

[0006] In another aspect, a method for storing data in an SSD having a first storage area for storing byte-addressable data, a second storage area for storing block-addressable data, and a controller communicatively coupled to the first and second storage areas via a bus, the method comprising: receiving a data packet from a host at an interface of the controller; and determining, at a processor of the controller, whether the data packet comprises byte-addressable data or block-addressable data. The method further comprises selecting either the first storage area or the second storage area based on the determination and storing the data associated with the data packet in the selected storage area. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A block diagram showing a hybrid SSD system that supports both byte-addressable and block-addressable protocols;

[0008] Figure 2 A block diagram showing the communication scheme between the hybrid SSD and the host CPU;

[0009] Figure 3 Demonstrating a decision method for decoding a data packet using a byte-addressable protocol or a block-addressable protocol;

[0010] Figure 4 Demonstrate a decision method for encoding a data packet using a byte-addressable protocol or a block-addressable protocol;

[0011] Figure 5 a block diagram showing exemplary byte-addressable command packet fields;

[0012] Figure 6 a block diagram showing exemplary read request specific packet fields; and

[0013] Figure 7 A flow chart showing a method for processing data packets utilizing a byte-addressable protocol or a block-addressable protocol is shown. DETAILED DESCRIPTION

[0014] SSD versatility and endurance can be improved by enabling the SSD to process and store data according to both byte-addressable and block-addressable protocols. Incorporating block and byte-addressable storage into an SSD improves the device's lifespan because if the byte-addressable storage becomes unavailable, the block-addressable storage can remain available. U.S. Patent Application No. 16 / 570,455, filed September 13, 2019, entitled "Reconfigurable SSD Storage Pool," which relates to the reclassification of storage devices in an SSD, is hereby incorporated by reference in its entirety.

[0015] Enabling an SSD to process and store data packets according to both block- and byte-addressable protocols requires equipping the SSD controller and storage to recognize and interpret data packets according to both protocols, and requires the SSD hardware and host to be able to transfer and store data packets.

[0016] Figure 1 A block diagram of a hybrid SSD system 100 supporting both byte-addressable and block-addressable protocols is shown. SSD system 100 includes an SSD 102 and a host 104 coupled via a bus 106. SSD 102 includes an SSD controller 108 having a processor 112, metadata registers 114, a packet decoder 121, and a block-addressable protocol controller 115 and a byte-addressable protocol controller 116. SSD 102 also includes an interface 111 and a memory 110 including a plurality of storage areas 118a through 118n. SSD controller 108 is coupled to the memory via a channel 117. Host 104 includes a host interface 120.

[0017] A channel or bus 106 couples a host 104 to an SSD 102. The host 104 transmits and receives data packets at a host interface 120. The data packets transmitted and received by the host include command packets and data for storage in the SSD 102, sometimes referred to as a command payload.

[0018] The SSD controller 108 receives data packets at the interface 111 and passes the data packets to the packet decoder 121. The packet decoder 121 determines the transmission protocol (byte addressable protocol or block addressable protocol) of the received data packet and passes the data packet to the appropriate protocol controller for encoding. The packet decoder 121 identifies whether the data packet contains an identifier indicating whether the content of the data packet is byte addressable or block addressable. If the packet decoder 121 determines that the data packet uses a byte addressable protocol, the packet decoder 121 passes the data packet to the byte addressable protocol controller 116 for decoding. If the packet decoder 121 determines that the data packet uses a block addressable protocol, the packet decoder 121 passes the data packet to the block addressable protocol controller 115 for decoding. The packet decoder 121 further updates the metadata register 114 with the type and destination of the data in the data packet. The method by which the packet decoder 121 determines the appropriate protocol for the data packet is described in more detail below.

[0019] When the packet decoder 121 identifies the data packet as byte-addressable, the byte-addressable protocol controller 116 processes the data packet by decoding the header and data in the data packet and transferring the data to the appropriate memory area of ​​the plurality of memory areas 118a to 118n. The byte-addressable protocol controller 116 prompts the processor 112 to update the metadata register 114 with the byte-addressable information. As will be explained below, in some embodiments, if the data packet does not include an identifier regarding the type of transport protocol, the packet decoder 121 defaults to transferring the data packet to the byte-addressable protocol controller 116. In some embodiments, the byte-addressable protocol controller 116 is a Gen-Z byte-addressable protocol controller.

[0020] When the packet decoder 121 identifies the data packet as block addressable, the block addressable protocol controller 115 processes the data packet by decoding the header and data in the data packet and transferring the data to the appropriate storage area in the plurality of storage areas 118a to 118n. The block addressable protocol controller 115 may prompt the processor 112 to update the metadata register 114. The packet decoder 121 may also provide feedback or confirmation to the host 104. In some embodiments, the block addressable protocol controller 115 is an NVMe Over Fabric block addressable protocol controller.

[0021] Although the byte addressable protocol controller 116 and the block addressable protocol controller 115 are shown in FIG. Figure 1108, the protocol controller may actually include multiple logical blocks within the SSD controller 108. The byte-addressable protocol controller 116 and the block-addressable protocol controller 115 each have the ability to decode header fields, decode specific transport protocol commands, and process, execute, and transmit data and commands for the byte-addressable protocol and the block-addressable protocol, respectively, within the SSD 102. In addition, although the packet decoder 121 is not shown in FIG. Figure 1 108, but the packet identification and routing functions of packet decoder 121 may be implemented as dedicated hardware logic located within interface 111 or byte-addressable protocol controller 116 to increase the speed of identification, classification, and packet routing in the SSD.

[0022] Within the SSD controller 108, the Gen-Z SSD 102 includes a dedicated hardware-based NVMe Over Fabric protocol encoding and decoding acceleration engine, which may be part of the block-addressable protocol controller 115. The SSD controller 108 and the block-addressable protocol controller 115 intercept NVMe Over Fabric protocol commands and command payloads embedded within Gen-Z command packets. Implementing the NVMe Over Fabric protocol encoding and decoding logic within the SSD controller 108 results in lower latency than systems that would separately include NVMe Over Fabric protocol logic in CPU software. Routing and classification of incoming packets can be implemented in hardware logic within the interface 111 to further reduce latency. The implementation of the NVMe Over Fabric protocol within the Gen-Z SSD 102, built on top of the Gen-Z protocol fabric, uses modified Gen-Z commands to exchange NVMe Over Fabric protocol commands and data. By using a unique operator class (OpClass) and operator code (OpCode) that may be manufacturer or vendor specific, a unique identifier is added to the data packet, allowing the Gen-Z SSD 102 to be classified using the conventional NVMe OverFabric protocol and use the block-addressable storage areas within the plurality of storage areas 118a to 118n for device discovery, data exchange, and error recovery processes. A packet decoder 121 is provided to receive and interpret the vendor-defined OpClass packet format containing various vendor-defined fields to identify the contents and protocol of the packet. In some embodiments, the NVMe OverFabric protocol may be provided by a software API on the emulated network interface of the SSD 102.

[0023] Data encoding may occur in SSD controller 108 for transmission to host 104, as well as in host 104 before data packets and commands are transmitted to SSD 102. Encoding of data packets and commands will be discussed below with respect to Figure 4 Briefly, to process block addressable protocol packets, block addressable protocol commands and data are encapsulated in byte addressable protocol command packets, as will be discussed below with respect to Figures 4 to 6 Description: An identifier within the header of a data packet indicates whether the command is a byte-addressable protocol command or whether the byte-addressable protocol data packet carries a block-addressable command and / or a command payload.

[0024] Each of the plurality of storage areas 118a to 118n is identified as a byte-addressable storage area or a block-addressable storage area and is identified in the metadata register 114. The plurality of storage areas 118a to 118n includes a first storage area 118a identified as a byte-addressable storage area and configured to store byte-addressable data and a second storage area 118b identified as a block-addressable storage area and configured to store block-addressable data. In some embodiments, the plurality of storage areas 118a to 118n is a hybrid storage memory, such as a storage class memory (SCM). In some embodiments, the plurality of storage areas 118a to 118n is a non-volatile flash memory. In some embodiments, the plurality of storage areas 118a to 118n is a dynamic random access memory (DRAM).

[0025] In some embodiments, bus 106 may be formed as a serializer / deserializer (SerDes) link that communicatively couples interface 111 of SSD 102 to host interface 120 of host 104. The SerDes link or interconnect coupling SSD 102 to host 104 at bus 106 is enabled to transfer data packets using both byte-addressable and block-addressable transfer protocols. For example, in some embodiments, the SerDes link is enabled to transfer data using the Gen-Z byte-addressable transfer protocol and to transfer data packets using the NVMe Over Fabric block-addressable protocol. SSD controller 108 supports storage of data packets using either byte- or block-addressable protocols by allowing byte-addressable commands and block-addressable NVMe Over Fabric protocols to operate on the same high-speed SerDes link.

[0026] SSD 102 implements the use of both byte-addressable and block-addressable protocols for storing data, allowing applications that run both byte-addressable commands and block-addressable protocols (such as the NVMe Over Fabric protocol) to work with SSD 102. Implementing the use of both byte-addressable commands and block-addressable protocols on a single SSD uses a single bus 106, such as a single SerDes link, and requires a small number of on-chip pins to implement. Conventional systems may require a much higher pin count on the host CPU and SSD, or require additional parallel buses or SerDes links. Therefore, an SSD that enables byte-addressable commands and block-addressable protocols has much higher bandwidth and much lower latency than a conventional SSD that only allows NVMe block storage via a SerDes link without the ability to handle byte-addressable protocols. SSD 102 can be used in consumer electronic devices, such as mobile phones, tablets, set-top boxes, dense servers, or high-performance computing (HPC) servers.

[0027] The SSD controller 108 may be instantiated as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) in which the functionality is provided by dedicated hardware logic gates. In some embodiments, some functions of the SSD controller 108 may be implemented as firmware running on the processor 112 or as microcode running on the block protocol controller 115 and the byte addressable protocol controller 116. The SSD controller 108 includes block addressable protocols, such as NVMe Over Fabric protocol encoding and decoding logic within the ASIC or FPGA. In some embodiments, block addressable protocols, such as NVMe Over Fabric protocol encoding and decoding, are performed in the SSD controller 108 in an encoding / decoding acceleration engine that intercepts or receives transmitted commands identified as containing block addressable protocols. The host 104 also includes embedded CPU resources that enable the host 104 to communicate with the SSD 102 and encode, decode, and process block addressable and byte addressable protocols.

[0028] Figure 2 A block diagram illustrating a communication scheme 200 between a hybrid SSD 202 and a host CPU 204 is shown. A bus 206 (e.g., Figure 1 The bus 106 in the Figure 1 ) coupled to a host CPU 204 (e.g. Figure 1 The hybrid SSD 202 includes a processor or controller capable of receiving, decoding, and processing block-addressable and byte-addressable commands. The host CPU 204 includes an interface for transmitting and receiving data packets to and from the hybrid SSD 202.

[0029] In some embodiments, the hybrid SSD 202 is a hybrid Gen-Z SSD that includes the ability to handle both Gen-Z byte-addressable commands and NVMe Over Fabric block-addressable commands. Bus 206, which can be a SerDes link or other channel, communicatively couples the hybrid SSD 202 to the CPU host 204, enabling both byte-addressable commands and block-addressable data protocols to be transmitted between the hybrid SSD 202 and the CPU host 204. In some implementations, bus 206 can be a Gen-Z SerDes. Both block-addressable and byte-addressable protocol commands run on top of bus 206 between the host CPU 204 and the hybrid SSD 202. The Gen-Z SerDes is able to transmit commands by encapsulating block-addressable protocol commands and command payloads within byte-addressable command packets. The hybrid Gen-Z SSD is then able to identify the protocol required to process the command and direct the data packet or command to the appropriate protocol controller within the SSD controller for further processing and storage.

[0030] Figure 3 A decision diagram 300 is shown for a method of decoding a data packet using a byte addressable protocol or a block addressable protocol. In step 302, a Gen-Z protocol packet decoder (e.g., Figure 1 The packet decoder 121 in the Figure 1 Host 104, Figure 2 The decoding process begins when a data packet is received from a CPU host 204 in the Gen-Z protocol. The Gen-Z protocol packet decoder can be used in conjunction with a general byte addressable protocol decoder (e.g. Figure 1 byte addressable protocol controller 116 in) or an SSD controller (e.g. Figure 1 The Gen-Z protocol packet decoder is formed as logic, microcode, or firmware in the SSD controller 108. In step 304, the decoder determines whether a Gen-Z identifier is detected in the received data packet. In some embodiments, the decoder determines whether a Gen-Z identifier is present by decoding a header field of the data packet and determining the presence of a unique identifier indicating that the data packet carries a Gen-Z command and command payload. The decoder can identify the presence of a unique vendor-specified OpClass or OpCode, as will be further described below. If the decoder determines that the data packet contains a Gen-Z identifier, such as a unique OpClass and OpCode, then in step 306, the decoder transmits the data packet to a Gen-Z identifier controller within the SSD controller 108. The Gen-Z identifier controller can be a universal byte-addressable protocol controller (e.g., Figure 1In step 310, the Gen-Z identifier controller passes the data packet to the Gen-Z byte addressable protocol controller (e.g., byte addressable protocol controller 116 in the SSD controller) or another controller within the SSD controller 108. Figure 1 byte addressable protocol controller 116 in the packet), wherein the data and commands contained in the packet are processed and stored in the appropriate memory area if necessary. In step 312, the metadata is stored, for example, in a metadata register (e.g. Figure 1 The metadata register 114 is updated to indicate the storage of the command or command payload. If necessary, the SSD controller 108 sends feedback to the host 104 encoder at step 318, and finally, at step 316, the Gen-Z protocol packet decoder method ends.

[0031] If the decoder determines that the data packet does not contain a Gen-Z identifier, then at step 308, the decoder determines whether the data packet contains an NVMe Over Fabric identifier. For example, Figure 5 and 6 Describe this identifier. The unique identifier in the header field of the data packet indicates that the data packet contains an NVMe Over Fabric command or payload within a Gen-Z command packet. If the decoder does not recognize the NVMe Over Fabric identifier in the header field of the data packet, the decoder defaults to treating the data packet as a Gen-Z data packet containing a Gen-Z protocol command and payload, and proceeds to step 310 to process the Gen-Z data packet as described above.

[0032] If the decoder recognizes the NVMe Over Fabric identifier in the data packet header field, then at step 314, the decoder passes the data packet to the NVMe Over Fabric block addressable protocol controller (e.g., Figure 1 The NVMe Over Fabric block-addressable protocol controller 115 processes, executes, and stores the NVMe Over Fabric command and command payload as needed. The NVMe Over Fabric block-addressable protocol controller 115 then updates the metadata register 114 or prompts the SSD controller 108 to update the register 114 at step 312, provides feedback to the host encoder at step 318 as needed, and ends the method at step 316.

[0033] While the method for decoding data packets is described with respect to the specific transport protocols of the Gen-Z byte-addressable protocol and the NVMe Over Fabric block-addressable protocol, the same principles of the method can be used with other pairs of transport protocols. The first transport protocol of SSD 102 and SSD controller 108 can be used to encapsulate commands with the second transport protocol, and a unique identifier in the header field of the data packet can be used to identify that the first transport protocol data packet carries the command and command payload using the second transport protocol. In this way, SSD 102 and SSD controller 108 can work with commands with multiple transport protocols to efficiently process commands from host 104.

[0034] Specifically, the received data packet may be a Gen-Z large read (LDM1), a large write MSG command, or a vendor-defined OpClass and OpCode. The vendor-defined OpClass and OpCode enable the transfer of control plane information between the host 104 and the SSD 102, including SSD internal metadata and controller operations. Such identifiers will be discussed below with respect to Figure 5 and 6 As further described, the host 104 encodes data packets for transmission to the SSD 102, thereby encapsulating block-addressable protocol commands and command payloads (e.g., NVMe Over Fabric protocol commands) within byte-addressable protocol data packets. The host uses a unique identifier to indicate the presence of block-addressable protocol commands and command payloads within the data packets. In some embodiments, the SSD 102 can also encode commands for transmission to the host, such as encoding block-addressable protocol commands and command payloads within byte-addressable protocol command packets.

[0035] Figure 4 A method 400 for deciding whether to encode a data packet using a byte-addressable protocol or a block-addressable protocol is shown. This method is typically used when the data packet is transmitted to an SSD (e.g., Figure 1 SSD 102, Figure 2 The hybrid SSD 202 in the host (eg Figure 1 Instance host 104, Figure 2 The encoding of the Gen-Z protocol packets may occur within the CPU host 204 in the SSD 102, but as described above, in some embodiments, the SSD 102 may also be capable of encoding data packets. Thus, the Gen-Z protocol packet encoder may be located within the host 104, or in some embodiments, may be located within the SSD controller (e.g., Figure 1 In some embodiments, the Gen-Z protocol packet encoder may be a byte-addressable protocol controller (e.g., Figure 1 Part of the byte-addressable protocol controller 116).

[0036] The method begins at step 402, where the Gen-Z protocol packet encoder begins encoding commands or command payloads into data packets for transmission. At step 404, the host 104 determines whether the target SSD 102 has notified the host of any changes to the state of the SSD 102 or the storage areas within the SSD 102 that would limit the SSD 102's ability to process block-addressable protocol commands or command payloads. If there has been a state change, then at step 406, the host 104 utilizes the Gen-Z identifier encoder controller to encode the data packet header fields normally using the byte-addressable protocol. In some implementations, the Gen-Z identifier encoder controller is part of the byte-addressable protocol controller 116 within the SSD controller 108. In some implementations, this may include inserting a unique identifier into the data packet header fields that identifies the packet as using the Gen-Z protocol, such as a unique vendor-defined OpClass and / or OpCode that identifies the packet as a Gen-Z protocol packet. The vendor-defined OpClass and OpCode may also pass control plane information such as SSD internal metadata and special controller operations from the host 104 to the SSD 102. In other embodiments, the Gen-Z identifier encoder controller may not add any unique identifier to the header field, and the lack of a unique identifier will be interpreted by the SSD controller 108 as an indication that the data packet uses the Gen-Z protocol. At step 408, the Gen-Z identifier encoder controller transmits the data packet to the Gen-Z byte addressable protocol controller 116 for encoding the command and command payload. At step 410, the host 104 updates the metadata of the data packet, and at step 420, the Gen-Z protocol packet encoder is complete and the data packet can be transmitted to the SSD 102.

[0037] If there is no state change at step 404, the host 104 determines whether it is necessary to encapsulate the NVMe Over Fabric block addressable protocol in a Gen-Z protocol packet. The host 104 determines whether there is an NVMe Over Fabric block addressable command or command payload to be transmitted. If there is no NVMe Over Fabric block addressable command or command payload to be transmitted, then at step 408, the host 104 passes the command to the Gen-Z byte addressable protocol controller 116 and continues encoding the Gen-Z byte addressable command normally.

[0038] If the host 104 determines that there is an NVMe Over Fabric block addressable command or command payload to be transmitted, then at step 414, the host 104 utilizes the NVMe Over Fabric block addressable protocol controller (e.g., Figure 1 The block-addressable protocol controller 115 in the host 104 processes the command and command payload and encapsulates the command and command payload into a Gen-Z command packet. Next, in step 416, the host 104 sets an identifier in the data packet header field to identify the presence of an NVMe Over Fabric block-addressable command and command payload in the data packet, for example, using a vendor-defined OpClass or OpCode as described above to indicate the presence of an NVMe Over Fabric block-addressable command and command payload. In step 418, the NVMe Over Fabric payload controller finalizes the data packet, and in step 410, the host 104 completes the metadata. The Gen-Z protocol packet encoder method then ends in step 420.

[0039] In some embodiments, feedback is provided from the updated metadata 410 to the host 104 throughout the process, such that the host 104 uses the metadata to determine at step 404 whether there was a state change.

[0040] As mentioned above about Figure 3 , the method for encoding data packets is described herein with respect to the specific transport protocols of the Gen-Z byte-addressable protocol and the NVMe Over Fabric block-addressable protocol, but the same principles of the method can be used with other paired transport protocols. The first transport protocol of SSD 102 and SSD controller 108 can be used to encapsulate commands having a second transport protocol, and a unique identifier in the header field of the data packet can be used to identify that the first transport protocol data packet carries the command and command payload using the second transport protocol. In this way, SSD 102 and SSD controller 108 can work with commands having multiple transport protocols to efficiently process commands from the host.

[0041] Figure 5 A block diagram 500 is shown that includes details of specific fields for identifying byte-addressable data or command packets of the command packet protocol. The specific fields of the command packet have a field name 530, a field abbreviation 532, a bit size 534, and a description 536. Row 538 includes a 5-bit R0 field with a reserved description. The specific fields are fields of byte-addressable command packets, but the fields can be used to identify that a byte-addressable command packet contains a command payload that carries a block-addressable command and payload.

[0042] However, any type of suitable identifier may be included in the data packet header to indicate to the SSD's processor or data packet decoder (e.g., Figure 1The processor 112 or packet decoder 212 in the SSD controller 108 in FIG. 1 identifies whether the data packet uses a byte-addressable protocol or a block-addressable protocol, and an example identifier is described herein. The identifier can be, for example, a unique value added to the header of the command within the 5-bit R0 reserved field to identify the command as a block-addressable command packet.

[0043] By utilizing specific fields of the byte-addressable command packet to identify the protocol of the command payload carried by the packet, the packet decoder 121 is able to determine how to process the command, such as determining which protocol controller (e.g., Figure 1 The byte addressable protocol controller 116 and the block addressable protocol controller in the processor are used to decode or transmit commands. The packet decoder 121 can be implemented in a processor (e.g. Figure 1 112 in the SSD), in the SSD controller 108, or in an interface of the SSD (e.g. Figure 1 Packet decoder 121 may be implemented as hardware logic to quickly process, classify, and route incoming data packets.

[0044] Another example of a specific field for identifying a byte addressable command packet for a read request is in Figure 6 Instructions. Figure 6 The block diagram 600 in FIG. 1 lists multiple fields as rows, and lists a field name column 630, a field abbreviation column 632, a bit size column 634, and a field description column 636. The first row 638 contains additional information for a read request specific command packet. The field RD size is 32 bits, and the field description of the field RD size indicates the number of bytes to be read based on the read request. The second row 640 contains a field R0 that is 9 bits in size and has a reserved description. The third row 642 contains a field R1 that is 6 bits in size and has a reserved description.

[0045] like Figure 5 , a read-specific data packet may include an identifier to indicate to packet decoder 121 whether the command payload is block addressable or byte addressable. For example, a unique 6-bit R1 field identifier in a command packet may be used to indicate to packet decoder 121 that a byte addressable command carries a block addressable protocol command and payload. In some embodiments, the identifier may indicate a Gen-Z command packet and that a Gen-Z command carries an NVMe Over Fabric protocol command and payload. The unique identifier may be any number of bits and may be located in any available field in the data packet header, as programmed by the manufacturer or vendor to enable SSD controller 108 to locate the identifier. Figure 5 and 6 The identifiers described in are exemplary only.

[0046] The identifier in the command packet can be read by packet decoder 121 within SSD controller 108 or interface 111 to determine that a byte-addressable command packet (e.g., a Gen-Z command packet) carries a block-addressable protocol (e.g., an NVMe Over Fabric protocol) command and payload. After packet decoder 121 has made this determination based on decoding of the command packet header fields, packet decoder 121 transmits the command to the appropriate protocol controller within SSD controller 108 for further processing and storage.

[0047] To achieve high line rate performance, such as Figure 1 The block-addressable protocol (e.g., NVMe Over Fabric) encoding and decoding acceleration engine described in

[15] is implemented using dedicated ASIC or FPGA logic. SSD 102 is therefore capable of encoding and decoding byte-addressable protocols, as well as block-addressable protocols if encapsulated within byte-addressable protocols.

[0048] Figure 7 A flow chart illustrating a method 700 for processing data packets using a byte addressable protocol or a block addressable protocol. In step 702, an SSD controller (e.g., Figure 1 The SSD controller 108 in the SSD controller interface (eg Figure 1 interface 111 in the host (eg Figure 1 Host 104, Figure 2 The CPU host 204 in the embodiment receives a first data packet. The first data packet is a byte-addressable data packet, but the command and payload within the data packet can be encoded for storage according to a block-addressable protocol or a byte-addressable protocol.

[0049] At step 704, the SSD controller 108 determines whether the first data packet contains byte addressable or block addressable protocol data and commands. The SSD controller 108 includes a packet decoder (e.g., Figure 1 The packet decoder 121 in the SSD controller or the processor 112 (e.g., processor 112) decodes the header of the first data packet to identify whether the first data packet includes an identifier indicating that the first data packet is encoded according to a block addressable protocol or a byte addressable protocol. The packet decoder can be implemented as a separate controller within the SSD controller, or can be implemented as hardware logic in the controller or interface to more quickly classify and route incoming data packets. As described above with respect to Figure 5 and 6As described above, a unique identifier may be found within the header of a data packet to indicate the protocol used in the command. The unique identifier may be or may utilize a vendor-defined OpClass and OpCode to identify the protocol of the command and command payload. In some embodiments, after SSD Controller 108 identifies the appropriate transport protocol for the data packet, SSD Controller 108 utilizes a block-addressable protocol controller / decoder (e.g., Figure 1 A block addressable protocol controller 115 in ) or a byte addressable protocol controller / decoder (e.g. Figure 1 The byte addressable protocol controller 116 in further processes the first data packet.

[0050] At step 706, the packet decoder 121 selects one of the first storage area and the second storage area for storing the first data packet based on the determination at step 704. The first storage area may be a byte-addressable storage area (e.g., Figure 1 118a in the memory area), and the second memory area may be a block-addressable memory area (e.g. Figure 1 The selection of the first or second storage area is based on the determination of step 706 whether the first data packet contains byte-addressable data or block-addressable data.

[0051] At step 708, data associated with the first data packet is transferred to a selected one of the first and second memory areas. At step 710, data associated with the first data packet is stored in the selected memory area.

[0052] In some embodiments, a register (e.g. Figure 1 The metadata in the register 114 in is updated to reflect the storage location of the first data packet and the transmission protocol determined for the first data packet.

[0053] Enabling SSD controller 108 to accept data packets containing byte-addressable or block-addressable data and appropriately identifying which protocol the data packet uses results in a versatile SSD capable of processing and storing data according to different protocols. Users can use the SSD in a more diverse manner and with greater efficiency due to the ability to process both block-addressable and byte-addressable data.

[0054] If an SSD is equipped to receive and process commands according to both byte-addressable and block-addressable protocols, a more versatile and efficient SSD can be provided for use with complex applications. By enabling byte-addressable commands and block-addressable protocols to be processed by a single SSD and transmitted to the SSD via a single bus 106, such as a single SerDes link, fewer on-chip pins are required for implementation. Conventional systems may require a much higher pin count on the host CPU and SSD or require additional parallel buses or SerDes links. Therefore, an SSD that enables byte-addressable commands and block-addressable protocols has much higher bandwidth and much lower latency than a conventional SSD that allows NVMe block storage via a SerDes link without the need for a byte-addressable protocol. An SSD that enables both byte-addressable and block-addressable protocols can be used in consumer electronics devices to achieve greater efficiency in processing and storing commands and data.

[0055] Other objects, advantages, and embodiments of various aspects of the present invention will be apparent to those skilled in the art and are within the scope of the description and drawings. For example, but not limitation, structural or functional elements may be rearranged in accordance with the present invention. Similarly, the principles of the present invention may be applied to other embodiments, which, even if not specifically described in detail herein, are still within the scope of the present invention.

Claims

1. A solid state drive (SSD) enabled to process and store block-addressable and byte-addressable data, the SSD comprising: a first memory area configured to store byte-addressable data; a second memory area configured to store block-addressable data; a controller communicatively coupled to the first storage area and the second storage area via a bus, the controller comprising: processor; and an interface configured to receive data packets from a host; wherein the controller is configured to: receiving, at the interface, a data packet from the host, the data packet including a header identifying a Gen-Z transport protocol used by the data packet; determining, at the processor, based on the header, whether the data packet contains byte-addressable data or block-addressable data; selecting the first storage area or the second storage area based on the determination; and Data associated with the data packet is stored in the selected memory area. 2 . The SSD of claim 1 , wherein the controller further comprises a decoder configured to decode data packets.

3. The SSD of claim 2, wherein the controller is further configured to decode the data packet at the decoder, and wherein determining whether the data packet includes byte-addressable data or block-addressable data is based on the decoding of the data packet. The SSD of claim 1 , wherein the controller is further configured to detect a header of the data packet. 5 . The SSD of claim 4 , wherein the header of the data packet includes an indication of whether the data packet uses a first transfer protocol or a second transfer protocol, wherein the second transfer protocol is different from the first transfer protocol.

6. The SSD of claim 5, wherein the controller is further configured to determine whether the data packet includes byte-addressable data or block-addressable data based on the indication of whether the data packet uses the first transfer protocol or the second transfer protocol.

7. The SSD of claim 6, wherein the first transmission protocol is a Gen-Z transmission protocol and the second transmission protocol is a Non-Volatile Memory Express (NVMe) Over Fabric transmission protocol.

8. The SSD according to claim 5, wherein the controller further comprises an NVMe Over Fabric transport protocol controller implemented in a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). 9 . The SSD of claim 1 , wherein the first storage area and the second storage area are implemented as storage class memories (SCMs).

10. The SSD of claim 1, wherein the first storage area and the second storage area are implemented as non-volatile flash memory.

11. The SSD of claim 1, wherein the controller is further configured to transmit the data associated with the data packet to the selected storage area via a serializer / deserializer (SerDes) link.

12. The SSD of claim 1, wherein the controller further comprises a register configured to include metadata address information for data stored in the first storage area and the second storage area, and wherein the controller is further configured to update metadata associated with the stored data in the register.

13. A method for storing data in an SSD, the SSD having a first storage area configured to store byte-addressable data, a second storage area configured to store block-addressable data, and a controller communicatively coupled to the first storage area and the second storage area via a bus, the method comprising: receiving, at an interface of the controller, a data packet from a host, the data packet including a header identifying a Gen-Z transport protocol used by the data packet; determining, at a processor in the controller based on the header, whether the data packet contains byte-addressable data or block-addressable data; selecting either the first storage area or the second storage area based on the determination; and Data associated with the data packet is stored in the selected memory area.

14. The method of claim 13, further comprising transmitting the data associated with the data packet to the selected memory area via a SerDes link.

15. The method of claim 13, further comprising: detecting a header of the data packet; and An indication of whether the data packet uses a first transport protocol or a second transport protocol is identified in the header of the data packet, wherein the second transport protocol is different from the first transport protocol.

16. The method of claim 15, wherein the first transport protocol is a Gen-Z transport protocol and the second transport protocol is an NVMe Over Fabric transport protocol.

17. The method according to claim 16, further comprising: If the header of the data packet includes an indication that the data packet uses the NVMe Over Fabric transport protocol, then: Transmitting the data packets to the NVMe Over Fabric transport protocol controller; Processing the data packet at the NVMe Over Fabric transport protocol controller; and Data associated with the data packet is transferred to the second memory area as block-addressable data.

18. The method of claim 17, further comprising: If the header of the data packet includes an indication that the data packet uses the Gen-Z transport protocol, then: Transmitting the data packet to a Gen-Z transport protocol controller; processing the data packet at the Gen-Z transport protocol controller; and Data associated with the data packet is transferred to the first memory area as byte-addressable data.

19. The method of claim 16, further comprising: Metadata associated with the data associated with the data packet and the selected first memory area or second memory area is updated in a register.

20. A method for decoding Gen-Z data packets in a solid-state drive (SSD), the method comprising: Receive data packets from the host; determining that the data packet does not include a first indicator that the data packet requires a Gen-Z transport protocol for storing the data packet; and determining that the data packet includes a second indicator that the data packet requires a non-volatile memory express (NVMe) OverFabric transport protocol for storing the data packet; and Storing the data of the data group in a block-addressable storage area of ​​the SSD; The SSD is configured to store block-addressable data requiring the NVMe Over Fabric transport protocol and byte-addressable data requiring the Gen-Z transport protocol.

21. The method of claim 20, further comprising: The data packet is decoded.

22. The method of claim 21, further comprising: decoding the data packet at a decoder; and Based on the decoding of the data packet, it is determined whether the data packet contains byte-addressable data or block-addressable data.

23. The method of claim 20, further comprising: A header of the data packet is detected.

24. The method of claim 23, wherein the header of the data packet includes an indication of whether the data packet uses a first transport protocol or a second transport protocol, wherein the second transport protocol is different from the first transport protocol.

25. The method of claim 24, further comprising: Based on the indication of whether the data packet uses the first transfer protocol or the second transfer protocol, it is determined whether the data packet contains byte-addressable data or block-addressable data.

26. The method of claim 25, wherein the first transport protocol is the Gen-Z transport protocol and the second transport protocol is a Non-Volatile Memory Express (NVMe) Over Fabric transport protocol.

27. The method of claim 20, further comprising: The data associated with the data packet is transferred to the selected memory area via a SerDes link.

28. The method of claim 20, further comprising: Metadata associated with the stored data is updated in a register configured to contain metadata address information for the stored data.

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