Shaping and optimized power cycling

Abstract

The system and method according to the present disclosure determines the duration of the current command queue in the controller, executes all complete commands that can be executed before the low power cycle begins. When the device enters power mode, the unexecuted commands can be fetched. In an alternative embodiment, a portion of the commands that can be executed before the low power cycle begins are executed, where the unexecuted portion of the commands are stored on the device, in an Always On (AON) memory. When the device enters power mode, the unexecuted portion is fetched and executed.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Application No. 16 / 883897, filed May 26, 2020, the entire contents of which are incorporated herein by reference. Background Technology Technical Field

[0004] The embodiments disclosed herein generally relate to power management in computer devices, and more specifically to optimizing power duty cycle management in computing devices.

[0005] Description of the Related Art

[0006] In the field of computing device power management, and specifically for mobile device power management, smaller devices with higher component complexity require more optimized power management to maintain battery power, reduce heat generation, and utilize resources in the best way. For these devices, it is beneficial to disconnect power from unused components (e.g., storage devices such as SSDs and other PCIe devices), or to power components that may be in use according to their duty cycle.

[0007] In existing methods, the power management of a component provides full power (i.e., power mode) to the component for a limited period of time, and then places the component in a low-power or "deep sleep" mode for another limited period of time. In these methods, to prepare for the low-power mode, all commands in the controller's command queue need to be completed; during this period, no additional commands are processed or received. Once all commands are completed, the component enters the low-power mode. Because the component is in power mode to execute the remaining commands, this delay in processing all remaining commands shortens the time the component can remain in low-power mode.

[0008] When transitioning from low-power mode to power mode, no commands are available in the controller, which must retrieve the next command from the host or other devices. This delay in executing any command causes a latency in the component, and the component's resources are in a dormant state (i.e., not executing commands), resulting in these resources being wasted when idle.

[0009] What is needed is a system and method for optimizing the execution of pending commands so that it can enter low-power mode more quickly and make efficient use of component resources immediately upon entering power mode. Summary of the Invention

[0010] This disclosure generally relates to systems and methods for power cycle optimization. The disclosed embodiments determine the duration of the current command queue in the controller and execute all complete commands that can be executed before the start of a low-power cycle. When the device enters a power mode, unexecuted commands can be retrieved. In an alternative embodiment, a portion of the commands that can be executed before the start of a low-power cycle is executed, wherein the unexecuted portion of the commands is stored on the device in an "always-on" (AON) memory. When the device enters a power mode, this unexecuted portion is retrieved and executed.

[0011] In one embodiment, the data storage device includes one or more memory devices and a controller coupled to the one or more memory devices. The controller is configured to receive a plurality of commands from a host at the data storage device, including a power decay time. The controller is also configured to calculate the expected execution duration of each of the plurality of commands, select the command whose duration will not exceed the power decay time from the plurality of commands, execute the command, and cause the data storage device to enter a power decay state during the power decay time.

[0012] In another embodiment, the data storage device includes one or more memory devices and a controller coupled to the one or more memory devices. The controller is configured to receive a plurality of commands from a host at the device, including a power fall time and a power rise time. The controller is also configured to calculate the expected execution duration of each of the plurality of commands, select from the plurality of commands a command whose duration will exceed the device's power fall time, execute a portion of that command that can be executed before the power fall time, and the device enters a power fall state at the power fall time.

[0013] In another embodiment, a system for controlling the power consumption of a device is disclosed. The system includes means for receiving a command from a host at the device, means for calculating the duration of the command, and means for determining the power decay time of the device. The system also includes means for selecting a command, means for determining whether the duration of the command will exceed the power decay time, and means for executing the command. The system may further include means for updating the power decay time of the device based on the duration of the command, and means for placing the device in a power decay state based on the power decay time. Attached Figure Description

[0014] Therefore, a detailed understanding of the foregoing features of this disclosure, a more specific description of this disclosure, and the foregoing brief overview can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of this disclosure and should therefore not be considered as limiting its scope, as this disclosure allows for other equally effective embodiments.

[0015] Figure 1 It is a schematic diagram of a computing system including host devices and storage devices according to the disclosed implementation scheme.

[0016] Figure 2 This is a schematic diagram of a data storage device according to the disclosed implementation scheme.

[0017] Figure 3 This is an example diagram of the power duty cycle based on the disclosed implementation scheme.

[0018] Figure 4 This is an example diagram based on the power duty cycle, related command execution, and data rate of existing methods.

[0019] Figures 5A-5B It is a flowchart for power cycle command optimization based on the disclosed implementation scheme.

[0020] Figure 6 It is based on the data and control path for power cycle optimization according to the disclosed implementation scheme.

[0021] Figure 7 A method for performing power cycle optimization using commands according to the disclosed implementation is shown.

[0022] Figure 8 A method for power cycle optimization using partial command execution according to the disclosed implementation is shown.

[0023] Figure 9 This is an example diagram showing the power duty cycle, related command execution, and data rate based on the disclosed implementation scheme.

[0024] For ease of understanding, the same reference numerals are used where possible to denote the same elements common in the accompanying drawings. It is conceivable that elements disclosed in one embodiment may be advantageously used in other embodiments without specific description. Detailed Implementation

[0025] In the following text, reference is made to embodiments of this disclosure. However, it should be understood that this disclosure is not limited to the specifically described embodiments. Rather, consider any combination of the following features and elements (whether or not related to different embodiments) to achieve and practice this disclosure. Furthermore, while embodiments of this disclosure may achieve advantages over other possible solutions and / or over the prior art, achieving a particular advantage through a given embodiment is not a limitation of this disclosure. Therefore, the following aspects, features, embodiments, and advantages are illustrative only and should not be considered elements or limitations of the appended claims unless expressly stated in the claims. Similarly, reference to “this disclosure” should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered elements or limitations of the appended claims unless expressly stated in the claims.

[0026] The system and method of this disclosure determine the duration of the current command queue in the controller and execute all complete commands that can be executed before the start of a low-power cycle. When the device enters power mode, any unexecuted commands can be retrieved. In an alternative embodiment, a portion of the commands that can be executed before the start of a low-power cycle is executed, wherein the unexecuted portion of the commands is stored on the device in an "always-on" (AON) memory. When the device enters power mode, this unexecuted portion is retrieved and executed. In some embodiments, completely unexecuted commands may be stored in AON memory.

[0027] Figure 1 This is a schematic block diagram illustrating a storage system 100 according to one or more technologies of the present disclosure, wherein data storage device 106 can be used as a storage device for host device 104. For example, host device 104 can utilize non-volatile memory device 110 included in data storage device 106 to store and retrieve data. Host device 104 includes host DRAM 138. In some examples, storage system 100 may include multiple storage devices, such as data storage device 106, that can operate as a storage array. For example, storage system 100 may include multiple data storage devices 106 configured to collectively serve as a low-cost / independent disk (RAID) redundant array of high-capacity storage devices for host device 104.

[0028] Host device 104 may include any of the broad range of devices, including computer servers, network attached storage (NAS) units, desktop computers, laptops, tablets, set-top boxes, mobile phones such as so-called "smart" phones, so-called "smart" tablets, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, etc.

[0029] Data storage device 106 includes a controller 108, non-volatile memory (NVM) 110, a power supply 111, volatile memory 112, an interface 114, and a buffer 116. The controller 108 includes internal memory or the buffer 116. In some examples, for clarity, data storage device 106 may include... Figure 1 Additional components not shown. For example, data storage device 106 may include a printed circuit board (PB) to which components of data storage device 106 are mechanically attached, and the PB includes conductive traces for electrically interconnecting components of data storage device 106, etc. In some examples, the physical dimensions and connector configuration of data storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, 3.5″ data storage devices (e.g., HDDs or SSDs), 2.5″ data storage devices, 1.8″ data storage devices, peripheral component interconnect (PCI), PCI expansion (PCI-X), PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe mini cards, MiniPCI, etc.). In some examples, data storage device 106 may be directly coupled (e.g., directly soldered) to the motherboard of host device 104.

[0030] The interface 114 of the data storage device 106 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc.

[0031] Electrical connections (e.g., a data bus, a control bus, or both) to interface 114 are electrically connected to controller 108, thereby providing an electrical connection between host device 104 and controller 108, allowing data exchange between host device 104 and controller 108. Interface 114 can be a connection unit for transferring data from host device 104 to data storage device 106 and vice versa. Such a connection unit can be a USB-A connection, USB-B connection, mini-USB-A connection, mini-USB-B connection, micro-USB-A connection, micro-USB-B connection, USB-C connection, or Lightning connection. The connection unit may include several pins with specific purposes. Furthermore, the connection unit is used for various purposes, such as synchronous transfer, interrupt transfer, and bulk transfer. The term "bulk transfer" refers to a large-scale, sporadic transfer that uses all remaining available bandwidth, but without guaranteeing bandwidth or latency. Bulk transfer is utilized when transferring files or data via a connection medium such as a USB cable. However, other methods of data transfer may be used, and the use of the term "USB cable" is not intended to be limiting.

[0032] For example, a USB-A connection has four pins. Each pin is used for a specific purpose, such as a power supply pin, a data (-) pin, a data (+) pin, and a power supply ground pin. Other connection units may have more or fewer than four pins, and each pin may have a different purpose. In some examples, the electrical connection of interface 114 may also allow data storage device 106 to receive power from host device 104. For example, as Figure 1 As shown, power supply 111 can receive power from host device 104 via interface 114.

[0033] Data storage device 106 includes NVM 110, which may include multiple memory devices or storage cells. NVM 110 can be configured to store and / or retrieve data. For example, a storage cell of NVM 110 can receive data and receive messages from controller 108 instructing the storage cell to store data. Similarly, a storage cell of NVM 110 can receive messages from controller 108 instructing the storage cell to retrieve data. In some examples, each storage cell in the storage unit may be referred to as a die. In some examples, a single physical chip may include multiple dies (i.e., multiple storage cells). In some examples, each storage cell may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0034] In some examples, each memory cell of the NVM 110 may include any type of non-volatile memory device, such as flash memory device, phase-change memory (PCM) device, resistive random access memory (ReRAM) device, magnetoresistive random access memory (MRAM) device, ferroelectric random access memory (F-RAM), holographic memory device, and any other type of non-volatile memory device.

[0035] NVM 110 may include multiple flash memory devices or memory cells. The flash memory devices may include NAND-based or NOR-based flash memory devices and may store data based on the charge contained in the floating gate of the transistors for each flash memory cell. In a NAND flash memory device, the flash memory device may be divided into multiple blocks, which may be divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NAND cells. Rows of NAND cells may be electrically connected using word lines to define pages within the multiple pages. A corresponding cell in each of the multiple pages may be electrically connected to a corresponding bit line. Furthermore, the NAND flash memory device may be a 2D or 3D device and may be a single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), or four-level cell (QLC). Controller 108 may write data to and read data from the NAND flash memory device at the page level and erase data from the NAND flash memory device at the block level.

[0036] Data storage device 106 includes a power supply 111 that can provide power to one or more components of the data storage device 106. When operating in standard mode, power supply 111 can use power provided by an external device such as host device 104 to power one or more components. For example, power supply 111 can use power received from host device 104 via interface 114 to power one or more components. In some examples, power supply 111 may include one or more power storage components configured to power one or more components when operating in a shutdown mode, such as when power reception from external devices is stopped. In this way, power supply 111 can be used as an onboard backup power source. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, etc. In some examples, the amount of electricity that can be stored by one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of one or more power storage components. In other words, as the amount of electricity stored by one or more power storage components increases, the cost and / or size of one or more power storage components also increases.

[0037] Data storage device 106 also includes volatile memory 112, which can be used by controller 108 to store information. Volatile memory 112 may include one or more volatile memory devices. In some examples, controller 108 may use volatile memory 112 as a cache. For example, controller 108 may store cached information in volatile memory 112 until the cached information is written to non-volatile memory 110. Figure 1 As shown, volatile memory 112 can consume power received from power supply 111. Examples of volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)).

[0038] Data storage device 106 includes a controller 108 that can manage one or more operations of data storage device 106. For example, controller 108 can manage reading data from NVM 110 and / or writing data to NVM. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 can initiate a data storage command to store data in NVM 110 and monitor the progress of the data storage command. Controller 108 can determine at least one operational characteristic of storage system 100 and store at least one operational characteristic in NVM 110. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 temporarily stores the data associated with the write command in internal memory before sending the data to NVM 110.

[0039] Figure 2 This is a schematic diagram of a data storage device 208 according to one embodiment. The data storage device 208 includes an interface 202 and a power distribution unit (PAU) 204. The interface 202 may be... Figure 1 Interface 114. Data storage device 208 also includes an array of memory devices 206A to 206N (collectively referred to as memory devices 206). The symbol "N" refers to the last memory device among a plurality of memory devices. Furthermore, memory device 206 may be... Figure 1The storage devices 110 are non-volatile memory or NVMe storage devices. Each of the storage devices 206A to 206N can be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.). However, the listed data storage sizes of the storage devices are not intended to limit or restrict. Furthermore, in one embodiment, the storage devices 206A to 206N are of the same type and have the same data storage size. In another embodiment, the storage devices 206A to 206N are of different types but have the same data storage size. In yet another embodiment, the storage devices 206A to 206N are of different types and have different data storage sizes.

[0040] The power distribution unit 204 can be connected to a controller (not shown) (such as...) Figure 1 The controller 108) is coupled to the PAU 204. The PAU 204 will be connected from the host device (such as...) Figure 1 The host device 104 receives power and distributes it to each memory device in the memory devices 206. The controller 108 can determine the appropriate power state for each memory device 206A to 206N, and the PAU 204 provides the corresponding power to each memory device 206A to 206N.

[0041] The host device 104 can provide appropriate power to the data storage device 208 through one or more pins on the interface 202. The appropriate power may be greater than or equal to the power required for the data storage device 208 to operate. For example, the data storage device 208 may receive approximately 5W of power from the host device 104. Furthermore, the data storage device 208 may draw approximately 500mW to approximately 15W of power from the host device 104. The previously mentioned power values ​​are not intended to be limiting but are intended to provide reference.

[0042] Memory devices 206A to 206N may have several power states (PS). For example, memory devices 206A to 206N may have the following five power states: PS0, PS1, PS2, PS3, and PS4. Each power state is associated with the operation of a different data storage device 208. Power states PS0, PS1, and PS2 are considered operating power states, utilizing approximately 1W to approximately 8W of power, while power states PS3 and PS4 are considered non-operating power states, utilizing approximately 2mW to approximately 50mW of power. Operating power states refer to host devices (such as...) Figure 1 The host device 104) is able to communicate with the memory devices 206A to 206N of the data storage device 208.

[0043] Power states are numbered sequentially, with higher numbers indicating lower power requirements and correspondingly higher exit delays. Furthermore, each power state has an associated power requirement and exit delay. PS0 may require 4.5W and has the lowest exit delay. PS1 may require less power than PS0, such as 3W, and its exit delay may be equal to or higher than that of PS0. PS2 may require less power than PS1, and its exit delay may be equal to or higher than that of PS1. PS3 may require less power than PS2, and its exit delay may be equal to or higher than that of PS2. PS4 may require less power than PS3, such as 5mW, and its exit delay may be equal to or higher than that of PS3, such as 50mW. The values ​​for power states and exit delays are not intended to be limiting, but rather to provide examples of possible implementations.

[0044] PS0 is referred to as the fully operational state, in which I / O commands are enabled and the device can generate interrupts. Interrupts are automatic transmissions of firmware execution caused by system timers or user commands. Furthermore, power states PS1, PS2, PS3, and PS4 are considered low-power states. Power states PS1 and PS2 are also operational states; however, their functionality is lower than that of PS0. Power states PS3 and PS4 are inactive states, and their power requirements are lower than those of the operational power states. Additionally, unused memory devices 206 are placed in the inactive power state PS4, thereby limiting idle power consumption to a minimum.

[0045] In order to generate I / O commands, memory devices 206A to 206N are woken up and placed in power state PS0. Controllers (such as...) Figure 1 The controller 108 uses PAU 204 to change the power state of memory devices 206A to 206N from PS0 to PS1, PS2, or PS3 as needed. However, in order to put memory devices 206A to 206N in PS4, memory devices 206A to 206N will need to be in power state PS3. However, when full operation is required, the controller 108 can use PAU 204 to allocate appropriate power to put all power states PS1, PS2, PS3, and PS4 in power state PS0.

[0046] Figure 3 This is an example diagram of the power duty cycle based on the disclosed implementation scheme. Storage devices (such as...) Figure 2The storage device 208 may experience a power duty cycle during a specific operating period. Time is plotted on the x-axis, and the percentage of power consumption is plotted on the y-axis. Power state PS1 may correspond to approximately 100% power consumption, and power state PS4 may correspond to approximately 10% power consumption. Deep sleep mode can refer to power state PS4. The approximately 10% power consumption utilized by the storage device during deep sleep mode enables the storage device to quickly recover into a full-power mode (e.g., wake-up), such as PS0, without undergoing a boot sequence. The term "wake-up" may be used in any temporal context to describe the storage device's recovery from deep sleep mode to full-power mode. Controllers (such as...) Figure 1 The part of the controller 108 responsible for quickly resuming from deep sleep mode to full power mode is the always-on (AON) module. When the storage device is in deep sleep mode, the AON module is fully powered.

[0047] A boot sequence can be the operation from when the storage device is turned off (e.g., not powered) until the storage device is in a power-operated state. A boot sequence may require more time to reach the power-operated state compared to waking from deep sleep mode. A power duty cycle mode may utilize approximately 100% power consumption for approximately 50% of the time (e.g., 100 milliseconds) and approximately 10% power consumption for approximately 50% of the time (e.g., 100 milliseconds). In terms of total power consumption, a power duty cycle mode may be more energy-efficient than continuous operation in half-power mode.

[0048] exist Figure 3 In the process, the storage device initially operates at approximately 100% power consumption or full operating power. At times A and C, the storage device enters a deep sleep mode (e.g., enters sleep mode), and power consumption decreases to approximately 10%. However, this decrease in power consumption to approximately 10% does not occur instantaneously. The gradual decrease in power consumption from time A to time A′ and from time C to time C′ is referred to as the tail. For optimal performance, the power consumption tail should be as small as possible, as it increases AON power consumption. Furthermore, when the storage device is woken from deep sleep mode at times B and D, it does not return to full operating power before times B′ and D′, respectively.

[0049] Figure 4 This is an example diagram based on the power duty cycle, related command execution, and data rate of existing methods. Figure 3 Its various aspects can be similar to Figure 4Description. Plot time on the x-axis and utilization percentage on the y-axis. For example, the percentage of power consumption from time A to time B is 100% power consumption, and the percentage of data rate (data transfer rate) utilization from time A to time B is 100% data rate. Power state PS1 may correspond to approximately 100% power consumption, and power state PS4 may correspond to approximately 10% power consumption. Deep sleep mode may refer to power state PS4. Power consumption curves are plotted as solid lines. Data rate curves are plotted as dotted dashed lines. Average power curves are plotted as dashed lines. Average data rate curves are plotted as dashed-dotted lines. Throughout the power duty cycle, average power remains constant at approximately 75% power consumption, and average data rate remains constant at approximately 50% data transfer rate.

[0050] At times A and A′, the data transfer rate begins to decrease in preparation for the storage device to enter a deep sleep mode. However, the power consumption of the storage device remains constant from time A to time B and from time A′ to time B′. Between time A and time B′ and between time A′ and time B′, the storage device is completing previously fetched commands (e.g., commands remaining in a queue or buffer) and remains at full operating power (PS1). According to existing methods, no additional commands are fetched or transferred during this period, nor is any additional data beyond that required to complete the previously fetched commands.

[0051] At times B and B′, the storage device has completed the remaining commands in the command queue or command buffer. From time B to time C and from time B′ to time C′, the device's power consumption gradually decreases from approximately 100% to approximately 10%. At times C and C′, the storage device enters a deep sleep mode. The area between the power consumption curve and the data rate curve between time B and time C, and between time B′ and time C′, corresponds to the additional power consumption of the storage device due to the power consumption tail.

[0052] At times E and E′, the data rate begins to increase from approximately 0% until it reaches approximately 100% at times H and H′. Because the storage device is in deep sleep mode, there is a hysteresis or delay before the storage device supplies more power to related components (such as memory devices 206A to 206N) to restore it to power state PS1. The power consumption hysteresis is represented by the time intervals between time E and time F, and between time E′ and time F′.

[0053] At times G and G′, the storage device recovers to full operating power, or approximately 100% power consumption. However, prior to times H and H′, the storage device does not have approximately 100% data rate, indicating that the command buffer or queue is not optimally filled. Similar to the power consumption tail described in the power decline process above, the area between the power consumption curve and the data rate curve between times F and H, and between times F′ and H′, corresponds to the additional power consumption caused by the storage device over-allocating resources to the queue or buffer for fewer than the optimal number of commands, during which time empty command queues are filled by fetching commands from the host and initiating those commands.

[0054] Figure 5A This is a flowchart of a method 500 for power cycle command optimization according to the disclosed embodiment. At block 502, the controller (such as...) Figure 1 The controller 108) is from the host (such as Figure 1 The host (104) receives the first command. At block 504, the controller calculates the expected / estimated NAND time, LDPC time, and HIM time in response to the command received from the host. At block 506, the calculation results from block 504 are stored in RAM3 (AON). At block 508, the controller waits to receive another command from the host. When the controller receives another command (such as a second command) from the host, method 500 begins at block 502.

[0055] Figure 5B This is a flowchart of method 550 for power cycle command optimization according to the disclosed embodiment. After the controller has completed method 500 for a command (such as a first command), at block 552, the controller begins processing the first command. Storage devices (such as...) Figure 2 The storage device 208 can operate in power duty cycle mode. At block 554, the controller checks the time until the next power cycle (e.g., from P1 to P4). At block 556, the controller checks the current task load of NAND, LDPC, and HIM, enabling the controller to identify which commands in the current task load can be completed before the next power cycle.

[0056] At box 558, the controller calculates the remaining time for the current NAND operation, LDPC operation, and HIM operation in the current task load. At box 560, a first command is selected from RAM3 (AON). At box 562, based on the calculations completed at box 558, the controller determines whether the first command selected at box 560 can be completed in the remaining time before the next power cycle. If the controller cannot complete the selected command in the remaining time, then at box 560, the controller selects another command from RAM3 (AON). However, if at box 562, the controller can complete the first command in the remaining time before the next power cycle, then at box 564, the controller generates instructions for the data path engine.

[0057] At box 566, the controller updates the current NAND load, LDPC load, and HIM load. At box 558, the updated load from box 566 is used to calculate the next iteration of the remaining time for the NAND, LDPC, and HIM operations of method 550. At box 568, the data path engine completes the instructions for commands generated by the controller at box 564. At box 570, the controller updates the current NAND load, LDPC load, and HIM load. At box 558, the updated load from box 570 is used to calculate the next iteration of the remaining time for the NAND, LDPC, and HIM operations of method 550. After updating the current NAND load, LDPC load, and HIM load at box 570, at box 572, the controller serves the next command in the command queue or command buffer.

[0058] Figure 6 The data and control paths for power cycle optimization 600 according to the disclosed embodiments are shown. The shown data and control paths describe embodiments of how read commands or write commands are executed. The data and control paths for power cycle optimization described herein are not intended to be limiting, but rather to provide examples of possible embodiments.

[0059] Host 602 directs data to data storage devices (such as...) Figure 2 The data storage device 208 sends commands to access data stored in the NVM 624. The command fetcher 604 of the controller 622 receives the commands sent by the host 602. The CPU and hardware (HW) engine 608 of the data storage device breaks down the commands received by the command fetcher 604 into smaller actions for different data paths (e.g., LDPC, HIM, XOR, etc.). The smaller actions are stored in RAM 4 610.

[0060] When controller 622 receives a command to access data in NVM 624, the relevant data is moved from NVM 624 to RAM1 612 via data path 620. The data then travels through LDPC 614 to RAM2 616. From RAM2 616, the data is moved to HIM 618, where HIM 618 moves the data to host 602.

[0061] During deep sleep mode, data stored in RAM1 612, RAM2 616, and RAM4 610 is lost. Although RAM3 606 may be smaller than RAM1 612, RAM2 616, and RAM4 610, in one embodiment, RAM3 606 is a dedicated AON RAM and is capable of saving commands when the storage device enters deep sleep mode. Because RAM3 606 is AON RAM, the CPU and HW engine 608 can selectively process commands that can be completed in the remaining time before the next power cycle occurs, during which the storage device enters deep sleep mode.

[0062] Figure 7 A method 700 for performing power cycle optimization using commands according to the disclosed embodiment is shown. At block 702, a storage device (such as...) Figure 2 Storage device 208) from host (such as Figure 6 The host (602) receives multiple commands. The storage device operates in a power cycling mode, where the storage device has a power decay time. The power decay time refers to the time when the device's power consumption begins to decrease, which may be later than the time when the data rate begins to decrease. At box 704, the controller (such as...) Figure 6 The controller 622) calculates the expected execution duration of each of the multiple commands stored in the command queue or command buffer.

[0063] At box 706, the controller selects one or more commands from a plurality of commands that can be completed in the remaining time before the storage device power decays. At box 708, each of the selected one or more commands is executed. At box 710, the storage device begins power decay to a deep sleep mode at the power decay time. In one embodiment, the power decay time can be predetermined, wherein the power decay times are at equal intervals. In another embodiment, the power decay time can be a set time after a prompt from the storage device or host device. Remaining commands that have not yet been executed in the command queue or command buffer are stored in AON RAM (such as...). Figure 6The remaining commands can be executed when the data storage device wakes from deep sleep mode (RAM3 606). In some implementations, some commands are executed in part, while the unexecuted parts are stored in AON RAM until the device exits deep sleep mode.

[0064] Figure 8 A method 800 for power cycle optimization is illustrated, using partial commands executed according to the disclosed embodiment. At block 802, a storage device (such as...) Figure 2 Storage device 208) from host (such as Figure 6 The host (602) receives multiple commands. The storage device operates in a power cycling mode, where the storage device has a power decay time. The power decay time refers to the time when the device's power consumption begins to decrease, which may be later than the time when the data rate begins to decrease. At box 804, the controller (such as...) Figure 6 The controller 622) calculates the expected execution duration of each of the multiple commands stored in the command queue or command buffer.

[0065] At box 806, the controller selects one or more commands from a plurality of commands that will not complete before the remaining time before the storage device power drops. At box 808, each of the selected one or more commands is executed. However, since the selected one or more commands cannot complete before the power drop time, the controller 622 executes a portion of the one or more commands. The one or more commands that have not yet completed, as well as the remainder of the one or more commands that have not yet been executed, are stored in AON RAM (such as...). Figure 6 In RAM 3 (606). At box 810, the storage device begins to power down to a deep sleep mode at a power-down time. In one embodiment, the power-down time may be predetermined, wherein the power-down times are at equal intervals. In another embodiment, the power-down time may be a set time after a prompt from the storage device or the host device. When the storage device resumes from deep sleep mode to full operating mode, commands stored in AON RAM can be executed.

[0066] Figure 9 This is an example diagram based on the power duty cycle of the disclosed implementation scheme and the associated command execution and data rate of 900. Figure 3 and Figure 4 Its various aspects can be similar to Figure 4Description. Plot time on the x-axis and utilization percentage on the y-axis. For example, the percentage of power consumption from time A to time B is 100% power consumption, and the percentage of data rate (data transfer rate) utilization from time A to time B is 100% data rate. Power state PS1 may correspond to approximately 100% power consumption, and power state PS4 may correspond to approximately 10% power consumption. Deep sleep mode may refer to power state PS4. Power consumption curves are plotted as solid lines. Data rate curves are plotted as dotted dashed lines. Average power curves are plotted as dashed lines. Average data rate curves are plotted as dashed-dotted lines. Throughout the power duty cycle, average power remains constant at approximately 60% power consumption, and average data rate remains constant at approximately 50% data transfer rate.

[0067] At times A and A′, the data transfer rate begins to decrease in preparation for the storage device to enter deep sleep mode. However, the power consumption of the storage device remains constant from time A to time B and from time A′ to time B′. Between time A to time C and time A′ to time C′, the power consumption of the storage device varies according to… Figure 5A , Figure 5B Method 500, Method 550, as described Figure 7 The method described in 700 and / or Figure 8 The method 800 described herein is completing previously acquired commands (e.g., remaining commands in a queue or buffer). In some implementations, one or more commands are partially completed, with the uncompleted portion stored in AON RAM. Due to the controller (such as...) Figure 6 The controller 622 is based on Figure 7 The method described in 700 and / or Figure 8 The method described in 800 selects a command, thus enabling the storage device to degrade power more quickly and to complete the selected command while the storage device degrades power. Figure 9 The time between time A and time B, and the time from time A′ to time B′ are significantly less than Figure 4 The time between time A and time B, and the time from time A′ to time B′.

[0068] At times C and C′, the storage device has already... Figure 5A , Figure 5B Method 500, Method 550, as described Figure 7 The method 700 and / or described in the document Figure 8 The method 800 described in the document completes the remaining commands in the command queue or command buffer. Remaining commands that have not yet been executed, or the unexecuted portion of commands that have not been fully completed, are stored in AON RAM (such as...). Figure 6The memory is stored in RAM (3606). For example, when the storage device is experiencing power degradation, the controller can acquire a first command that can be fully executed and a second command that can be partially completed before the power degradation time. The portion of the second command that has not been completed before the power degradation time, and any other remaining commands, are stored in AON RAM. From time B to time D and from time B′ to time D′, the device's power consumption gradually decreases from approximately 100% to approximately 10%. At time D and time D′, the storage device enters a deep sleep mode.

[0069] At times E and E′, the power consumption rate of the storage device increases, indicating that the device is reviving from deep sleep mode to full operating state. At times F and F′, the data rate begins to increase from approximately 0% until it reaches approximately 100% at times H and H′. At times G and G′, the storage device returns to full operating power or approximately 100% power consumption. Because AON RAM includes commands that were not completed or executed before the previous power consumption of the storage device decreased, the controller is able to service these commands when the power consumption of the storage device increases without fetching commands from the host. For example, when the storage device wakes from deep sleep mode, a portion of a previous second command stored in AON RAM that was not completed before the storage device entered deep sleep mode is executed. The controller can fetch a third command from the remaining commands that have not yet been executed to provide service as the storage device is reviving to full operating mode. In some implementations, additional commands can be fetched from the host while executing commands from AON RAM and partially executed commands.

[0070] By selecting partial or complete commands to complete during the remaining time before the storage device enters deep sleep mode, the power consumption tail of the storage device is reduced, allowing full utilization of storage device resources during power surges, instead of waiting to fetch commands from the host as in existing methods. Furthermore, when the storage device wakes from deep sleep mode, it can serve unfinished or unexecuted commands stored in AON RAM while the storage device is recovering to full operating mode. Therefore, when operating in power cycling mode, the storage device can achieve higher performance than existing methods (such as...). Figure 4 (As shown in the figure) a better performance-to-power ratio.

[0071] In one embodiment, the data storage device includes one or more memory devices and a controller coupled to the one or more memory devices. The controller is configured to receive a plurality of commands from a host at the data storage device, including a power decay time. The controller is also configured to calculate the expected execution duration of each of the plurality of commands, select the command whose duration will not exceed the power decay time from the plurality of commands, execute the command, and cause the data storage device to enter a power decay state during the power decay time.

[0072] A command is a member of a subset of commands, wherein the combined expected duration of each command in the subset will not exceed the power fall-off time. The controller is further configured to update the device's power fall-off time after executing a command based on the command's execution duration. The controller is further configured to select a second command from the subset whose duration will not exceed the updated power fall-off time. The controller is further configured to update the device's power fall-off time based on the second command's execution duration. The controller is further configured to select a second command from the subset whose duration will exceed the updated power fall-off time. The controller is further configured to execute a portion of the second command. The controller is further configured to store the unexecuted portion of the second command. The controller is further configured to power a data storage device during the power rise-off time and is further configured to retrieve and execute the unexecuted portion of the second command during the power rise-off time. The controller is further configured to retrieve a third command from the host during the execution of the unexecuted portion of the second command.

[0073] In another embodiment, the data storage device includes one or more memory devices and a controller coupled to the one or more memory devices. The controller is configured to receive a plurality of commands from a host at the device, including a power fall time and a power rise time. The controller is also configured to calculate the expected execution duration of each of the plurality of commands, select from the plurality of commands a command whose duration will exceed the device's power fall time, execute a portion of that command that can be executed before the power fall time, and the device enters a power fall state at the power fall time.

[0074] The controller is further configured to store the unexecuted portion of the command before the power decline time. The controller is also configured to cause the device to enter a power rise state during the power rise time, acquire the unexecuted portion of the command, and execute the unexecuted portion of the command. The controller is further configured to acquire additional commands from the host during either acquiring or executing the unexecuted portion of the command.

[0075] In another embodiment, a system for controlling the power consumption of a device is disclosed. The system includes means for receiving a command from a host at the device, means for calculating the duration of the command, and means for determining the power decay time of the device. The system also includes means for selecting a command, means for determining whether the duration of the command will exceed the power decay time, and means for executing the command. The system may further include means for updating the power decay time of the device based on the duration of the command, and means for placing the device in a power decay state based on the power decay time.

[0076] The system also includes means for recalculating the power fall time based on the duration of the command, thereby generating a recalculated power fall time. Means for receiving the command receive a second command at the device. The system also includes means for determining that a second duration of the second command will exceed the recalculated power fall time. The system also includes means for executing a portion of the second command that will not exceed the power fall time. The system also includes means for storing the unexecuted portion of the second command and executing the unexecuted portion of the second command during the power rise time of the device.

[0077] While the foregoing describes embodiments of this disclosure, other and additional embodiments of this disclosure may be contemplated without departing from the basic scope of this disclosure, the scope of which is defined by the appended claims.

Claims

1. A data storage device, the data storage device comprising: One or more memory devices; and A controller coupled to the one or more memory devices, wherein the controller is configured to: Multiple commands are received from the host at the data storage device, including the power drop time; Calculate the expected execution duration for each of the plurality of commands; Select from the plurality of commands a command whose duration will not exceed the power drop time; Execute the command; and This causes the data storage device to enter a power reduction state during the power reduction period.

2. The data storage device according to claim 1, wherein, The command is a member of a subset of the plurality of commands, wherein the combined expected duration of each command in the subset will not exceed the power decay time.

3. The data storage device according to claim 1, wherein, The controller is further configured to update the power decay time of the data storage device after the command is executed, based on the execution duration of the command.

4. The data storage device according to claim 3, wherein, The controller is further configured to select from the plurality of commands a second command whose duration will not exceed the updated power drop time.

5. The data storage device according to claim 4, wherein, The controller is further configured to update the power decay time of the data storage device based on the execution duration of the second command.

6. The data storage device according to claim 3, wherein, The controller is further configured to select from the plurality of commands a second command whose duration will exceed the updated power decay time.

7. The data storage device according to claim 6, wherein, The controller is further configured to be part of executing the second command.

8. The data storage device according to claim 7, wherein, The controller is further configured to store the unexecuted portion of the second command.

9. The data storage device according to claim 8, wherein, The controller is further configured to supply power to the data storage device during the power rise time, and is further configured to acquire the unexecuted portion of the second command during the power rise time and execute the unexecuted portion of the second command.

10. The data storage device according to claim 9, wherein, The controller is further configured to retrieve a third command from the host during the non-execution portion of the second command.

11. A data storage device, the data storage device comprising: One or more memory devices; and A controller, coupled to the one or more memory devices, is configured to: Receive multiple commands from the host at the device, including power drop time and power rise time; Calculate the expected execution duration for each of the plurality of commands; Select from the plurality of commands a command whose duration will exceed the power decay time of the device; The portion of the command that can be executed before the power drop time; as well as The device is brought into a power-down state during the power-down time.

12. The data storage device according to claim 11, wherein, The controller is further configured to store the unexecuted portion of the command before the power drop time.

13. The data storage device according to claim 12, wherein, The controller is further configured to: The device enters the power rise state during the power rise time; Obtain the unexecuted portion of the command; and Execute the unexecuted portion of the command.

14. The data storage device according to claim 13, wherein, The controller is further configured to retrieve additional commands from the host during either the retrieval of the unexecuted portion of the command or the execution of the unexecuted portion of the command.

15. A system for controlling the power consumption of a device, the system comprising: A means for receiving commands from a host at a device; A means for calculating the duration of the command; A means for determining the power drop time of the device; A means for selecting the command; A means for determining whether the duration of the command will exceed the power drop time; A means for executing the command in response to the duration of the command not exceeding the power drop time; A means for updating the power drop time of the device based on the duration of the command; and A means for placing the device into a power-down state based on the power-down time.

16. The system of claim 15, further comprising means for recalculating the power fall time based on the duration of the command, thereby generating a recalculated power fall time.

17. The system according to claim 16, wherein, The device for receiving the command receives the second command at the device.

18. The system of claim 17, further comprising means for determining that the second duration of the second command will exceed the recalculated power drop time.

19. The system of claim 18, further comprising means for executing the second command that will not exceed a portion of the power drop time.

20. The system of claim 19, further comprising means for storing an unexecuted portion of the second command and executing the unexecuted portion of the second command during the power rise time of the device.

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