Determining optimal thread counts for each core in a multi-core processor complex

Abstract

In a method for determining an optimal number of threads available for execution of a task by each core in a multi-core processor complex, a first processing measure is determined based on threads executing on cores of a processor chip, where each core includes circuitry for independently executing a plurality of threads. Based on the first processing measure, a number of threads to be executed on the cores is determined. A second processing measure is determined based on threads executing on the cores of the processor chip. An adjustment is made to the determined number of threads to be executed based on the second processing measure, resulting in a determination of an adjusted number of threads. The adjusted number of threads on the cores are used to execute instructions.

Description

TECHNICAL FIELD

[0001] The present invention relates to computer program products, systems and methods for determining an optimal number of threads available to perform tasks on each core in a multi-core processor complex. BACKGROUND

[0002] In processor chips or complexes that provide simultaneous multithreading, multiple cores on a processor chip can each implement multiple threads that can be executed simultaneously to parallelize workloads. Each core on a processor chip requires hardware, caches such as LI and L2 caches, and pipeline hardware for the core. Threads on a core share core hardware. Further, each thread can have dedicated resources in the core, such as a subset of pipeline resources, and threads on a core can share caches, such as L2 and L3 caches available to the core. Each core can also have a dedicated LI cache.

[0003] The cores on a processor chip can be run in different modes to dynamically change the number of threads on a core that can be used for processing or placed in an idle state. Typically, a user issues a command to control how many threads are run on each core, which requires quiescing task scheduling to the cores for processing.

[0004] There is a need in the art for improved techniques for determining an optimal number of threads to run on each core in a multi-core system and changing the number of threads that can run on each core to achieve the optimal number of threads. SUMMARY

[0005] Computer program products, systems and methods are provided for determining an optimal number of threads available to perform tasks on each core in a multi-core processor complex. A first processing measurement is determined based on threads executing on the cores of the processor chip, where each core includes circuitry to independently execute multiple threads. Based on the first processing measurement, a number of threads to execute on the cores is determined. A second processing measurement is determined based on the threads executing on the cores of the processor chip. An adjustment to the determined number of threads to execute is determined based on the second processing measurement, resulting in an adjusted number of threads. The instructions are executed with the adjusted number of threads on the cores.

[0006] With the above embodiments, an optimal number of threads to execute on multiple cores in a multi-core processor is determined based on two different processing measurements to optimize two different processing attributes. A first processing measurement is used to determine an optimal number of threads to optimize a first processing factor, and then a second processing measurement is used to adjust the determined optimal number of threads to optimize an alternate measurement to provide a dual factor optimization.

[0007] In a further embodiment, the first processing measure includes a number of input / output (I / O) operations from threads executing on cores of a processor complex, and wherein the second processing measure includes a number of threads executing on the cores based on the determined number of I / O operations.

[0008] With the above embodiment, the optimal number of threads is determined to optimize for the number of I / O operations, which will increase the number of available threads as the number of I / O operations increases to maintain performance as the I / O load increases.

[0009] In a further embodiment, a range of lock spin times is maintained and correlated to adjustments to the determined number of threads. The adjustment to the determined number of threads is determined in correlation to a lock spin time range that includes the determined lock spin time.

[0010] With the above embodiment, the optimal number is further adjusted and optimized based on lock spin times to attempt to reduce lock spin times, which impede performance. As lock spin times increase, the adjustment to reduce the number of threads increases to reduce the number of available threads, which reduces lock contention and overall system lock spin times.

[0011] In a further embodiment, the determined number of threads executing on each core includes less than a number of threads available to independently execute on each core. The task is only scheduled to execute on the determined number of threads on each core, leaving at least one thread idle on the plurality of cores.

[0012] With the above embodiment, threads are effectively idled by only scheduling the task to execute on the determined number of threads and not idle threads. This avoids the need to take the processor complex offline to reconfigure the available threads by leaving the processor cores online but using the scheduler to avoid scheduling tasks to idle cores.

[0013] In another embodiment, the first processing measure includes a lock spin time of threads executing in a core waiting to obtain a lock on a resource, and the second processing measure includes at least one of a number of I / O operations from threads executing on the core and cross-memory bus traffic between the core and shared memory used by the core.

[0014] With the above embodiment, the optimal number is selected based on lock spin times to reduce threads to reduce lock spin times. Depending on the number of operations, the optimal number can be further adjusted, such as increased, to make a second optimization based on the number of operations.

[0015] A computer program product, system, and method for determining an optimal number of threads available for performing tasks per core in a multi-core processor complex is also provided. A number of input / output (I / O) operations from threads executing on a core of the processor complex is determined, where each core includes circuitry for independently executing a plurality of threads. Based on the determined number of I / O operations, a number of threads to execute on the core is determined. Instructions are executed with the determined number of threads on the core.

[0016] With the above embodiments, an optimal number of threads is determined based on I / O operations to select an optimal number based on a level of I / O operations in the complex to maintain performance as the number of I / O operations increases.

[0017] A computer program product, system, and method for determining an optimal number of threads available for performing tasks per core in a multi-core processor complex is also provided. A lock spin time for threads executing in a core waiting to obtain a lock to a compute resource is determined. Based on the determined lock spin time, a number of threads to execute on the core is determined. The determined number of threads on the core are used to execute instructions.

[0018] With the above embodiments, an optimal number of threads is determined based on lock spin times for all threads waiting to access a compute resource to select an optimal number to reduce lock contention and lock spin times to improve system performance by reducing the wait time to obtain a lock. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 An embodiment of a computing environment is shown.

[0020] Figure 2 An embodiment of thread information for threads implemented in a core of a processor complex is shown.

[0021] Figure 3 An embodiment of thread availability information for threads implemented on a core is shown.

[0022] Figure 4 An embodiment of an optimal number of threads for a range of input / output (I / O) operations is shown.

[0023] Figure 5 An embodiment of an optimal number of threads for an I / O operations table is shown.

[0024] Figure 6 An embodiment of a lock spin time adjustment for an optimal number of threads for a range of lock spin times for all threads is shown.

[0025] Figure 7 An embodiment of a lock spin time adjustment table for adjusting an optimal number of threads is shown.

[0026] Figure 8 An embodiment of operations to determine and use the optimal number of threads per core based on I / O operations and lock spin time is shown.

[0027] Figure 9 An additional embodiment of operations to determine and use the optimal number of threads per core based on first and second processing measurements is shown.

[0028] Figure 10 An embodiment of optimal thread numbers for a lock spin time range table is shown.

[0029] Figure 11 An embodiment of an I / O operation adjustment table for adjusting the optimal number of threads is shown.

[0030] Figure 12 An embodiment of operations to determine and use the optimal number of threads per core based on I / O operations is shown.

[0031] Figure 13 An embodiment of operations to determine and use the optimal number of threads per core based on lock spin time is shown.

[0032] Figure 14 An embodiment of Figure 1 A computing environment in which components of the DETAILED DESCRIPTION

[0033] The described embodiments provide improvements in computer technology for determining the optimal number of threads to execute on cores of a processor complex in order to concurrently multithread tasks on the threads. The described embodiments determine the optimal number of threads to execute on cores of a processor complex that takes into account one or more processing measurements to optimize performance based on two different processing measurements.

[0034] The described embodiments provide further improvements in operations to adjust the optimal number of threads available on each processor core by indicating the optimal number of threads per core as available in thread availability information and threads of other cores as idle such that tasks are scheduled only on those threads of the cores that are indicated as available. This avoids the delay of causing cores to go offline to reconfigure the threads available or idle in each core by indicating the available and idle threads in separate thread availability information.

[0035] The described embodiments can determine an optimal number of threads available to each core that takes into account a number of processing measurements and properties, such as a number of I / O operations from threads executing on the core, cross-memory bus traffic between cores, shared memory used by the core, lock spin time of threads executing in the core waiting to obtain a lock on a resource, etc. In one embodiment, the optimal number of threads can be determined by first determining an optimal number of threads to execute on a core based on a determined number of I / O operations, and then determining an adjustment to the optimal number of threads to execute based on a determined lock spin time spent by threads waiting for a lock on a computing resource to become available.

[0036] Figure 1 An embodiment of a computing system 100 is shown having a plurality of processor complexes 1021, 1022... 102 n The plurality of processor complexes 1021, 1022... 102 n may access shared memory 106 through a memory interface 104. Each processor complex 102 i may include a plurality of processing cores 1081, 1082, 108 m-1 , 108 m , each having an on-board LI cache 1101, 1102, 110 m-1 , 110 m . Each pair of cores, such as 1081, 1082and 108 m-1 , 108 m may share an L2 cache 1121... 112 m / 2 and a larger L3 cache 1141.... 114 m / 2 , such as having an International Business Machines processor. Each processor complex 102 i may include a single-chip module (SCM). The L3 cache 114 i includes embedded dynamic random access memory (DRAM).

[0037] Each core 108 i may include hardware and circuitry for independently executing threads 116 i to allow parallelization of workloads and simultaneous multithreading of threads 116 i across cores 1081, 1082and 108 m-1 , 108 m . Simultaneous multithreading allows a single core 108 i to dispatch instructions from different threads 116 i at the same time.

[0038] Shared memory 106 includes program components executed by one or more of threads 116 i , including a thread manager 120 to manage availability of threads 116 i in cores 108 i ; a task scheduler 122 to schedule tasks to threads 116 i ; thread information 200 having information about processing of I / O operations and lock spin times for threads 116 i waiting to obtain locks on resources; thread availability information 300 indicating availability of threads 116 i to receive tasks on cores 108 i ; a lock manager 124 to manage access of locks to computing resources 126 in system 100, such as read / write queues, least recently used (LRU) lists, storage, processing, and other computing resources; an optimal thread for I / O operations 400 to provide an optimal number of threads available for different ranges of I / O operations; and lock spin time adjustment 600 to provide adjustment to the optimal number of threads for different ranges of lock spin times.

[0039] In alternative embodiments, the arrangement of cores sharing L2 and L3 caches can be different than shown in Figure 1 .

[0040] In embodiments of Figure 1 , memory 106 is external to processor complexes 1021, 1022... 102 n . In alternative embodiments, each processor complex 102 i may include a shared memory for all cores 108 i embedded on processor complex 102 i . Program components 120, 122, 124 and data 200, 300, 400 and 500 are shown in shared memory 106. In further embodiments, some or all of these program components and information can be maintained in L3 114 i or L2112 i caches. L2 cache 112 i may be used to cache data evicted from L1 cache 110 i and L3 cache 114 i may be used to cache data evicted from L2 cache 112 i .

[0041] In one embodiment, each processor complex 102 iIndividual instances of program components 120, 122, 124 and data 200, 300, 400 and 500 can be maintained in shared memory 106. In further embodiments, there can be a set of program components 120, 122, 124 and data 200, 300, 400 and 500 to manage the allocation of threads across processor complexes 1021... 102 n

[0042] The term "processor complex" can also be referred to as "processing unit," "processor," "processor chip," and the like. Cores 108 i Threads 116 i may be implemented in hardware circuitry to perform tasks in one or more integrated circuit dies. Further, processor complexes, cores, and threads can include virtual processing components that operate with respect to virtual processor complexes, cores, threads, memory, and caches implemented in physical host processing and memory resources.

[0043] In certain embodiments, computing system 100 includes a storage controller that provides access to a shared non-volatile storage.

[0044] Memory 106 can include one or more memory devices that are volatile or non-volatile, such as dynamic random access memory (DRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), spin transfer torque (STT)-MRAM, SRAM memory devices, DRAM, ferroelectric random access memory (FeTRAM), nanowire-based non-volatile memory, and direct-embedded memory module (DIMM), NAND storage devices (e.g., flash memory), solid state drive (SSD) storage devices, non-volatile RAM, and the like.

[0045] Figure 2 An embodiment of thread information 200 maintained in a thread 116 i in a core 108 i of a processor complex 102 i includes: a total number of I / O operations performed during a measurement period for all threads 1161... 116 i in the processor complex 102 m ; a number of threads used 204, which can include less than all of the threads 1161... 116 m , leaving some threads idle on each core 108 i ; a number of cores 206 on the processor complex 102 i ; and a number of processor complexes 102 i implemented in all cores 108 i ​The maximum number of threads available is 208; the lock spin time across all threads is 210, which is equivalent to 1161…116 processor cycles for all threads. m It must wait to acquire the lock from lock manager 124 to access computing resource 126.

[0046] Figure 3 It shows a specific core 108 i And thread 116 j Maintained thread availability information 300 i The embodiment includes: a core 302; a thread 304; an idle / available flag 306 indicating whether thread 304 is idle and not receiving any tasks or is available to receive tasks from the task scheduler 122; an assigned task 308 assigned to thread 304 on core 406; and a task queue 310 for queuing the assigned tasks for execution by thread 304. The task scheduler 122 may use load balancing to distribute tasks to processor complex 102. i Core 108 i Thread 116 j .

[0047] Figure 4 Entries 400 are shown in the optimal thread for I / O operations. i The embodiment includes: a range of I / O operations 402 and a maximum thread adjustment 404 for the range 402. For example, adjustment 404 may include a percentage of the maximum number of threads 208, which increases for a larger number of I / O operations because more threads are needed to handle the larger number of I / O operations to maintain the performance of system 100.

[0048] Figure 5 Examples of embodiments of the optimal threads for I / O operations table 500 (such as table 400) are provided, which provide different percentages of the maximum number of threads 208 for different ranges of I / O operations, wherein the optimal number of threads increases for higher ranges of I / O operations.

[0049] Figure 6 Entry 600 in the lock spin time thread adjustment table 600 is shown. iThe embodiment further includes: measuring the range of lock spin times in CPU cycles for all threads 602 within a time period; and a corresponding adjustment to the optimal number of threads 604. Adjustment 604 may include reducing the determined optimal number of threads by a percentage, the percentage reduction increasing for higher ranges of lock spin times 602. To reduce latency from higher lock spin times, the number of operating threads is reduced to reduce lock contention for accessing computing resource 126. Thus, as the lock spin time for all threads increases, the percentage reduction to the optimal number of threads increases to reduce the number of threads contributing to lock contention.

[0050] Figure 7 An example of an embodiment of adjusting the lock spin time thread adjustment table 600 is provided, which provides different percentage reductions to the optimal number of threads, wherein the percentage reduction increases for a higher percentage range of CPU cycles spent waiting for the lock (i.e., lock spin time).

[0051] Figure 8 The process of determining which threads are made available for task scheduler 122 to execute tasks, as shown by thread manager 120, is illustrated by thread 116. i An example of an idle operation. Figure 8 The operation can be performed periodically to adjust each core 108. i Thread 116 i The number of cores is adjusted to minimize I / O operation processing latency and lock contention. Initiation (in box 800) adjusts the number of cores to 108. j Thread 116 used for task scheduling i When the number of threads is measured, thread manager 120 operates from processor complex 102 during the measurement period. i Core 1081…108 m Threads 1161…116 executing on m Determine the total number of I / O operations 202 (in box 802). Based on I / O operation table 400 (such as table 500...). Figure 5 The optimal number of threads is determined (in box 804) for the range of I / O operations 402 (which includes the total number of determined I / O operations across thread 202). The determined optimal number of threads includes the number of threads determined by entry 400. i The percentage adjustment specified in field 404 for each core 108 i The maximum number of threads is 208, and the number of entries is 400. i It has I / O operating range 402, which includes core 108 during the measurement period. i The number of I / O operations determined on the [the data / platform].

[0052] Thread manager 120 is confirmed (in box 806) in cores 1081…108 m All threads executing in 1161…116 m Waiting 210 to obtain the lock spin time on computing resource 126. Based on the determined lock spin time, an adjustment 604 for the determined optimal number of threads is determined from lock spin time adjustment table 600 (in box 808). For example, entry 600 in lock spin time adjustment table 600 i It was determined to have 116 threads including all threads. i Waiting for the determined lock spin time of 210 within the range of lock spin time 602, and from the determined entry 600 i Adjustment 604 is determined. The determined adjustment is applied (in box 810) to the determined optimal number of threads to produce an adjusted optimal number of threads. The adjusted optimal number of threads for both I / O operation performance and lock contention is divided (in box 812) by the number of cores 206 to produce the optimal number of available threads per core. For each core 108 i Thread manager 120 is targeting core 108 i Thread availability information for the optimal number of available threads per core (300) i The LIGO thread indicator (in box 814) is available, and it is for core 108. i Thread availability information 300 for threads not indicated as available i The thread is indicated as idle. For example, if there are four threads per core, and three threads are the optimal number of threads available per core, then the thread availability information for three (optimal) threads is 300. i Field 306 indicates which threads are available, and field 300 contains thread availability information for a single thread. i Field 306 indicates that a thread is idle. Clear the count of I / O operations on all threads 202 and the lock spin time on all threads 210 (at box 816) to allow for a new measurement for the next measurement period, so that it can be used in... Figure 8 In the next instance of the operation, adjust the optimal number of available threads.

[0053] use Figure 8 In one embodiment, the optimal number of threads available for each core is determined to optimize the number of available threads by increasing the number of threads as I / O operations increase in system 100 and decreasing the number of threads by decreasing the lock spin time due to increased lock contention caused by more parallel thread operations, thereby minimizing I / O operation latency.

[0054] by updating thread availability information 300 in memory 106 to indicate available and idle threads, further described embodiments avoid the delay of adjusting the optimal number of threads available in processor complex 102 i The task scheduler 122 only schedules tasks on threads 116 i indicated as available in thread availability information 300 i . In this way, updating the number of threads that become available and idle for each core 108 i does not require reconfiguring the core.

[0055] Figure 9 Further embodiments of operations performed by thread manager 120 to determine threads available for execution of tasks by task scheduler 122 and threads 116 i to idle are shown. The operations of Figure 9 may be performed periodically to adjust the number of threads 116 i for task scheduling for each core 108 i on multiple factors. In initiating (at block 900) the operations to adjust the number of threads 116 j for task scheduling in each core 108 i , thread manager 120 determines (at block 802) a first processing measure based on threads 1161...116 i executed on cores 1081...108 m of processor complex 102 m during a measurement period. Based on the first processing measure, the optimal number of threads to execute on cores 1081...108 m is determined (at block 904).

[0056] Thread manager 120 determines (at block 906) a second processing measure based on threads 1161...116 i executed on cores 1081...108 m of processor complex 102 m during a measurement period. Based on the second processing measure, an adjustment to the determined optimal number of threads is determined (at block 908). The determined adjustment is applied (at block 910) to the determined optimal number of threads to produce an adjusted optimal number of threads. The adjusted optimal number of threads optimized based on the first and second processing measures is divided (at block 912) by the number of cores 206 to produce an optimal number of available threads per core. For each core 108 i , thread manager 120 updates thread availability information 300 i for each core 108 iThe LIGO thread indicator (in box 914) is available, and it is for core 108. i Thread availability information 300 for threads not indicated as available i The thread is indicated as idle. For example, if there are four threads per core, and three threads are the optimal number of threads available per core, then the thread availability information for three (optimal) threads is 300. i Field 306 indicates which threads are available, and field 300 contains thread availability information for a single thread. i Field 306 indicates that a thread is idle. Clear the first and second processing measurements (at box 916) to allow new measurements to be taken for the next measurement time period. Figure 9 Used in the next instance of the operation to adjust the optimal number of available threads.

[0057] use Figure 9 In one embodiment of the operation, the optimal number of threads available for each core is determined based on multiple different processor measurements to optimize the number of available threads. In one embodiment, a first processing measurement may include at least one of the following: the number of I / O operations from threads executing on a core, cross-memory bus traffic between cores, memory operations, etc., and a second processing measurement may include the lock spin time of threads executing within a core waiting to acquire a lock on a resource. In a further embodiment, the first processing measurement may include the lock spin time of threads executing within a core waiting to acquire a lock on a resource, and the second processing measurement may include at least one of the following: the number of I / O operations from threads executing on a core, cross-memory bus traffic between cores, shared memory used by the core, etc. Additional computing resource usage that affects system performance may also be considered for the first and second processing measurements to optimize across multiple processing measurements.

[0058] Figure 10 and Figure 11 An embodiment of an adjustment table is provided when the first processing measure includes the lock spin time of threads executing in the core waiting to acquire a lock on a resource and the second processing measure includes the number of I / O operations from threads executing on the core. Figure 10 This illustrates how the percentage of lock spin time 1002 maps to different optimal thread counts 1004, where the optimal thread count is calculated as cores 1081...108. n The percentage of the maximum number of threads available (208). The different ranges of lock spin time (1002) therefore map to different percentages of the maximum number of threads (1004).

[0059] In use Figure 10 After calculating the optimal number of threads based on lock spin time, then it can be done as follows: Figure 11The range of I / O operations shown determines the adjustment for the optimal number of threads. Figure 11 The optimal number of threads 1104 is shown for different I / O ranges 1102. As the range of I / O operations 1102 increases, the adjustment 1104 to the determined optimal number of threads is less, because more threads are needed to maintain performance for larger ranges of I / O operations.

[0060] Figure 12 The thread manager 120 determines which threads are available for task scheduler 122 to execute tasks based solely on the number of I / O operations, and makes thread 116 available for task execution. i Another embodiment of the idle operation. It can be executed periodically. Figure 12 Operations to adjust each core 108 i Thread 116 i The number of cores is adjusted to minimize I / O operation processing latency and lock contention. Initiation (in box 1200) is used to adjust the number of cores by 108. j Thread 116 used for task scheduling i When the number of threads is measured, thread manager 120 operates from processor complex 102 during the measurement period. i Core 1081…108 m Threads 1161…116 executing on m Determine the total number of I / O operations 202 (in box 1202). Based on the optimal thread (such as) in I / O operation table 400. Figure 5 The table in (in box 1204) determines (in box 1204) the optimal number of threads 404 corresponding to the range 402 of I / O operations, where the range 402 of I / O operations includes the total number of determined I / O operations across threads 202. The optimal number of threads is determined by the determined entries 400. i The percentage adjustment specified in field 404 for each core 108 i The maximum number of threads is 208, and the number of entries is 400. i It has I / O operating range 402, which includes core 108 during the measurement period. i The number of I / O operations determined on the [the device / system].

[0061] Figure 13 The thread manager 120 determines which threads are available to the task scheduler 122 to execute tasks and which threads 116 are available to execute tasks based solely on a lock spin time 210 of all threads executing on all cores waiting to acquire a lock on a computing resource, performed by the thread manager 120. i Additional embodiments of idle operation. Figure 13 The operation can be performed periodically to adjust each core 108. i Thread 116i to minimize I / O operation processing latency and lock contention. Upon initiating (at block 1300) an operation to adjust the number of threads 116 for task scheduling in each core 108 j i , the thread manager 120 determines (at block 1302) a percentage of the maximum number of threads 208 for each core 108 m that, when executed, results in a lock spin time 210 for all threads 116 m waiting 210 to acquire a lock on a computing resource 126. From the best thread 1000 Figure 10 determined (at block 1304) for the lock spin time 1000 Figure 10 , the maximum number of threads 1004 is determined that includes the best number of threads corresponding to a range of lock spin times 1002 that includes the determined lock spin times 120 across all threads 202. The determined best number of threads 1004 includes the maximum number of threads 208 for each core 108 i adjusted by the percentage specified in column 1004 for the determined range of lock spin times 1002 that includes the determined lock spin times 210 across all threads during the measurement period.

[0062] In the described embodiments, the variables i, j, m, n, etc. when used with different elements can represent the same or different instances of that element.

[0063] The present application can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present application.

[0064] ​A computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, semiconductor, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer readable storage media include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0065] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0066] Computer readable program instructions for carrying out operations of the present application can be assembly instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present application.

[0067] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0068] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include non- transitory computer readable storage media that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer readable storage medium having instructions for causing an apparatus to implement aspects of the function / act specified in the flowchart and / or block diagram block or blocks.

[0069] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0070] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0071] Figure 1 The computing components can be implemented in one or more computer systems, such as Figure 14 The computer system 1402 is shown. The computer system / server 1402 can be described in the general context of computer system executable instructions (such as program modules) executed by the computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. The computer system / server 1402 can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked via a communication network. In a distributed cloud computing environment, program modules may reside in local and remote computer system storage media, including memory storage devices.

[0072] like Figure 14 As shown, the computer system / server 1402 is illustrated as a general-purpose computing device. Components of the computer system / server 1402 may include, but are not limited to, one or more processors or processing units 1404, such as… Figure 1 Processor Complex 102 i System memory 1406, such as Figure 1 The system includes a shared memory 106 and a bus 1408 that couples the various system components, including system memory 1406, to the processor 1404. Bus 1408 represents one or more of several types of bus architectures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example and not limitation, such architectures include the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MCA) bus, the Enhanced ISA (EISA) bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0073] The computer system / server 1402 typically includes a variety of computer system readable media. Such media might include, for example, RAM 1410 and / or ROM 1412, which can be volatile and / or non-volatile media. The RAM 1410 and / or ROM 1412 can also be used as a functional medium for loading and / or storing software.

[0074] The system memory 1406 can include computer system readable media in the form of volatile memory, such as random access memory (RAM) 1410 and / or cache memory 1412. The computer system / server 1402 can further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 1413 can be provided for reading from and writing to non-removable, non-volatile magnetic media (not shown and typically called a "hard drive"). Although not explicitly shown, a magnetic disk drive can also be provided for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive can be provided for reading from or writing to a removable, non-volatile optical disk (such as a CD-ROM, DVD-ROM or other optical media). Each of these disk drives and their associated computer system media, including the storage system 1413, can be connected to the system bus 1408 by one or more disk drive interfaces. As will be seen, the storage system 1413 can include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the application, as described herein.

[0075] The program / utility 1414, having a set (at least one) of program modules 1416, can be stored in memory 1406 by way of example, and not limitation, as well as an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data or some combination thereof, can include an implementation of a networking environment. The components of the computer 1402 can be implemented as program modules 1416 which generally carry out the functions and / or methodologies of embodiments of the application as described herein. Figure 1 The system of the present application can be implemented in one or more computer systems 1402, where the computer systems can communicate over a network if they are implemented in multiple computer systems 1402.

[0076] The computer system / server 1402 can also communicate with one or more external devices 1418 such as a keyboard, a pointing device, a display 1420, etc.; one or more devices that enable a user to interact with the computer system / server 1402; and / or any devices (e.g., network card, modem, etc.) that enable the computer system / server 1402 to communicate with one or more other computing devices. Such communication can occur via Input / Output (I / O) interfaces 1422. Still yet, the computer system / server 1402 can communicate with one or more networks such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet) via network adapter 1424. As depicted, network adapter 1424 communicates with the other components of the computer system / server 1402 via bus 1408. It should be understood that although not shown, other hardware and / or software components could be used in conjunction with the computer system / server 1402. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

[0077] The terms "a" or "an", as used herein, mean "one or more" unless otherwise explicitly stated.

[0078] The terms "including," "includes," "comprising," "comprises," "has," "having," and the like, as used herein, are meant to be broad and encompass the terms "consisting of" and "consisting essentially of."

[0079] Enumerated lists of items do not imply any or all items are mutually exclusive, unless specifically stated otherwise.

[0080] The terms "a," "an," and "the" as used herein mean "one or more" unless otherwise explicitly stated.

[0081] Devices that are in communication with each other need not be in continuous communication with each other, unless expressly specified otherwise. In addition, devices that are in communication with each other can communicate directly or indirectly through one or more intermediaries.

[0082] A description of an embodiment with multiple components in communication with each other does not imply that all such components are required. To the contrary, a variety of optional components are described to illustrate various potential embodiments of the present application.

[0083] When a single device or article is described herein, it will be readily apparent that more than one device / article (whether or not they cooperate) can be used in place of a single device / article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device / article can be used in place of the more than one device or article or a different number of devices / articles can be used instead of the shown number of devices or programs. The functionality and / or the features of a device can be alternatively embodied by one or more other devices which are not explicitly described as having such functionality / features. Thus, other embodiments of the application need not include the device itself.

[0084] The foregoing description of various embodiments of the application has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the application be limited not with this detailed description, but rather by the claims appended hereto. The specification and examples given herein will be supplemented by a detailed description of or a discussion of the synthetic procedure or process of preparation of the composition of the application. As such, numerous modifications and adaptations thereof will be apparent to those skilled in the art without departing from the scope of the application.

Claims

1. A computer program product for determining a number of threads to be executed in a core of a processor complex, wherein, The computer program product includes a computer readable storage medium having computer readable program code embodied therein, the computer readable program code, when executed, performs operations comprising: determining a first processing measurement based on threads executing on the cores of the processor complex, wherein each core includes circuitry to independently execute a plurality of threads; determining an optimal number of threads available to execute on the cores based on the first processing measurement; determining a second processing measurement based on the threads executing on the cores of the processor complex, wherein the first processing measurement is different than the second processing measurement; determining an adjustment based on the second processing measurement; applying the adjustment to the optimal number of threads to result in an adjusted number of threads; allocating the adjusted number of threads among the cores to determine an available number of threads for each core; for each of the cores, performing: indicating at least one of the available number of threads determined for the core as available to execute an instruction; and indicating at least one of the available number of threads determined for the core as idle; and executing the instruction on the core with the available number of threads, wherein determining the first processing measurement includes determining a number of input / output (I / O) operations from threads executing on a core of a processor complex, and wherein determining the second processing measurement includes determining a lock spin time of the threads executing on the core waiting to obtain a lock on a resource.

2. The computer program product of claim 1, wherein, determining an optimal number of threads available to execute on the cores includes: maintaining an association of a plurality of I / O operation ranges and adjustments to a maximum number of threads available to execute on the cores; determining an adjustment to the maximum number of threads associated with an I / O operation range that includes the determined number of I / O operations; and computing the optimal number of threads by applying the determined adjustment to the maximum number of threads available to execute on the cores.

3. The computer program product of claim 2, wherein, the adjustment includes reducing the maximum number of threads by a percentage, wherein the percentage is decreased for higher I / O operation ranges.

4. The computer program product of claim 1, wherein, determining the adjustment based on the second processing measurement includes: maintaining an association of ranges of lock spin times and adjustments to the determined optimal number of threads; and determining an adjustment to the optimal number of threads associated with a lock spin time range that includes the determined lock spin time.

5. The computer program product of claim 4, wherein, the adjustment to the determined optimal number of threads includes reducing the determined optimal number of threads by a percentage, wherein the percentage is increased for higher lock spin time ranges.

6. The computer program product of claim 1, wherein, the operations further include: scheduling a task to execute on at least one of the available number of threads indicated as available to execute an instruction.

7. A system for determining a number of threads to execute in a core of a processor complex, comprising: a plurality of cores to execute threads; and a computer-readable storage medium having computer-readable program code embodied therein, the computer-readable program code, when executed on at least one of the cores, performs operations comprising: determining a first processing measurement based on threads executing on the cores of the processor complex, wherein each core includes circuitry to independently execute a plurality of threads; determining an optimal number of threads available to execute on the cores based on the first processing measurement; determining a second processing measurement based on the threads executing on the cores of the processor complex, wherein the first processing measurement is different than the second processing measurement; determining an adjustment based on the second processing measurement; applying the adjustment to the optimal number of threads to yield an adjusted number of threads; allocating the adjusted number of threads among the cores to determine an available number of threads for each core; for each of the cores, performing: indicating at least one of the available number of threads determined for the core as available to execute an instruction; and indicating at least one of the available number of threads determined for the core as idle; and executing the instruction on the core with the available number of threads, wherein determining the first processing measurement includes determining a number of input / output (I / O) operations from threads executing on a core of a processor complex, and wherein determining the second processing measurement includes determining a lock spin time of the threads executing on the core waiting to obtain a lock on a resource.

8. The system of claim 7, wherein, determining an optimal number of threads available to execute on the cores includes: maintaining a plurality of I / O operation ranges and an association of adjustments to a maximum number of threads available to execute on the cores; determining an adjustment to the maximum number of threads associated with an I / O operation range that includes the determined number of I / O operations; and computing the optimal number of threads by applying the determined adjustment to the maximum number of threads available to execute on the cores.

9. The system of claim 7, wherein, determining the adjustment based on the second processing measurement includes: maintaining a range of lock spin times and an association of adjustments to the optimal number of threads determined; and determining an adjustment to the optimal number of threads associated with a lock spin time range that includes the determined lock spin time.

10. The system of claim 7, wherein, the operations further include: scheduling a task to execute on at least one of the available number of threads indicated as available to execute an instruction.

11. A method for determining a number of threads to execute in a core of a processor complex, comprising: determining a first processing measurement based on threads executing on the cores of the processor complex, wherein each core includes circuitry to independently execute a plurality of threads; determining an optimal number of threads available to execute on the cores based on the first processing measurement; determining a second processing measurement based on the threads executing on the cores of the processor complex, wherein the first processing measurement is different than the second processing measurement; determining an adjustment based on the second processing measurement; applying the adjustment to an optimal number of threads for the thread to obtain an adjusted thread number; allocating the adjusted thread number among the cores to determine an available thread number for each core; for each of the cores, performing: indicating at least one thread of the available number of threads determined for the core as available to execute an instruction; and indicating at least one thread of the available number of threads determined for the core as idle; and executing the instruction on the core with the available number of threads, wherein determining the first processing measure includes determining a number of input / output (I / O) operations from a thread executing on a core of a processor complex, and wherein determining the second processing measure includes determining a lock spin time for the thread executing on the core waiting to obtain a lock on a resource.

12. The method of claim 11, wherein, determining an optimal number of threads available for execution on the core includes: maintaining an association of a plurality of I / O operation ranges and adjustments to a maximum number of threads available for execution on the core; determining an adjustment to the maximum number of threads associated with an I / O operation range that includes the determined number of I / O operations; and calculating the optimal number of threads by applying the determined adjustment to the maximum number of threads available for execution on the core.

13. The method of claim 11, wherein, determining the adjustment based on the second processing measure includes: maintaining an association of a range of lock spin times and adjustments to an optimal number of threads determined; and determining an adjustment to the optimal number of threads associated with a lock spin time range that includes the determined lock spin time.

14. The method of claim 11, further comprising: scheduling a task to execute on only at least one thread of the available number of threads indicated as available to execute an instruction.

Images