Machine learning based methods and apparatus for integrated circuit design delay calculation and verification

Abstract

A method for integrated circuit design with delay verification includes storing configuration files of a slew rate machine learning (ML) model, a signal line delay ML model, and a cell delay ML model. A user design is received, slew rate feature values, signal line delay feature values, and cell delay feature values are extracted from the user design, the configuration files are loaded to form inference cores, and operations of the slew rate inference core are performed to calculate predicted slew rate values sent to a ML design tool. Operations of the signal line delay inference core are performed to calculate predicted signal line delay values sent to the ML design tool. Operations of the cell delay inference core are performed to generate predicted cell delay values sent to the ML design tool. The user design is iterated until a user design is obtained that has no timing violations.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 62 / 946,352, filed December 10, 2019, and U.S. Non-Provisional Patent Application Serial No. 17 / 111,218, filed December 3, 2020, the contents of which are incorporated herein by reference in their entirety. Background Technology

[0003] The performance evaluation capabilities of design tools enable designers to achieve timing shutdown and guarantee that a given design will meet its performance requirements once implemented on the target silicon. This critical capability requires design tools that impact design performance, and in some cases, combine highly accurate delay calculation algorithms for each component, cell, or IP, as well as each signal line topology used in the design. Meanwhile, delay calculation presents increasing challenges as technology advances to smaller process technology nodes, increasing the complexity and diversity of capabilities and features integrated into the same hardware architecture. Consequently, this makes traditional delay calculation algorithms extremely difficult to tune, test, and guarantee accurate results.

[0004] Smaller technology nodes increase the number of parameters affecting signal propagation delay, necessitating adjustments to existing parameters. Examples of such new and / or modified parameters include on-chip offset, IR drop, coupling capacitance, the relationship between signal transition delay and propagation delay, the ratio between wire resistance and wire capacitance, and the ratio of signal transition delay over the entire clock cycle.

[0005] Similarly, the increased complexity of modern system-on-chip (SoC) architectures increases the diversity of signal line topologies and environments that design tools need to handle accurately. Furthermore, this complexity allows for the integration of much larger designs onto a single chip, resulting in significantly increased development time for tweaking traditional delay computation algorithms (thus impacting time-to-market for products such as field-programmable gate arrays (FPGAs)) and runtime experienced by designers iterating on these algorithms to achieve timing shutdowns.

[0006] Current approaches include implementations of moment-matching analysis (i.e., asymptotic waveform evaluation (AWE)), which are based on explicit moment matching to approximate the time- or frequency-domain circuit response of a reduced-order model. More recent implementations, primarily used in ASIC design (such as the Passive Reduced-Order Interconnect Macro Modeling Algorithm (PRIMA) and Padévia Lanczos (PVL)), employ implicit moment matching based on Krylov subspaces. This approach has long been considered highly accurate, providing efficient and stable solutions for many interconnect topologies, especially in FPGA environments. However, recent developments have revealed shortcomings in convergence and stability. The increasing complexity of FPGA interconnects across various component types further exacerbates these challenges. While first-order approximations such as those described by Gupta, R., Tutuianu, B., and Pileggi, LT in "The Elmore delay as abound for RC trees with generalized input signals," IEEE Transactions on the Computer-Aided Design of Integrated Circuits and Systems, Volume: 16, Issue: 1, pp. 95-104, may be stable, such guarantees do not exist for higher-order extensions. For most designs implemented in 28nm SoC FPGAs, up to 20% of the signal line delay cannot achieve the third-order accuracy of the AWE and requires reverting to the lower second-order accuracy. Another drawback of AWE involves the fact that reduced-order models cannot guarantee passivity.

[0007] An existing alternative approach is to develop software-friendly architectures; for example, making timing friendliness a requirement for the architecture. In such approaches, the architecture is heavily buffered, has no intermediate taps on its routing tracks, and, where possible, has balanced rise and fall timing characteristics. Such architectures have reasonably predictable timing, which allows for the use of lookup tables populated with pre-simulated values ​​using highly accurate electrical simulators, such as SPICE (Simulation Programming with Integrated Circuits Focused) programs. In this case, no complex numerical solvers are needed to obtain high-quality timing information. However, this simplification comes at the cost of more limited routing flexibility and thus limits the maximum performance achievable with such architectures.

[0008] Therefore, there is a need for a modern delay calculation algorithm that is highly accurate (i.e., within a few percent of SPICE) compared to electrical simulation, easy to tune using deep submicron technology, highly reliable, and run by end users, and faster than existing technology solutions. Summary of the Invention

[0009] According to one aspect of the present invention, a method for designing an integrated circuit (IC) with delay verification is disclosed. The method includes storing configuration files for a conversion rate machine learning (ML) model, a signal line delay ML model, and a cell delay ML model. A user design is received, and feature values ​​for each of the conversion rate feature, signal line delay feature, and cell delay feature are extracted from the user design to obtain conversion rate feature values, signal line delay feature values, and cell delay feature values. The conversion rate ML model configuration file is loaded to form a conversion rate inference core. The operation of the conversion rate inference core is performed using the extracted conversion rate feature values ​​as input to calculate a predicted conversion rate value, and the predicted conversion rate value is sent to a design flow tool. The signal line delay ML model configuration file is loaded to form a signal line delay inference core. The operation of the signal line delay inference core is performed using the extracted signal line delay feature values ​​as input to calculate a predicted signal line delay value, and the predicted signal line delay value is sent to the design flow tool. The cell delay ML model configuration file is loaded to form a cell delay inference core. The operation of the cell delay inference core is performed using the extracted cell delay feature values ​​as input to calculate a predicted cell delay value, and the predicted cell delay value is sent to the design flow tool. Iterate through the user design process until a final user design free of timing violations is obtained.

[0010] An IC design system with delay verification is disclosed. The system includes a data storage device configured to store configuration files for slew rate ML models, signal line delay ML models, and cell delay ML models. A user design feature extractor is coupled to the data storage device and configured to extract slew rate feature values, signal line delay feature values, and cell delay feature values ​​from the user design. An ML design flow tool is coupled to the user design feature extractor and the data storage device. A prediction ML module is coupled to the data storage device, the user design feature extractor, and the ML design flow tool. The prediction ML module is configured to load the slew rate ML model configuration file to form a slew rate inference core, load the signal line delay ML model configuration file to form a signal line delay inference core, and load the cell delay ML model configuration file to form a cell delay inference core. The prediction ML module is configured to perform operations on the slew rate inference core using the extracted slew rate feature values ​​as input to calculate predicted slew rate values, perform operations on the signal line delay inference core using the extracted signal line delay feature values ​​as input to calculate predicted signal line delay values, and perform operations on the cell delay inference core using the extracted cell delay feature values ​​as input to calculate predicted cell delay values. The prediction ML module is configured to send predicted slew rate values, predicted signal line delay values, and predicted cell delay values ​​to the design flow tool. The ML design flow tool is configured to iterate through the user design until no timing violations are found, in order to identify the final user design.

[0011] This invention offers several advantages over existing technologies. Compared to many prior art methods / systems, this invention has the potential for faster runtime during ML model inference. The slow phase is training performed only once per product during tool design (when generating the ML model). This invention is more reliable than many prior art methods / systems because it does not rely on human interpretation to achieve accurate modeling of active components, and the method and apparatus of this invention avoid the numerical limitations of iterative solvers that require evaluation for every generation of products. Furthermore, this invention is scalable to easily include new features affecting latency computation. Attached Figure Description

[0012] The invention will now be explained in more detail with reference to the embodiments and accompanying drawings:

[0013] Figure 1 This is a block diagram of an IC design and ML model generation system according to one aspect of the present invention;

[0014] Figure 2 This is a block diagram of an IC design system for delay verification using an inference chip according to one aspect of the present invention;

[0015] Figure 3This is a flowchart illustrating a method for designing an IC with delayed verification according to one aspect of the present invention;

[0016] Figure 4 This is a diagram illustrating the conversion rate inference core according to one aspect of the present invention;

[0017] Figure 5 This is a diagram illustrating a signal line delay inference core according to one aspect of the present invention;

[0018] Figure 6 This is a diagram illustrating a cell delay inference core according to one aspect of the present invention;

[0019] Figure 7 This is a flowchart illustrating a method for generating an ML model according to one aspect of the present invention; and

[0020] Figure 8 This is a flowchart illustrating a method for performing verification and testing of an ML model according to one aspect of the present invention. Detailed Implementation

[0021] Those skilled in the art will recognize that the following description is merely illustrative and not intended to be limiting in any way. Other embodiments will readily occur to those skilled in the art.

[0022] Figure 1An IC design and ML model generation system 40 is shown, having an input and output (I / O) module 1 comprising one or more physical devices for coupling inputs to and sending outputs from the IC design and ML model generation system 40. The I / O module 1 includes feature inputs 2 and existing reference design (ERD) example inputs 3. The IC design and ML model generation system 40 further includes an ERD feature extractor 4, a design flow tool 5, a training, verification, and testing ML module 6, a data storage device 11, and one or more IC design systems 20 for latency verification using inference chips, which may be simply referred to as the "IC design system" 20 below. Optionally, the IC design and ML model generation system 40 includes a processor 7. The I / O module 1, feature inputs 2, ERD example inputs 3, ERD feature extractor 4, training, verification, and testing ML module 6, design flow tool 5, data storage device 11, and optional processor 7 are coupled together via a communication subsystem 9 (e.g., a system bus). I / O module 1, feature input 2, ERD example input 3, ERD feature extractor 4, training, validation, and testing ML module 6, design flow tool 5, data storage device 11, and optional processor 7 form an ML model generation system 10, which may, for example, be housed in a single computer enclosure, wherein each of the ERD feature extractor 4, training, validation, and testing ML module 6, and design flow tool 5 is a corresponding software module. In one example, ML module 6 is an ML software program, such as TensorFlow software from Google LLC in Mountain View, California, operable for generating, training, validating, testing, and saving ML models.

[0023] The data storage device 11 includes a slew rate database 12, a signal line delay database 13, and a cell delay database 14. In one example, each element of the data storage device 11 (specifically the slew rate database 12, the signal line delay database 13, and the cell delay database 14) includes one or more of random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive and / or tape drive, or other data storage media as known in the art. In some embodiments, data, programs, or other information may be stored remotely, for example, in the “cloud.”

[0024] The Training, Validation, and Testing ML Module 6 includes software, firmware, and / or hardware for designing, training, validating, and testing ML models, and then saving the ML models for customer use through circuit design tools, as well as an ML framework. Given the characteristics and architecture of the model, the software used to actually generate the model can use commercially available ML frameworks for generating ML models, such as the TensorFlow software program mentioned above, or similar software programs and associated libraries as known in the art.

[0025] In one example, design flow tool 5 includes at least one timing-driven tool, such as a timing-driven location and routing tool or a static timing analyzer tool. The actual delay of a given element represents the so-called true label. In an exemplary embodiment, which will be used as an example in the following discussion of the invention, design flow tool 5 may include a SPICE platform builder and a SPICE simulator, which may include one or more software programs operable on an optional processor 7. The operation of design flow tool 5 (e.g., the SPICE platform builder and SPICE simulator) is controlled by instructions from ERD feature extractor 4.

[0026] IC design system 20 may be located in the same physical facility as IC design delay verification ML model generation system 40 and directly coupled to other components of system 40, as indicated by arrow 8. In one example, IC design system 20 is located in a different location from ML model generation system 10 and is coupled to ML model generation system 10 via communication system 16, which may be, for example, the Internet and may include one or more optical communication systems, wireless communication systems, or wired communication systems as known in the art.

[0027] In one example, IC design system 20 is configured to download conversion rate ML model profile 34, signal line delay ML model profile 35, and cell delay ML model profile 36, as well as one or more software programs, including a user-defined feature extractor 31, ML design flow tool 32, and predictive ML module 33 from ML model generation system 10 (see [link to ML model generation system 10]). Figure 2 It is configured to perform design, verification, and optionally programming and fabrication of IC devices independently of the ML model generation system 10.

[0028] Figure 2 The IC design system 20 includes an input and output (I / O) module 23, which includes one or more physical devices for coupling inputs and sending outputs from the IC design system 20. I / O module 32 includes user design inputs 21. The IC design system 20 also includes a data storage device 22, a user design feature extractor 31, an ML design flow tool 32, and a predictive ML module 33.

[0029] The slew rate ML model profile 34, the signal line delay ML model profile 35, and the cell delay ML model profile 36 are stored in the data storage device 22. In one example, the data storage device 22 includes random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive and / or tape drive, or other data storage media as known in the art. In some embodiments, data, programs, or other information may be stored remotely, for example, in the “cloud.”

[0030] User design feature extractor 31 includes one or more platforms or files that indicate the corresponding signal line topology (i.e., how components are connected together) of the input user design, making it operable to extract feature values ​​from the user design.

[0031] In one example, the predictive ML module 33 includes the ML components required to perform ML operations, but does not include the ML software, firmware, and / or hardware components used to generate the ML model. In this example, since timing is determined using the ML model, the ML design flow tool 32 will not include comprehensive modeling software, such as those that may be included in... Figure 1 SPICE in the design flow tool 5 (or other computationally intensive IC design tools commonly used in existing design systems).

[0032] The IC design system 20 may optionally include a dedicated hardware module (e.g., a dedicated configurable accelerator or dedicated ASIC formed on an FPGA) specifically configured to perform neural network operations, and this dedicated hardware module may also be referred to hereinafter as a “neural network engine” 30. The IC design system 20 may also optionally include one or more displays 28, random access memory (RAM) 24, a processor 25, a mask generator 26, and a device programmer 27.

[0033] I / O module 23, user design input 21, user design feature extractor 31, ML design flow tool 32, predictive ML module 33, optional neural network engine 30, optional RAM 24, optional display 28, optional processor 25, optional mask generator 26, and optional device programmer 27 are coupled together via communication subsystem 29, which may be, for example, a system bus. In one embodiment, each of the user design feature extractor 31, ML design flow tool 32, and predictive ML module is a corresponding software module, whose machine-readable instructions are stored on data storage device 22 and run on the optional processor 25.

[0034] Figure 3A method 100 for an IC design with delay verification is illustrated, the method comprising generating (101) a slew rate ML model, a signal line delay ML model, and a cell delay ML model. The slew rate ML model is a predictor of the slew rate (slew rate value), in which all parameters are calculated. The signal line delay ML model is a predictor in which all parameters are calculated to predict the signal line delay (signal line delay value). The cell delay ML model is a predictor in which all parameters are calculated to predict the cell delay (cell delay value).

[0035] The slew rate ML model configuration file, signal line delay ML model configuration file, and cell delay ML model configuration file are stored (102). The slew rate ML model configuration file includes the architecture of the slew rate ML model and the parameters developed from the training of the slew rate ML model (which will be further explained below), and can be stored as a slew rate ML model configuration file 34. Figure 1 Conversion rate database 12 and Figure 2 The data storage device 22 contains the signal line delay ML model configuration file, which includes the architecture of the signal line delay ML model and the parameters developed from training the signal line delay ML model. It can be stored as the signal line delay ML model configuration file 35. Figure 1 Signal line delay database 13 and Figure 2 The data storage device 22 contains the unit-delayed ML model configuration file, which includes the architecture of the unit-delayed ML model and the parameters developed from training the unit-delayed ML model. It can be stored as the unit-delayed ML model configuration file 36. Figure 1 In the unit delay database 14 and Figure 2 In the data storage device 22.

[0036] Receive user design (103). In Figure 2 In the illustrated implementation, user design input 21 is configured to receive user designs, which may be in the form of one or more data files defining an IC design to be formed on a device wafer (by manufacturing the device or programming a programmable logic device). The received user design may be stored in data storage device 22. Alternatively, the user design may be created by the user using ML design flow tool 32, and the user design may be stored in data storage device 22. In this example, the user design file (103) is read from data storage device 22 and received at user design feature extractor 31.

[0037] Extract the feature values ​​of slew rate feature, signal line delay feature, and cell delay feature from the user design (104) to obtain the slew rate feature value, signal line delay feature value, and cell delay feature value of the user design. Figure 2 In the illustrated embodiment, the user design feature extractor 31 is configured to receive an input user design, or a user design created using the ML design flow tool 32, and extract slew rate feature values, signal line delay feature values, and cell delay feature values ​​from the user design. Alternatively, the user design feature extractor 31 can be operated to extract feature values ​​by providing instructions to the ML design flow tool 32, such that the ML design flow tool 32 is operable to perform the extraction in response to receiving instructions from the user design feature extractor 31.

[0038] The slew rate ML model configuration file (into RAM or the neural network engine) is loaded to form a slew rate inference core (105); the operations of the slew rate inference core are performed (106) using the extracted slew rate feature values ​​as input to calculate the predicted slew rate value for each signal in the user design; and optionally, the calculated predicted slew rate value is sent to the ML design flow tool (107). In one example, the prediction ML module 33 is configured to load the slew rate ML model configuration file 34 into RAM 24 or the neural network engine 30 to form a slew rate inference core 37, perform the operations of the slew rate inference core 37 using the extracted slew rate feature values ​​as input to calculate the predicted slew rate value; and send the predicted slew rate value to the ML design flow tool 32.

[0039] Figure 4 An exemplary inference core 37 is shown, which includes input neurons 41 that calculate the predicted slew rate value, multiple rows of hidden neurons 42-43, and output neurons 44. In this example, features (represented by input neurons 41) include the number (NAD) of active devices (in an FPGA, these devices could be multiplexers or simple switches) between the source and sink, the total resistance (R) between the source and sink, and the capacitance (C) between the source and sink. SS The total capacitance (C) of the entire signal line at its output generates the slew rate. NET ) and fan-out (FAN).

[0040] return Figure 2The signal line delay ML model configuration file 35 is loaded (into RAM or the neural network engine) to form a signal line delay inference core (108); the operation of the signal line delay inference core is performed (109) using the extracted signal line delay feature values ​​as input to calculate the predicted signal line delay value for each signal line in the user design; and optionally, the calculated predicted signal line delay value is sent to the ML design flow tool (110). In one example, the prediction ML module 33 is configured to load the signal line delay ML model configuration file 35 into RAM 24 or the neural network engine 30 to form a signal line delay inference core 38, perform the operation of the signal line delay inference core 38 using the extracted signal line delay feature values ​​as input to calculate the predicted signal line delay value; and send the calculated predicted signal line delay value to the ML design flow tool 32.

[0041] Figure 5 An exemplary inference core 38 is shown, which includes an input neuron 51 that generates a predicted signal line delay value, multiple rows of hidden neurons 52-53, and an output neuron 54. In this example, features (represented by the input neuron 51) include NAD, R, and C. SS C NET The input slewing rate on the inputs of the FAN, signal line driver (NDISR), and the track type (TRACK) between the source and sink of the signal line. In the FPGA example, the track type can be identified by a buffer name that captures the combination of track buffer, track length, and multiplexer on the track. In ASICs, these characteristics are explicitly listed separately in place of the track type. Tracks can be short, medium, or long lines with additional subtypes to capture different track lengths.

[0042] return Figure 2 The system loads a unit delay ML model configuration file (into RAM or a neural engine) to form a unit delay inference core (111); uses the extracted unit delay feature values ​​as input to perform the operations of the unit delay inference core (112) to calculate the predicted unit delay value for each unit in the user design; and optionally, sends the calculated unit delay value to the ML design flow tool (113). In one example, the prediction ML module 33 is configured to load a unit delay ML model configuration file 36 into RAM 24 or a neural engine 30 to form a unit delay inference core 39, use the extracted unit delay feature values ​​as input to perform the operations of the unit delay inference core 39 to calculate the predicted unit delay value; and send the predicted unit delay value to the ML design flow tool 32.

[0043] Figure 6An exemplary unit delay inference core 39 is shown. The high unit delay inference core includes input neurons 61 that generate predicted unit delay values, multiple rows of hidden neurons 62-63, and output neurons 64. Unit delay features include unit input pins (unit input pins), the states of the remaining inputs (other input pin states) (which can be all inputs minus the states of the inputs involved in the delay calculation), unit output pins (unit output pins), the states of the remaining outputs (other output pin states) (which can be all outputs minus the states of the outputs involved in the delay calculation), the input slewing rate on the unit inputs (input slewing rate), and the output load on the unit outputs (output load). The time delay from each unit input to a specific unit output is different; therefore, the feature specification includes which multiple inputs are being used and which multiple outputs (if more than one) are being used. Additionally, the logical states of other inputs to the unit may affect the input-to-output timing delay, and these are also specified as unit features.

[0044] In one implementation, in response to receiving an instruction from the ML design flow tool 32 (e.g., whenever a new user design is about to be evaluated), execution is performed. Figure 3 Steps 104 to 113 are performed automatically by the IC design system 20 without user intervention. In response to instructions, the prediction ML module 33 is operable to load the configuration files (slew rate ML model configuration file 34, signal line delay ML model configuration file 35, or cell delay ML model configuration file 36) required to execute the instructions into RAM 24 or the neural network engine 30 to form a slew rate inference chip 37, a signal line delay inference chip 38, or a cell delay inference chip 39, and to perform the required neural network operations. Since the result of each operation is output by the corresponding inference chip 37 to inference chip 39, the prediction ML module 33 is operable to couple the output to the ML design flow tool 32 and send the result of each operation to the ML design flow tool 32.

[0045] In one example, the user design feature extractor 31 is operable to send data and instructions to the ML design flow tool 32 during the end-user's design activities and receive responses from it so as to extract feature values ​​using the ML design flow tool 32 and practice the prediction ML module 33.

[0046] The user design is iterated (114) within the ML design flow tool 32 until a final user design free of timing violations is obtained. In one example, the ML design flow tool 32 iterates the user design (e.g., using one or more of a synthesis tool, placer tool, router tool, and static timing analyzer (STA) tool) and calculates predicted slew rate values, predicted signal line delay values, and predicted cell delay values ​​until the user design of the target IC is free of timing violations to identify the final user design.

[0047] In one example, step 114 includes determining whether a timing violation exists in the user design; and if a timing violation exists, one or more of the synthesis tool, layout tool, routing tool, and STA tool of design flow tool 32 are operable to iterate the design automatically without user intervention to repeatedly modify the design (e.g., by changing the synthesis of one or more components, the layout of one or more components, the routing between components, and / or the static timing of one or more components) and repeat steps 104 through 113 (exercising the user design feature extractor 31 and the prediction ML module 33 as needed) until a final user design without timing violations is obtained.

[0048] The method may optionally include programming (115) an end-user design to a target FPGA IC device. In one example, device programmer 27 performs programming on the actual silicon to be used in an end-user product according to an embodiment of the invention, wherein the end-user design is implemented in a user-programmable integrated circuit, such as an FPGA. FPGA device programmers are available from FPGA manufacturers and many third-party vendors. To perform programming, one or more packaged FPGA devices are placed in a device socket, and appropriate data and voltages are applied to the packaged device to implement the design as the actual circuitry within the packaged FPGA device.

[0049] The method may optionally include generating multiple photomasks (116) corresponding to an end-user design. In one example, a mask generator 26 is operable to generate photomasks. More specifically, the optional mask generator 26 is a device that performs the actual generation of the geometry of the photomask for fabricating the actual silicon to be produced in an embodiment of the invention, wherein the design is implemented in an integrated circuit defined by the mask. Integrated hardware systems are available from many vendors to transform design data into physical geometry and transfer the pattern to, for example, a chromium photomask.

[0050] Figure 7 Showing the execution Figure 3An exemplary method (200) for step 101. Method 200 includes receiving input (201) indicating features of the IC design and the architecture of each of the slew rate ML model, signal line delay ML model, and cell delay ML model. Figure 1 In the illustrated embodiment, feature input 2 is configured to receive input indicating features (e.g., in the form of one or more electronic documents), which may be stored in data storage device 11 or directly coupled to ERD feature extractor 4. Inputs indicating the architecture of the slew rate ML model, signal line delay ML model, and unit delay ML model may be received via I / O module 1 and may include parameters, hyperparameters, etc., and may be stored in data storage device 11 or directly coupled to training, validation, and testing ML module 6.

[0051] Receive the ERD example (202) as input. In Figure 1 In the embodiment shown, the ERD example input 3 is configured to receive an ERD example (from a known design with valid timing) and store the received ERD example in the data storage device 11 or directly couple the received ERD example to the ERD feature extractor 4.

[0052] ERD conversion rate feature values ​​are extracted from ERD examples, ERD conversion rate ground truth labels corresponding to the extracted ERD conversion rate feature values ​​are calculated, and the generated conversion rate ML model is trained, validated, and tested using the extracted ERD conversion rate feature values ​​and the corresponding ERD conversion rate ground truth labels to generate a conversion rate ML model (203). Optionally, as further described below, the extracted ERD conversion rate feature values ​​(preferably combined with conversion rate ground truth values) are divided into training datasets, validation datasets, and test datasets. Further optionally, training, validation, and testing of the generated conversion rate ML model are performed based on the corresponding training datasets, validation datasets, and test datasets. In one embodiment, training, validation, and testing of the generated conversion rate ML model are performed using commercially available programs (such as the TensorFlow software program mentioned above) based on the corresponding training datasets, validation datasets, and test datasets. Further optionally, training is performed using a random forest algorithm.

[0053] By extracting ERD signal line delay feature values ​​from ERD examples, calculating the true ERD signal line delay labels corresponding to the extracted ERD signal line delay feature values, and using the extracted ERD signal line delay feature values ​​and corresponding true ERD signal line delay labels to perform training, validation, and testing on the generated signal line delay ML model to generate a trained signal line delay ML model, thus generating the signal line delay ML model (204). Optionally, as further described below, the extracted ERD signal line delay feature values ​​(preferably combined with true signal line delay values) are divided into training datasets, validation datasets, and test datasets. Further optionally, commercially available software programs (such as the TensorFlow software program mentioned above) are used to perform training, validation, and testing on the generated signal line delay ML model based on the corresponding training datasets, validation datasets, and test datasets. Further optionally, a random forest algorithm is used to perform training.

[0054] By extracting ERD unit delay feature values ​​from ERD examples, calculating the true ERD unit delay labels corresponding to the extracted ERD unit delay feature values, and using the extracted ERD unit delay feature values ​​and corresponding true ERD unit delay labels to perform training, validation, and testing on the generated unit delay ML model, a unit delay ML model is generated (205). Optionally, as further described below, the extracted ERD unit delay feature values ​​(preferably combined with true unit delay values) are divided into training datasets, validation datasets, and test datasets using commercially available software programs (such as the TensorFlow software program mentioned above). Further optionally, training, validation, and testing of the generated unit delay ML model are performed based on the corresponding training datasets, validation datasets, and test datasets. Further optionally, training is performed using a random forest algorithm.

[0055] In one example, the training of the slew rate ML model, the signal line delay ML model, and the cell delay ML model uses a random forest training algorithm applied via a software program (e.g., a TensorFlow program).

[0056] In one example, the ERD feature extractor 4 receives input indicating features, sends data and instructions to a design flow tool 5, and receives responses from it to construct a platform (e.g., a SPICE platform) using the design flow tool 5 (e.g., a SPICE platform builder). This platform has values ​​of design features used by a specific ML model (e.g., signal line tracks, buffers, and switches) and the corresponding signal line topology (i.e., how the various components are connected together). The ERD feature extractor 4 is operable to read the received ERD example and extract the ERD feature values, and construct instances of a slew rate database 12, a signal line delay database 13, and a cell delay database 14, wherein the extracted ERD slew rate feature values ​​(i.e., ERD slew rate feature values) are stored in the instance of the slew rate database 12, the extracted ERD signal line delay feature values ​​(i.e., ERD signal line delay feature values) are stored in the instance of the signal line delay database 13, and the extracted ERD cell delay feature values ​​(i.e., ERD cell delay feature values) are stored in the instance of the cell delay database 14. Then, the ERD feature extractor 4 is operable to send data and instructions to the design flow tool 5 and receive responses from it. The design flow tool 5 is then operable to run a SPICE simulation or other circuit simulator program and calculate the ERD true label for each slew rate (slew rate true label), each signal line delay (signal line delay true label), and each cell delay (cell delay true label) in the ERD example. The design flow tool 5 stores the calculated ERD true labels (e.g., by concatenating each calculated true label to a corresponding feature value used to generate true labels to form data records), and stores the slew rate data records in the corresponding instances of the slew rate database 12, the signal line delay data records in the corresponding instances of the signal line delay database 13, and the cell delay data records in the corresponding instances of the cell delay database 14.

[0057] The training, validation, and testing ML module 6 divides the conversion rate data records (including the calculated ERD conversion rate true labels and the extracted ERD conversion rate feature values) to create a conversion rate training dataset, a conversion rate validation dataset, and a conversion rate test dataset, and stores these datasets in corresponding instances of the conversion rate database 12; it also divides the signal line delay data records (including the calculated ERD signal line delay true labels and the extracted ERD signal line delay feature values) to create a signal line delay training dataset, a signal line delay validation dataset, and a signal line delay test dataset, and stores these datasets in corresponding instances of the signal line delay database 13; and it further divides the unit delay data records (including the calculated ERD unit delay true labels and the extracted ERD unit delay feature values) to create a unit delay training dataset, a unit delay validation dataset, and a unit delay test dataset, and stores these datasets in corresponding instances of the unit delay database 14. In one example, a data matrix containing data records is read into a data frame for processing and is randomly split, with 20% going into the training dataset, 20% into the validation dataset, and the remainder into the test dataset.

[0058] The training, validation, and testing ML module 6 generates a conversion rate ML model using the features and architecture of the received conversion rate ML model, trains the conversion rate ML model using the training dataset, and stores the configuration file (conversion rate ML model configuration file) of the trained ML model in the corresponding instance of the conversion rate database 12; it generates a signal line delay ML model using the features and architecture of the received signal line delay ML model, trains the signal line delay ML model using the signal line delay training dataset, and stores the configuration file (signal line delay ML model configuration file) of the trained ML model in the corresponding instance of the signal line delay database 13; and it generates a unit delay ML model using the features and architecture of the received unit delay ML model, trains the unit delay ML model using the unit delay training dataset, and stores the configuration file (unit delay ML model configuration file) of the trained unit delay ML model in the corresponding instance of the unit delay database 14. During training, various sets of configuration parameters (also known as hyperparameters) are evaluated, and the set of hyperparameters that best balances training time and ML model accuracy is selected for training the signal line delay ML model, the unit delay ML model, and the conversion rate ML model.

[0059] The Training, Validation, and Testing ML Module 6 validates the trained slew rate ML model using the slew rate validation dataset, the trained signal line delay ML model using the signal line delay validation dataset, and the trained unit delay ML model using the unit delay validation dataset.

[0060] Figure 8 An exemplary training, validation, and testing process (300) is illustrated, including performing initial training and validation (301) on the ML model to identify the first-validated ML model (first-validated slew rate ML model, first-validated signal line delay ML model, or first-validated cell delay ML model). In one example, the first validation of the trained ML model includes feature dropout sensitivity analysis and removal of unnecessary features from the first-validated ML model to avoid overfitting (in this case, the first-validated ML model may not accurately filter out noise in the removed data). The feature dropout sensitivity analysis preserves sufficient features (slew rate features, signal line delay features, and cell delay features, respectively) so that the first-validated ML model does not degenerate to more than the minimum precision value.

[0061] Method 300 includes determining whether the first validated ML model meets predetermined criteria (302). In one example, the predetermined criterion is an error measurement. In this embodiment, the root mean square error (RMSE) or R-squared analysis on the test dataset is used to determine the error in each ML model. The determined error is compared with a stored error threshold (e.g., stored in data storage device 11). If the error exceeds the threshold, the ML model validation fails. In one example, the error threshold is selected to be approximately the same as the error between the design flow tool 5 and the silicon measurement results of the IC device formed using the design flow tool 5, which may be, for example, 5%. In an exemplary embodiment, steps 301 to 302 are performed by the training, validation, and testing ML module 6 of the ML model generation system 10.

[0062] If the first validated ML model meets the predetermined criteria, the validation process ends after online 321, and the training, validation and testing ML module 6 proceeds to testing (310) the first validated ML model.

[0063] The Training, Validation, and Testing ML Module 6 is operable to determine (303) whether the failed ML model is the first failure (303). If the failed ML model is the first failure, the values ​​of additional features of the first-failure ML model are extracted (304) (e.g., the Training, Validation, and Testing ML Module 6 instructs the ERD Feature Extractor 4 and / or the Design Flow Tool 5 to perform the extraction) and stored (305). The Training, Validation, and Testing ML Module 6 updates (306) the first-failure ML model to take the additional features into account, and optionally, stores the updated first-failure ML model in the data storage device 11. The Training, Validation, and Testing ML Module 6 then retrains (307) the first-failure ML model and revalidates (308) the retrained updated first-failure ML model, and stores the revalidated first-failure ML model in the data storage device 11. If the revalidated first-failure ML model does not meet predetermined criteria (309), the process returns to step 303. If the first failed ML model, after revalidation, does indeed meet the predetermined criteria (309), the validation process ends and proceeds to the test ML model (310).

[0064] If the ML model fails more than once (303), the training, validation, and testing ML module 6 adds (311) additional training data from a new ERD example set to the training dataset of the ML model that fails again to generate an updated training dataset, and optionally, stores the updated training dataset. The training, validation, and testing ML module 6 retrains (312) the ML model that fails again using the updated training dataset, stores (313) the retrained ML model that fails again; and revalidates (314) the ML model that fails again, and optionally, stores the revalidated ML model that fails again. If the revalidated ML model that fails again does not meet a predetermined criterion (309), steps 303 and steps 311 to 314 are repeated (i.e., additional training data is added each time via reference numeral 311) until the predetermined criterion is met in step 309. If the re-validated failed ML model meets the predetermined criteria (309), the validation process ends, and the training, validation, and testing ML module 6 proceeds to testing (310) the re-validated failed ML model.

[0065] The Training, Validation, and Testing ML module 6 tests (310) the trained and validated slew rate ML model using the slew rate test dataset, the trained and validated signal line delay ML model using the signal line delay test dataset, and the trained and validated unit delay ML model using the unit delay test dataset. In one example, the tests identify a predetermined rating for each ML model, and each ML model is tested to identify the rating of a particular ML model. If the rating of a particular ML model meets the predetermined rating, then only that ML model is used.

[0066] When the validation and testing of the ML model (optionally) results in the generation of a new ML model, the new ML model is stored (e.g., by overriding the configuration file of a specific ML model), such that the configuration file of the final conversion rate ML model is stored in an instance of conversion rate database 12; the configuration file of the final signal line delay ML model is stored in an instance of signal line delay database 13; and the configuration file of the final cell delay ML model is stored in an instance of cell delay database 14.

[0067] While embodiments and applications of the invention have been shown and described, it will be apparent to those skilled in the art that further modifications can be made without departing from the inventive concept herein. Therefore, the invention is not limited except in the spirit of the appended claims.

Claims

1. A method for designing an integrated circuit with delay verification, the method comprising: Configuration files for storage conversion rate machine learning (ML) models, signal line delay (ML) models, and cell delay (ML) models; Receive user design; Extract the feature values ​​of slew rate feature, signal line delay feature and cell delay feature from the user design to obtain slew rate feature value, signal line delay feature value and cell delay feature value; Load the conversion rate ML model configuration file to form the conversion rate inference core; The extracted conversion rate feature values ​​are used as input to perform the operation of the conversion rate inference core to calculate the predicted conversion rate value; Load the signal line delay ML model configuration file to form the signal line delay inference core; The extracted signal line delay feature values ​​are used as input to perform the operation of the signal line delay inference core to calculate the predicted signal line delay value; Load the cell delay ML model configuration file to form the cell delay inference core; The extracted cell delay feature values ​​are used as input to perform the cell delay inference core operation to calculate the predicted cell delay value; as well as The user design is iterated using ML design flow tools in response to the predicted conversion rate value, the predicted signal line delay value, and the predicted cell delay value until a final user design free of timing violations is obtained.

2. The method of claim 1, wherein, Loading the conversion rate ML model configuration file of the conversion rate ML model to form the conversion rate inference core further includes loading the conversion rate ML model configuration file into a neural network engine, the neural network engine being operable to perform the operation of the conversion rate inference core using the obtained conversion rate feature values ​​as input to calculate the predicted conversion rate value.

3. The method of claim 1, further comprising programming the end-user design into the target field-programmable gate array integrated circuit device.

4. The method of claim 1, further comprising generating a plurality of photomasks corresponding to the end-user design.

5. The method according to claim 1, wherein the method further comprises: The predicted conversion rate value is sent to the ML design flow tool; Send the predicted signal line delay value to the ML design flow tool; as well as The predicted cell delay value is sent to the ML design flow tool.

6. The method according to claim 1, wherein the method further comprises: Generate the conversion rate ML model, the signal line delay ML model, and the cell delay ML model.

7. The method according to claim 6, wherein the method further comprises: Receive inputs indicating the features of the integrated circuit design and the architecture of the conversion rate ML model, the signal line delay ML model, and the cell delay ML model; as well as Receive existing reference design ERD examples, in: Generating the conversion rate ML model includes extracting ERD conversion rate feature values ​​from the ERD example, calculating the true ERD conversion rate label corresponding to the extracted ERD conversion rate feature values, and using the extracted ERD conversion rate feature values ​​and the corresponding true ERD conversion rate label to perform training, validation, and testing on the generated conversion rate ML model. Generating the signal line delay ML model includes extracting ERD signal line delay feature values ​​from the ERD example, calculating the true ERD signal line delay labels corresponding to the extracted ERD signal line delay feature values, and using the extracted ERD signal line delay feature values ​​and the corresponding true ERD signal line delay labels to train, validate, and test the generated signal line delay ML model; and Generating the unit delay ML model includes extracting ERD unit delay feature values ​​from the ERD example, calculating ERD unit delay labels corresponding to the extracted ERD unit delay feature values, and using the extracted ERD unit delay feature values ​​and corresponding ERD unit delay labels to perform training, validation, and testing on the generated unit delay ML model.

8. The method of claim 7, wherein, Verifying the slew rate ML model, the signal line delay ML model, and the cell delay ML model further includes: Perform the first validation to identify the ML model for the first validation; Determine whether the ML model validated in the first test meets the predetermined criteria; If the first validated ML model meets the predetermined criteria, then proceed to testing the first validated ML model; and Each ML model that fails to meet the predetermined criteria during its first validation is identified as a failed ML model, and the failed ML model is modified to meet the predetermined criteria.

9. The method of claim 8, wherein, The modification of the failed ML model further includes: Determine whether the failed ML model is failing for the first time; If the failed ML model is the first failure, then extract the values ​​of the additional features of the first failed ML model, update the first failed ML model to take the additional features into account, retrain the first failed ML model, and revalidate the first failed ML model; and If the ML model fails more than once, additional training data is added to the training dataset of the failed ML model from a new ERD example set to generate an updated training dataset. The failed ML model is then retrained using this updated training dataset, and the failed ML model is revalidated.

10. An integrated circuit design system for delay verification using inference chips, the integrated circuit design system comprising: A data storage device for storing configuration files of a conversion rate machine learning (ML) model, a signal line delay (ML) model, and a unit delay (ML) model; A user design feature extractor is coupled to the data storage device, and the user design feature extractor is used to extract slew rate feature values, signal line delay feature values, and cell delay feature values ​​from the user design. An ML design flow tool, which is coupled to the user design feature extractor and the data storage device; as well as A predictive ML module, coupled to the data storage device, the user-designed feature extractor, and the ML design flow tool, is configured to: The slew rate ML model configuration file is loaded to form the slew rate inference core, the signal line delay ML model configuration file is loaded to form the signal line delay inference core, and the cell delay ML model configuration file is loaded to form the cell delay inference core. The extracted slew rate feature values ​​are used as input to perform the operation of the slew rate inference core to calculate the predicted slew rate value; the extracted signal line delay feature values ​​are used as input to perform the operation of the signal line delay inference core to calculate the predicted signal line delay value; and the extracted cell delay feature values ​​are used as input to perform the operation of the cell delay inference core to calculate the predicted cell delay value. The predicted conversion rate value, the predicted signal line delay value, and the predicted cell delay value are sent to the ML design flow tool. The ML design flow tool is configured to iterate the user design in response to the predicted conversion rate value, the predicted signal line delay value, and the predicted cell delay value until the user design is free of timing violations in order to identify the final user design.

11. The integrated circuit design system for delay verification using an inference chip according to claim 10, wherein the integrated circuit design system further comprises: One or more inputs, the one or more inputs being used to receive inputs indicating features of the integrated circuit design, to receive the architecture of the conversion rate ML model, the signal line delay ML model and the cell delay ML model, and to receive an existing reference design ERD example; An ERD feature extractor, coupled to the input, is configured to extract ERD feature values ​​from the received ERD example to obtain ERD slew rate feature values, ERD signal line delay feature values, and ERD cell delay feature values; Design flow tool, coupled to the ERD feature extractor, is used to calculate the true ERD slew rate label corresponding to the extracted ERD slew rate feature value, calculate the true ERD signal line delay label corresponding to the extracted ERD signal line delay feature value, and calculate the true ERD cell delay label corresponding to the extracted ERD cell delay feature value. Training, validating, and testing the ML module, which is configured as follows: Generate a conversion rate ML model and perform training, validation, and testing using the extracted ERD conversion rate feature values ​​and the corresponding ERD conversion rate ground truth labels; Generate a signal line delay ML model and perform training, validation, and testing using the extracted ERD signal line delay feature values ​​and corresponding ERD signal line delay ground truth labels; and Generate a unit delay ML model and perform training, validation, and testing using the extracted ERD unit delay feature values ​​and the corresponding ERD unit delay ground truth labels.

12. The integrated circuit design system for delay verification using an inference chip according to claim 10, the integrated circuit design system further comprising at least one of a device programmer or a mask generator coupled to the ML design flow tool.

13. A method for designing an integrated circuit with delay verification, the method comprising: It receives inputs from the architecture of the integrated circuit design, including machine learning (ML) models of characteristics and conversion rates, signal line delay (ML) models, and cell delay (ML) models. Receive existing reference design ERD examples; The conversion rate ML model is generated by extracting ERD conversion rate feature values ​​from the ERD example, calculating the true ERD conversion rate label corresponding to the extracted ERD conversion rate feature values, and using the extracted ERD conversion rate feature values ​​and the corresponding true ERD conversion rate label to train, validate, and test the generated conversion rate ML model. The signal line delay ML model is generated by extracting ERD signal line delay feature values ​​from the ERD example, calculating the true ERD signal line delay labels corresponding to the extracted ERD signal line delay feature values, and using the extracted ERD signal line delay feature values ​​and the corresponding true ERD signal line delay labels to train, validate, and test the generated signal line delay ML model. The unit delay ML model is generated by extracting ERD unit delay feature values ​​from the ERD example, calculating ERD unit delay labels corresponding to the extracted ERD unit delay feature values, and using the extracted ERD unit delay feature values ​​and corresponding ERD unit delay labels to perform training, validation, and testing on the generated unit delay ML model. The configuration files for the generated conversion rate ML model, the signal line delay ML model, and the cell delay ML model are stored. Receive user design; Extract the values ​​of slew rate feature, signal line delay feature and cell delay feature from the user design to obtain slew rate feature value, signal line delay feature value and cell delay feature value; Load the conversion rate ML model configuration file to form the conversion rate inference core; The extracted conversion rate feature values ​​are used as input to perform the operation of the conversion rate inference core to calculate the predicted conversion rate value; Load the signal line delay ML model configuration file to form the signal line delay inference core; The extracted signal line delay feature values ​​are used as input to perform the operation of the signal line delay inference core to calculate the predicted signal line delay value; Load the cell delay ML model configuration file to form the cell delay inference core; The extracted cell delay feature values ​​are used as input to perform the cell delay inference core operation to calculate the predicted cell delay value; as well as The user design is iterated in response to the predicted conversion rate value, the signal line delay value, and the cell delay value until a final user design without timing violations is obtained.

14. The method of claim 13, wherein, The training uses the random forest training algorithm.

15. The method of claim 13, further comprising: The extracted ERD conversion rate feature values ​​and the corresponding calculated true labels of ERD conversion rates are divided into conversion rate training dataset, conversion rate validation dataset, and conversion rate test dataset. The generated conversion rate ML model was trained using the conversion rate training dataset. The generated conversion rate ML model was validated using the aforementioned conversion rate validation dataset; The generated conversion rate ML model was tested using the aforementioned conversion rate test dataset; as well as The predicted conversion rate value is sent to the design flow tool.

16. The method of claim 15, further comprising: The extracted ERD signal line delay feature values ​​and corresponding ERD signal line delay true labels are divided into signal line delay training dataset, signal line delay verification dataset, and signal line delay test dataset. The signal line delay ML model is trained using the signal line delay training dataset. The signal line delay ML model was validated using the signal line delay validation dataset. The signal line delay ML model was tested using the signal line delay test dataset; and The predicted signal line delay value is sent to the design flow tool.

17. The method of claim 16, further comprising: The extracted ERD unit delay feature values ​​and corresponding ERD unit delay true labels are divided into unit delay training dataset, unit delay validation dataset, and unit delay test dataset. The unit-delayed ML model is trained using the unit-delayed training dataset. The unit-delayed ML model is validated using the unit-delayed validation dataset. The unit-delay ML model is tested using the unit-delay test dataset; and The predicted cell delay value is sent to the design flow tool.

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