A method and GPU for reducing bandwidth for tessellation factors

Abstract

A graphics pipeline reduces the number of tessellation factors written to and read from graphics memory. A hull shader stage detects whether tessellation factors for at least a threshold percentage of a thread group of patches are the same, and whether tessellation factors for a threshold percentage of the thread group of patches have the same value that indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline. In response to detecting that tessellation factors for at least the threshold percentage of the thread group are the same, the hull shader stage bypasses writing at least a subset of the tessellation factors for the thread group of patches to graphics memory, thus reducing bandwidth and improving efficiency of the graphics pipeline.

Description

Background Technology

[0001] A graphics processing unit (GPU) uses a graphics pipeline consisting of a series of programmable shaders and fixed-function hardware blocks to process three-dimensional (3-D) graphics. For example, a 3-D model of an object visible in a frame can be represented by a set of triangles, other polygons, or patches that are processed in the graphics pipeline to produce pixel values ​​for display to the user. Triangles, other polygons, or patches are collectively referred to as primitives. The process involves mapping a tessellation factor to primitives to represent a finer level of detail indicated by the tessellation factor, which specifies the granularity of the primitives produced by the tessellation process. The GPU includes dedicated memory for storing tessellation factors so that they can be used to map to the primitives being processed in the graphics pipeline. The tessellation factors stored in the dedicated GPU memory are populated with programmatically generated data. Dedicated GPU memory is typically relatively small, which limits the number of tessellation factors that can be stored in it. Furthermore, the overhead required to write and read tessellation factors from memory can be significant. Attached Figure Description

[0002] This disclosure will be better understood by referring to the accompanying drawings, and many features and advantages of this disclosure will be apparent to those skilled in the art. The same reference numerals are used in different drawings to indicate similar or identical items.

[0003] Figure 1 It is a block diagram of a processing system including a graphics processing unit (GPU) according to some implementation schemes, the GPU being used to create visual images intended to be output to a display.

[0004] Figure 2 A graphics pipeline, according to some implementations, is described that can process high-order geometric primitives to generate rasterized images of three-dimensional (3D) scenes while storing and retrieving reduced amounts of surface subdivision factors from memory.

[0005] Figure 3 Depicting according to some implementation schemes Figure 2 The shell shader of the graphics pipeline bypasses writing the subdivision factor to memory and sends an instruction to the face extractor of the graphics pipeline in response to detecting a subdivision factor of at least a threshold percentage of the subdivision factor of the thread group having a value indicating that the face of the thread group should be culled.

[0006] Figure 4 Depicting according to some implementation schemes Figure 2The shell shader of the graphics pipeline bypasses writing the subdivision factor to memory and sends an indication to the face extractor of the graphics pipeline in response to detecting that the subdivision factor of the thread group is at least a threshold percentage with a value indicating that the face of the thread group will be passed to the subdivision stage of the graphics pipeline.

[0007] Figure 5 Depicting according to some implementation schemes Figure 2 The shell shader of the graphics pipeline writes a single instance of the subdivision factor to memory and sends an indication to the patch extractor of the graphics pipeline of all subdivision factors for which the single subdivision factor applies to the patch.

[0008] Figure 6 Multiple surface subdivision factors for packing facets into a single word are described according to some implementation schemes.

[0009] Figure 7 This is a flowchart illustrating a method for bypassing the writing of at least a subset of surface subdivision factors into memory, according to some embodiments. Detailed Implementation

[0010] A graphics pipeline for processing three-dimensional (3-D) graphics is formed by an arrangement of fixed-function hardware blocks supported by programmable shaders and memory. These arrangements are typically specified by the processing order of graphics application programming interfaces (APIs), such as those specified in the specifications of Direct3D 11, Microsoft DX 11 / 12, or the Khronos Group OpenGL / Vulkan API. An example of a graphics pipeline includes a geometric front end implemented using vertex shaders and shell shaders that act on higher-order primitives, such as faces representing 3-D models of a scene.

[0011] The geometry front end provides high-order primitives, such as surface patches and tessellation factors generated by the shell shader, to a surface subdivision unit implemented as a fixed-function hardware block in some implementations. Surface subdivision allows for the dynamic addition and reduction of detail from a 3D polygon mesh based on control parameters. The surface subdivision unit generates low-order primitives (such as triangles, lines, and points) from the input high-order primitives based on tessellation parameters (also referred to herein as tessellation factors) that control the fineness of the 3D polygon mesh. Surface subdivision allows for the production of smoother surfaces than those generated from the original 3D polygon mesh. Low-order primitives, such as polygons, are formed by interconnected vertices. For example, common objects (such as meshes) consist of multiple triangles formed by three vertices. The low-order primitives are provided to the geometry back end, which includes a geometry shader, to replicate, color, or subdivide the low-order primitives. For example, a large amount of hair generation can be provided via the functionality of the geometry shader.

[0012] The vertices of primitives generated from the portion of the graphics pipeline that processes geometric workloads in object space are then... example like The pixel workload in image space is provided via primitive, vertex, and index buffers, as well as a cache memory buffer. The pixel portion includes a fixed-function hardware arrangement combined with a programmable pixel shader to perform culling, rasterization, depth testing, color blending, etc., on the primitives to generate fragments or pixels from the input geometry. In some cases, fragments are individual pixels or subpixels. The programmable pixel shader then colors the fragments to merge them with the scene frame image for display.

[0013] Figures 1 to 7 Systems and techniques for improving the efficiency and bandwidth of graphics processing pipelines are disclosed. In some embodiments, a method for bypassing writing and reading tessellation factors from graphics memory includes: detecting at a shell shader of the graphics processing pipeline of a graphics processing unit (GPU) whether at least a threshold percentage of the tessellation factors of all faces or all faces in a thread group have the same value, and whether the at least threshold percentage of the tessellation factors indicates that faces in the thread group should be culled or that faces in the thread group will be passed to a tessellation extractor. If the at least threshold percentage of the tessellation factors of the thread group indicates that faces in the thread group should be culled (referred herein to as tessellation factors with a value of zero), the shell shader bypasses writing the tessellation factors to graphics memory and sends a message to a face extractor indicating that the tessellation factors of the thread group will be discarded. In response to receiving said message, the face extractor bypasses reading the tessellation factors of the thread group from graphics memory and discards the faces of the thread group.

[0014] If the shell shader determines that at least a threshold percentage of the tessellation factor of the thread group indicates that the facets of the thread group (referred to herein as tessellation factors with a value of one) will be passed to the tessellation stage, the shell shader writes the tessellation factor of the thread group to graphics memory and sends a message to the facet extractor indicating that all tessellation factors of the thread group indicate that the facets of the thread group will be passed to the tessellation stage. In response to receiving the message, the facet extractor bypasses reading the tessellation factor from graphics memory and provides the facets of the thread group to the tessellation stage.

[0015] In some implementations, if the shell shader determines that at least a threshold percentage of the tessellation factors in a thread group have values ​​that are equal to each other but neither zero nor one, the shell shader writes a single instance of the tessellation factor values ​​to memory and sends a message to the patch extractor indicating that a single value of the tessellation factor stored in graphics memory is applied to all the tessellation factors of the patches in the thread group. In response to receiving the message, the patch extractor reads the single tessellation factor from graphics memory and applies the single tessellation factor to each of the patches in the thread group, then provides the patch to the tessellation extractor.

[0016] If the tessellation factors of the facets in a thread group do not have values ​​equal to each other, in some implementations, the shell extractor performs integer compression to write more than one compressed tessellation factor of the facet in a single word to graphics memory. For example, a contour facet is associated with two tessellation factors. Therefore, in some implementations, the shell extractor writes the two tessellation factors for the contour facet in a single word to graphics memory. Similarly, a triangle facet is associated with four tessellation factors. In some implementations, the shell extractor writes all four tessellation factors associated with the triangle facet in a single word to graphics memory. A quadrilateral facet is associated with six tessellation factors. In some implementations, the shell extractor writes the first three tessellation factors associated with the quadrilateral facet in the first single word to graphics memory and the remaining three tessellation factors associated with the quadrilateral facet in the second single word to graphics memory.

[0017] Each patch primitive type (e.g., contour lines, triangles, and quadrilaterals) is associated with two, four, or six tessellation factors. In particular, for tessellation factors equal to zero or one, the bandwidth consumed in writing and reading tessellation factors from GPU memory can be greater than the bandwidth saved by any reduction in the granularity of the tessellation primitives produced using the tessellation factor. By reducing the amount of data written to and read from GPU memory, the graphics processing pipeline improves the bandwidth and efficiency of the GPU.

[0018] Figure 1This is a block diagram of a processing system 100 for implementing bandwidth tessellation factor reduction according to some embodiments. The processing system 100 includes a central processing unit (CPU) 102, a system memory 104, a graphics processing subsystem 106 including a graphics processing unit (GPU) 108, and a display device 110, all communicatively coupled together via a system data bus 112. As shown, the system data bus 112 connects the CPU 102, the system memory 104, and the graphics processing subsystem 106. In other embodiments, the system memory 104 is directly connected to the CPU 102. In some embodiments, the CPU 102, portions of the graphics processing subsystem 106, the system data bus 112, or any combination thereof, are integrated into a single processing unit. Furthermore, in some embodiments, the functionality of the graphics processing subsystem 106 is included in a chipset or some other type of dedicated processing unit or coprocessor.

[0019] The CPU 102 executes programming instructions stored in the system memory 104, acts on data stored in the system memory 104, sends instructions and / or data to be completed (e.g., work or tasks to be performed) to the graphics processing unit 108, and configures the various parts of the graphics processing subsystem 106 for the GPU 108 to perform its work. In some embodiments, the system memory 104 includes dynamic random access memory (DRAM) for storing programming instructions and data for processing by the CPU 102 and the graphics processing subsystem 106.

[0020] In various implementations, CPU 102 sends instructions intended for processing in GPU 108 to a command buffer. In some implementations, the command buffer is located, for example, at system memory 104 coupled to system data bus 112. In other implementations, CPU 102 sends graphics commands for GPU 108 to a separate memory communicatively coupled to system data bus 112. The command buffer temporarily stores a stream of graphics commands, which includes input to GPU 108. The stream of graphics commands includes, for example, one or more command groups and / or one or more status update groups. In some implementations, the command groups include drawing commands (also interchangeably referred to as “drawing calls”) instructing GPU 108 to perform processing on image data to be output for display. For example, a drawing command instructs GPU 108 to render pixels defined by a set of one or more vertices stored in memory (e.g., defined in a vertex buffer). In some implementations, the geometry defined by the set of one or more vertices corresponds to multiple primitives to be rendered.

[0021] GPU 108 receives and processes work transferred from CPU 102. For example, in various embodiments, GPU 108 processes work such as rendering and displaying graphical images on display device 110 using one or more graphics pipelines 114. Graphics pipeline 114 includes fixed-function stages and programmable shader stages. Fixed-function stages include typical hardware stages included in the GPU's fixed-function pipeline. Programmable shader stages include streaming multiprocessors. Each of the streaming multiprocessors is capable of executing a relatively large number of threads simultaneously. Furthermore, each of the streaming multiprocessors is programmable to perform processing tasks related to a variety of applications, including but not limited to linear and nonlinear data transformations, filtering of video and / or audio data, modeling operations (e.g., applying physics to determine the position, velocity, and other properties of objects), etc. In other embodiments, graphics processing subsystem 106 is used for non-graphics processing.

[0022] Furthermore, as shown in the figure, system memory 104 includes application program 116 (e.g., an operating system or other application), application programming interface (API) 118, and GPU driver 120. Application program 116 generates calls to API 118 to produce a desired set of results, typically in the form of a sequence of graphical images. Graphics processing subsystem 106 includes GPU data bus 122, which communicatively couples GPU 108 to graphics memory 124. In various embodiments, the GPU uses graphics memory 124 and system memory 104 for memory operations in any combination. CPU 102 allocates portions of these memories for GPU 108 to perform work. For example, in various embodiments, GPU 108 receives instructions from CPU 102, processes the instructions to render graphics data and images, and stores the images in graphics memory 124. Subsequently, GPU 108 displays the graphical images stored in graphics memory 124 on display device 110. Graphics memory 124 stores data and programming used by GPU 108. Figure 1 As shown, the graphics memory 124 includes a frame buffer 126, which stores data for driving the display device 110.

[0023] In various implementations, GPU 108 includes one or more computing units, such as one or more processing cores 128, which include one or more processing units 130, such as executing threads according to a Single Instruction Multiple Data (SIMD) execution model while simultaneously executing other threads in a wavefront. Processing unit 130 may also be interchangeably referred to as a SIMD unit. A SIMD execution model is an execution model in which multiple processing elements share a single program control flow unit and a program counter and thus execute the same program but are able to execute the program with different data. The processing cores 128 of GPU 108 may also be interchangeably referred to as shader cores or streaming multiprocessors (SMX). The number of processing cores 128 implemented in GPU 108 is a matter of design options.

[0024] Each of one or more processing cores 128 executes a corresponding instantiation of a specific work item to process incoming data, wherein the basic unit of execution in one or more processing cores 128 is a work item (e.g., a thread). Each work item represents a single instantiation of a set of kernels executed in parallel, for example, by a command to be executed in parallel on the device. Work items are executed by one or more processing elements as part of a thread group (e.g., a workgroup) executed at processing core 128. In various embodiments, GPU 108 issues and executes a single processing unit 130. Multiple wavefronts are included in a “thread group,” which comprises a set of work items designated to execute the same program. The thread group is executed by executing each of the wavefronts that constitute the thread group. In some embodiments, wavefronts are executed sequentially on a single processing unit 130, or partially or fully in parallel on different SIMD units. In other embodiments, all wavefronts from the thread group are processed at the same processing core 128. Wavefronts may also be interchangeably referred to as warp, vector, or thread. In some implementations, wavefronts include instances of parallel execution of shader programs, where each wavefront comprises multiple work items that are executed concurrently on a single processing unit 130 according to the SIMD paradigm (e.g., an instruction control unit executes the same instruction stream with multiple data). Scheduler 132 performs operations related to scheduling various wavefronts on different processing cores 128 and processing units 130, as well as other operations on the graphics processing subsystem 106 for orchestrating various tasks.

[0025] The parallelism provided by one or more processing cores 128 is suitable for graphics-related operations such as pixel value calculation, vertex transformation, tessellation, geometry shading, and other graphics operations. The graphics pipeline 114 receives graphics processing commands from the CPU 102 and thus provides computational tasks to one or more processing cores 128 for parallel execution. Some graphics pipeline operations (such as pixel processing and other parallel computational operations) require the same command stream or computational kernel to be executed on a stream or set of input data elements. The corresponding instantiation of the same computational kernel is executed concurrently on multiple processing units 130 within one or more processing cores 128 to process such data elements in parallel. As referred to herein, for example, a computational kernel is a function containing instructions declared in a program and executed on the processing core 128. This function is also referred to as a kernel, shader, shader program, or program.

[0026] The following text is about Figure 2 In more detail, GPU 108 includes a graphics pipeline 114 that reduces the number of tessellation factors written to and read from graphics memory 124. Abstract patch types include contours, triangles, and quadrilaterals. A contour patch is a horizontal line defined by two tessellation factors. A triangle patch is a triangle defined by three outer tessellation factors and one inner tessellation factor, for a total of four tessellation factors. A quadrilateral patch is a square defined by four outer tessellation factors and two inner tessellation factors, for a total of six tessellation factors. In some implementations, each tessellation factor comprises 32 bits. Therefore, writing all tessellation factors of all patches of a thread group to and reading all tessellation factors of patches of a thread group from graphics memory 124 consumes significant bandwidth. Graphics pipeline 114 detects whether at least a threshold percentage of the tessellation factors of the thread groups of a patch are the same, and in some embodiments, detects whether the at least threshold percentage of the tessellation factors of the thread groups of a patch is zero (i.e., indicating that the patch should be discarded) or one (i.e., indicating that the patch will be passed to the tessellation stage of graphics pipeline 114). In some embodiments, the threshold is programmable and is set to a relatively high value, such as 98%. In response to detecting that the threshold percentage of the tessellation factors of the thread groups are the same (or, in some embodiments, the threshold percentage of the tessellation factors is zero or one), graphics pipeline 114 bypasses writing a subset of the tessellation factors of the thread groups of a patch to graphics memory 124 and reading a subset of the tessellation factors of the thread groups of a patch from said graphics memory, thus reducing bandwidth and improving the efficiency of graphics pipeline 114.

[0027] Figure 2A graphics pipeline, according to some implementations, is described that can process high-order geometric primitives to generate rasterized images of three-dimensional (3D) scenes while storing and retrieving reduced amounts of surface subdivision factors from memory. Figure 2 The various elements and pipeline stages associated with the GPU are illustrated. In some implementations, the graphics pipeline includes... Figure 2 Other elements and stages not shown. It should also be noted that... Figure 2 This is merely illustrative, and for example, in some implementations, the actual functional units and pipeline stages shown share hardware circuitry, even if they are in... Figure 2 The stages are schematically shown as separate phases. It should also be understood that each of the stages, elements, and units of the graphics processing pipeline 200 is implemented as needed and therefore includes, for example, appropriate circuitry and / or processing logic for performing associated operations and functions.

[0028] In various implementations, the graphics processing pipeline 200 is configured to render graphics as images depicting a scene with three-dimensional geometry but potentially two-dimensional geometry in virtual space (sometimes referred to herein as "world space"). The graphics processing pipeline 200 typically receives a representation of the three-dimensional scene, processes the representation, and outputs a two-dimensional raster image. These stages of the graphics processing pipeline 200 process data initially presented as attributes at the endpoints (or vertices) of geometric primitives, where primitives provide information about the objects being rendered. Typical primitives in three-dimensional graphics include triangles and lines, where the vertices of these geometric primitives provide information about, for example, xyz coordinates, texture, and reflectivity.

[0029] Throughout the graphics processing pipeline 200, data is read from and written to one or more memory cells, which typically... Figure 2 This is represented as graphics memory 210. Graphics memory 210 includes a hierarchy of one or more memories or caches for implementing buffers and storing surface tessellation factors, vertex data, texture data, etc. Figure 1 Some implementation schemes of the system memory 104 shown are used to implement the graphics memory 210.

[0030] Graphics memory 210 includes video memory and / or hardware state memory, which includes various buffers and / or graphics resources utilized in the rendering pipeline. In various embodiments, one or more individual memory units of graphics memory 210 are embodied as one or more video random access memory units, one or more caches, one or more processor registers, etc., depending on the nature of the data in a particular rendering stage. Therefore, it should be understood that graphics memory 210 refers to any processor-accessible memory utilized in the graphics processing pipeline 200. Processing units such as dedicated GPUs are configured to perform various operations in the pipeline and read / write to graphics memory 210 accordingly.

[0031] The early stages of the graphics processing pipeline 200 include operations performed in world space before the scene is rasterized and converted into screen space as a set of discrete picture elements suitable for output on a pixel display device. Throughout the graphics processing pipeline 200, various resources contained in the graphics memory 210 are utilized at pipeline stages, and the inputs and outputs to the stages are temporarily stored in buffers contained in the graphics memory 210 before the final values ​​of the image are determined.

[0032] Input assembler stage 220 is configured to access information from graphics memory 210 for defining objects representing parts of the scene model. For example, in various embodiments, input assembler stage 220 reads metadata (e.g., points, lines, and / or triangles) from a user-filled buffer and assembles the data into primitives to be used by other pipeline stages of graphics pipeline 200. As used herein, the term "user" refers to application 116 or other entity that provides shader code and 3D objects for rendering to graphics pipeline 200. Input assembler stage 220 assembles vertices into several different primitive types (such as line lists, triangle strips, or primitives with adjacency) based on the metadata included in the user-filled buffer and formats the assembled primitives for use by the remainder of graphics pipeline 200.

[0033] In various implementations, the graphics processing pipeline 200 acts on one or more virtual objects, which are defined by a set of vertices set in world space and have geometry defined relative to coordinates in the scene. For example, the input data utilized in the graphics processing pipeline 200 includes a polygonal mesh model of scene geometry, the vertices of which correspond to primitives processed in the rendering pipeline according to aspects of this disclosure, and an initial vertex geometry is set in graphics memory during the application phase implemented by the CPU.

[0034] Vertex processing stage 230 includes various computations to process the vertices of objects in world-space geometry. In some embodiments, vertex processing stage 230 includes vertex shader stage 232 to perform vertex shader computations, which manipulate various parameter values ​​of vertices in the scene, such as position values ​​(e.g., XY coordinates and Z-depth values), color values, lighting values, texture coordinates, etc. Preferably, vertex shader computations are performed by one or more programmable vertex shaders 232. Vertex shader computations are performed uniquely for each region overlapping with an object, and during vertex shading, object region indices are used to determine which rendering contexts and associated parameters the object uses, and therefore how vertex values ​​should be manipulated for subsequent rasterization. In various embodiments, vertex shader stage 232 is implemented in software, logically receiving a single vertex of a primitive as input and outputting a single vertex. Some embodiments of the vertex shader implement Single Instruction Multiple Data (SIMD) processing, enabling the simultaneous processing of multiple vertices.

[0035] Vertex processing stage 230 optionally includes additional vertex processing calculations that subdivide primitives and generate new vertices and new geometry in world space. In the depicted embodiment, vertex processing stage 230 includes a vertex shader stage 232, a shell shader stage 233, a patch extractor 234, a surface tessellation stage 235, a domain shader stage 236, and a geometry shader stage 237. The shell shader stage 233 acts on input higher-order patches or control points used to define input patches. The shell shader stage 233 outputs a surface tessellation factor and other patch data. Primitives generated by the shell shader stage 233 can be provided to the surface tessellation stage 235 by the patch extractor 234. The surface tessellation stage 235 receives objects (such as patches) from the shell shader stage 233 and generates information identifying primitives corresponding to the input objects, for example, by surface tessell subdividing the input objects based on the surface tessellation factor provided by the shell shader stage 233 to the surface tessellation stage 235. Subdivision subdivides input high-order primitives (such as patches) into a set of low-order output primitives, representing a finer level of detail, for example, indicated by a subdivision factor that specifies the granularity of the primitives produced by the subdivision process. Therefore, a scene model can be represented by a smaller number of high-order primitives (to save memory or bandwidth), and additional detail can be added by subdividing the high-order primitives.

[0036] Domain shader stage 236 takes the domain location as input, and in some implementations, takes other face data as input. Domain shader stage 236 acts on the provided information and generates a single vertex for output based on the input domain location and other information. Geometry shader stage 237 receives the input faces and outputs up to four primitives generated by geometry shader stage 237 based on the input primitives. In some implementations, geometry shader stage 237 retrieves vertex data from graphics memory 210 and generates new graphical primitives, such as lines and triangles, from the vertex data in graphics memory 210. Specifically, geometry shader stage 237 retrieves vertex data of primitives as a whole and generates zero or more primitives. For example, geometry shader stage 237 may act on a triangle primitive with three vertices.

[0037] Once vertex processing stage 230 is complete, the scene is defined by a set of vertices, each with a set of vertex parameter values ​​stored in graphics memory 210. In some implementations, the vertex parameter values ​​output from vertex processing stage 230 include positions defined using different homogeneous coordinates for different regions.

[0038] The graphics processing pipeline 200 then proceeds to the rasterization stage 240. The rasterization stage 240 performs shading operations and other operations, such as clipping, perspective splitting, pruning, and viewport selection. In various embodiments, the rasterization stage 240 transforms the scene geometry into screen space and a set of discrete picture elements (e.g., pixels used during the graphics processing pipeline; however, note that the term pixel does not necessarily mean that a pixel corresponds to a display pixel value in the final display buffer image). The virtual space geometry is transformed into screen space geometry by computing the projection of objects and vertices from world space onto the viewport (or “viewport”) of the scene, which consists of a plurality of discrete screen space pixels sampled by the rasterizer. According to aspects of this disclosure, the screen region comprises a plurality of distinct regions with different rendering parameters, including different rasterization parameters for the different regions.

[0039] The rasterization process stage 240 depicted in the figure includes a primitive assembly stage 242, which sets up primitives defined by each set of vertices in the scene. Each vertex is defined by a vertex index, and each primitive is defined relative to these vertex indices and stored in an index buffer of the graphics memory 210. Primitives should include at least triangles, each defined by three vertices, and also point primitives, line primitives, and other polygonal shapes. During the primitive assembly stage 242, certain primitives are culled. For example, those primitives whose vertex indices and homogeneous coordinate space positions indicate a certain wrap-around order are considered backfaces and are therefore culled from the scene. The primitive assembly stage 242 also includes screen space transformations of primitive vertices, which may include different screen space transformation parameters for different regions of the screen.

[0040] Rasterization stage 240 performs clipping and perspective splitting to transform points to homogeneous space and map vertices to the viewport. Raster data is captured to integer positions, then culled and clipped (to draw the minimum number of pixels), and per-pixel attributes (from per-vertex attributes) are interpolated. In this way, rasterization stage 240 determines which pixel primitives overlap, clips primitives and prepares primitives for the pixel shader, and determines how to invoke pixel shader stage 250.

[0041] In a conventional geometry pipeline, the shell shader stage 233 writes all tessellation factors of all faces to graphics memory 210, and the face extractor 234 reads all tessellation factors of all faces from graphics memory 210. This can waste computational resources and create a processing bottleneck. For example, there are often a large number of rounds where all or a large proportion of the tessellation factors are the same. The shell shader stage 233 detects whether at least a threshold percentage of the tessellation factors of a thread group of faces are the same. If at least a threshold percentage of the tessellation factors of a thread group are the same, in some embodiments, the shell shader stage 233 further detects whether the at least threshold percentage of the tessellation factors of the thread group indicates that the faces of the thread group should be culled (e.g., having a value of zero) or indicates that the faces of the thread group will be passed to the tessellation stage 235 (e.g., having a value of one). In response to detecting that at least a threshold percentage of the tessellation factors of a thread group are the same, the shell shader stage 233 bypasses writing at least a subset of the tessellation factors to graphics memory 210. For example, in response to the detection that at least a threshold percentage of the tessellation factors of a thread group of faces all have the same value of zero or one, the shell shader stage 233 sends a message to the face extractor 234. The shell shader stage 233 bypasses writing the tessellation factors to graphics memory 210, and the face extractor 234 bypasses reading the tessellation factors from graphics memory 210 in response to receiving the message. In response to the detection that at least a threshold percentage of the tessellation factors of a thread group are the same, but not equal to zero or one, the shell shader stage 233 writes a single instance of the values ​​of most of the tessellation factors to graphics memory 210 and sends a message to the face extractor 234 indicating that a single value of the tessellation factor stored in graphics memory 210 applies to all faces of the thread group.

[0042] Figure 3 Depicting according to some implementation schemes Figure 2The shell shader 233 of the graphics pipeline bypasses writing the tessellation factor to graphics memory 210 and sends an indication to the patch extractor 234 of the graphics pipeline that all tessellation factors of the thread group have values ​​indicating that patches of the thread group should be discarded. In response to the shell shader stage 233 detecting that at least a threshold percentage of the tessellation factors of the patches of the thread group have values ​​indicating that patches of the thread group should be discarded (e.g., having a value of zero), the shell shader stage 233 bypasses writing the tessellation factors of the thread group to graphics memory 210. The shell shader stage 233 also sends a message 302 to the patch extractor 234 indicating that all tessellation factors of all patches of the thread group have values ​​indicating that patches of the thread group should be discarded (e.g., equal to zero). In response to receiving message 302, the patch extractor 234 bypasses reading the tessellation factors of the thread group from graphics memory 210. Because a tessellation factor of zero discards a patch, the patch extractor 234 additionally discards the patches of the thread group instead of passing them to the tessellation stage (not shown).

[0043] Figure 4 Depicting according to some implementation schemes Figure 2 The shell shader stage 233 of the graphics pipeline bypasses writing the tessellation factor to graphics memory 210 and sends an indication to the patch extractor 234 of the graphics pipeline in response to detecting that at least a threshold percentage of the tessellation factor of the thread group has a value indicating that the patches of the thread group will be passed to the tessellation stage. In response to the shell shader stage 233 detecting that at least a threshold percentage of the tessellation factor of the thread group's patches has a value indicating that the patches of the thread group will be passed to the tessellation stage (e.g., having a value of one), the shell shader stage 233 bypasses writing the tessellation factor of the thread group to graphics memory 210. The shell shader stage 233 also sends a message 402 to the patch extractor 234 indicating that the tessellation factor of the thread group's patches has a value indicating that the patches of the thread group will be passed to the tessellation stage (e.g., equal to zero). In response to receiving message 402, the patch extractor 234 bypasses reading the tessellation factor of the thread group from graphics memory 210. The patch extractor 234 further expands the patches of the thread group and passes them to the surface subdivision processor (not shown).

[0044] Figure 5 Depicting according to some implementation schemes Figure 2The shell shader stage 233 of the graphics pipeline writes a single instance of the tessellation factor value to graphics memory 210 and sends an indication to the patch extractor 234 of the graphics pipeline that the single tessellation factor value applies to all tessellation factors of the patch. In response to detecting that all tessellation factors associated with patch 506 have the same value, the shell shader stage 233 bypasses writing all tessellation factors of the patch to graphics memory 210. Instead, the shell shader stage 233 writes a single instance of the tessellation factor 502 to graphics memory 210 and sends a flag 504 to the patch extractor 234 indicating that the single instance of the tessellation factor value applies to all tessellation factors corresponding to patch 506. In response to receiving the flag 504, the patch extractor 234 reads the single instance of patch 506 and tessellation factor 502 from graphics memory 210. The patch extractor 234 applies the surface subdivision factor 502 to all surface subdivision factors corresponding to the patch 506, and provides the patch 506 and the surface subdivision factor 502 to the surface subdivision stage 235, which uses the surface subdivision factor to generate the final primitive.

[0045] Figure 6Multiple subdivision factors for a facet packaged in a single word are depicted according to some embodiments. In some embodiments, the shell shader stage writes the subdivision factors to graphics memory in 32-bit words. The value of each subdivision factor is between 0 and 64. Therefore, 8 bits can be used to write each subdivision factor. To reduce the number of words written to and read from graphics memory 210, in some embodiments, the shell shader stage (not shown) packages multiple subdivision factors in a single word. For example, a contour facet has two subdivision factors. The shell shader stage writes a single word 601 to graphics memory (not shown), the word including a first subdivision factor TF-1 602 and a second subdivision factor TF-2 604 corresponding to the contour facet. As another example, a triangle facet has four subdivision factors. The shell shader stage writes a single word 611 into graphics memory, the word comprising a first tessellation factor TF-1 612, a second tessellation factor TF-2 614, a third tessellation factor TF-3 616, and a fourth tessellation factor TF-4 618 corresponding to the triangular facet. Similarly, the quadrilateral facet has six tessellation factors. Because all six 8-bit tessellation factors cannot fit into a single 32-bit word, the shell shader stage packages the six tessellation factors corresponding to the quadrilateral facet into two words. For example, the shell shader stage writes a first word 621 and a second word 627 into graphics memory. The first word includes a first tessellation factor TF-1 622, a second tessellation factor TF-2 624, and a third tessellation factor TF-3 626 corresponding to quadrilateral patches. The second word includes a fourth tessellation factor TF-4 628, a fifth tessellation factor TF-5 630, and a sixth tessellation factor TF-6 632 corresponding to quadrilateral patches. Therefore, the shell shader stage reduces the number of words of tessellation factors written to and read from graphics memory from two to one (in the case of contour patches), from four to one (in the case of triangle patches), and from six to two (in the case of quadrilateral patches).

[0046] Figure 7 This is a flowchart illustrating a method 700 for bypassing the writing of at least a subset of surface subdivision factors to memory, according to some embodiments. In some embodiments, the method is... Figure 1 Graphics pipeline 114 or Figure 2 The graphics processing pipeline 200 is used for implementation.

[0047] At block 702, shell shader stage 233 determines whether the tessellation factors of all faces in the thread group have at least a threshold percentage of equal values. If, at block 702, shell shader stage 233 determines that the tessellation factors of all faces in the thread group do not have at least a threshold percentage of equal values, the method flow continues to block 704. At block 704, shell shader stage 233 determines whether all tessellation factors of the faces in the thread group have equal values. If, at block 704, shell shader stage 233 determines that all tessellation factors of the faces do not have equal values, the method flow continues to block 706. At block 706, shell shader stage 233 writes the tessellation factors of the faces to graphics memory 210. In some embodiments, shell shader stage 233 writes multiple tessellation factors corresponding to a face into a single word. For example, for a contour patch with two subdivision factors, shell shader stage 233 writes both subdivision factors of the contour patch into a single word. For a triangular patch with four subdivision factors, shell shader stage 233 writes all four subdivision factors of the triangle into a single word. For a quadrilateral patch with six subdivision factors, shell shader stage 233, for example, writes the first three subdivision factors of the quadrilateral patch into a first word and the last three subdivision factors of the quadrilateral patch into a second word.

[0048] If, at box 704, the shell shader stage 233 determines that the tessellation factors of at least a threshold percentage of the faces have equal values, the method flow continues to box 708. At box 708, the shell shader stage 233 writes a single instance of the tessellation factor to graphics memory 210 and sends a flag 504 to the face extractor indicating that the single instance of the tessellation factor applies to all tessellation factors corresponding to the face.

[0049] If, at box 702, the shell shader stage 233 determines that the tessellation factors of all faces in the thread group have at least a threshold percentage of equal values, the method flow continues to box 710. At box 710, the shell shader stage 233 determines whether the tessellation factors of all faces in the thread group have values ​​indicating that faces of the thread group should be discarded. If, at box 710, the shell shader stage 233 determines that the tessellation factors of all faces in the thread group have values ​​indicating that faces of the thread group should be discarded, the method flow continues to box 712. At box 712, the shell shader stage 233 bypasses writing the tessellation factors of the thread group to graphics memory 210 and sends message 302, indicating that the tessellation factors of the thread group have values ​​indicating that faces of the thread group should be discarded, to the face extractor 234. In response to receiving message 302, the face extractor 234 bypasses reading the tessellation factors of the thread group from graphics memory 210 and discards (discards) the faces of the thread group.

[0050] At box 710, if the shell shader stage 233 determines that at least a threshold percentage of the tessellation factor for all faces of the thread group does not have a value indicating that faces of the thread group should be discarded, the method flow continues to box 714. At box 714, the shell shader stage 233 determines whether at least a threshold percentage of the tessellation factor for all faces of the thread group has a value indicating that faces of the thread group will be passed to the tessellation stage 235. If, at box 714, the shell shader stage determines that at least a threshold percentage of the tessellation factor for all faces of the thread group has a value indicating that faces of the thread group will be passed to the tessellation stage 235, the method flow continues to box 716. At box 716, the shell shader stage 233 bypasses writing the tessellation factor of the faces of the thread group to graphics memory 210 and sends message 402, indicating that all tessellation factors of all faces of the thread group have a value indicating that faces of the thread group will be passed to the tessellation stage 235, to the face extractor 234. In response to receiving message 402, patch extractor 234 unfolds a patch from graphics memory 210 and provides the patch to tessellation stage 235. If, at block 714, shell shader stage 233 determines that at least a threshold percentage of the tessellation factors for all patches in the thread group does not have a value indicating that patches in the thread group will be passed to tessellation stage 235, the method flow continues to block 708. In this case, because the shell shader stage has determined that at least a threshold percentage of the tessellation factors for all patches in the thread group have equal values, at block 706, the shell shader writes a single instance of the most common tessellation factor value to graphics memory 210 and sends a flag 504 to the patch extractor indicating that the single tessellation factor stored in graphics memory 210 applies to all tessellation factors for all patches in the thread group.

[0051] Computer-readable storage media include any non-transitory storage medium or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compressed optical discs (CDs), digital versatile optical discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tapes, or magnetic hard disks), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical systems (MEMS) based storage media. In some embodiments, the computer-readable storage medium is embedded in a computing system (e.g., system RAM or ROM), fixedly attached to a computing system (e.g., a magnetic hard disk drive), removably attached to a computing system (e.g., an optical disc or a USB-based flash memory), or coupled to a computer system via a wired or wireless network (e.g., a network accessible storage device (NAS)).

[0052] In some implementations, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing the software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data that, when executed by one or more processors, manipulate one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, disk or optical disc storage devices, solid-state storage devices such as flash memory, cache, random access memory (RAM), or one or more other non-volatile memory devices. The executable instructions stored on the non-transitory computer-readable storage medium are source code, assembly language code, object code, or other instruction formats that can be interpreted or executed by one or more processors.

[0053] It should be noted that not all activities or elements described in the general description above are required, nor is it necessary to include only a portion of a specific activity or apparatus. Furthermore, one or more additional activities or elements may be performed in addition to the described activities or elements. Moreover, the order in which the activities are listed is not necessarily the order in which they are performed. Additionally, the concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes can be made without departing from the scope of this disclosure as set forth in the appended claims. Therefore, this specification and drawings are to be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of this disclosure.

[0054] The benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, these benefits, advantages, solutions to problems, and any features that may lead to or make more apparent any benefit, advantage, or solution should not be construed as key, essential, or fundamental features of any or all claims. Furthermore, the specific embodiments disclosed above are illustrative only, as the disclosed subject matter can be modified and practiced in different but equivalent ways that are obvious to those skilled in the art who have benefited from the teachings herein. There is no intention to limit oneself to the details of the construction or design shown herein, except as described in the appended claims. Therefore, it is apparent that the specific embodiments disclosed above are subject to change or modification, and all such variations are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as set forth in the appended claims.

Claims

1. A method comprising: In response to detecting at the shell shader stage of the GPU's graphics pipeline that at least a threshold percentage of the tessellation factors corresponding to multiple faces in a thread group have the same value, the process bypasses writing at least a subset of the tessellation factors corresponding to the multiple faces to the graphics memory of the graphics pipeline.

2. The method according to claim 1, further comprising: In response to detecting at least a threshold percentage of the surface subdivision factor indicating that the plurality of faces should be culled at the shell shader stage, a message indicating that the plurality of faces should be culled is sent to the face extractor of the graphics pipeline; At the patch extractor, in response to receiving the message, the reading of the surface subdivision factor corresponding to the plurality of patches from the graphics memory is bypassed; as well as The plurality of dough pieces are discarded at the dough piece extractor.

3. The method according to claim 1, further comprising: In response to detecting at least the threshold percentage of the subdivision factor corresponding to the plurality of patches at the shell shader stage, indicating that the plurality of patches will be passed to the subdivision stage of the graphics pipeline, a message indicating that all the subdivision factors corresponding to the plurality of patches will be passed to the subdivision stage of the graphics pipeline is sent to the patch extractor of the graphics pipeline. Bypassing the writing of the surface subdivision factor into the graphics memory; At the patch extractor, in response to receiving the message, the reading of the surface subdivision factor corresponding to the plurality of patches from the graphics memory is bypassed; as well as The plurality of facets are sent to the surface subdivision stage.

4. The method according to claim 1, further comprising: In response to detecting at the outer shell shader stage that the subdivision factor corresponding to at least a threshold percentage of one of the plurality of patches has the same value that neither indicates that the plurality of patches should be discarded nor that the plurality of patches will be passed to the subdivision stage of the graphics pipeline, the value of the subdivision factor is written to the graphics memory once and a flag indicating that the value applies to all subdivision factors corresponding to the patch is sent to the patch extractor of the graphics pipeline; In response to receiving the flag at the patch extractor, the value is read from the graphics memory; as well as The value is applied to all surface subdivision factors corresponding to the patch.

5. The method according to claim 1, further comprising: In response to detecting at the outer shell shader stage that all the subdivision factors corresponding to one of the plurality of patches are not the same, at least one word is written to the graphics memory, the at least one word including the plurality of subdivision factors corresponding to the patch and an indication that the at least one word includes the plurality of subdivision factors.

6. The method of claim 5, wherein the patch comprises a contour patch, and the at least one word comprises two surface subdivision factors.

7. The method of claim 5, wherein the patch comprises a triangular patch, and the at least one word comprises four surface subdivision factors.

8. The method of claim 5, wherein the patch comprises a quadrilateral patch, and the at least one word comprises six surface subdivision factors.

9. The method according to claim 5, further comprising: Integer compression is performed on the surface subdivision factor to generate a compressed surface subdivision factor; as well as The compressed surface subdivision factor is written into the graphics memory.

10. A GPU comprising: A patch extractor, configured to read surface subdivision factors stored in graphics memory; as well as The shell shader stage is configured as follows: In response to detecting that at least a threshold percentage of the surface subdivision factors have the same value, the process bypasses writing at least a subset of the surface subdivision factors corresponding to multiple patches in the thread group to the graphics memory.

11. The GPU of claim 10, wherein: The shell shader stage is further configured to, in response to detecting that at least a threshold percentage of the surface subdivision factors have values ​​indicating that the plurality of patches should be discarded, indicate to the patch extractor that all the surface subdivision factors corresponding to the plurality of patches have values ​​indicating that the plurality of patches should be discarded; and The sheet extractor is also configured to: In response to receiving the instruction, bypassing the reading of the surface subdivision factor corresponding to the plurality of patches from the graphics memory; and Discard the multiple facets.

12. The GPU of claim 10, further comprising: Surface subdivision stage; The shell shader stage is further configured to, in response to detecting that at least a threshold percentage of the surface subdivision factors corresponding to the plurality of patches have values ​​indicating that the plurality of patches will be passed to the surface subdivision stage, indicate to the patch extractor that all the surface subdivision factors corresponding to the plurality of patches have values ​​indicating that the plurality of patches will be passed to the surface subdivision stage; and The patch extractor is further configured to provide the plurality of patches to the surface subdivision stage of the GPU in response to receiving the instruction.

13. The GPU of claim 10, wherein: The shell shader stage is also configured to, in response to detecting that all the subdivision factors corresponding to one of the plurality of patches have the same value that neither indicates that the plurality of patches should be discarded nor that the plurality of patches will be passed to the subdivision stage, write the value of the subdivision factor to the graphics memory once and send a flag to the patch extractor indicating that the value applies to all the subdivision factors corresponding to the patch. and The patch extractor is also configured to read the value from the graphics memory in response to receiving the flag and apply the value to all surface subdivision factors corresponding to the patch.

14. The GPU of claim 10, wherein: The shell shader stage is also configured to, in response to detecting that all the subdivision factors corresponding to one of the plurality of patches are different, write at least one word to the graphics memory, the at least one word including the plurality of subdivision factors corresponding to the patch and an indication that the at least one word includes the plurality of subdivision factors.

15. The GPU of claim 14, wherein the patch comprises a contour patch, and the at least one word comprises two surface subdivision factors.

Images