Reprogramming memory cells to compress threshold voltage distribution and improve data retention

Abstract

This disclosure describes techniques for reprogramming memory cells to compress threshold voltage distribution and improve data retention. In one aspect, the memory cells of word line WLn are reprogrammed after the memory cells of an adjacent, later-programmed word line WLn+1 have been programmed. This reprogramming may be limited to the lower-state memory cells of WLn adjacent to the lower-state memory cells of WL+1. The programming pulse magnitudes used in this reprogramming may be customized for the data states of the WLn memory cell and the adjacent WLn+1 memory cell. In some cases, the programming pulse magnitudes may be grouped to reduce the complexity and time of the implementation. This reprogramming may be performed during the idle time of the control circuitry after the initial programming operation has been completed.

Description

Background Technology

[0001] This technology relates to the operation of memory devices.

[0002] Semiconductor memory devices have become increasingly common in a variety of electronic devices. For example, non-volatile semiconductor memories are used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0003] Charge storage materials (such as floating gates) or charge trapping materials can be used in such memory devices to store charges representing data states. Charge trapping materials can be arranged vertically in a three-dimensional (3D) stacked memory structure or horizontally in a two-dimensional (2D) memory structure. An example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture, which comprises a stack of alternating conductive and dielectric layers.

[0004] Memory devices include memory cells that can be arranged in series to form NAND strings (e.g., NAND chains), where select-gate transistors are positioned at the ends of the NAND string to selectively connect the channels of the NAND string to source lines or bit lines. However, various challenges exist in operating such memory devices. Attached Figure Description

[0005] Figure 1A This is a block diagram of an example memory device.

[0006] Figure 1B Depicting Figure 1A Example of temperature sensing circuit 116.

[0007] Figure 2 It is shown Figure 1A A block diagram of one embodiment of the sensing block 51.

[0008] Figure 3 Depicting Figure 1A An exemplary embodiment of the power control circuit 115 for supplying voltage to a block of memory cells.

[0009] Figure 4 This is a perspective view of a memory device 500, which includes... Figure 1A A set of blocks in an exemplary 3D configuration of memory structure 126.

[0010] Figure 5 It shows Figure 1A An exemplary transistor 520 in the memory structure 126.

[0011] Figure 6A Depicting Figure 4An exemplary cross-sectional view of a portion of BLK0, which includes NAND strings 700n and 710n.

[0012] Figure 6B Depicting Figure 6A A close-up view of the stacked area 622.

[0013] Figure 7A Depicting and Figure 4 and Figure 6A An exemplary view of the NAND strings in a consistent block BLK0.

[0014] Figure 7B Depicting the connection to Figure 7A An exemplary view of the memory cells WL5 and WL6 in subblock SB0, the memory cells having corresponding NAND strings, bit lines and sensing circuitry.

[0015] Figure 8A An exemplary Vth distribution is depicted after initial programming of a set of memory cells connected to WLn.

[0016] Figure 8B An exemplary Vth distribution of a set of memory cells connected to WLn is depicted after programming a set of memory cells connected to WLn+1.

[0017] Figure 8C An exemplary Vth distribution of a set of memory cells connected to WLn after reprogramming is depicted.

[0018] Figure 9A The diagram at steps 1100 and 1101 is described. Figure 8A and Figure 11A An exemplary voltage signal used in consistent initial programming operations.

[0019] Figure 9B Depicting in Figure 9A Examples of verification voltages used in different programming loops.

[0020] Figure 10 Describes the use of execution and Figure 9A An exemplary voltage signal for consistent initial programming operations.

[0021] Figure 11A The process for programming and reprogramming memory cell groups to compress the Vth distribution and improve data retention is described.

[0022] Figure 11B Depicting and Figure 11A Step 1100 or 1101 is consistent with the procedure for programming a set of memory cells in the initial programming operation.

[0023] Figure 11C Depicting and Figure 11A Step 1104 is consistent with the process of reprogramming a set of memory cells.

[0024] Figure 11C1 Depicting and Figure 11A Step 1104 is consistent with the process of reprogramming a set of memory cells in multiple operations.

[0025] Figure 11D Depicting and Figure 11A Steps 1102 or 1103 are consistent with the process for reading a set of memory cells.

[0026] Figure 11E Depicting and Figure 11D Step 1140 is consistent with the process used to determine whether the memory cell needs to be reprogrammed.

[0027] Figure 12A Depicting and Figure 11A A first exemplary table of consistent programming pulse values ​​for reprogramming, wherein programming pulse values ​​for data state Er-E of WLn+1 are grouped.

[0028] Figure 12B Depicting and Figure 11A A second exemplary table of consistent programming pulse values ​​for reprogramming, wherein the programming pulse value of the AE state memory cell of WLn varies as the data state of the memory cell of WLn+1 changes between Er and E.

[0029] Figure 12B1 A third exemplary table depicting the values ​​of programmed pulses includes Figure 12B The first subset of the programming pulse values, in the range of 14.75V-18V, is used for... Figure 11C1 Step 1128 is the first reprogramming operation.

[0030] Figure 12B2 A fourth exemplary table depicting the values ​​of programmed pulse magnitudes includes Figure 12B The second subset of the programming pulse values, in the range of 18.25V-20V, is used for... Figure 11C1 The second reprogramming operation in step 1129.

[0031] Figure 12C Depicting and Figure 11A A fifth exemplary table of consistent programming pulse values ​​for reprogramming, wherein the programming pulse values ​​of the data states Er-B and CE of WLn+1 form the first group and the second group, respectively.

[0032] Figure 12DDepicting and Figure 11A A sixth exemplary table of consistent programming pulse values ​​for reprogramming, wherein the programming pulse values ​​of data states A and B of WLn and data state Er-E of WLn+1 form a first group, and the programming pulse values ​​of data state CE of WLn and data state Er-E of WLn+1 form a second group.

[0033] Figure 12E Depicting and Figure 11A A seventh exemplary table of consistent programming pulse values ​​for reprogramming, wherein the programming pulse values ​​for the data states Er and A, B and C, and D and E of WLn+1 form the first group, the second group, and the third group, respectively.

[0034] Figure 12F Depicting and Figure 11A An eighth exemplary table of consistent programming pulse values ​​for reprogramming, wherein the programming pulse values ​​of WLn data state AC and WLn+1 data state Er-B, WLn data state AC and WLn+1 data state CE, WLn data state D and E and WLn+1 data state Er-B, and WLn data state D and E and WLn+1 data state CE form the first group, the second group, the third group, and the fourth group, respectively.

[0035] Figure 13A Depicting and Figure 12A A consistent graph of programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse.

[0036] Figure 13B Depicting and Figure 12B A consistent graph of programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse.

[0037] Figure 13B1 Depicting and Figure 12B1 A consistent graph of programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse.

[0038] Figure 13B2 Depicting and Figure 12B2 A consistent graph of programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse.

[0039] Figure 13CDepicting and Figure 12C A consistent graph of programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse.

[0040] Figure 13D Depicting and Figure 12D A consistent graph of programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse.

[0041] Figure 13E Depicting and Figure 12E A consistent graph of programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse.

[0042] Figure 13F Depicting and Figure 12F A consistent graph of programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse.

[0043] Figure 14 A graph depicting the time comparison between the failure bit count with and without reprogramming is presented. Detailed Implementation

[0044] Apparatus and techniques for reprogramming memory cells to compress threshold voltage distribution and improve data retention are described. Reprogramming can be performed after the initial programming operation.

[0045] In some memory devices, memory cells are interconnected, such as in NAND strings within a block or sub-block. Each NAND string includes: a plurality of memory cells connected in series between one or more drain-select-gate transistors (called SGD transistors) at the drain end of the NAND string's connection bit line; and one or more source-select-gate transistors (called SGS transistors) at the source end of the NAND string or other memory strings or connected groups of memory cells at the source end of the connection source line. Furthermore, the memory cells may be arranged with a common control gate line (e.g., a word line) serving as a control gate. A set of word lines extends from the source side of the block to the drain side of the block. Memory cells can be connected in other types of strings and in other ways.

[0046] In a 3D memory structure, memory cells can be arranged in stacked vertical NAND strings, where the stack includes alternating conductive and dielectric layers. The conductive layers serve as word lines connecting to the memory cells. Each NAND string may have a pillar shape that intersects the word lines to form a memory cell. In a 2D memory structure, memory cells can be arranged in horizontal NAND strings on a substrate.

[0047] After erasing a block of memory cells in an erase operation, programming can occur, where the memory cells are programmed according to the word line programming order. For example, programming can begin with the word line on the source side of the block and proceed to the word line on the drain side, one word line at a time. Alternatively, word lines can be programmed in a sub-block programming order, for example, when there are four sub-blocks (…). Figure 7A When programming, the process extends from SB0 to SB3. For example, first a portion of the memory cells of WLn in SB0 is programmed, then a portion of the memory cells of WLn in SB1 is programmed, then a portion of the memory cells of WLn in SB2 is programmed, and then a portion of the memory cells of WLn in SB3 is programmed. WLn refers to the word line selected for programming. The programming operation may include one or more sets of increasing programming voltages or pulses, which are applied to the word line in the corresponding programming cycle (also known as the program-verify iteration), such as... Figure 9A As described, a verification test can be performed after each programming voltage to determine whether the memory cell has been programmed. This occurs when the memory cell is in the allocated data state, represented by a threshold voltage (Vth) distribution, such as... Figure 8A As shown, the programming is complete.

[0048] However, programming the memory cell on the (n+1)th word line (e.g., WLn+1) tends to alter the Vth of the previously programmed memory cell on the adjacent nth word line WLn. Specifically, adjacent word line interference (NWI) involves capacitive coupling between adjacent memory cells in a NAND string, where a later-programmed memory cell can increase the Vth of an earlier-programmed adjacent memory cell. NWI is expected to worsen in future 3D memory devices as the distance between adjacent memory cells in a NAND string decreases. Data retention loss and lateral charge shift between adjacent memory cells can also alter the Vth of the memory cell from the expected level. Data retention loss is worse at higher temperatures.

[0049] The above problems can be partially addressed by using fine-grained programming processes, such as those involving multiple program iterations, to provide a narrow Vth distribution for the data state. However, this requires additional time and does not compensate for the effects of programming adjacent word lines or adequately address the problem of data retention loss.

[0050] The technology provided in this paper addresses the aforementioned and other problems. In one aspect, after the memory cell of an adjacent, later-programmed word line WLn+1 is programmed, the memory cell of word line WLn is reprogrammed. In one method, reprogramming is limited to the lower-state memory cells of WLn adjacent to the lower-state memory cell of WLn+1. This helps avoid the effects of program interference because it avoids using relatively high programming pulses to program higher-state memory cells. Furthermore, the programming pulse magnitude used in reprogramming can be customized for the data state of the WLn memory cell and the adjacent WLn+1 memory cell of the same NAND string. For example, see... Figures 12A to 12F The table. For example... Figure 12B As shown, for example, when the state of the WLn memory cell is relatively high and / or the state of the WLn+1 memory cell is relatively low, the programming pulse value can be relatively high.

[0051] In some cases, programmable pulse values ​​can be grouped to reduce the complexity and time required for implementation, such as in... Figure 12A and Figures 12C to 12F In some cases, reprogramming can occur in multiple reprogramming operations, such as in... Figure 12B1 and Figure 12B2 In some cases, memory cells are reprogrammed by applying multiple programming pulses to the corresponding word lines and controlling the corresponding bit line voltages to achieve programming during a single programming pulse within the multiple programming pulses, such as... Figures 13A to 13F As described in the diagram, the corresponding bit line voltage is controlled to suppress programming of memory cells during the remaining programming pulses in a plurality of programming pulses. Reprogramming can also be performed without performing verification tests, saving time. Therefore, reprogramming a single memory cell can involve a single programming pulse without verification tests, saving time.

[0052] After the initial programming operation is completed, reprogramming can be performed relatively quickly during the idle time of the control circuit, ensuring that reprogramming does not delay other higher-priority tasks of the control circuit. For example, an entire block of memory cells can be programmed, followed by reprogramming of each word line. Alternatively, a portion of the block can be programmed, followed by reprogramming of each programmed word line. Reprogramming of different word lines can be alternated with other tasks of the control circuit.

[0053] Reprogramming can compress the Vth distribution and improve data preservation.

[0054] These and other features will be discussed further below.

[0055] Figure 1AThis is a block diagram of an exemplary storage device. Memory device 100, such as a non-volatile memory system, may include one or more memory dies 108. Memory die 108 or a chip includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable via word lines through row decoder 124 and via bit lines through column decoder 132. Read / write circuitry 128 includes a plurality of sensing blocks 51, 52, ..., 53 (sensing circuitry) and allows for parallel reading or programming of pages of memory cells. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one or more memory dies 108. The controller may be separate from the memory dies. Commands and data are transmitted between host 140 and controller 122 via data bus 120 and between controller and one or more memory dies 108 via line 118.

[0056] The memory structure can be a 2D memory structure or a 3D memory structure. The memory structure may include one or more memory cell arrays, including 3D arrays. The memory structure may include a monolithic 3D memory structure in which multiple memory stages are formed on (but not in) a single substrate (such as a wafer), without intermediate substrates. The memory structure may include any type of non-volatile memory, which is monolithically formed in one or more physical stages of memory cell arrays having active regions disposed on a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is on or within the substrate.

[0057] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126 and includes a state machine, on-chip address decoder 114, power control module 115 (power control circuitry), temperature sensing circuitry 116, programming pulse table 117, and PE cycle counting and sorting circuitry 119. Storage area 113 may be provided, for example, for operating parameters and software / code. In one embodiment, the state machine is programmed by software. In other embodiments, the state machine does not use software and is implemented entirely in hardware (e.g., electrical circuitry).

[0058] On-chip address decoder 114 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. Power control module 115 controls the power and voltage supplied to word lines, select gate lines, bit lines, and source lines during memory operation. This power control module may include drivers for word lines, SGS and SGD transistors, and source lines. See also... Figure 3In one approach, the sensing block may include a bit line driver. Temperature sensing circuitry 116 can detect the temperature of the memory device, for example, every minute, throughout the lifetime of the memory device. The programming pulse magnitude value in programming pulse table 117 can be adjusted based on the temperature. For example, as the temperature increases, the programming pulse magnitude value can be reduced because the memory cells become easier to program.

[0059] Programming pulse table 117 indicates the values ​​of programming pulses used for reprogramming, as discussed herein. See, for example, [link to table 117]. Figures 12A to 12F Programming pulse table 117 can also indicate the correspondence between programming pulse values ​​and programming pulse counts. For example, see... Figures 13A to 13F .

[0060] The PE cycle counting and classification circuit 119 tracks the number of program-erase (PE) cycles of a block and classifies the block into categories based on the number of PE cycles. For example, a first category, a second category, and a third category can represent relatively low, intermediate, or relatively high numbers of PE cycles. The first category, the second category, and the third category can represent the beginning, middle, and end of a block's lifetime, respectively. Furthermore, blocks can be reclassified periodically, and the number of blocks in each group can change over time. The programming pulse magnitude value in the block's programming pulse table 117 can be adjusted based on the PE classification. For example, as the number of PE cycles increases, the programming pulse magnitude value can be reduced because the memory cell becomes easier to program.

[0061] For a detailed example implementation of the temperature sensing circuit, see [link to example implementation]. Figure 1B Circuits 116 and 119, and Table 117 may include hardware, software, and / or firmware for performing the processes described herein.

[0062] In some specific implementations, some components of the components may be combined. In various designs, one or more components (alone or in combination) of the components other than memory structure 126 may be considered as at least one control circuit configured to perform the techniques described herein, including the steps of the processes described herein. For example, the control circuit may include any one or a combination of control circuit 110, state machine 112, decoders 114 and 132, power control module 115, temperature sensing circuit 116, programming pulse table 117, PE cycle counting and classification circuit 119, failure bit determination circuit 127, sensing blocks 51, 52…53, read / write circuit 128, controller 122, etc.

[0063] An off-chip controller 122 (in one embodiment, circuitry) may include a processor 122e, memories such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct numerous read errors. RAM 122b may be DRAM, which includes a storage location 122c for uncommitted data. During programming, a copy of the data to be programmed is stored in storage location 122c until programming is successfully completed. In response to successful completion, the data is erased from this storage location and committed or released to a block of memory cells. Storage location 122c may store one or more word lines of data.

[0064] A memory interface 122d may also be provided. The memory interface, which communicates with the ROM, RAM, and processor, is a circuit that provides an electrical interface between the controller and the memory die. For example, the memory interface can change the format or timing of signals, provide buffers, isolate surges, latch I / O, etc. The processor can issue commands to the control circuitry 110 (or any other component of the memory die) via the memory interface 122d.

[0065] The memories in controller 122, such as ROM 122a and RAM 122b, include code such as a set of instructions, and the processor is operable to execute that set of instructions to provide the functionality described herein. Alternatively or otherwise, the processor may access the code from a subset 126a of the memory structure, such as reserved areas of memory cells in one or more word lines.

[0066] For example, the controller can use code to access memory structures, such as for programming, reading, and erasing operations. The code may include boot code and control code (e.g., a set of instructions). Boot code is the software that initializes the controller during boot or startup and enables it to access memory structures. The controller can use the code to control one or more memory structures. Upon power-up, processor 122e fetches boot code from ROM 122a or subset 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0067] The controller, such as RAM 122b and / or control circuitry 110, may store parameters indicating the expected number of failed bits in the block. These parameters may include, for example, the number of bits per cell stored in the memory cell, a portion of the word line programmed in the block or sub-block, a portion of the sub-block programmed in the block, the strength of the ECC processing used to store and read data in the block, the duration of the pre-read voltage pulse (if used), and read accuracy, such as bit line or word line voltage settling time and the number of sense passes.

[0068] Generally, control code may include instructions to perform the functions described herein, including the steps of the flowcharts discussed further below, and provide voltage waveforms, including those discussed further below. Control circuitry may be configured to execute instructions for performing the functions described herein.

[0069] In one embodiment, the host is a computing device (e.g., a laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0070] In addition to NAND flash memory, other types of non-volatile memory can also be used.

[0071] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (DRAM) or static random access memory (SRAM) devices; non-volatile memory devices, such as resistive random access memory (ReRAM), electrically erasable programmable read-only memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM); and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured with NAND or NOR.

[0072] The memory device can be formed from passive and / or active components in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as antifuse or phase-change materials, and optional steering elements, such as diodes or transistors. Furthermore, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0073] Multiple memory elements can be configured such that they are connected in series or that each element can be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically contains memory elements connected in series. A NAND string is an example of a group of transistors connected in series, comprising memory cells and SG transistors.

[0074] NAND memory arrays can be configured such that the array consists of multiple strings of memory, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, such as in a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0075] Semiconductor memory elements located within and / or on a substrate can be arranged in two or three dimensions, such as 2D memory structures or 3D memory structures.

[0076] In a 2D memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a 2D memory structure, the memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of the memory elements are formed, or it may be a carrier substrate attached to the memory elements after they have been formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0077] Memory elements can be arranged in a single memory device level in an ordered array (such as in multiple rows and / or columns). However, memory elements can be arranged in unconventional or non-orthogonal configurations. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0078] Arrange a 3D memory array such that the memory elements occupy multiple planes or multiple memory device levels to form a three-dimensional structure (i.e., in the x, y and z directions, where the z direction is substantially perpendicular to the main surface of the substrate and the x and y directions are substantially parallel to the main surface of the substrate).

[0079] As a non-limiting example, a 3D memory structure can be vertically arranged as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column having multiple memory elements. These columns can be arranged in a 2D configuration, for example, in the xy-plane, resulting in a 3D arrangement of the memory elements, where the elements are located on multiple vertically stacked memory planes. Other configurations of the three-dimensional memory elements can also constitute a 3D memory array.

[0080] By way of non-limiting example, in a 3D NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other 3D configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The 3D memory array can also be designed in both NOR and ReRAM configurations.

[0081] Typically, in a monolithic 3D memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic 3D memory array may also have one or more memory layers located at least partially within a single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic 3D array, the layer constituting each memory device level of the array is typically formed on the layer of the lower memory device level of the array. However, the layers of adjacent memory device levels in a monolithic 3D memory array may be shared between memory device levels or there may be intermediate layers between memory device levels.

[0082] 2D arrays can be formed individually and then packaged together to form a non-monolithic memory device with multi-layered memory. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic 3D memory array. Furthermore, multiple 2D or 3D memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0083] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0084] Those skilled in the art will recognize that this technology is not limited to the described 2D and 3D exemplary structures, but encompasses all relevant memory structures as described herein and as understood by those skilled in the art in terms of their nature and scope.

[0085] Figure 1B Depicting Figure 1A An example of a temperature sensing circuit 116. This circuit includes pMOSFETs 131a, 131b, and 134, bipolar transistors 133a and 133b, and resistors R1, R2, and R3. I1, I2, and I3 represent currents. Voutput is the temperature-based output voltage supplied to the analog-to-digital converter (ADC) 129. Vbg is a temperature-independent voltage. A voltage level generation circuit 135 uses Vbg to set multiple voltage levels. For example, a reference voltage can be divided into several levels using a resistor divider circuit.

[0086] The ADC compares Voutput with the voltage level and selects the closest match, outputting the corresponding digital value (VTemp) to the processor 122e. This is data indicating the temperature of the memory device. In one approach, ROM fuse 123 stores data that correlates the matched voltage level with temperature. The processor then uses the temperature to set temperature-based parameters in the memory device, such as by utilizing comparator circuitry.

[0087] Vbg is obtained by applying a base-emitter voltage (Vbe) and a voltage drop across resistor R2 across transistor 131b. Bipolar transistor 133a has a larger area (factor N) than transistor 133b. PMOS transistors 131a and 131b are of equal size and arranged in a current mirror configuration, such that currents I1 and I2 are approximately equal. Therefore, Vbg = Vbe + R2 × I2 and I1 = Ve / R1, thus I2 = Ve / R1. Therefore, Vbg = Vbe + R2 × kTln(N) / R1 × q, where T is temperature, k is the Boltzmann constant, and q is the unit of charge. The source of transistor 134 is connected to the supply voltage Vdd, and the node between the transistor's drain and resistor R3 is the output voltage Voutput. The gate of transistor 134 is connected to the same terminal as the gates of transistors 131a and 131b, and the current through transistor 134 mirrors the current through transistors 131a and 131b.

[0088] Figure 2 It is shown Figure 1A A block diagram of one embodiment of the sensing block 51. The individual sensing block 51 is divided into one or more core portions referred to as sensing circuits 60-63 or sensing amplifiers, and a common portion referred to as management circuitry 190. In one embodiment, each sensing circuit is connected to a corresponding bit line and NAND string, and the common management circuitry 190 is connected to a group of multiple (e.g., four or eight) sensing circuits. Each sensing circuit in the group communicates with its associated management circuitry via a data bus 176. Therefore, there are one or more management circuits communicating with the sensing circuitry of a group of memory elements (memory cells).

[0089] As an example, sensing circuit 60 operates during a programming cycle to provide a pre-charge / programming-suppression voltage to unselected positioning lines or a programming-enable voltage to selected positioning lines. See also Figure 10 In the Vbl, the unselected bit line connects to the unselected NAND string and the unselected memory cell within it. The unselected memory cell can be a memory cell within the unselected NAND string, where the memory cell is connected to either the selected or unselected word line. Alternatively, the unselected memory cell can be a memory cell within the selected NAND string, where the memory cell is connected to the unselected word line. The selected bit line connects to the selected NAND string and the selected memory cell within it.

[0090] The sensing circuit 60 also operates during the verification test in the programming cycle to sense the memory cell, thereby determining whether it has been programmed by reaching the assigned data state (e.g., as indicated by Vth, the verification voltage of the assigned data state). The sensing circuit 60 also operates during read operations to determine the data state to which the memory cell has been programmed. The sensing circuit performs this sensing by determining whether the conduction current in the connected bit lines is above or below a predetermined threshold level. This indicates whether Vth of the memory cell is below or above the word line voltage, respectively.

[0091] The sensing circuit may include a selector 56 or a switch connected to transistor 55 (e.g., nMOS). Based on the voltage at the control gate 58 and drain 57 of transistor 55, the transistor may operate as a transmission gate or a bit line clamp. When the voltage at the control gate is sufficiently higher than the voltage at the drain, the transistor operates as a transmission gate to pass the voltage at the drain to the bit line (BL) at the source 59 of the transistor. For example, a programming-suppression voltage such as 1V to 2V may be passed when pre-charging and suppressing an unselected NAND string. Alternatively, a programming-enable voltage such as 0V may be passed to allow programming in a selected NAND string. Selector 56 may pass a supply voltage Vdd (e.g., 3V to 4V) to the control gate of transistor 55 to make it operate as a transmission gate.

[0092] When the voltage at the control gate is lower than the voltage at the drain, transistor 55 operates as a source follower to set or clamp the bit line voltage at Vcg-Vth, where Vcg is the voltage at the control gate 58 and Vth (e.g., 1V) is the threshold voltage of transistor 55. This assumes the source line is at 0V. This mode can be used during sensing operations such as read and verification operations. Therefore, the bit line voltage is set by transistor 55 based on the voltage output by selector 56. For example, selector 56 can pass Vbl_sense + Vth (e.g., 1.5V) to transistor 55 to provide Vbl_sense (e.g., 0.5V) on the bit line. Vbl selector 173 can pass a relatively high voltage, such as Vdd, to the drain 57, which is higher than the control gate voltage on transistor 55, to provide source follower mode during sensing operations.

[0093] Vbl selector 173 can transmit one of a plurality of voltage signals. For example, the Vbl selector can transmit a program-suppress voltage signal that increases from an initial voltage (e.g., 0V) to a program-suppress voltage, such as Vbl_unsel (also referred to as Vbl_inh) for the corresponding bit line of an unselected NAND string during a programming cycle. Vbl selector 173 can transmit a programming-enable voltage signal, such as 0V, for the corresponding bit line of a selected NAND string during a programming cycle. Figure 3 In this process, the Vbl selector can receive voltage signals from the first voltage source, the second voltage source, and the third voltage source 440a-440c respectively, and select one of these signals, for example, based on a command from the processor 192.

[0094] In one approach, the selector 56 of each sensing circuit can be controlled separately from the selectors of other sensing circuits. The Vbl selector 173 of each sensing circuit can also be controlled separately from the Vbl selectors of other sensing circuits.

[0095] During sensing, sensing node 171 is charged until an initial voltage Vsense_init, such as 3V, is reached. The sensing node is then passed to bit lines via transistor 55, and the amount of decay of the sensing node is used to determine whether the memory cell is in a conductive or non-conductive state. Specifically, comparator circuit 175 determines the amount of decay by comparing the sensing node voltage with a trip voltage during sensing. If the sensing node voltage decays below the trip voltage Vtrip, the memory cell is in a conductive state and its Vth is equal to or lower than the verification voltage. If the sensing node voltage does not decay below Vtrip, the memory cell is in a non-conductive state and its Vth is higher than the verification voltage. For example, the comparator circuit 175 sets the sensing node latch 172 to 0 or 1 based on whether the memory cell is in a conductive or non-conductive state. The data in the sensing node latch can be read by processor 192 and used to update bits of trip latch 174. Subsequently, for the next programming cycle, the processor can use the bits in the trip latch and the allocated data state in latches 194-197 to determine whether the memory cell and NAND string are selected for or not for programming in the programming cycle, thereby passing the appropriate enable or suppress bit line voltage to the bit line respectively. Latches 194-197 can be considered as data latches or user data latches because they store the data to be programmed into the memory cell.

[0096] The management circuitry 190 includes a processor 192, four sets of exemplary data latches 194-197 for the sensing circuits 60-63, and an I / O interface 196 coupled between the data latch sets and the data bus 120. Each sensing circuit may be provided with a set of three data latches, for example, including individual latches LDL, MDL, and UDL. In some cases, different numbers of data latches may be used. In a three-bit implementation per unit, the LDL stores bits for the next page of data, the MDL stores bits for intermediate page data, and the UDL stores bits for the previous page of data.

[0097] Processor 192 performs calculations to determine the data stored in the sensed memory cells and stores the determined data in the set of data latches. Each set of data latches 194-197 stores data bits determined by processor 192 during a read operation and data bits imported from data bus 120 during a programming operation; these data bits represent write data to be programmed into memory. I / O interface 196 provides an interface between data latches 194-197 and data bus 120.

[0098] During a read operation, the system operates under the control of state machine 112, which controls the supply of different control gate voltages to the addressed memory cell. As it progresses through various predefined control gate voltages corresponding to different memory states supported by the memory, a sensing circuit can trip at one of these voltages, and the corresponding output is provided from the sensing circuit to the processor 192 via data bus 176. The processor 192 then determines the resulting memory state by considering the tripping event of the sensing circuit and information about the control gate voltages applied via input line 193 from the state machine. It then calculates the binary code of the memory state and stores the resulting data bits in data latches 194-197.

[0099] Some implementations may include multiple processors 192. In one implementation, each processor 192 will include output lines (not shown) such that each output line is wire-ORed together. In some implementations, the output lines are inverted before being connected to the wires or lines. This configuration allows for rapid determination of when the programming process is complete during programming verification testing, as the state machine receiving the wires or lines can determine when all programmed bits have reached the desired level. For example, when each bit reaches its desired level, a logic zero for that bit is sent to the wire or line (or data one is inverted). When all bits output data 0 (or data one is inverted), the state machine knows to terminate the programming process. Because each processor communicates with eight sensing circuits, the state machine needs to read the wires or lines eight times, or logic can be added to the processor 192 to accumulate the results of the relevant bit lines, so that the state machine only needs to read the wires or lines once. Similarly, by correctly selecting the logic levels, the global state machine can detect when the first bit changes its state and adjust the algorithm accordingly.

[0100] During the programming or verification operation of a memory cell, the data to be programmed (written data) is stored in data latch groups 194-197 from the data bus 120. During reprogramming, the corresponding set of data latches for the memory cell can store data indicating when the memory cell can be reprogrammed based on the programming pulse magnitude value.

[0101] Under the control of the state machine, the programming operation applies a series of programming voltage pulses to the control gate of the addressed memory cell. The amplitude of each voltage pulse can be incrementally increased by one step from the previous programming pulse during the process, a process known as incremental step pulse programming. Each programming voltage is followed by a verification operation to determine whether the memory cell has been programmed to the desired memory state. In some cases, the processor 192 monitors the read-back memory state relative to the desired memory state. When both are consistent, the processor 192 sets the bit line to a programming-inhibited mode, such as by updating its latch. This prevents further programming of the memory cell coupled to the bit line, even if additional programming pulses are applied to its control gate.

[0102] Each set of data latches 194-197 can be implemented as a stack of data latches for each sensing circuit. In one embodiment, each sensing circuit 60 has three data latches. In some specific implementations, the data latches are implemented as shift registers so that parallel data stored therein is converted into serial data for the data bus 120 and vice versa. All data latches corresponding to read / write blocks of memory cells can be connected together to form a block shift register, thereby enabling the serial transfer of input or output data blocks. Specifically, the read / write circuit module group is adjusted such that its data latch group shifts data sequentially into or out of the data bus as if they were part of a shift register for the entire read / write block.

[0103] Data latches indicate when an associated memory cell has reached certain milestones in a programming operation. For example, a latch might identify when the Vth of a memory cell is below a specific verification voltage. Data latches also indicate whether a memory cell is currently storing one or more bits from a page of data. For example, an LDL latch can be used to store the next page of data. An LDL latch is toggled (e.g., from 0 to 1) when the next page bit is stored in the associated memory cell. An MDL or UDL latch is toggled for each three-bit cell when the middle or previous page bit is stored in the associated memory cell, respectively. This occurs when the associated memory cell has completed programming.

[0104] Figure 3 Depicting Figure 1A An exemplary specific implementation of a power control circuit 115 for supplying voltage to blocks of memory cells is provided. In this example, the memory structure 126 includes a group 410 of four associated blocks BLK_0 to BLK_3, and another group 411 of four associated blocks BLK_4 to BLK_7. The blocks may be in one or more planes. Figure 1A The line decoder 124 provides voltages to the word lines and the select gate of each block via a transfer transistor 422. The line decoder provides control signals to the transfer transistors, which connect blocks to the line decoder. In one approach, the transfer transistors for each group of blocks are controlled by a common control gate voltage. Therefore, all transfer transistors in a group of blocks are either on or off at a given time. If a transfer transistor is on, voltage from the line decoder is provided to the corresponding control gate line or word line. If a transfer transistor is off, the line decoder is disconnected from the corresponding control gate line or word line, causing voltage to float on the corresponding control gate line or word line.

[0105] For example, control gate line 412 is connected to transmission transistor groups 413, 414, 415, and 416, which in turn are connected to control gate lines BLK_4, BLK_5, BLK_6, and BLK_7, respectively. Control gate line 417 is connected to transmission transistor groups 418, 419, 420, and 421, which in turn are connected to control gate lines BLK_0, BLK_1, BLK_2, and BLK_3, respectively.

[0106] Typically, programming or reading operations are performed on a selected block at a time within a block. Erasing operations can be performed on a selected block or a sub-block. The line decoder connects global control line 402 to local control line 403. Control lines represent conductive paths. Voltage is supplied on the global control lines of many voltage drivers. Some voltage drivers can supply voltage to switch 450 connected to the global control line. Control transfer transistor 424 is used to transfer voltage from the voltage driver to switch 450.

[0107] The voltage driver may include a selected data word line (WL) driver 447 that provides voltage on the selected data word line during programming or read operations. Driver 447 may provide a pre-charge voltage and a programming voltage on WLn during a programming cycle of a programming operation. Driver 448 may be used for unselected data word lines, and dummy word line drivers 449 and 449a may be used respectively for... Figure 6A Voltages are provided on the dummy word lines WLDD and WLDS. For example, driver 448 can be used to apply a precharge voltage and a pass voltage on unselected word lines during a programming cycle of a programming operation. See also Figure 10 VWL_unsel in.

[0108] The voltage driver may also include a separate SGD driver for each sub-block. For example, such as in Figure 7A In this configuration, SGD drivers 446, 446a, 446b, and 446c can be provided for SB0, SB1, SB2, and SB3, respectively. In one option, SGS driver 445 is common to different sub-blocks within the block.

[0109] Various components, including the line decoder, can receive commands from a controller, such as state machine 112 or controller 122, to perform the functions described herein.

[0110] Well voltage driver 430 supplies voltage to well region 611b in substrate via control line 432. Figure 6A A voltage Vsl is provided. The well voltage driver 430 is an example of a source line driver, where the well region 611b is a source line, for example, a conductive path connected to the source end of a NAND string. In one approach, the well region 611a is common to the block. The block also shares a set of bit lines 442.

[0111] Bit line voltage driver 440 includes a voltage source that supplies voltage to the bit lines. For example, the bit line voltage driver may include a first voltage source 440A configured to output a programming-suppression voltage signal. This signal increases from an initial level such as 0V to a final peak level such as Vbl_unsel to precharge the channels of the corresponding NAND string and prevent programming of the memory cells in the NAND string.

[0112] The bit line voltage driver may also include a second voltage source 440b configured to output a programming-enable voltage signal. This signal may have a fixed voltage, such as 0V, which allows programming of selected memory cells in the corresponding NAND string. The bit line voltage driver may also include a third voltage source 440c configured to output a fixed voltage Vbl_sense, which allows sensing of selected memory cells in the corresponding NAND string. Sensing may occur during a read or verification test. Voltage sources 440A, 440b, and 440c may be connected to sensing circuitry and, for example, used to... Figure 2 The Vbl selector 173 provides the voltage.

[0113] In such Figures 4 to 7B In the stacked memory device shown, multiple sets of interconnected memory cells can be arranged in NAND strings that extend vertically upward from a substrate. In one approach, the bottom (or source end) of each NAND string contacts the substrate, for example, a well region, and the top (or drain end) of each NAND string is connected to a corresponding bit line.

[0114] Figure 4 This is a perspective view of a memory device 500, which includes... Figure 1AA set of blocks in an exemplary 3D configuration of a memory structure 126. On the substrate are exemplary blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements), and peripheral regions having circuitry used by the blocks. Peripheral regions 504 extend along the edges of each block, while peripheral regions 505 are located at the ends of the block set. The circuitry may include voltage drivers that can be connected to the block's control gate layer, bit lines, and source lines. In one approach, control gate layers at a common height in the blocks are commonly driven. The substrate 501 may also carry circuitry beneath the blocks, and one or more lower metal layers patterned in conductive paths to carry signals from the circuitry. These blocks are formed in a middle region 502 of the memory device. In an upper region 503 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals from the circuitry. Each block includes a stacked region of memory cells, where alternating stacked layers represent word lines. In one possible approach, each block has opposing layered sides from which vertical contacts extend upwards to the upper metal layer to form a connection with the conductive path. While four blocks are depicted as an example, two or more blocks extending in the x and / or y directions could be used.

[0115] In one possible approach, these blocks are arranged in a plane, with the length of the plane in the x-direction representing the direction in which the signal path to the word line extends through one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction representing the direction in which the signal path to the bit line extends through one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device. These blocks can also be arranged in multiple planes.

[0116] Figure 5 Depicting Figure 1A An exemplary transistor 520 in the memory structure 126. The transistor includes a control gate CG, a drain D, a source S, and a channel CH, and may, for example, represent a memory cell or a select gate transistor. The drain terminal of the transistor is optionally connected to the bit line BL via one or more other transistors in the NAND string, and the source terminal of the transistor is optionally connected to the source line SL via one or more other transistors in the NAND string.

[0117] Figure 6A Depicting Figure 4 An exemplary cross-sectional view of a portion of BLK0, which includes NAND strings 700n and 710n. In this example, NAND strings 700n and 710n are in different sub-blocks. The block includes a stack 610 of alternating conductive layers (word line layers) and dielectric layers. These layers may be rectangular plates having a height in the z-direction, a width in the y-direction, and a length in the x-direction.

[0118] The stack is described as comprising one, but optionally one or more, alternating conductive and dielectric layers. The stack includes a set of alternating conductive and dielectric layers, wherein memory vias are formed during the manufacturing process.

[0119] The conductive layers include SGS, WLDS, WL0-WL95, WLDD, and SGD(0). WLDS and WLDD are dummy word lines or conductive layers connected to dummy memory cells that are not qualified to store user data. A dummy memory cell may have the same structure as a data memory cell, but the controller considers that the memory cell unqualified to store any type of data, including user data. One or more dummy memory cells may be provided at the drain and / or source ends of the NAND string of the memory cell to provide a gradual transition of the channel voltage gradient. WL0-WL95 are data word lines connected to the data memory cell that are qualified to store user data. By way of example only, the stack includes ninety-six data word lines. DL is an exemplary dielectric layer.

[0120] The top 653 and bottom 650 of the stack are depicted. WL95 is the topmost data word line or conductive layer, and WL0 is the bottommost data word line or conductive layer.

[0121] Each NAND string includes a memory hole 618 or 619, which is filled with a material forming a memory cell adjacent to a word line. For example, in Figure 6B The stacked area 622 is shown in more detail below.

[0122] It is formed by stacking on substrate 611. In one method, well region 611a (see also...) Figure 3 The n-type source diffusion layer or well is located in the substrate. The well region contacts the source terminal of each string of memory cells in the block. In one possible embodiment, the n-type well region 611a is subsequently formed in a p-type well region 611b, which in turn is formed in an n-type well region 611c, which in turn is formed in a p-type semiconductor substrate 611d. In one approach, the n-type source diffusion layer may be shared by all blocks in a plane, and a source line SL is formed to provide voltage to the source terminal of each NAND string in the block.

[0123] The NAND string 700n has a source terminal 613 at the bottom 616b of the stack 610 and a drain terminal 615 at the top 616a of the stack. Metal-filled slots can be provided periodically across the stack as local interconnects extending through the stack, such as to connect source lines to lines above the stack. The slots can be used during word line formation and subsequently filled with metal. Vias can be connected at one end to the drain terminal of the NAND string and at the other end to a bit line.

[0124] In one method, a block of memory cells comprises a stack of alternating control gates and dielectric layers, and the memory cells are arranged in vertically extending memory vias within the stack.

[0125] In one approach, each block includes a trapezoidal edge, with vertical interconnects connecting to each layer, including the SGS, WL, and SGD layers, and extending upwards to a horizontal path to the voltage driver.

[0126] Figure 6B Depicting Figure 6A A close-up view of the stacked region 622. Memory cells are formed at different levels of the stack at the intersection of word line layers and memory vias. SGD transistor 716 connected to SGD(0), dummy memory cell 715 connected to WLDD, and data memory cells 712-714 connected to WL93-WL95 are depicted respectively.

[0127] Atomic layer deposition can be used, for example, to deposit multiple layers along the sidewalls (SW) of memory via 629 and / or within each word line layer. For example, each pillar 685 or column formed by the material within the memory via may include a barrier oxide layer 663, a charge trapping layer 664 or film, such as silicon nitride (Si3N4) or other nitrides, a tunnel layer 665 (e.g., gate oxide), a channel 660 (e.g., comprising polysilicon), and a dielectric core 666 (e.g., comprising silicon dioxide). The word line layer may include a metal barrier layer 661 and a conductive metal 662 (such as tungsten) as a control gate. For example, control gates 690-694 are provided. In this example, all layers except the metal are provided within the memory via. In other methods, some of the layers may be within the control gate layer. Additional pillars are similarly formed in different memory vias. The pillars may form pillared active regions (AA) of the NAND string.

[0128] Each NAND string or each group of connected transistors includes a channel that extends continuously from one or more source-end selected-gate transistors to one or more drain-end selected-gate transistors. For example, channels 700a, 710a, 720a, and 730a extend continuously from the source end to the drain end in NAND strings 700n, 710n, 720n, and 730n, respectively.

[0129] Each memory via may be filled with multiple annular layers, including a barrier oxide layer, a charge trapping layer, a tunneling layer, and a channel layer. The core region of each memory via is filled with the host material, and the multiple annular layers are located between the core region and the word line in each memory via.

[0130] NAND strings can be considered to have floating channels because the length of the channels is not formed on the substrate. Furthermore, NAND strings are provided by multiple word line layers stacked one on top of the other and separated from each other by dielectric layers.

[0131] When a memory cell is programmed, electrons are stored in a portion of the charge-trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge-trapping layer and then pass through the tunnel layer. The Vth of the memory cell increases proportionally to the amount of charge stored. During an erase operation, the electrons return to the channel.

[0132] While the examples above pertain to 3D memory devices with vertically extending NAND strings, the techniques presented herein are also applicable to 2D memory devices where the NAND strings extend horizontally on a substrate. Both 2D and 3D NAND strings can have polysilicon channels with grain boundary traps. Furthermore, these techniques can also be applied to memory devices with other channel materials.

[0133] Figure 7A Depicting and Figure 4 and Figure 6A An exemplary view of the NAND strings in a consistent block BLK0. The NAND strings are arranged in a 3D configuration within sub-blocks of the block. Each sub-block includes multiple NAND strings, with one example NAND string depicted. For example, SB0, SB1, SB2, and SB3 include example NAND strings 700n, 710n, 720n, and 730n, respectively. The NAND strings have... Figure 6A Consistent data word lines, dummy word lines, and select gate lines. Each sub-block comprises a set of NAND strings extending in the x-direction and having a common SGD line or control gate layer. NAND strings 700n, 710n, 720n, and 730n are located in sub-blocks SB0, SB1, SB2, and SB3, respectively. Block programming can be based on word line programming order. One option is to program memory cells in different word line portions within different sub-blocks one at a time, before programming memory cells in the next word line. For example, this could involve programming WL0 in SB0, SB1, SB2, and SB2, then programming WL1 in SB0, SB1, SB2, and SB2, and so on. For example, the word line programming order could start with WL0 (source end word line) and end with WL95 (drain end word line).

[0134] NAND strings 700n, 710n, 720n, and 730n each have channels 700a, 710a, 720a, and 730a, respectively. Additionally, NAND string 700n includes an SGS transistor 701, dummy memory cells 702, data memory cells 703-714, dummy memory cells 715, and an SGD transistor 716. NAND string 710n includes an SGS transistor 721, dummy memory cells 722, data memory cells 723-734, dummy memory cells 735, and an SGD transistor 736. NAND string 720n includes an SGS transistor 741, dummy memory cells 742, data memory cells 743-754, dummy memory cells 755, and an SGD transistor 756. The NAND string 730n includes an SGS transistor 761, a dummy memory cell 762, data memory cells 763-774, a dummy memory cell 775, and an SGD transistor 776.

[0135] This example depicts one SGD transistor at the drain end of each NAND string and one SGS transistor at the source end of each NAND string. In one approach, the SGD transistors in SB0, SB1, SB2, and SB3 can be driven by separate control lines SGD(0), SGD(1), SGD(2), and SGD(3), respectively. In another approach, multiple SGD and / or SGS transistors can be provided in the NAND string.

[0136] Figure 7B Depicting the connection to Figure 7A An exemplary view of the memory cells WL5 and WL6 in sub-block SB0, each memory cell having a corresponding NAND string, bit line, and sensing circuitry. (The image shows...) Figure 7A The NAND string 700n in SB0 contains memory cells 708 and 709, channel 700a, and corresponding bit line BL0. SB0 also includes NAND strings 701n, 702n, and 703n, which have channels 700b, 700c, and 700d, respectively, and are connected to bit lines BL1, BL2, and BL3, respectively. Bit lines BL0-BL3 are respectively connected to... Figure 2 The sensing circuits 60-63.

[0137] Memory cells 708, 708a, 708b, and 708c are connected to WL5, and memory cells 709, 709a, 709b, and 709c are connected to WL6. WL5 is an example of a reprogrammed word line WLn, and WL6 is an example of an adjacent, later-programmed word line WLn+1. Furthermore, in the NAND string 700n, memory cell 708 is an example of a reprogrammed first memory cell, and memory cell 709 is an example of an adjacent second memory cell. Memory cells 708 and 709 form a pair of adjacent memory cells in the NAND string. Similarly, memory cells 708a and 709a, 708b and 709b, and 708c and 709c form an additional three pairs of adjacent memory cells.

[0138] As discussed further below, the decision to reprogram memory cell 708 can be based on its data state and the data state of memory cell 709. Furthermore, if reprogramming is performed, the programming pulse value during reprogramming can be a function of the data states (or other threshold voltage ranges) of memory cells 708 and 709.

[0139] Memory cells 708-708c can be programmed in the same reprogramming operation using the same or different programming pulse values. For example, during a specific programming pulse applied to WL5, memory cell 708 can be enabled for programming, while memory cells 708a-708c are disabled for programming.

[0140] Figure 8A An exemplary Vth distribution of a set of memory cells connected to WLn after initial programming is depicted. Figures 8A to 8C In the diagram, a common vertical axis depicts multiple memory cells on a logarithmic scale, and a common horizontal axis depicts the Vth of the memory cells on a linear scale. Furthermore, each memory cell stores three bits, resulting in eight data states.

[0141] Each memory cell can be associated with a data state based on the data written in the program command. Based on the data state of the memory cell, the memory cell will remain in an erase (Er) state or be programmed into a programmed data state. For example, in a one-bit memory device per cell, there are two data states: erase and programmed. In a two-bit memory device per cell, there are four data states: erase and three programmed data states, referred to as A, B, and C data states. In a three-bit memory device per cell, there are eight data states: erase and seven programmed data states, referred to as A, B, C, D, E, F, and G data states. In a four-bit memory device per cell, there are sixteen data states: erase state S0 and fifteen data states S1-S15. Each data state can be represented by a series of corresponding threshold voltages (Vth) in the memory cell. For example, an A-state memory cell has a Vth in the range VrA-VrB.

[0142] After a memory cell is programmed, data can be read back during a read operation. A read operation may involve applying a series of read voltages to a word line while sensing circuitry determines whether a cell connected to the word line is in a conductive (on) or non-conductive (off) state. If the cell is in a non-conductive state, the Vth of the memory cell exceeds the read voltage. This read voltage is set to a level between threshold voltage levels expected in adjacent data states. Furthermore, during a read operation, the voltage of an unselected word line ramps up to a read-through or on level that is high enough to place the unselected memory cell in a strongly conductive state to avoid interfering with the sensing of the selected memory cell. The word line being programmed or read is referred to as the selected word line WLn.

[0143] In one approach, at the start of a programming operation, memory cells are initially in an erase (Er) state, as shown by Vth distribution 800. After successful programming, memory cells allocated to the AG state are represented by Vth distributions 811-817, respectively. Memory cells in the Er state are represented by Vth distribution 810, which shifts upward from the initial Vth distribution 800 due to program interference.

[0144] Memory cells programmed to the AG state are verified using verification voltages (Vverify) from VvA to VvG. These Vth distributions are obtained immediately after the programming operation, assuming no adjacent word line interference or data retention loss. Read voltages VrA to VrG are used to read the state of the memory cell during a read operation.

[0145] In an erase operation, a memory cell transitions from a Vth distribution of programmed data states (e.g., state AG) to an erase state. The erase operation includes an erase phase where the memory cell is biased for erasure, followed by an erase-verification test. The erase-verification test can be performed using an erase verification voltage VvEr applied to the word line.

[0146] In this eight-state example, the Er-G state is an example of the assigned data state, and the AG state is an example of the programmed data state.

[0147] Figure 8B An exemplary Vth distribution for a set of memory cells connected to WLn after programming a set of memory cells connected to WLn+1 is depicted. WLn has not yet been reprogrammed. As mentioned, the Vth of the WLn memory cells can increase due to NWI, especially when the data state of the WLn+1 memory cell is significantly higher than that of its neighboring WLn memory cells. For example, the Vth increase for the A-state memory cells of WLn is maximum when the neighboring WLn+1 memory cell is in state G. When the data state of the WLn+1 memory cell is low, the Vth of the WLn memory cells typically does not increase due to NWI. For example, the Vth for the A-state memory cells of WLn may be unaffected when the neighboring WLn+1 memory cell is in state Er. The A-state memory cells of WLn may experience an intermediate amount of Vth increase when the neighboring WLn+1 memory cell is in an intermediate state (such as state D); or the D-state memory cells of WLn may experience an intermediate amount of Vth increase when the neighboring WLn+1 memory cell is in state G.

[0148] Typically, as the data state of a WLn memory cell increases, the increase in Vth due to NWI becomes smaller. For example, the increase in Vth for a D-state memory cell of WLn will be less than the increase in Vth for an A-state memory cell of WLn, such as when the WLn+1 memory cell is in the G state.

[0149] Given the above, the Vth distribution of the programming data state will consist of different component Vth distributions, which represent different amounts of Vth increase due to NWI. For example, the Vth distribution 801 of state A includes Vth distribution 811, which indicates no upward shift, such as for a state A WLn memory cell adjacent to a state Er WLn+1 memory cell; and Vth distribution 821, which indicates a significant upward shift, such as for a state A WLn memory cell adjacent to a state G WLn+1 memory cell. For simplicity, two component Vth distributions are depicted. Vth distribution 810 will also include other component Vth distributions, such as for a state A WLn memory cell adjacent to a state AF WLn+1 memory cell. When WLn+1 is programmed, the Vth distribution for the programming data state widens and shifts upward due to the change in the component Vth distributions.

[0150] Similarly, the Vth distribution 802 for state B includes a Vth distribution 812 that indicates no upward shift, such as for a state B memory cell adjacent to a state WLn+1 memory cell; and a Vth distribution 822 that indicates a significant upward shift, such as for a state B memory cell adjacent to a state G memory cell.

[0151] The Vth distribution 803 for state C includes a Vth distribution 813, which indicates no upward shift, such as for a state C memory cell WLn adjacent to a state Er memory cell WLn+1; and a Vth distribution 823, which indicates a significant upward shift, such as for a state C memory cell WLn adjacent to a state G memory cell WLn+1.

[0152] The Vth distribution 804 for state D includes a Vth distribution 814, which indicates no upward shift, such as for a state D memory cell adjacent to a state D memory cell WLn+1 memory cell; and a Vth distribution 824, which indicates a significant upward shift, such as for a state D memory cell adjacent to a state G memory cell WLn+1 memory cell.

[0153] The Vth distribution 805 for state E includes a Vth distribution 815, which indicates no upward shift, such as for an E-state WLn memory cell adjacent to an Er-state WLn+1 memory cell; and a Vth distribution 825, which indicates a significant upward shift, such as for an E-state WLn memory cell adjacent to a G-state WLn+1 memory cell.

[0154] The Vth distribution 806 for state F includes Vth distribution 816, which indicates no upward shift, such as for an F-state WLn memory cell adjacent to an Er-state WLn+1 memory cell; and Vth distribution 826, which indicates a small upward shift, such as for an F-state WLn memory cell adjacent to a G-state WLn+1 memory cell. The F-state memory cell is minimally affected by the data state of its adjacent WLn+1 memory cell.

[0155] The Vth distribution 807 for state F essentially includes the Vth distribution 817, indicating no significant upward shift. The memory cell for state G is minimally affected by the data state of the adjacent WLn+1 memory cell.

[0156] Programming the WLn+1 memory cell widens and shifts the Vth distribution of the WLn memory cell upwards. If the widening is too large, this can lead to read errors, even if the read voltages VrA-VrG are adjusted.

[0157] The reprogramming techniques described herein can counteract widening to compress the Vth distribution. In one aspect, the technique is based on classifying each WLn memory cell into a corresponding Vth range. For example, Vth range 840 includes a subset of data states, such as states Er-E, which can be considered lower data states among multiple data states Er-G. Vth range 841 includes another subset of data states, such as states F and G, which can be considered one or more higher data states among multiple data states. In one approach, the decision to reprogram a WLn memory cell is based on whether the WLn memory cell and its adjacent WLn+1 memory cell are both classified as lower data states.

[0158] Figure 8C An exemplary Vth distribution of a set of memory cells connected to WLn after reprogramming is depicted. Reprogramming increases Vth distributions 811-815 to become narrower Vth distributions 831-835 (each for state AE). Therefore, reprogramming adds the lower tail of Vth distributions 801-805. Thus, the overall Vth distributions 801a-805a for state AE are respectively... Figure 8B The Vth distribution 801-805 is narrower. In this example, the F and G state memory cells of WLn are not reprogrammed because their Vth is already relatively narrow. Furthermore, relatively large programming pulses would be required to increase the Vth of these higher state memory cells, which could potentially cause program interference to the lower state memory cells of WLn.

[0159] Figure 9A The diagram at steps 1100 and 1101 is described. Figure 8A and Figure 11A An exemplary voltage signal used in a consistent initial programming operation. Voltage signal 900 includes a set of programming pulses applied to the word line selected for programming, including an initial programming pulse 901. This initial programming pulse has a voltage Vpgm_init, and dVpgm represents the step size between consecutive programming pulses. As an example, a single programming pass with fifteen programming cycles is used. As the programming operation progresses, a verification signal (including exemplary verification signal 902) in each programming cycle may include a lower allocation data state, then an intermediate allocation data state, and then a higher allocation data state, such as... Figure 9B As shown. See also Figure 10 Signals, such as details of programming loops.

[0160] The example verification signal depicts three verification voltages for simplicity. The verification signal is applied to the selected word line during the programming cycle after the programming pulse is applied. During the verification test, the memory cell is sensed to determine its programming progress while the verification signal is applied. The verification signal includes one or more voltages used to determine whether the memory cell has completed programming to the allocated data state. The result of sensing Vth relative to the verification voltage can be used to suppress further programming of the memory cell.

[0161] Data that is programmed or read can be arranged into pages. For example, with two bits per unit, two pages of data can be stored in memory cells connected to the word line. The next and previous pages of data can be determined by reading the memory cells using read voltages VrA and VrC; and VrB, respectively.

[0162] With three bits per cell, three pages of data can be stored in memory cells connected to the word lines. The data for the next, middle, and previous pages can be determined by reading the memory cells using the read voltages of VrA and VrE; VrB; and VrC and VrG, respectively.

[0163] Figure 9B Depicting in Figure 9A Examples of verification voltages used in different programming loops. Horizontal bars and... Figure 9A The programming cycle axis is aligned in time. These bars overlap in some programming cycles, allowing verification operations to be performed on multiple data states within the programming cycle. In the case of eight data states, the bars indicate that verification voltages for states A, B, C, D, E, F, and G will be applied to programming cycles 1-4, 3-6, 5-8, 7-10, 9-12, 11-14, and 12-15, respectively.

[0164] In one approach, the programming cycle for performing verification tests is predetermined before programming operations. In another approach, the programming cycle for performing verification tests is adaptively determined as programming progresses. For example, after a specified portion of a memory cell in state A has passed its verification test, the verification test for state B can begin in the next programming cycle.

[0165] Figure 10 Describes the use of execution and Figure 9A An exemplary voltage signal for a consistent initial programming operation. The vertical dimension represents voltage, and the horizontal dimension represents time, where the time points are t0-t12. The depicted time period corresponds to a programming cycle and includes a pre-charge phase 1007 (t0-t2), a programming phase 1008 (t2-t8), and a verification phase 1009 (t9-t12). Voltage signals 1000, 1010, 1030, 1040, and 1050 represent VWLn, VWL_unsel, Vsg, Vbl, and Vsl, respectively.

[0166] During the pre-charge phase, VWLn and VWL_unsel can be set to the pre-charge voltage, such as 1V-2V.

[0167] For bit lines of unselected NAND strings, for example at t0, the programming-suppression voltage signal (curve 1041) ramps up from 0V to 2V to provide a small channel boost during the precharge phase and suppress programming during the programming phase. For bit lines of selected NAND strings, a fixed voltage such as 0V is applied (curve 1032) to avoid channel boost during the precharge phase and allow programming during the programming phase. The programming-enable voltage signal at 0V is depicted by curve 1042.

[0168] The SGD transistors of both the selected and unselected sub-blocks are in a conducting state at this time, for example, with a voltage of Vsg = 6V. This allows the bit line voltage to be transmitted to the channel. The SGS transistors of both the selected and unselected sub-blocks can also be in a conducting state at this time, for example, with a voltage of 6V to allow Vsl = 1V to be transmitted to the source terminal of the channel.

[0169] Vsgd is set to 6V to deliver the bit line voltage to the drain terminal of the NAND string. During the programming phase, VWLn and Vwl_unsel ramp up, for example, starting at t3, to provide capacitive coupling to the channel of the suppressed NAND string. Then, at t5, VWLn ramps up further to the peak programming pulse level of Vpgm (curve 1001) and remains at Vpgm until t4. After the programming pulse is applied, the word line voltage ramps down during recovery. During the programming pulse, Vsgd of the selected sub-block, i.e., Vsgd_sel (curve 1031), is high enough to provide a conducting selected SGD transistor for the selected NAND string, which receives Vbl_sel = 0V, but low enough to provide a non-conductive selected SGD transistor for the suppressed NAND string, which receives Vbl_unsel = 2V. The Vsgd of an unselected subblock, i.e., Vsgd_unsel (curve 1032), can be set to 0V to provide the corresponding SGD transistor in a non-conductive state.

[0170] Subsequently, during the verification phase, one or more verification tests are performed by applying a verification signal with one or more verification voltages (Figure 1002) to WLn, and for each verification voltage, sensing the conductivity state of memory cells in selected NAND strings of selected sub-blocks. SGD and SGS transistors are in a strongly conductive state to allow sensing of selected memory cells. During the verification test, Vbl_sense = 0.5V is applied to the bit line.

[0171] The voltage shown is an example.

[0172] Figure 11A A process for programming and reprogramming a group of memory cells to compress the Vth distribution and improve data retention is described. Step 1100 includes programming a first group of memory cells connected to the first word line (WLn) in an initial programming operation. For example, Figure 9A The programming signals can be used to obtain Figure 8A The Vth distribution. Step 1101 includes programming the second set of memory cells connected to the adjacent second word line (WLn+1) in the initial programming operation. Typically, programming can be performed one word line at a time in a block or sub-block.

[0173] Steps 1102-1104 can be executed by the control circuit at some point after programming (when it reaches an idle state), ensuring no delay for other more important tasks. In one method, the control circuit is configured to read a first memory cell WLn, read a second memory cell WLn+1, and determine whether to reprogram the first memory cell based on the control circuit entering an idle state after programming the second memory cell. In another option, after programming the second set of memory cells, reading and reprogramming are performed in response to receiving a read command involving the first set of memory cells.

[0174] Step 1102 includes reading the first set of memory cells to classify the Vth of each memory cell into a corresponding Vth range (including one or more data states). In one approach, each memory cell is classified into a single data state. In another approach, which provides lower but sufficient read accuracy in a simplified implementation, each cell is classified into a corresponding Vth range that includes multiple adjacent data states. For example, refer to... Figure 8B The read operation can use read voltages VrA-VrF to determine the data state of the Er-E memory cell. The read voltage VrG can be omitted so that memory cells with states F and G are classified together in the Vth range 841. For example, when VrF is applied to WLn, non-conductive memory cells with Vth > VrF can be classified in the Vth range 841. Figures 12A to 12F The programming pulse table discusses various other threshold voltage ranges and read voltages.

[0175] Step 1103 includes reading the second set of memory cells to classify the Vth of each memory cell into a corresponding Vth range (including one or more data states), as discussed in conjunction with step 1102. The corresponding Vth range may be the same as or different from the range in step 1102.

[0176] Step 1104 includes reprogramming the memory cell for each memory cell in the first group of memory cells if the corresponding Vth range is below a specified voltage (or the corresponding data state is below one or more highest data states), and if the corresponding Vth range of an adjacent memory cell in the second group of memory cells is below a specified voltage (or the corresponding data state is below one or more highest data states). For example, the specified voltage could be VrF, as in combination with... Figure 8BThe discussion focuses on this. Equivalently, one or more highest data states can be states F and G. In this case, a decision is made to reprogram the memory cells in the first group of memory cells if the memory cells in the first group of memory cells and the adjacent memory cells in the second group of memory cells are in states Er-E. Typically, the decision to reprogram the first memory cell in the first group of memory cells can be made based on whether the corresponding data state is lower than 25% of the highest data state (e.g., F and G) among multiple data states (e.g., Er-G) and based on whether the corresponding data state of the adjacent second memory cells in the second group of memory cells is lower than 25% of the highest data state among multiple data states.

[0177] If a memory cell in the first group of memory cells and / or an adjacent memory cell in the second group of memory cells are in an F or G state (e.g., 25% of the highest data states), a decision is made not to reprogram the memory cells in the first group of memory cells. The specified voltage and one or more highest data states of the first group of memory cells in WLn may be the same as or different from those of the second group of memory cells in WLn+1.

[0178] from Figures 8A to 8C In retrospect, reprogramming lower-state memory cells is most relevant in terms of compacting the Vth distribution.

[0179] Optionally, the program can be reprogrammed to repeat multiple times at specified intervals.

[0180] Figure 11B Depicting and Figure 11A Steps 1100 or 1101 are consistent with the procedure for programming a set of memory cells in an initial programming operation. The initial programming operation begins at step 1110. Step 1111 includes storing data in a corresponding set of latches for the memory cells to be programmed (e.g., memory cells assigned state AG in an eight-state method) to identify the assigned programming data state among multiple data states. For example, one could use... Figure 2 The latches are 194-197. Step 1111a includes storing data in the appropriate latch group for memory cells that are not programmed (e.g., memory cells assigned to the Er state) to identify the erase data state.

[0181] Step 1112 includes a pre-charge phase for executing the programming loop. In this phase, a programmable-inhibit voltage signal pre-charges the channel of the unselected NAND string. See also... Figure 10Steps 1112a-1112d are part of step 1112. Step 1112a includes reading the latch set to identify memory cells to be programmed in the current programming cycle (PL). Step 1112b includes applying a programming-enable voltage (e.g., 0V) to the corresponding bit line of the memory cell to be programmed in the current PL. Step 1112c includes reading the latch set to identify memory cells not to be programmed in the current PL. Step 1112d includes applying a programming-reject voltage (e.g., 1V-2V) to the corresponding bit line of the memory cell not to be programmed in the current PL.

[0182] Step 1113 includes the programming phase of executing a programming cycle. This may involve applying a programming voltage to a selected word line and passing the voltage to unselected word lines, as in combination. Figure 10 As mentioned, step 1114 includes a verification phase of executing the programming loop. This may involve applying a verification voltage signal to a selected word line and applying a pass voltage to an unselected word line while sensing selected memory cells, such as in combination. Figure 10 As mentioned.

[0183] Step 1115 includes updating the data in the latch based on the verification phase to identify selected and unselected memory cells for the next programming cycle. The sensing results may also be output to the controller to allow it to determine whether programming has been completed for a specific data state or whether the programming operation has been completed.

[0184] Step 1116 determines whether a next programming loop exists. If the decision step is true, step 1112 is repeated for the next programming loop. If the decision step 1116 is false, the programming operation is performed at step 1117.

[0185] Figure 11C Depicting and Figure 11A Step 1104 is consistent with the process for reprogramming a set of memory cells. The reprogramming operation begins at step 1120. Step 1121 includes setting the correspondence between PL (or programming pulse (PP) number) and Vpgm (programming pulse magnitude value), for example at programming pulse table 117. Figures 13A to 13F An example is depicted comparing programming cycle numbers with programming pulse magnitudes. In one approach, the magnitudes of the programming pulses are incremented, starting from the lowest magnitude in the programming pulse table, such as... Figures 12A to 12F In the middle, and ending with the highest value. In such cases... Figure 12B1 and Figure 12B2 In this case, the programmed pulse values ​​can be divided into two subsets, with reprogramming performed through each subset.

[0186] Step 1122 sets the programming cycle number PL = 1. Step 1123 includes storing data in the corresponding latch group for the memory cell to be reprogrammed to identify the corresponding PL for programming. Identifying the PL among multiple PLs in the reprogramming operation is used to identify the programming pulse magnitude value among multiple programming pulse magnitude values. For example, it can be used... Figure 2 The latches 194-197. Step 1123a includes storing data in the corresponding latch group to suppress programming for memory cells that are not reprogrammed, for example, during a reprogramming operation.

[0187] Step 1124 includes a pre-charge phase for executing the programming loop, similar to... Figure 11B Step 1112 is part of step 1124. Steps 1124a-1124d are part of step 1124. Step 1124a includes reading the latch set to identify memory cells to be reprogrammed in the current programming cycle (e.g., the memory cells mentioned in step 1123). Step 1124b includes applying a programming-enable voltage (e.g., 0V) to the corresponding bit line of the memory cell to be reprogrammed in the current PL. Step 1124c includes reading the latch set to identify memory cells not to be reprogrammed in the current PL. Step 1124d includes applying a programming-reject voltage (e.g., 1V-2V) to the corresponding bit line of the memory cell not to be reprogrammed in the current PL.

[0188] Step 1124 includes the programming phase of executing the programming loop, similar to... Figure 11C Step 1113. In one method, the reprogramming operation may be omitted. Figure 10 The verification phase of the programming cycle is removed to save time. Therefore, reprogramming operations can be performed within the time frame. Figure 10 The voltage signal is used during the time period t0-t8. The reprogramming operation can also be omitted. Figure 10 The programming loop includes a pre-charge phase to save additional time.

[0189] Step 1125 determines whether a next programming cycle exists. If the determination is true, PL is incremented at step 1127, and step 1124 is repeated for the next programming cycle. If the determination is false, a reprogramming operation is performed at step 1126.

[0190] Figure 11C1 Depicting and Figure 11A Step 1104 is consistent with the process for reprogramming a set of memory cells in multiple operations. Step 1128 includes performing a first reprogramming operation on a portion of the lower data state memory cells of the set of memory cells of WLn, and applying a first subset of programming pulse magnitude values ​​to WLn. For example, in Figure 12B1In this process, a portion of the lower data state memory cells of a set of memory cells in WLn may be memory cells in state AD (adjacent to memory cells in state Er-E on WLn+1), and a first subset of the programming pulse magnitude values ​​may be 14.75V-18V in increments of 0.25V. Step 1129 includes performing a second reprogramming operation on another portion of the lower data state memory cells of the set of memory cells in WLn, and applying a second subset of the programming pulse magnitude values ​​to WLn. For example, in Figure 12B2 In WLn, another portion of the lower data state memory cells of a set of memory cells can be memory cells in states D and E (which are adjacent to memory cells in states Er-E on WLn+1), and a second subset of the programming pulse magnitude values ​​can be 18.25V-20V in increments of 0.25V. The lower data state memory cells include states AE or Er-E, and a portion of the lower data state memory cells overlaps with another portion because they both include state D.

[0191] By performing individual reprogramming operations, highly accurate reprogramming can be provided using a large number of different programming pulse values ​​without requiring an excessive number of data state latches for each NAND string. For example, Figure 12B The programming pulse table includes twenty-two distinct values, ranging from 14.75V to 20V in 0.25V increments. This requires five data status latches to identify which programming pulse should be applied to a given memory cell, as five binary latches can store up to thirty-two distinct values. Four binary latches are insufficient, as they can only store up to sixteen distinct values. In contrast, Figure 12B1 The table includes fourteen different values ​​(underlined voltages) ranging from 14.75V to 18V in 0.25V increments. Four data status latches are sufficient to identify which programming pulse should be applied to a given memory cell. Figure 12B2 The table includes eight different values ​​(underlined voltages) in 0.25V increments within a range of 18.25V-20V. Therefore, four data status latches are again sufficient to handle individual reprogramming operations.

[0192] Figure 11D Depicting and Figure 11ASteps 1102 or 1103 are consistent with the process for reading a group of memory cells. Step 1130 initiates a read operation for the first group of memory cells connected to the first word line WLn. Step 1131 includes applying a control gate read voltage (Vcgr) to the first word line and applying a read pass voltage to the remaining unselected word lines. Step 1132 includes sensing the conductive or non-conductive state of each memory cell in the first group of memory cells. Decision step 1133 determines whether to apply the next Vcgr. If decision step 1133 is true, step 1131 is repeated. If decision step 1133 is false, the reading is completed and step 1134 includes classifying the threshold voltage of each memory cell in the first group of memory cells into a corresponding data state or threshold voltage range based on the sensing.

[0193] Steps 1134 and 1139 together identify lower data state memory cells in the first group of memory cells that are adjacent to lower data state memory cells in the second group of memory cells (e.g., in Er-E state), and higher data state memory cells in the first group of memory cells that are adjacent to higher data state memory cells in the second group of memory cells (e.g., in F and G states). The lower data state memory cells in the first and second groups of memory cells comprise the lowest programmed data state (e.g., state A) among a plurality of data states; and the higher data state memory cells in the first and second groups of memory cells comprise the highest data state (e.g., state G) among a plurality of data states.

[0194] Step 1135 initiates a read operation for the second set of memory cells connected to the second word line WLn+1. Step 1136 includes applying a control gate read voltage (Vcgr) to the second word line and applying a read pass voltage to the remaining unselected word lines. Step 1137 includes sensing the conductive or non-conductive state of each memory cell in the second set of memory cells. Decision step 1138 determines whether to apply the next Vcgr. If decision step 1138 is true, step 1136 is repeated. If decision step 1138 is false, the reading is completed and step 1139 includes classifying the threshold voltage of each memory cell in the second set of memory cells into a corresponding data state or threshold voltage range based on the sensing.

[0195] Step 1140 includes determining, for each memory cell in the first group of memory cells, whether to reprogram the memory cell based on its corresponding data state or threshold voltage range and based on the corresponding data state or threshold voltage range of adjacent memory cells in the second group of memory cells. See also Figure 11A Step 1104 and Figure 11E .

[0196] In one approach, the data states of a pair of memory cells, specifically the WLn memory cell and the adjacent WLn+1 memory cell, can be stored in a set of associated latches. In another approach, the data state of one memory cell in the pair is stored in a set of associated latches, and the data state of the other memory cell in the pair is stored in another location, such as an off-chip controller 122, for example, at the ECC engine 245, or at an on-chip location such as circuitry 110.

[0197] Figure 11E Depicting and Figure 11D Step 1140 is consistent with the process for determining whether to reprogram a memory cell. An exemplary memory cell in the first group of memory cells is referred to as a first memory cell, and an exemplary adjacent memory cell in the second group of memory cells is referred to as a second memory cell. The process can be performed for each memory cell in the first group of memory cells. Step 1150 determines whether the threshold voltage range of the first memory cell is below a specified voltage (or its data state is below one or more of the highest data states among a plurality of data states). For example, in Figure 8B In this context, VrF can be a specified voltage, and one or more highest data states can be F and G states. Therefore, the decision step determines whether the first memory cell is in the Er-E state. If decision step 1150 is false, step 1153 instructs a decision not to reprogram the first memory cell. For example, if the first memory cell is in the F or G state, then reprogramming the first memory cell is not required. If decision step 1150 is true, then decision step 1151 is reached.

[0198] Step 1151 determines whether the threshold voltage range of the adjacent second memory cell is lower than a specified voltage (or its data state is lower than one or more of the highest data states among a plurality of data states). If step 1151 is false, step 1153 instructs the first memory cell not to be reprogrammed. For example, if the adjacent second memory cell is in state F or G, the first memory cell may not be reprogrammed. If step 1151 is true, step 1152 instructs a decision to reprogram the first memory cell.

[0199] Figures 12A to 12FThe programming pulse tables depict exemplary programming pulse voltages or magnitudes. Each table lists the data states of the WLn memory cells in the left-hand column and the data states of the adjacent WLn+1 memory cells in the top row. For each pair of WLn and WLn+1 data states, there is a corresponding programming pulse magnitude for reprogramming the corresponding WLn memory cell. The symbol "na" indicates not applicable, meaning that no reprogramming was performed for the indicated pair of WLn and WLn+1 data states. Figure 12A and Figures 12C to 12F In the middle, the dashed box identifies the programming pulse value of the grouped data status.

[0200] Figure 12A Depicting and Figure 11A A first exemplary table of consistent programming pulse values ​​for reprogramming is provided, where programming pulse values ​​for the data states Er-E of WLn+1 are grouped. Generally, grouping the WLn and / or WLn+1 data states reduces implementation complexity because it reduces the number of different programming pulse values ​​and read operations. This example groups the WLn+1 data states. The method still provides good results because it customizes the programming pulse values ​​for the data states of the WLn memory cells. There are five programming pulse values ​​in a 16-20V range, incremented by 1V. No reprogramming occurs when the WLn memory cell is in the Er, F, or G states. Furthermore, no reprogramming occurs when the WLn+1 memory cell is in the F or G states. This applies to each of the exemplary programming pulse values ​​provided herein. When the WLn memory cell is in the AE state, the programming pulse values ​​are 16-20V respectively.

[0201] It is sufficient to perform a read operation on WLn+1 using VrF to identify the memory cell as being in the Er-E Vth range or the F and G Vth range. It is sufficient to perform read operations on WLn using VrA-VrF instead of VrG, because, as with WLn+1, the F and G state memory cells of WLn do not need to be distinguished from each other.

[0202] Figure 12B Depicting and Figure 11A A second exemplary table of consistent programming pulse magnitudes for reprogramming, wherein the programming pulse magnitudes of the AE state memory cell of WLn vary as the data state of the memory cell of WLn+1 changes between Er and E. This example customizes the programming pulse magnitudes for each different pair of WLn and WLn+1 states.

[0203] When the WLn memory cell is in state AE and the WLn+1 memory cell is in state Er, the programming pulse values ​​are 16V-20V respectively. When the WLn memory cell is in state AE and the WLn+1 memory cell is in state A, the programming pulse values ​​are 15.75V-19.75V respectively. When the WLn memory cell is in state AE and the WLn+1 memory cell is in state B, the programming pulse values ​​are 15.50V-19.50V respectively. When the WLn memory cell is in state AE and the WLn+1 memory cell is in state C, the programming pulse values ​​are 15.25V-19.25V respectively. When the WLn memory cell is in state AE and the WLn+1 memory cell is in state D, the programming pulse values ​​are 15V-19V respectively. When the WLn memory cell is in state AE and the WLn+1 memory cell is in state E, the programming pulse values ​​are 14.75V-18.75V respectively. It should be noted that this is valid when some programming pulse values ​​are used for multiple combinations of WLn / WLn+1 data states.

[0204] The programming pulse value is relatively high when the data state of the WLn memory cell (first memory cell) is relatively high and the data state of the adjacent WLn+1 memory cell (second memory cell) is relatively low.

[0205] Typically, when a memory cell is in a relatively low data state and has a relatively low Vth, a relatively low programming pulse is sufficient to increase the Vth of the memory cell. Furthermore, when the data state or Vth of the WLn+1 memory cell exceeds the data state or Vth of the WLn memory cell by a relatively large amount, the programming pulse value can be relatively small.

[0206] This example includes twenty-two different programmed pulse values, for example, 14.75V-20V in 0.25V increments, which requires five binary latches to store data to identify each value. As mentioned, for example, combined with... Figure 11C During the reprogramming of a memory cell, data in the corresponding latch set can be read to determine whether programming of the memory cell is suppressed or enabled during the application of a given programming pulse to the word line. Also as mentioned above, it may be helpful to divide the reprogramming process into multiple reprogramming operations, where the latches of the NAND string are configured differently in each reprogramming operation to reduce the number of latches required to identify the magnitude of the programming pulse. Figure 12B1 and Figure 12B2 Provided for use Figure 12B Examples of the first and second reprogramming operations for the programming pulse magnitude values.

[0207] You can use VrA-VrF instead of VrG to perform read operations on WLn and WLn+1.

[0208] Figure 12B1 A third exemplary table depicting the values ​​of programmed pulses includes Figure 12B The first subset of the programming pulse values, in the range of 14.75V-18V, is used for... Figure 11C1 Step 1128 is the first reprogramming operation. The underlined voltage is used for the current reprogramming operation.

[0209] When the WLn memory cell is in state AC and the WLn+1 memory cell is in state Er, the programming pulse values ​​are 16V-18V. When the WLn memory cell is in state AC and the WLn+1 memory cell is in state A, the programming pulse values ​​are 15.75V-17.75V. When the WLn memory cell is in state AC and the WLn+1 memory cell is in state B, the programming pulse values ​​are 15.50V-17.50V. When the WLn memory cell is in state AC and the WLn+1 memory cell is in state C, the programming pulse values ​​are 15.25V-17.25V. When the WLn memory cell is in state AC and the WLn+1 memory cell is in state D, the programming pulse values ​​are 15V-18V. When the WLn memory cell is in state A- and the WLn+1 memory cell is in state E, the programming pulse values ​​are 14.75V-17.75V.

[0210] This example includes fourteen different programmed pulse values, which require four binary latches to store data to identify each value.

[0211] Figure 12B2 A fourth exemplary table depicting the values ​​of programmed pulse magnitudes includes Figure 12B The second subset of the programming pulse values, in the range of 18.25V-20V, is used for... Figure 11C1 The second reprogramming operation in step 1129. The underlined voltage is used for the current reprogramming operation.

[0212] When the WLn memory cell is in state D or E and the WLn+1 memory cell is in state Er, the programming pulse value is 19V or 20V, respectively. When the WLn memory cell is in state D or E and the WLn+1 memory cell is in state A, the programming pulse value is 18.75V or 19.75V, respectively. When the WLn memory cell is in state D or E and the WLn+1 memory cell is in state B, the programming pulse value is 18.50V or 19.50V, respectively. When the WLn memory cell is in state D or E and the WLn+1 memory cell is in state C, the programming pulse value is 18.25V or 19.25V, respectively. When the WLn memory cell is in state E and the WLn+1 memory cell is in state D, the programming pulse value is 19V. When both the WLn and WLn+1 memory cells are in state E, the programming pulse value is 18.75V.

[0213] This example includes eight different programming pulse values, which can be processed by four binary latches for the first reprogramming operation.

[0214] When performing multiple reprogramming operations, the number of read operations can be reduced in each reprogramming operation. For example, five read voltages VrA-VrE can be used in the first reprogramming operation (see...). Figure 8B The read operations using VrF and VrG can be omitted because there is no need to distinguish between E, F, and G states. Using VrE to distinguish between the D state and the higher EG state is sufficient.

[0215] Three read voltages VrD-VrF can be used in the second reprogramming operation (see...). Figure 8B The read operations using VrA-VrC can be omitted because it is not necessary to distinguish between Er-C states. Using VrD to distinguish between D state and lower Er-C states is sufficient. The read operations using VrG can be omitted because it is not necessary to distinguish between F and G states. Using VrF to distinguish between E state and higher F and G states is sufficient.

[0216] It should be noted that the programming pulse value can be divided in different ways in different reprogramming operations. In another example, Figure 12B1 The combination of WLn=D / WLn+1=D and WLn=D / WLn+1=E can be moved to Figure 12B2 The second reprogramming operation. This will result in ten different programming pulse values ​​in the second reprogramming operation, while maintaining fourteen programming pulse values ​​in the first reprogramming operation. Figure 12B1 In this modification, there will be one less read operation for WLn because VrE can be omitted. Using VrA-VrD instead of VrA-VrE for reading is sufficient.

[0217] Figure 12C Depicting and Figure 11A A fifth exemplary table of consistent programming pulse values ​​for reprogramming, wherein the programming pulse values ​​for the data states Er-B and CE of WLn+1 form the first and second groups, respectively. Read operations on WLn can be performed using VrA-VrF instead of VrG. Read operations on WLn+1 can be performed using VrC and VrF.

[0218] Here, grouping significantly reduces the number of read operations on WLn+1. Furthermore, only ten different programming pulse values ​​exist.

[0219] When the WLn memory cell is in state A and the WLn+1 memory cell is in state Er-B or CE, the programming pulse value is 15.75V or 15V, respectively. When the WLn memory cell is in state B and the WLn+1 memory cell is in state Er-B or CE, the programming pulse value is 16.75V or 16V, respectively. When the WLn memory cell is in state C and the WLn+1 memory cell is in state Er-B or CE, the programming pulse value is 17.75V or 17V, respectively. When the WLn memory cell is in state D and the WLn+1 memory cell is in state Er-B or CE, the programming pulse value is 18.75V or 18V, respectively. When the WLn memory cell is in state E and the WLn+1 memory cell is in state Er-B or CE, the programming pulse value is 19.75V or 19V, respectively.

[0220] Figure 12D Depicting and Figure 11A A sixth exemplary table of consistent programming pulse values ​​for reprogramming, wherein the programming pulse values ​​for data states A and B of WLn and data state Er-E of WLn+1 form a first group, and the programming pulse values ​​for data state CE of WLn and data state Er-E of WLn+1 form a second group. This example divides the data states of WLn into a first subset of data states A and B and a second subset of data state CE. Read operations can be performed on WLn using VrA, VrC, and VrF. A read operation can be performed on WLn+1 using VrF.

[0221] Here, grouping significantly reduces the number of read operations on WLn and WLn+1. Furthermore, only two different programming pulse values ​​exist, for example, 16.5V and 19V.

[0222] When the WLn memory cell is in state A or B and the WLn+1 memory cell is in state Er-E, the programming pulse value is 16.5V. When the WLn memory cell is in state CE and the WLn+1 memory cell is in state Er-E, the programming pulse value is 19V.

[0223] Figure 12E Depicting and Figure 11A A seventh exemplary table of consistent programming pulse values ​​for reprogramming, wherein the programming pulse values ​​for the data states Er and A, B and C, and D and E of WLn+1 form the first, second, and third groups, respectively. Read operations can be performed on WLn using VrA and VrF. Read operations can be performed on WLn+1 using VrB, VrD, and VrF.

[0224] Here, grouping significantly reduces the number of read operations on WLn+1 and the number of different programming pulse values. There are eleven different programming pulse values, for example, 14.87V-19.87V in 0.5V increments.

[0225] When the WLn memory cell is in state A and the WLn+1 memory cell is in state Er or A, state B or C, or state D or E, the programming pulse values ​​are 15.87, 15.37, or 14.87, respectively. When the WLn memory cell is in state B and the WLn+1 memory cell is in state Er or A, state B or C, or state D or E, the programming pulse values ​​are 16.87, 16.37, or 15.87, respectively. When the WLn memory cell is in state C and the WLn+1 memory cell is in state Er or A, state B or C, or state D or E, the programming pulse values ​​are 17.87, 17.37, or 16.87, respectively. When the WLn memory cell is in state D and the WLn+1 memory cell is in state Er or A, state B or C, or state D or E, the programming pulse values ​​are 18.87, 18.37, or 17.87, respectively. When the WLn memory cell is in state E and the WLn+1 memory cell is in state Er or A, state B or C, or state D or E, the programming pulse values ​​are 19.87, 19.37, or 18.87, respectively.

[0226] Figure 12F Depicting and Figure 11AAn eighth exemplary table of consistent programming pulse values ​​for reprogramming is provided, wherein the programming pulse values ​​for data states AC of WLn and Er-B of WLn+1, data states AC of WLn and CE of WLn+1, data states D and E of WLn and Er-B of WLn+1, and data states D and E of WLn and CE of WLn+1 form the first, second, third, and fourth groups, respectively. The programming pulse value groups are obtained by grouping the data states of WLn and WLn+1. Here, grouping significantly reduces the number of read operations on WLn and WLn+1 and the number of different programming pulse values. Four different programming pulse values ​​exist, for example, 16V, 16.75V, 18.5V, and 19.25V.

[0227] When the WLn memory cell is in AC state and the WLn+1 memory cell is in Er-B or CE state, the programming pulse value is 16.75V or 16V, respectively. When the WLn memory cell is in D or E state and the WLn+1 memory cell is in Er-B or CE state, the programming pulse value is 19.25V or 18.5V, respectively.

[0228] Through Figure 12B To obtain the values ​​in the table, interpolation is performed between them. Figures 12C to 12F Some programmed pulse values.

[0229] Figures 13A to 13F A series of programming pulses applied to the word line WLn to reprogram the memory cells connected to the word line is depicted. The vertical axis depicts the voltage, and the horizontal axis depicts the time or programming cycle (PL) number. During each programming pulse, some memory cells are disabled for programming, while others are enabled for programming, such as by setting their bit line voltages high or low, respectively. The decision to suppress or enable a memory cell during a given programming pulse can be based on data in its latch that identifies the magnitude of the programming pulse or the corresponding programming pulse number for which the memory cell should be enabled. As mentioned, for each memory cell in WLn, the decision can be based on a pair of data states, for example, the data state of the WLn memory cell and the data state of the adjacent WLn+1 memory cell. Figures 13A to 13F The data state pairs for which programming is enabled are depicted. In some cases, a series of data states are provided instead of a single data state. The remaining data state pairs, not shown, indicate that the WLn memory cell is disabled from programming during the programming pulse.

[0230] In different examples, the programming pulses are depicted as having a uniform duration. However, the duration of the programming pulses can vary with magnitude. Different programming-enable bit line voltages can also be used to potentially reduce the number of programming pulses. For example, in Figure 13B In this example, a relatively small 0.25V step size exists in the programming pulse. The data state combination for PP=1 can be combined with the data state combination for PP=2. For example, a 15V programming pulse for PP=2 can be applied to WLn, while a programming-enable voltage (such as 0V) is applied to the A / D data state combination and a higher programming-enable voltage (such as 0.25V) is applied to the A / E data state combination, which is lower than the programming-suppression voltage. Therefore, these two data state combinations can be programmed simultaneously. The control gate-drain voltage of the WLn memory cell with the A / E combination is the same as Vcg=15V and Vbl=0.25V, just as Vcg=14.75V and Vbl=0V. Following this example, the number of programming pulses can potentially be halved. For example, the data state combinations for PP = 1, 3, 5, 7, 9, 11, 13, 15, 17, 19 and 21 can be combined with the data state combinations for PP = 2, 4, 6, 8, 10, 12, 14, 16, 18, 20 and 22, respectively.

[0231] Figure 13A Depicting and Figure 12A A consistent graph of programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse. Five programming pulses (PP) 1300 (labeled 1-5) have magnitudes of 16-20V as indicated. Region 1301 of the graph shows which WLn memory cells are enabled for each programming pulse based on their respective data states and the data states of the adjacent WLn+1 memory cells. For example, the symbol A / Er-E under PP=1 represents a pair of data states, either state A on WLn or state Er-E on WLn+1. The symbols are in the format of "WLn data state / WLn+1 data state", for example, "data state of the first memory cell of WLn / data state of the adjacent second memory cell of WLn+1". The A / Er-E, B / Er-E, C / Er-E, D / Er-E, and E / Er-E data state pairs are enabled in programming pulses 1-5, respectively.

[0232] Figure 13B Depicting and Figure 12BA consistent graph of programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse. Twenty-two programming pulses 1310 (labeled 1-22) have magnitudes of 14.75-20V as indicated. Region 1311 of the graph indicates the enabled data state pairs as follows: A / E for PP=1, A / D for PP=2, A / C for PP=3, A / B for PP=4, A / A and B / E for PP=5, A / Er and B / D for PP=6, B / C for PP=7, B / B for PP=8, B / A and C / E for PP=9, B / Er and C / D for PP=10, and so on. C / C for 1, C / B for PP=12, C / A and D / E for PP=13, C / Er and D / D for PP=14, D / C for PP=15, D / B for PP=16, D / A and E / E for PP=17, D / Er and E / D for PP=18, E / C for PP=19, E / B for PP=20, E / A for PP=21, and E / Er for PP=22.

[0233] Figure 13B1 Depicting and Figure 12B1 A consistent graph of the programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse. The fourteen programming pulses 1320 (labeled 1-14) have magnitudes of 14.75-18V as indicated. Area 1321 of the graph indicates the enabled data status pairs for PP=1 (A / E), PP=2 (A / D), PP=3 (A / C), PP=4 (A / B), PP=5 (A / A and B / E), PP=6 (A / Er and B / D), PP=7 (B / C), PP=8 (B / B), PP=9 (B / A and C / E), PP=10 (B / Er and C / D), PP=11 (C / C), PP=12 (C / B), PP=13 (C / A and D / E), and PP=14 (C / Er and D / D).

[0234] Figure 13B2 Depicting and Figure 12B2A consistent graph of the programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse. The eight programming pulses 1330 (labeled 1-8) have magnitudes of 18.25V-20V as indicated. Region 1331 of the graph indicates the enabled data state pairs as follows: D / C for PP=1, D / B for PP=2, D / A and E / E for PP=3, D / Er and E / D for PP=4, E / C for PP=5, E / B for PP=6, E / A for PP=7, and E / Er for PP=8.

[0235] Figure 13C Depicting and Figure 12C A consistent graph of programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse. Ten programming pulses 1340 (labeled 1-10) have magnitude values ​​of 15-19.75 as indicated. Region 1341 of the graph indicates the enabled data state pairs as follows: A / CE for PP=1, A / Er-B for PP=2, B / CE for PP=3, B / Er-B for PP=4, C / CE for PP=5, C / Er-B for PP=6, D / CE for PP=7, D / Er-B for PP=8, E / CE for PP=9, and E / Er-B for PP=10.

[0236] Figure 13D Depicting and Figure 12D A graph showing the consistent programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse. The two programming pulses 1350 (labeled 1 and 2) have magnitudes of 16.5V and 19V, respectively, as indicated. Region 1351 of the graph indicates the enabled data state pairs as A / Er-E and B / Er-E for PP=1, and C / Er-E, D / Er-E, and E / Er-E for PP=2.

[0237] Figure 13E Depicting and Figure 12EA consistent graph of programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse. Eleven programming pulses 1360 (labeled 1-11) have magnitudes of 14.87-19.87V as indicated. Region 1361 of the graph indicates the enabled data state pairs as follows: A / DE for PP=1, A / BC for PP=2, A / Er-A and B / DE for PP=3, B / BC for PP=4, B / Er-A and C / DE for PP=5, C / BC for PP=6, C / Er-A and D / DE for PP=7, D / BC for PP=8, D / Er-A and E / DE for PP=9, E / BC for PP=10, and E / Er-A for PP=11.

[0238] Figure 13F Depicting and Figure 12F A consistent graph of the programming pulses used for reprogramming operations, and an indication of the combination of data states of the WLn memory cell and the adjacent WLn+1 memory cell enabled for each programming pulse. The four programming pulses 1370 (labeled 1-4) have magnitudes of 16V-19.25V as indicated. Region 1371 of the graph indicates the enabled data state pairs as follows: A / CE, B / CE, and C / CE for PP=1; A / Er-B, B / Er-B, and C / Er-B for PP=2; D / CE and E / CE for PP=3; and D / Er-B and E / Er-B for PP=4.

[0239] Figure 14 A graph is plotted comparing the failure bit count (FBC) time with and without reprogramming. As mentioned, the reprogramming technique presented in this paper can compress the Vth distribution and improve data retention. The improvement can be measured by the failure bit count (FBC) or the number of errors in a read operation. The number of errors should be below the ECC limit, as depicted by the dashed line. In this case, the memory cell is programmed at t=0, and a subsequent read operation is performed after some time has elapsed. Curve 1400 represents the case without reprogramming, in which the FBC increases relatively rapidly toward the ECC limit. Curve 1401 represents the case with reprogramming, in which the FBC increases relatively slowly toward the ECC limit.

[0240] Specifically, at t=0, when reprogramming is performed, the FBC is low because the Vth distribution is narrow. After t=0, the FBC increases over time due to data retention loss. When reprogramming is performed, the data retention loss is low because reprogramming increases Vth after the initial amount of data retention loss has occurred.

[0241] Therefore, in one specific embodiment, an apparatus includes: a set of memory cells arranged in a set of NAND strings; a set of word lines connected to the set of memory cells, the set of word lines including a first word line connected to a first memory cell in the set of memory cells and a second word line connected to a second memory cell in the set of memory cells, the first memory cell being adjacent to the second memory cell; and control circuitry connected to the set of memory cells. The control circuitry is configured to program the first memory cell, program the second memory cell after programming the first memory cell, read the first memory cell after programming the second memory cell to classify a threshold voltage of the first memory cell into a corresponding threshold voltage range, read the second memory cell after programming the second memory cell to classify a threshold voltage of the second memory cell into a corresponding threshold voltage range, and determine whether to reprogram the first memory cell based on the corresponding threshold voltage range of the first memory cell and the corresponding threshold voltage range of the second memory cell.

[0242] In another specific implementation, a method includes: programming a first set of memory cells connected to a first word line into a plurality of data states; programming a second set of memory cells connected to a second word line adjacent to the first word line into the plurality of data states; after the programming of the second set of memory cells, reading a corresponding data state of each memory cell in the first set of memory cells and a corresponding data state of each memory cell in the second set of memory cells, identifying a subset of the first set of memory cells to be reprogrammed based on the reading, and reprogramming the subset of the first set of memory cells, the reprogramming including applying a plurality of programming pulses to the first word line; and for each memory cell in the subset of the first set of memory cells, enabling reprogramming of the memory cell during a corresponding programming pulse of the plurality of programming pulses, and suppressing reprogramming of the memory cell during the remaining programming pulses of the plurality of programming pulses.

[0243] In another embodiment, an apparatus includes: a first set of memory cells connected to a first word line in a block; a second set of memory cells connected to a second word line in the block, wherein the first word line is adjacent to the second word line and the first set of memory cells; and control circuitry. The control circuitry is configured to: program the first set of memory cells into a set of data states; after programming the first set of memory cells, program the second set of memory cells into the set of data states; read the first set of memory cells and the second set of memory cells; and based on the read, identify a lower data state memory cell in the first set of memory cells adjacent to a lower data state memory cell in the second set of memory cells, and a higher data state memory cell in the first set of memory cells adjacent to a higher data state memory cell in the second set of memory cells; and reprogram the lower data state memory cell in the first set of memory cells adjacent to the lower data state memory cell in the second set of memory cells, while suppressing reprogramming of the higher data state memory cell in the first set of memory cells adjacent to the higher data state memory cell in the second set of memory cells.

[0244] The specific embodiments of the invention described above have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the foregoing teachings. The described embodiments were chosen to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and various modifications suitable for the intended particular use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A memory device, comprising: A control circuit is configured to be connected to: a set of memory cells arranged in a set of NAND strings and connected to a set of word lines, the set of word lines being connected to the set of memory cells, the set of word lines including a first word line connected to a first memory cell in the set of memory cells and a second word line connected to a second memory cell in the set of memory cells, the first memory cell being adjacent to the second memory cell; The control circuit is configured as follows: Program the first memory unit; The second memory unit is programmed after the first memory unit is programmed. After the programming of the second memory cell, the first memory cell is read to classify the threshold voltage of the first memory cell into the corresponding threshold voltage range; After the programming of the second memory cell, the second memory cell is read to classify the threshold voltage of the second memory cell into the corresponding threshold voltage range; and Whether to reprogram the first memory cell is determined based on whether the corresponding threshold voltage range of the first memory cell and the corresponding threshold voltage range of the second memory cell are lower than a specified voltage.

2. The memory device according to claim 1, wherein: The specified voltage is below the threshold voltage range of one or more of the highest data states among a plurality of data states.

3. The memory device according to claim 1 or 2, wherein: In order to perform the reprogramming, the control circuit is configured to set the programming pulse value of the first memory cell based on the corresponding threshold voltage range of the first memory cell and the corresponding threshold voltage range of the second memory cell.

4. The memory device according to claim 3, wherein: The control circuit is configured to set the programming pulse value to be relatively high when the corresponding threshold voltage range of the first memory cell is relatively high and the corresponding threshold voltage range of the second memory cell is relatively low.

5. The memory device according to claim 3, wherein: The control circuit is configured to set the programming pulse value to a relatively low value when the corresponding threshold voltage range of the first memory cell is relatively low and the corresponding threshold voltage range of the second memory cell is relatively high.

6. The memory device according to claim 1 or 2, wherein: The corresponding threshold voltage range of the second memory cell includes many of the multiple data states.

7. The memory device according to claim 1 or 2, wherein: The control circuit is configured to read the first memory cell, read the second memory cell, and determine whether to reprogram the first memory cell based on the fact that the control circuit enters an idle state after the programming of the second memory cell.

8. The memory device according to claim 1 or 2, wherein: The corresponding threshold voltage range of the first memory cell includes corresponding data states among multiple data states; and The control circuit is configured to determine whether to reprogram the first memory cell based on whether the corresponding data state is lower than one or more of the highest data states among the plurality of data states.

9. The memory device according to claim 8, wherein: The corresponding threshold voltage range of the second memory cell includes the corresponding data state among the plurality of data states; and The control circuit is configured to determine whether to reprogram the first memory cell based on whether the corresponding data state of the second memory cell is lower than one or more of the highest data states among the plurality of data states.

10. The memory device according to claim 1 or 2, wherein: The corresponding threshold voltage range of the first memory cell includes corresponding data states among multiple data states; and The control circuit is configured to determine whether to reprogram the first memory cell based on whether the corresponding data state is lower than 25% of the highest data state among the plurality of data states.

11. A method for operating a memory device, comprising: The first set of memory cells connected to the first word line is programmed into multiple data states; The second set of memory cells connected to the second word line is programmed into the plurality of data states, the second word line being adjacent to the first word line; After the programming of the second set of memory cells, the corresponding data state of each memory cell in the first set of memory cells and the corresponding data state of each memory cell in the second set of memory cells are read, a subset of the first set of memory cells to be reprogrammed is identified based on the read, and the subset of the first set of memory cells is reprogrammed, the reprogramming including applying a plurality of programming pulses to the first word line; as well as For each memory cell in the subset of the first group of memory cells, reprogramming of the memory cell is enabled during the corresponding programming pulse of the plurality of programming pulses, and reprogramming of the memory cell is suppressed during the remaining programming pulses of the plurality of programming pulses.

12. The method according to claim 11, wherein: The identification of the subset of the first group of memory cells to be reprogrammed includes identifying adjacent memory cell pairs, each pair including a memory cell from the first group of memory cells having a data state lower than one or more of the highest data states among the plurality of data states, and a memory cell from the second group of memory cells having a data state lower than one or more of the highest data states among the plurality of data states.

13. The method according to claim 11 or 12, wherein: For each memory cell in the subset of the first group of memory cells for which reprogramming is enabled, the corresponding programming pulse has a magnitude based on the corresponding data state of the memory cell and the corresponding data state of the adjacent memory cells in the second group of memory cells.

14. The method according to claim 11 or 12, wherein: After the programming of the second set of memory cells, the reading and reprogramming are performed in response to receiving a read command involving the first set of memory cells.

15. The method according to claim 11 or 12, wherein: The first group of memory cells and the second group of memory cells are in NAND strings, and each NAND string is connected to a corresponding latch group; and The reprogramming includes configuring the respective latch group, applying a first portion of the plurality of programming pulses to the first word line, then reconfiguring the respective latch group, and applying a second portion of the plurality of programming pulses to the first word line.

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