Magnetic tunnel junctions including spinel and methods of making the same

Abstract

This invention relates to a magnetoresistive memory device, comprising a first electrode, a second electrode spaced apart from the first electrode, and a vertical magnetic tunneling junction stack located between the first electrode and the second electrode. The vertical magnetic tunneling junction stack comprises: a first textured nonmagnetic layer containing a first nonmagnetic transition metal, a second textured nonmagnetic layer containing a second nonmagnetic transition metal, a magnesium oxide dielectric layer located between the first and second textured nonmagnetic layers, a reference layer located between the first and second textured nonmagnetic layers, a free layer located between the first and second textured nonmagnetic layers, and a spinel layer located between the reference layer and the free layer, and includes a polycrystalline spinel material having a (001) texture in an axial direction extending between the reference layer and the free layer.

Description

[0001] Related applications

[0002] This application claims priority to U.S. non-provisional application No. 16 / 944,758, filed July 31, 2020, and U.S. non-provisional application No. 16 / 944,826, filed July 31, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates in general to the field of magnetoresistive memory devices, and more specifically to magnetoresistive memory devices comprising a magnetic tunnel junction having a spinel dielectric tunnel barrier layer and a method for manufacturing the same. Background Technology

[0004] Magnetoresistive memory devices can store information using the resistance difference between a first configuration and a second configuration. In the first configuration, the magnetization direction of the ferromagnetic free layer is parallel to the magnetization of the ferromagnetic reference layer, and in the second configuration, the magnetization direction of the free layer is antiparallel to the magnetization of the reference layer. Programming a magnetoresistive memory device requires various external power sources to flip the magnetization direction of the free layer; these external power sources can be magnetic or employ spin-transfer mechanisms.

[0005] Spin torque-transfer magnetoresistive random access memory (STT-MRAM) devices require scalability exceeding the current required for operation. The scalability of STT-MRAM devices, based on interface perpendicular magnetic anisotropy (PMA), necessitates significantly enhanced PMA to achieve the thermal stability required for reliable information retention in MRAM devices. Simultaneously, low power consumption during write operations requires efficient magnetization manipulation. The need for both a high energy barrier for retention and a low energy barrier for efficient switching is a key challenge for systems with high PMA. Summary of the Invention

[0006] According to one aspect of this disclosure, a magnetoresistive memory device includes a first electrode, a second electrode spaced apart from the first electrode, and a vertical magnetic tunneling junction stack located between the first electrode and the second electrode. The vertical magnetic tunneling junction stack includes: a first textured nonmagnetic layer comprising a first nonmagnetic transition metal, a second textured nonmagnetic layer comprising a second nonmagnetic transition metal, a magnesium oxide-coated dielectric layer located between the first and second textured nonmagnetic layers, a reference layer located between the first and second textured nonmagnetic layers, a free layer located between the first and second textured nonmagnetic layers, and a spinel layer located between the reference layer and the free layer, and includes a polycrystalline spinel material having a (001) texture in an axial direction extending between the reference layer and the free layer.

[0007] According to another aspect of this disclosure, a method of forming a magnetoresistive memory device includes forming a first electrode over a substrate; depositing a magnetic tunnel junction stack over the first electrode, wherein the magnetic tunnel junction stack includes: a first texture-destructive nonmagnetic layer comprising a first nonmagnetic transition metal, a reference layer comprising a first amorphous ferromagnetic material, a spinel layer comprising an amorphous spinel material, a free layer comprising a second amorphous ferromagnetic material, a magnesium oxide-coated dielectric layer comprising grains having a (001) texture, and a second texture-destructive nonmagnetic layer comprising a second nonmagnetic transition metal; performing an annealing process to induce solid-phase epitaxial crystallization of the materials of the free layer, the spinel layer, and the reference layer using the magnesium oxide-coated dielectric layer as a crystallization template layer to convert the amorphous spinel material into a polycrystalline spinel material having a (001) texture along an axial direction perpendicular to the interface between the spinel layer and the free layer; and forming a second electrode over a portion of the magnetic tunnel junction stack before or after the annealing process.

[0008] According to another embodiment of this disclosure, a spin-orbit torque (SOT) magnetoresistive memory device includes an electrode, a nonmagnetic heavy metal SOT layer spaced apart from the electrode, and a vertical magnetic tunneling junction stack located between the electrode and the SOT layer. The vertical magnetic tunneling junction stack includes: a first textured nonmagnetic layer containing a first nonmagnetic transition metal, a second textured nonmagnetic layer containing a second nonmagnetic transition metal, a magnesium oxide dielectric layer located between the first and second textured nonmagnetic layers, a reference layer located between the first and second textured nonmagnetic layers, a free layer located between the first and second textured nonmagnetic layers, and a spinel layer located between the reference layer and the free layer, and includes a polycrystalline spinel material having a (001) texture in an axial direction extending between the reference layer and the free layer.

[0009] According to another embodiment of this disclosure, a method for forming a spin-orbit torque (SOT) magnetoresistive memory device includes forming a nonmagnetic heavy metal SOT layer over a substrate; depositing a magnetic tunnel junction stack over the SOT layer, wherein the magnetic tunnel junction stack includes: a first texture-destructive nonmagnetic layer comprising a first nonmagnetic transition metal, a reference layer comprising a first amorphous ferromagnetic material, a spinel layer comprising an amorphous spinel material, a free layer comprising a second amorphous ferromagnetic material, a magnesium oxide dielectric layer comprising grains having (001) texture, and a second texture-destructive nonmagnetic layer comprising a second nonmagnetic transition metal; performing an annealing process to induce solid-phase epitaxial crystallization of the materials of the free layer, the spinel layer, and the reference layer using the magnesium oxide dielectric layer as a crystallization template layer to convert the amorphous spinel material into a polycrystalline spinel material having (001) texture along an axial direction perpendicular to the interface between the spinel layer and the free layer; and forming an electrode over a portion of the magnetic tunnel junction stack before or after the annealing process. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a random access memory device including magnetoresistive memory cells in an array configuration according to an embodiment of the present disclosure.

[0011] Figure 2 This is a schematic vertical cross-sectional view of a first exemplary magnetoresistive memory cell according to a first embodiment of the present disclosure.

[0012] Figure 3 This is a schematic vertical cross-sectional view of a second exemplary magnetoresistive memory cell according to a second embodiment of the present disclosure.

[0013] Figure 4 and Figure 5 This is a schematic vertical cross-sectional view of a third exemplary magnetoresistive memory cell and a fourth exemplary magnetoresistive memory cell according to a third embodiment of the present disclosure. Detailed Implementation

[0014] As discussed above, embodiments of this disclosure relate to a magnetoresistive memory device comprising a spinel dielectric tunnel barrier layer in a magnetic tunnel junction and a method thereof.

[0015] The accompanying drawings are not to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that no repetition of an element exists. Numbers such as “first,” “second,” and “third” are used only to identify similar elements and may be used differently throughout the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0016] Like reference numerals refer to like or similar elements. Unless otherwise specified, elements having the same reference numeral are assumed to have the same composition and the same function. Unless otherwise indicated, "contact" between elements refers to direct contact between the elements providing a shared edge or surface. If two or more elements do not contact each other directly, the two elements are "separated" from each other. As used herein, a first element positioned "on" a second element may be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is an electrical conduction path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component.

[0017] As used herein, a "layer" refers to a portion of material including a region having a thickness. The layer may extend over the entirety of an underlying or overlying structure, or may have a scope less than the scope of the underlying or overlying structure. Additionally, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below it.

[0018] As used herein, "spinel" refers to a dielectric compound having the following chemical formula: M x Q y O z , where 0.95 < x < 1.05, 1.95 < y < 2.05 and 3.95 < z < 4.05, and M and Q are different metals. In one embodiment, x = 1, y = 2 and z = 4. Exemplary spinels include MgAl2O4, ZnAl2O4, SiMg2O4, SiZn2O4, MgGa2O4, doped derivatives thereof in which a certain fraction of at least one metal element is replaced by another metal element while retaining the crystal structure, and oxygen-deficient derivatives thereof.

[0019] In crystalline magnesium oxide (MgO) dielectric tunneling barriers comprising magnetic tunnel junctions (MTJs), a large tunneling magnetoresistance (TMR) ratio (defined as the ratio of the difference between higher and lower tunneling resistances to the lower tunneling resistance) originates from coherent tunneling. The TMR of MgO-based MTJs is high at lower operating voltages, potentially exceeding 200%. However, maintaining such a high TMR ratio (>200%) at higher voltages to achieve a better signal-to-noise ratio is challenging. In other words, the TMR ratio of MgO-based MTJs decreases significantly as the operating voltage increases. The sharp decrease in TMR of MgO-based MTJs with increasing voltage bias on the MTJ is thought to be primarily due to crystalline defects at the interface between the MgO barrier and the ferromagnetic free layer and ferromagnetic reference layer of the MTJ.

[0020] The inventors of this disclosure recognize that a relatively large lattice mismatch of about 3% to 5% at the interface between crystalline magnesium oxide and typical ferromagnetic materials (e.g., CoFeB or CoFe) results in lattice mismatch dislocations and leads to a decrease in TMR under higher voltage bias conditions. The inventors also recognize that spinel (such as MgAl2O4) has a smaller lattice mismatch (in the range of 0.2% to 0.5%) with typical body-centered cubic ferromagnetic materials (such as CoFeB or CoFe). Therefore, the use of spinel in magnetic tunnel junctions can provide the desired tunneling barrier characteristics. In an illustrative example, a lattice-matched epitaxial heterostructure comprising a magnetic tunnel junction using spinel as a tunneling dielectric layer can be constructed on a (001) magnesium oxide substrate, providing approximately 300% or greater tunneling magnetoresistance.

[0021] Tunneling magnetoresistance (TMR) of lattice-matched epitaxial heterostructures, including magnetic tunnel junctions employing spinel as the tunneling dielectric layer, offers superior performance at higher operating voltages. For example, the TMR ratio of lattice-matched epitaxial heterostructures is approximately half that of lattice-matched epitaxial heterostructures under near-zero bias conditions, and can be approximately 150% to approximately 300%. In contrast, conventional MgO-based magnetic tunnel junctions exhibit a TMR ratio of only approximately 125% or less at operating voltages in the 1V to 1.3V range. However, spinel materials provide high TMR when in a crystalline state (e.g., having a spinel lattice structure) with a preferred (001) crystal orientation (also referred to herein as "(001) textured spinel"), whereas amorphous spinel does not provide this enhanced TMR effect of (001) textured spinel. While deposited MgO is typically polycrystalline in nature with a preferred (001) crystal orientation, spinel is usually deposited in an amorphous state unless it is grown over an expensive crystalline (001) MgO substrate. Therefore, it is difficult to form polycrystalline (001) textured spinel over cheaper, commercially available silicon or silicon oxide (e.g., glass) substrates.

[0022] Embodiments of this disclosure provide a method for growing highly (001)-textured spinel materials on amorphous ferromagnetic materials, such as amorphous CoFeB, using a (001)-textured MgO layer as a crystallization template. This method can be used to form MTJs on substrates other than crystalline MgO substrates (i.e., other than (001) crystalline MgO wafers), such as over silicon or silicon oxide substrates. In magnetic memory applications (such as magnetoresistive random access memory devices based on magnetic tunnel junctions), MTJs exhibit large tunneling magnetoresistance under high voltage bias conditions. Without being bound by any particular theory, it is believed that the large TMR at the applied electric field is due to improved interfaces and reduced interface defects between the spinel dielectric tunnel barrier layer and the free and / or reference ferromagnetic layers contacting the spinel dielectric tunnel barrier layer. According to one aspect of this disclosure, a method for forming a polycrystalline spinel layer with a (001) texture between two ferromagnetic material layers provides a less expensive lattice-matched epitaxial heterostructure including a magnetic tunnel junction comprising a spinel tunneling dielectric layer.

[0023] As used herein, (001) texture in a material layer refers to a growth condition or crystal structure in which grains occupy more than 50% of the total volume of the material layer in a growth direction or axial direction perpendicular to the (001) plane. In other words, (001) texture in a material layer refers to a growth condition or crystal structure in which grains occupy more than 50% of the total volume of the material layer in a growth direction or axial direction perpendicular to the (001) plane. <001> The axial direction refers to the growth conditions or crystal structure in which grains occupy more than 50% (e.g., 80% to 99%) of the entire volume of the material layer. As used herein, the axial direction refers to the direction perpendicular to the plane of the interface between adjacent layers. Within the (001) textured material, there is a (001) plane along the growth plane (i.e., having a direction as the axial direction). <001> The volume fraction of grains in the direction can be in the range of 0.5 to 1, such as 0.8 to 0.99.

[0024] In existing magnetic tunnel junction devices employing MgAl2O4 as the tunneling dielectric, i.e., devices where the magnetization direction is parallel to the interface between the MgAl2O4 and the ferromagnetic material layer, a large tunneling magnetoresistance (approximately 300%) is observed in magnetic tunnel junctions having in-plane magnetic anisotropy. According to one aspect of this disclosure, a method for manufacturing a vertical magnetic tunnel junction device is provided, comprising a spinel tunneling dielectric layer and a ferromagnetic material layer having vertical magnetic anisotropy, i.e., in this magnetic tunnel junction device, these ferromagnetic material layers have magnetic moments aligned along an axial direction perpendicular to the interface between the spinel layer and the two ferromagnetic material layers. Furthermore, the orientation of the magnetic free layer can be controlled by the magnitude of the applied voltage and / or current bias.

[0025] Furthermore, to avoid being bound by a specific theory, the improved lattice matching between the spinel dielectric tunnel barrier layer and the thin ferromagnetic layer can induce a stronger interfacial PMA in such a thin ferromagnetic layer, which is beneficial for forming vertical MTJs with higher thermal stability. In addition, the use of a spinel layer can improve the durability of the MRAM. Various aspects of embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0026] See Figure 1 A schematic diagram of a magnetoresistive memory device 500 comprising a plurality of magnetoresistive memory cells 180 according to an embodiment of the present disclosure is shown. In one embodiment, the magnetoresistive memory device 500 may be configured as a magnetoresistive random access memory (MRAM) device comprising a two-dimensional array or a three-dimensional array of the magnetoresistive memory cells 180 according to an embodiment of the present disclosure. As used herein, a “random access memory device” means a memory device containing memory cells that allow random access, i.e., access to any selected memory cell upon a command to read the contents of a selected memory cell.

[0027] The magnetoresistive memory device 500 may include a memory array region 550 containing an array of corresponding magnetoresistive memory cells 180 located at the intersections of respective word lines 30 and bit lines 90. The magnetoresistive memory device 500 may also include a combination of a row decoder 560 connected to the word line 30, programming and sensing circuitry 570 (which may include programming transistors, sense amplifiers, and other bit line control circuitry) connected to the bit line 90, a column decoder 580 connected to the bit line 90 via the programming and sensing circuitry 570, and a data buffer 590 connected to the programming and sensing circuitry 570. Multiple instances of the magnetoresistive memory cells 180 are provided to form an array configuration of the magnetoresistive memory device 500. Thus, each magnetoresistive memory cell 180 may be a two-terminal device including a corresponding first electrode and a corresponding second electrode. It should be noted that the placement and interconnection of components are illustrative, and components may be arranged in different configurations. Additionally, the magnetoresistive memory cells 180 may be manufactured as discrete devices, i.e., single isolated devices.

[0028] refer to Figure 2 The illustration shows a first exemplary magnetoresistive memory cell 180 according to an embodiment of the present disclosure. The illustrated magnetoresistive memory cell 180 may be... Figure 1 The STT-MRAM type magnetoresistive memory cells 180 are shown in an array of magnetoresistive memory cells 180. Each magnetoresistive memory cell in the magnetoresistive memory cells 180 may be formed over a substrate 300, which may be a combination of: a substrate whose lattice is not matched to a spinel dielectric tunnel barrier layer (e.g., a silicon or silicon oxide substrate not explicitly shown), guiding and driving circuitry elements (such as field-effect transistors, diodes, bidirectional threshold switches, or other semiconductor devices) for operating the array of magnetoresistive memory cells 180 to be formed thereon, and a dielectric material layer (not explicitly shown) embedded in a metal interconnect structure (not explicitly shown) and covering these guiding devices. The metal interconnect structure may provide electrical connections between driving circuitry elements and may be configured to provide electrical connections to the array of magnetoresistive memory cells 180 via word lines 30 and bit lines 90, or, in the case of a discrete group of metal interconnect structures, the magnetoresistive memory cells 180 may be configured to be accessed by a discrete group of metal interconnect structures not shared with other magnetoresistive memory cells 180.

[0029] When using word lines 30 and bit lines 90, a lower-level dielectric layer 330 can be embedded in a lower-group access line, which, depending on the configuration, can be either a word line 30 or a bit line 90. Material layers can be deposited on top of the lower-level dielectric layer 330, and this material stack can be patterned to form a two-dimensional array of magnetoresistive memory cells 180. A memory-level dielectric layer 380 can be formed around the two-dimensional array of magnetoresistive memory cells 180, and this memory-level dielectric layer can be planarized to provide a horizontal top surface planar with respect to the top surface of the magnetoresistive memory cells 180. A higher-level dielectric layer 390 can be formed to embed higher-group access lines. In one embodiment, the lower-group access line can be a word line 30 and the higher-group access line can be a bit line 90. Alternatively, the lower-group access line can be a bit line 90 and the higher-group access line can be a word line 30. Generally, word line 30 may contact one of the first electrode 110 and the second electrode 184, and bit line 90 may contact the other of the first electrode 110 and the second electrode 184. In an alternative configuration where each magnetoresistive memory cell 180 is individually addressed by dedicated boot (i.e., selector) elements (e.g., access transistors, diodes, or bidirectional threshold switching devices, the number of which may be the same as the number of magnetoresistive memory cells 180), a pair of dedicated conductive paths not shared with other magnetoresistive memory cells 180 may contact the first electrode 110 and the second electrode 184. Although not shown in the figures, boot (i.e., selector) elements may be inserted between the magnetoresistive memory cell 180 and one of the access lines (which may be word line 30 or bit line 90). Generally, Figure 2 The magnetoresistive memory cell 180 shown can be incorporated into any circuit setup that enables the detection of tunneling magnetoresistive data.

[0030] In one embodiment, the lower-level dielectric layer 330 and the higher-level dielectric layer 390 comprise respective dielectric materials, such as undoped silicate glass, doped silicate glass, organosilicon glass, or silicon nitride. The thickness of each of the lower-level dielectric layer 330 and the higher-level dielectric layer 390 may range from 50 nm to 600 nm, such as 100 nm to 300 nm, but smaller and larger thicknesses are also possible. Each of the word line 30 and the bit line 90 may comprise a highly conductive metal, such as tantalum, tungsten, titanium, copper, molybdenum, ruthenium, stacks thereof, or alloys thereof. In one embodiment, each of the word line 30 and the bit line 90 may comprise a combination of a conductive metal barrier pad containing TiN, TaN, and / or WN and a conductive filler material located within the metal barrier pad. The conductive filler material may include copper, tungsten, molybdenum, tantalum, titanium, ruthenium, etc. The thickness of word line 30 and bit line 90 can be in the range of 50nm to 600nm, such as 100nm to 300nm, but smaller and larger thicknesses are also possible.

[0031] Material layers are deposited on top of the lower-level dielectric layer 330 to provide a two-dimensional array of magnetoresistive memory cells 180, which may include, from bottom to top: a first electrode layer 110 (which is subsequently patterned to form the first electrode 110), an optional synthetic antiferromagnetic (SAF) structure stack 120, a magnetic tunnel junction stack 140, and a second electrode layer (which is subsequently patterned to form the second electrode 184). The SAF structure stack 120 (if present) includes antiferromagnetic coupling layers that may contain at least one ferromagnetic material layer 112, at least one nonmagnetic spacer layer 114, and at least one second ferromagnetic layer 116.

[0032] A 140-layer magnetic tunnel junction stack may be located above a 120-layer SAF structure and includes, from bottom to top or from top to bottom, a first texture-destructive nonmagnetic layer 126, a reference layer 132, a spinel layer 150, a free layer 136, a magnesium oxide-coated dielectric layer 155, an optional ferromagnetic coating layer 166, a second texture-destructive nonmagnetic layer 176, and a metal coating layer 182. While embodiments of this disclosure are described with the following embodiment in which the 140-layer magnetic tunnel junction stack includes, from bottom to top, a first texture-destructive nonmagnetic layer 126, a reference layer 132, a spinel layer 150, a free layer 136, a magnesium oxide-coated dielectric layer 155, an optional ferromagnetic coating layer 166, a second texture-destructive nonmagnetic layer 176, and a metal coating layer 182, alternative embodiments in which the order of the layers in the 140-layer magnetic tunnel junction stack is reversed during the deposition process are explicitly contemplated herein. In this alternative embodiment, a 120-layer stack of SAF structure is formed on top of a 140-layer stack of magnetic tunnel junction.

[0033] The first electrode layer comprises a first nonmagnetic metallic electrode material, which can be used as a seed crystal material for a material layer subsequently deposited thereon. The first electrode layer comprises a nonmagnetic transition metal and may comprise one or more of Ta, Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, W, Re, Os, and Ir. In one embodiment, the first electrode layer may comprise tantalum. The first electrode layer can be used as a seed layer. The first electrode layer may be deposited, for example, by sputtering. The first electrode layer may have a thickness in the range of 2 nm to 10 nm. The first electrode layer may be deposited as a polycrystalline layer with a predominant (111) texture or as an amorphous layer. As used herein, crystal texture in a material layer refers to growth conditions or crystal structures with grains predominantly oriented perpendicular to the crystal planes (i.e., occupying more than 50% of the total volume of the material layer, such as 80% to 99%). For example, (111) texture in a material layer refers to a growth condition or crystal structure in which grains occupy more than 50% of the total volume of the material layer in a growth direction or axial direction perpendicular to the (111) plane. In other words, (111) texture in a material layer refers to a growth condition or crystal structure in which grains occupy more than 50% of the total volume of the material layer in a growth direction or axial direction perpendicular to the (111) plane. <111> The axial direction refers to the growth conditions or crystal structure in which the grains occupy more than 50% (e.g., 80% to 99%) of the entire volume of the material layer. As used herein, the axial direction refers to the direction perpendicular to the plane of the interface between adjacent layers. In one embodiment, the first electrode layer comprises a polycrystalline tantalum layer having a (111) texture. Within the first electrode layer are (111) planes along the growth plane (i.e., having a axial direction). <111> The volume fraction of the grains (in the direction of orientation) can be in the range of 0.5 to 1, such as 0.8 to 0.99. Optionally, an annealing process can be performed to induce crystallization of the first electrode layer. In one embodiment, the first electrode layer may comprise tantalum and / or may be substantially composed of tantalum.

[0034] At least one ferromagnetic material layer 112 comprises cobalt, a cobalt-iron alloy (CoFe), or a cobalt-iron-boron alloy (“CoFeB”). In one embodiment, the SAF spacer layer 114 comprises iridium, ruthenium, or chromium. In one embodiment, the SAF structure 120 may comprise a Co / Pt superlattice.

[0035] Each of the first texture-destructive nonmagnetic layer 126, reference layer 132, spinel layer 150, free layer 136, optional overlay ferromagnetic layer 166, and second texture-destructive nonmagnetic layer 176 can be deposited as a corresponding amorphous material layer by sputtering or other suitable deposition processes at room temperature (298K) or between room temperature and 100°C.

[0036] The first texture-breaking non-magnetic layer 126 may include a first non-magnetic transition metal, which may be tungsten, ruthenium, tantalum, niobium, molybdenum, rhenium, platinum, palladium, iridium, or an alloy thereof that can provide high spin-orbit coupling. The first texture-breaking non-magnetic layer 126 may include a non-magnetic transition metal having a melting point of at least 1,500 °C, such that bulk diffusion within the first texture-breaking non-magnetic layer 126 is not sufficient to cause further crystallization therein or is not sufficient to serve as a template for solid-phase epitaxy in a subsequent annealing process. The first texture-breaking non-magnetic layer 126 may be deposited as an amorphous material by physical vapor deposition performed at room temperature. The first texture-breaking non-magnetic layer 126 may have a thickness in the range of 0.2 nm to 1 nm.

[0037] The reference layer 132 may be formed by depositing a first amorphous ferromagnetic material. For example, the reference layer 132 may include an amorphous CoFe layer, an amorphous CoFeB layer, or an amorphous stack of a Co / Ni multilayer or a Co / Fe multilayer. The reference layer 132 may be deposited as an amorphous material by physical vapor deposition performed at room temperature. The thickness of the reference layer 132 may be in the range of 0.8 nm to 1.2 nm, although smaller and larger thicknesses may also be employed.

[0038] The spinel layer 150 may be formed by depositing an amorphous spinel material, which may comprise and / or may consist essentially of: MgAl2O4, ZnAl2O4, SiMg2O4, SiZn2O4, MgGa2O4, doped derivatives thereof in which a certain fraction of at least one metal element is replaced by another metal element while retaining the crystal structure, and oxygen-deficient derivatives thereof. Preferably, Mg x Al y O z , where 0.95 < x < 1.05, 1.95 < y < 2.05, and 3.95 < z < 4.05, such as using MgAl2O4. In the process immediately following deposition, the spinel layer 150 contains the spinel material in an amorphous form. In one embodiment, the amorphous spinel material of the spinel layer 150 may be directly deposited on the amorphous metal material of the reference layer 132. The spinel layer 150 may be formed by physical vapor deposition or vacuum evaporation of a source material containing the constituent atoms of the spinel material. The thickness of the spinel layer 150 of the STT MRAM memory cell 180 may be in the range of 0.8 nm to 1.2 nm, although smaller and larger thicknesses may also be employed.

[0039] The free layer 136 can be formed by depositing a second amorphous ferromagnetic material. For example, the free layer 136 may comprise an amorphous CoFe layer, a CoFeB layer, or an amorphous stack of Co / Ni multilayers or Co / Fe multilayers. The free layer 136 can be deposited as an amorphous material by physical vapor deposition performed at room temperature. The thickness of the free layer 136 can range from 0.5 nm to 2.0 nm, but smaller and larger thicknesses are also possible.

[0040] The magnesium oxide covering dielectric layer 155 can be deposited by sputtering or by vacuum evaporation. The magnesium oxide covering dielectric layer 155 is formed using a (001) texture. In other words, with... <001> The growth direction and (001) growth plane form the main part of the magnesium oxide covering dielectric layer. The tendency to provide (001) texture in the deposited magnesium oxide covering dielectric layer is an inherent crystallization characteristic of magnesium oxide. The deposition temperature of the magnesium oxide covering dielectric layer 155 can be room temperature. The thickness of the magnesium oxide covering dielectric layer 155 can be in the range of 0.5 nm to 2 nm, such as 0.5 nm to 0.8 nm, but smaller and larger thicknesses are also possible.

[0041] The optional overlay ferromagnetic layer 166 can be formed by depositing additional amorphous ferromagnetic material. For example, the overlay ferromagnetic layer 166 may comprise an amorphous stack of amorphous CoFe layers, CoFeB layers, Co / Ni multilayers, or Co / Fe multilayers. The overlay ferromagnetic layer 166 can be deposited as an amorphous material by physical vapor deposition performed at room temperature. The thickness of the overlay ferromagnetic layer 166 can range from 0.2 nm to 0.8 nm, but smaller and larger thicknesses are also possible.

[0042] The second texture-destructive nonmagnetic layer 176 may comprise a second nonmagnetic transition metal, which may be tungsten, ruthenium, tantalum, niobium, molybdenum, rhenium, platinum, palladium, iridium, or alloys thereof. The second texture-destructive nonmagnetic layer 176 comprises a nonmagnetic transition metal having a melting point of at least 1,500°C, such that bulk diffusion within the second texture-destructive nonmagnetic layer 176 is insufficient to cause further crystallization therein or to serve as a template for solid-state epitaxy in subsequent annealing processes. The first nonmagnetic transition metal of the first texture-destructive nonmagnetic layer 126 and the second nonmagnetic transition metal of the second texture-destructive nonmagnetic layer 176 may be selected independently. In one embodiment, the first and second nonmagnetic transition metals may be tungsten. The second texture-destructive nonmagnetic layer 176 may be deposited as an amorphous material by physical vapor deposition performed at room temperature. The thickness of the second texture-destructive nonmagnetic layer 176 may be in the range of 0.2 nm to 1.0 nm.

[0043] The optional cover metal layer 182 comprises a non-magnetic transition metal and may include one or more of Ta, Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, W, Re, Os, and Ir. The cover metal layer 182 can be deposited by sputtering. The thickness of the cover metal layer 182 can range from 2 nm to 10 nm, such as 5 nm to 8 nm, but smaller and larger thicknesses are also possible.

[0044] The second electrode 184 layer comprises a non-magnetic transition metal and may include one or more of Ta, Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, W, Re, Os, and Ir. The second electrode layer can be deposited by sputtering. The thickness of the second electrode layer can range from 2 nm to 10 nm, such as 5 nm to 8 nm, but smaller and larger thicknesses are also possible. In one embodiment, the overlay metal layer 182 may comprise tantalum, and the second electrode 184 layer may comprise ruthenium.

[0045] Optionally, the post-deposition annealing process can be performed in the presence of a magnetic field at an elevated temperature ranging from 250°C to 500°C. Generally, the elevated temperature of the annealing process is selected such that the solid-state epitaxy of the materials of the free layer 136, the spinel layer 150, and the reference layer 132 is caused by the elevated temperature of the annealing process.

[0046] The (001) textured grains in the magnesium oxide-covered dielectric layer 155 can be further grown and fused during the thermal annealing process while maintaining the (001) texture. The entire magnesium oxide-covered dielectric layer 155 comprises large (001) textured grains occupying a predominant volume (e.g., more than 80%, and / or more than 90%, and / or more than 95%, and / or more than 98%, and / or more than 99%). The (001) textured crystal structure of the magnesium oxide-covered dielectric layer 155 serves as a crystallization template for the amorphous material of the free layer 136, spinel layer 150, and reference layer 132, and optionally for the amorphous material of the covering ferromagnetic layer 166, during a solid-state epitaxial process occurring during the thermal annealing process. In other words, in one embodiment, the thermal annealing process comprises a solid-state epitaxial process. Following the solid-phase epitaxial process, the spinel layer 150 comprises a polycrystalline spinel material having a (001) texture along an axial direction perpendicular to the interface between the spinel layer 150 and the free layer 136.

[0047] The grains in each layer between the first texture-destructive nonmagnetic layer 126 and the second texture-destructive nonmagnetic layer 176 are oriented along the (001) direction after a solid-state epitaxial process. The spinel layer 150 is transformed into a highly (001) textured spinel layer. The average grain size in the spinel layer 150 (i.e., the diameter of a sphere having the same volume as the average volume of the grains) can be approximately the thickness of the spinel layer 150 or greater. For example, the average grain size in the spinel layer 150 can be in the range of 1 nm to 4 nm, but smaller and larger grain sizes are also possible.

[0048] The grains of magnetic material in the free layer 136, reference layer 132, and optional overlay ferromagnetic layer 166 grow along a (001) texture during a solid-state epitaxial process. Additionally, due to an external magnetic field, the free layer 136, reference layer 132, and optional overlay ferromagnetic layer 166 are magnetized vertically during a thermal annealing process. The spinel layer 150 serves as the dielectric tunnel barrier layer of the magnetic tunnel junction, and the magnesium oxide overlay dielectric layer 155 serves as the overlay dielectric layer of the magnetic tunnel junction.

[0049] Generally, a solid-state epitaxial process accompanied by annealing transforms each of the reference layer 132, free layer 136, and overlay ferromagnetic layer 166 into a corresponding polycrystalline ferromagnetic material layer with a (001) texture. The grains in the free layer 136 are epitaxially aligned with the grains within the magnesium oxide overlay dielectric layer 155 during the solid-state epitaxial process. As used herein, if there is epitaxial alignment, i.e., atomic registration, between the atoms of the material layers (which span the interface between two material layers), then two contact grains of different material layers are epitaxially aligned with each other. The grains in the spinel layer 150 are epitaxially aligned with the grains in the free layer 136 during the solid-state epitaxial process. The grains in the reference layer 132 are epitaxially aligned with the grains in the spinel layer 150 during the solid-state epitaxial process. The amorphous ferromagnetic material in the overlay ferromagnetic layer 166 is transformed into a polycrystalline ferromagnetic material with a (001) texture through a solid-state epitaxial process. The grains covering the ferromagnetic layer 166 can be epitaxially aligned with the grains within the magnesium oxide covering dielectric layer 155 during the solid-state epitaxial process.

[0050] A stack of layers including a reference layer 132, a spinel layer 150, a free layer 136, and an optional overlay ferromagnetic layer 166 forms a lattice-matched epitaxial heterostructure (132, 150, 136, 166), wherein the different material layers are epitaxially oriented at the boundaries of the material layers. The epitaxial orientation across the different material layers can be grain-to-grain epitaxial orientation, and grain boundaries can propagate through the different material layers within the lattice-matched epitaxial heterostructure (132, 150, 136, 166).

[0051] In one embodiment, each of the first texture-destructive nonmagnetic layer 126 and the second texture-destructive nonmagnetic layer 176 prevents the propagation of crystal alignment of the material across it during a solid-state epitaxy process. In the absence of the first texture-destructive nonmagnetic layer 126, the grain structure within the SAF structure 120 would propagate to the reference layer 132 and the spinel layer 150. According to one aspect of this disclosure, the presence of the first texture-destructive nonmagnetic layer 126 prevents such propagation of the crystal structure from the sides of the SAF structure 120 through the first texture-destructive nonmagnetic layer 126 and allows solid-state epitaxy in which the textured crystal structure in the magnesium oxide-covered dielectric layer 155 serves as a template throughout the free layer 136, the spinel layer 150, and the reference layer 136. According to another aspect of this disclosure, the presence of the second textured nonmagnetic layer 176 prevents such propagation of crystal structures from the sides of the overlay metal layer 182 through the second textured nonmagnetic layer 176, and allows solid-phase epitaxy, wherein the textured crystal structure in the magnesium oxide overlay dielectric layer 155 serves as a template for the entire optional overlay ferromagnetic layer 166. The optional overlay ferromagnetic layer 166 has the function of immediately providing amorphous material on the magnesium oxide overlay dielectric layer 155, which allows grains within the magnesium oxide overlay dielectric layer 155 to grow to a larger size during the annealing process.

[0052] In one embodiment, the first nonmagnetic transition metal of the first texture-destroying nonmagnetic layer 126 can be deposited as amorphous and remain amorphous during the solid-state epitaxial process, and / or the second nonmagnetic transition metal of the second texture-destroying nonmagnetic layer 176 can be deposited as amorphous and remain amorphous during the solid-state epitaxial process. Alternatively, the first nonmagnetic transition metal of the first texture-destroying nonmagnetic layer 126 can be deposited during the solid-state epitaxial process to have (111) texture and maintain the (111) texture, and / or the second nonmagnetic transition metal of the second texture-destroying nonmagnetic layer 176 can be deposited during the solid-state epitaxial process to have (111) texture and maintain the (111) texture. The high melting temperatures of the first and second nonmagnetic transition metals provide a low bulk diffusion coefficient for the materials of the first and second texture-destroying nonmagnetic layers 126 and 176, therefore, the first and second texture-destroying nonmagnetic layers 126 are not used as templates for solid-state epitaxy. In other words, the lack of bulk diffusion suppresses amorphous changes or further crystallization in the first texture-destroying nonmagnetic layer 126 and the second texture-destroying nonmagnetic layer 176 during the annealing process. In one embodiment, the first and second nonmagnetic transition metals may be independently selected from tungsten, ruthenium, tantalum, niobium, molybdenum, rhenium, platinum, palladium, and iridium, and the thickness of each of the first and second texture-destroying nonmagnetic layers 126 may be in the range of 0.2 nm to 1.0 nm.

[0053] The material stack including a first electrode layer 110, stacks 112, 114, 116, 126, 132, 150, 136, 155, 166, 176, 182, and a second electrode layer 184 can be patterned to form at least one magnetoresistive memory cell 180. For example, a photoresist layer (not shown) can be applied over the second electrode layer 184, and the photoresist layer can be photolithographically patterned to form a two-dimensional array of discrete photoresist material portions with two-dimensional periodicity. An anisotropic etching process can be performed to etch the unmasked portions of the first electrode layer 110, stacks 112, 114, 116, 126, 132, 150, 136, 155, 166, 176, 182, and the second electrode layer 184. The first electrode layer 110, the stacked layers 112, 114, 116, 126, 132, 150, 136, 155, 166, 176, 182, and each retained portion of the second electrode layer constitute a magnetoresistive memory cell 180. A two-dimensional array of magnetoresistive memory cells 180 can be formed. The photoresist layer can be removed, for example, by ashing.

[0054] Each magnetoresistive memory cell 180 includes a first electrode 110, which is a patterned portion of a first electrode layer. Each magnetoresistive memory cell 180 includes a second electrode 184, which is a patterned portion of a second electrode layer. Each adjacent combination of layers 112, 114, and 116 within the magnetoresistive memory cell 180 constitutes a synthetic antiferromagnetic (SAF) structure 120. Each adjacent combination of the reference layer 132, the spinel layer 150, and the free layer 136 constitutes a ferromagnetic tunnel junction structure 140.

[0055] Subsequently, a higher-level dielectric layer 390 embedded with higher-group access lines can be formed. In one embodiment, the lower-group access lines may be word lines 30 and the higher-group access lines may be bit lines 90. Each second electrode 184 may be connected by one of the higher-group access lines (such as bit line 90).

[0056] Figure 2The first exemplary magnetoresistive memory cell 180 includes a spin torque transfer (STT) magnetoresistive memory (e.g., STT-MRAM) device. During operation of the STT-MRAM device, tunneling current flows through a spinel dielectric tunnel barrier layer 150 between a reference layer 132 and a free layer 136 to program the magnetization direction of the free layer 136 to a state parallel to the magnetization direction of the reference layer 132 (i.e., a low-resistance cell state) or an antiparallel state (e.g., a high-resistance cell state) by applying a voltage between the word line and the bit line. In one embodiment, layer 150 may be thicker than layer 155. The magnitude of the voltage drop across the spinel dielectric tunnel barrier layer 150 may be greater than the magnitude of the voltage drop across the magnesium oxide-covered dielectric layer 155. The spinel dielectric tunnel barrier layer 150 provides at least 250% TMR at higher biases, such as 250% to 300% TMR, which results in a better signal-to-noise ratio and better durability due to fewer interface defects than the MgO dielectric tunnel barrier layer.

[0057] Figure 3 This is a schematic vertical cross-sectional view of a second exemplary magnetoresistive memory cell 180A according to a second embodiment, wherein the second exemplary magnetoresistive memory cell 180A is used as a voltage-controlled magnetic anisotropy (VCMA) cell. By increasing the thickness of the spinel dielectric tunnel barrier layer 150 to more than 1.2 nm, it is possible to... Figure 2 The first exemplary memory cell 180 derives from the second exemplary magnetoresistive memory cell 180A. For example, the thickness of the spinel dielectric tunnel barrier layer 150 may be 1.5 nm to 3 nm. In this second embodiment, the higher thickness of the spinel dielectric tunnel barrier layer 150 prevents tunneling current from flowing through the spinel dielectric tunnel barrier layer 150 during programming of the cell 180A. Therefore, the applied voltage is used to switch the magnetization direction of the free layer 136. The applied voltage lowers the energy barrier height of the spinel dielectric tunnel barrier layer 150 in one bias direction and raises the energy barrier height in another bias direction. Improved quality and reduced defect density at the lattice-matched interface between the ferromagnetic layers (132, 136) and the crystalline spinel dielectric tunnel barrier layer 150 can cause a strong PMA. Without being bound by any particular theory, it is believed that this strong PMA can lead to a need for higher switching energy to switch (i.e., flip) the magnetization direction of the free layer 136, which provides improved device thermal stability.

[0058] Optionally, an ultrathin conductive insert layer 250 may be formed between the spinel dielectric tunnel barrier layer 150 and the free layer 136 to further enhance the VCMA effect in this second embodiment. The insert layer 250 may comprise a nonmagnetic metal (such as hafnium or palladium) or an antiferromagnetic layer (such as iridium). The thickness of the insert layer 250 may be between 0.02 nm and 0.1 nm. Therefore, the insert layer 250 may be a discontinuous layer (e.g., a metal dust removal layer).

[0059] Figure 4 This is a schematic vertical cross-sectional view of a third exemplary magnetoresistive memory cell 280 according to a third embodiment, wherein the third exemplary magnetoresistive memory cell 280 is used as a spin-orbit torque (SOT) cell (i.e., SOT MRAM cell). Figure 4 The SOT MRAM cell 280 shown is a three-terminal device. Therefore, the SOT magnetoresistive memory device containing the SOT MRAM cell 280 is different from... Figure 1 The STT or VCMA magnetoresistive memory device 500 shown is different because the SOT magnetoresistive memory device includes three access lines, instead of... Figure 1 The two access lines shown are word line 30 and bit line 90. Therefore, Figure 4 The illustrated SOT MRAM cell 280 includes a top access line 90 (e.g., a bit line) electrically connected to a first electrical terminal 401 of the SOT magnetoresistive memory device, and a non-magnetic heavy metal SOT layer 410 having strong spin-orbit coupling and contact with the free layer 136. The SOT layer 410 is electrically connected to a second electrical terminal 402 and a third electrical terminal 403 of the SOT magnetoresistive memory device.

[0060] When the electrical write current (Iwr) passes laterally through the SOT layer 410 between the second electrical terminal 402 and the third electrical terminal 403, a spin current is generated in a direction perpendicular to this current via the spin Hall effect (SHE). This spin current exerts a torque on the magnetization of the free layer 136. Therefore, the SOT layer 410 assists in the transition of the magnetization direction in the free layer 136 through the spin Hall effect. Thus, the SOT layer 410 is also referred to as a metal auxiliary layer, i.e., a metal layer that assists in the magnetic transition in the free layer 136.

[0061] Since write operations in an SOT device occur via the STO layer 410, very little current flows through the magnetic tunnel junction 140, which includes the free layer 136. The read current Ird flows vertically through the magnetic tunnel junction 140 between the first terminal 401 and the second terminal 402.

[0062] The STO layer 410 can be made of a conductive material with a high spin-orbit coupling strength, such as Pt, Ta, W, Hf, Ir, CuBi, CuIr, AuPt, AuW, PtPd, or PtMgO. The STO layer 410 can have a thickness of 5 nm to 10 nm, but smaller and larger thicknesses are also possible.

[0063] In this implementation scheme, the following can be omitted. Figure 2 and Figure 3 The first electrode layer 110 is shown, and the position of the magnetic tunnel junction 140 relative to the SAF structure 120 is reversed, such that the SAF structure 120 is formed above the magnetic tunnel junction 140 and below the second electrode 184.

[0064] Specifically, the SOT layer 410 serves as the first electrode of unit 280. A first texture-destructive nonmagnetic layer 126 may be positioned on the SOT layer 410. An optional in-plane magnetized ferromagnetic layer 266 may be formed on the first texture-destructive nonmagnetic layer 126. The optional in-plane magnetized ferromagnetic layer 266 may comprise a CoFe layer or a CoFeB layer having a thickness of at least 2 nm (such as 2 nm to 3 nm). At such thicknesses, the CoFe layer or CoFeB layer typically has an in-plane magnetization direction perpendicular to the magnetization direction of the free layer 136. The in-plane CoFeB layer or CoFe layer 266 serves as a built-in magnetic field source for achieving field-free deterministic SOT switching. A magnesium oxide dielectric layer 155 may be formed on the optional in-plane magnetized ferromagnetic layer 266. In this embodiment, the magnesium oxide dielectric layer 155 may have a thickness of 0.5 nm to 1 nm. A thin magnesium oxide dielectric layer 155 allows sufficient spin-polarized electrons generated by the SOT layer 410 to pass through it for switching the magnetization direction of the free layer 136. In an alternative embodiment, the magnesium oxide dielectric layer 155 may be formed on the first texture-disrupted nonmagnetic layer 126, and an in-plane magnetized ferromagnetic layer 266 may be formed on the magnesium oxide dielectric layer 155. A nonmagnetic metal layer 412 may be formed on the magnesium oxide dielectric layer 155. The nonmagnetic metal layer 412 may be a platinum or tantalum layer and may have a thickness of 1 nm to 2 nm. Layers 126, 266, 155, and 412 may extend beyond the lateral boundaries of cell 280.

[0065] A free layer 136 may be formed on the non-magnetic metal layer 412. In this embodiment, the free layer 136 may have a thickness of 0.2 nm to 0.8 nm. A spinel dielectric tunnel barrier layer 150 may be formed on the free layer 136. In this embodiment, the spinel dielectric tunnel barrier layer 150 may have a thickness of 0.5 nm to 2 nm. A reference layer 132 may be formed on the spinel dielectric tunnel barrier layer 150. In this embodiment, the reference layer 132 may have a thickness of 0.5 nm to 2 nm. A second textured non-magnetic layer 176 may be formed on the reference layer 132, a SAF structure 120 may be formed on the second textured non-magnetic layer 176, and a second electrode 184 may be formed on the SAF structure 120.

[0066] Figure 5 This is a schematic vertical cross-sectional view of a fourth exemplary magnetoresistive memory cell 280A, an alternative aspect to the third embodiment. The fourth exemplary magnetoresistive memory cell 280A can be derived by omitting the optional in-plane magnetized ferromagnetic layer 266 and nonmagnetic metal layer 412, and by forming a magnesium oxide dielectric layer 155 over the spinel dielectric tunnel barrier layer 150. Figure 4 A third exemplary memory cell 280 is derived. In this cell 280A, a free layer 126 may be positioned on a first texture-destructive nonmagnetic layer 126.

[0067] In the third embodiment, the improved quality and reduced defect density of the lattice-matched interface between the ferromagnetic layers (132, 136) and the crystalline spinel dielectric tunnel barrier layer 150 can induce a strong PMA. Without being bound by any particular theory, it is believed that this strong PMA can lead to a need for higher switching energies to switch (i.e., flip) the magnetization direction of the free layer 136, which provides improved thermal stability for the SOT MRAM cell 280 or 280A.

[0068] Referring to all the accompanying drawings and according to all embodiments of this disclosure, the magnetic tunnel junction of the embodiments of this disclosure can provide a large tunneling magnetoresistance ratio of about 300% or higher at high bias voltages in the range of 0.5V to 1.0V, and is believed to provide enhanced durability compared to prior art magnetic tunnel junction devices employing magnesium oxide dielectric tunneling barrier layers due to improved interface quality and fewer defects. The (001) texture in the magnesium oxide overlay dielectric layer 155 induces (001) texture in each of the spinel dielectric barrier layer 150, the free layer 136, the reference layer 132, and the optional overlay ferromagnetic layer 166.

[0069] According to various embodiments of this disclosure, a magnetoresistive memory device (180, 180A, 280, 280A) includes a first electrode (110 or 410), a second electrode 284 spaced apart from the first electrode, and a vertical magnetic tunneling junction stack located between the first electrode and the second electrode. The vertical magnetic tunneling junction stack includes: a first textured nonmagnetic layer 126 containing a first nonmagnetic transition metal, a second textured nonmagnetic layer 176 containing a second nonmagnetic transition metal, a magnesium oxide-coated dielectric layer 155 located between the first and second textured nonmagnetic layers, a reference layer 132 located between the first and second textured nonmagnetic layers, a free layer 136 located between the first and second textured nonmagnetic layers, and a spinel layer 150 located between the reference layer and the free layer, and includes a polycrystalline spinel material having a (001) texture in an axial direction extending between the reference layer and the free layer.

[0070] In one embodiment, at least 80% of the total volume of the spinel layer 150 is occupied by spinel grains having a (001) texture. In other words, more than 80% (which may be greater than 90%, and / or greater than 95%, and / or greater than 98%) of the total volume of the spinel layer 150 is occupied by spinel grains having a (001) plane perpendicular to the axial direction. In one embodiment, the reference layer 132 and the free layer 136 have a (001) texture. In other words, more than 50% (which may be greater than 80%, and / or greater than 90%, and / or greater than 95%, and / or greater than 98%) of the total volume of the reference layer 132 is occupied by grains of a ferromagnetic material layer having a (001) plane perpendicular to the axial direction, and more than 50% (which may be greater than 80%, and / or greater than 90%, and / or greater than 95%, and / or greater than 98%) of the total volume of the free layer 136 is occupied by grains of a ferromagnetic material layer having a (001) plane perpendicular to the axial direction.

[0071] In one embodiment, the grains of free layer 136 are epitaxially aligned with the grains of spinel layer 150 across the interface between free layer 136 and spinel layer 150. In one embodiment, magnesium oxide-coated dielectric layer 155 comprises grains having a (001) texture, and the grains of free layer 136 are epitaxially aligned with the grains of magnesium oxide-coated dielectric layer 155 across the interface between magnesium oxide-coated dielectric layer 155 and free layer 136. In one embodiment, the grains of reference layer 132 are aligned with the grains of spinel layer 150 across the interface between reference layer 132 and spinel layer 150.

[0072] In one embodiment, a magnetoresistive memory device may include a capping ferromagnetic layer 166 that includes a polycrystalline ferromagnetic material having a (001) texture. A magnesium oxide capping dielectric layer 155 is located between the free layer 136 and the capping ferromagnetic layer 166 and includes grains having a (001) texture; and the grains of the capping ferromagnetic layer 166 are epitaxially aligned with the grains of the magnesium oxide capping dielectric layer 155 across the interface between the magnesium oxide capping dielectric layer 155 and the capping ferromagnetic layer 166.

[0073] In one embodiment, the spinel layer 150 has the chemical formula M x Q y O z , where 0.95 < x < 1.05, 1.95 < y < 2.05 and 3.95 < z < 4.05, and M and Q are different metals such as Mg x Al y O z , where 0.95 < x < 1.05, 1.95 < y < 2.05 and 3.95 < z < 4.05. In one embodiment, the spinel layer 150 includes a material selected from: MgAl2O4, ZnAl2O4, SiMg2O4, SiZn2O4, MgGa2O4, doped derivatives thereof in which a certain fraction of at least one metal element is replaced with another metal element while retaining the crystal structure, and oxygen-deficient derivatives thereof.

[0074] In one embodiment, the magnetoresistive memory device includes a synthetic antiferromagnetic (SAF) structure 120 located between one of the electrodes (184, 110 or 410) and the reference layer 132.

[0075] In one embodiment, each of the free layer 136 and the reference layer 132 has a respective easy magnetization axis parallel to the axial direction. Thus, the perpendicular magnetic tunnel junction structure may have perpendicular magnetic anisotropy.

[0076] In one embodiment, each of the free layer 136 and the reference layer 132 includes a CoFe alloy or a CoFeB alloy, the magnesium oxide capping dielectric layer 155 consists essentially of magnesium oxide, and the first texture-breaking nonmagnetic layer 126 and the second texture-breaking nonmagnetic layer 176 consist essentially of tungsten.

[0077] In one embodiment, the spinel layer 150 has a thickness in the range of 0.8 nm to 3 nm, the magnesium oxide capping dielectric layer 155 has a thickness in the range of 0.02 nm to 2 nm, the free layer 136 has a thickness in the range of 0.5 nm to 2 nm, and the reference layer 132 has a thickness in the range of 0.8 nm to 1.2 nm.

[0078] In Figure 2 In the first embodiment shown, the spinel layer 150 is a dielectric tunnel barrier layer having a thickness in the range of 0.5 nm to 1.2 nm, and the magnetoresistive memory device 180 includes a spin-transfer torque magnetoresistive memory device. Figure 3 In the second embodiment shown, the spinel layer has a thickness in the range of 1.5 nm to 3 nm, and the magnetoresistive memory device 180A includes a voltage-controlled magnetic anisotropic magnetoresistive memory device.

[0079] In one embodiment, the magnetic tunnel junction stack includes a magnetic tunnel junction that provides a tunneling magnetoresistive ratio in the range of 200% to 300% over a voltage range of 0.5V to 1.0V. Random access memory arrays comprising two-dimensional arrays of examples of magnetoresistive memory devices are also provided.

[0080] exist Figure 4 and Figure 5 In the third embodiment shown, the magnetoresistive memory device (280 or 280A) further includes a nonmagnetic heavy metal SOT layer 410, and the magnetoresistive memory device (280 or 280A) includes a three-terminal spin-orbit torque (SOT) magnetoresistive memory device. The spin-orbit torque (SOT) magnetoresistive memory device (280 or 280A) includes an electrode 184, a nonmagnetic heavy metal SOT layer 410 spaced apart from the electrode 184, and a stack of vertical magnetic tunnel junctions 140 located between the electrode and the SOT layer. The vertical magnetic tunnel junction 140-layer stack includes: a first textured nonmagnetic layer 126 containing a first nonmagnetic transition metal, a second textured nonmagnetic layer 176 containing a second nonmagnetic transition metal, a magnesium oxide dielectric layer 155 located between the first textured nonmagnetic layer and the second textured nonmagnetic layer, a reference layer 132 located between the first textured nonmagnetic layer and the second textured nonmagnetic layer, a free layer 136 located between the first textured nonmagnetic layer and the second textured nonmagnetic layer, and a spinel layer 150 located between the reference layer and the free layer, and includes a polycrystalline spinel material having a (001) texture in an axial direction extending between the reference layer and the free layer.

[0081] exist Figure 4In the spin-orbit torque (SOT) magnetoresistive memory device 280, a first textured nonmagnetic layer 126 is located above the SOT layer 410, an in-plane magnetized ferromagnetic layer 266 is located above the first textured nonmagnetic layer 126, and a magnesium oxide dielectric layer 155 is located above the first textured nonmagnetic layer 126. The magnesium oxide dielectric layer 155 is formed above or below the in-plane magnetized ferromagnetic layer 266. A nonmagnetic metal layer 412 is located above the in-plane magnetized ferromagnetic layer 266 and the magnesium oxide dielectric layer 155, a free layer 136 is located above the nonmagnetic metal layer 412, a spinel layer 150 is located above the free layer 136, a reference layer 132 is located above the spinel layer 150, a second textured nonmagnetic layer 176 is located above the reference layer 132, and an electrode 184 is located above the second textured nonmagnetic layer 176.

[0082] exist Figure 5 In the spin-orbit torque (SOT) magnetoresistive memory device 280A, a first textured nonmagnetic layer 126 is located above the SOT layer 410, a free layer 136 is located above the first textured nonmagnetic layer 126, a spinel layer 150 is located above the free layer 136, a magnesium oxide dielectric layer 155 is located above the spinel layer 150 (and can be directly positioned on the spinel layer), a reference layer 132 is located above the magnesium oxide dielectric layer 155, a second textured nonmagnetic layer 176 is located above the reference layer 132, and an electrode 184 is located above the second textured nonmagnetic layer 176.

[0083] In the third embodiment, the magnesium oxide dielectric layer 155 has a thickness in the range of 0.5 nm to 1 nm, the free layer 136 includes a CoFeB layer or a CoFe layer with a thickness in the range of 0.2 nm to 0.8 nm, and the reference layer 132 includes a CoFeB layer or a CoFe layer with a thickness in the range of 0.5 nm to 2 nm.

[0084] While specific preferred embodiments have been mentioned above, it will be understood that this disclosure is not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. While embodiments employing specific structures and / or configurations are shown in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A magnetoresistive memory device, the magnetoresistive memory device comprising: First electrode; The second electrode is spaced apart from the first electrode; and A vertical magnetic tunneling junction stack, wherein the vertical magnetic tunneling junction stack is located between the first electrode and the second electrode, the vertical magnetic tunneling junction stack comprising: The first textured non-magnetic layer comprises a first non-magnetic transition metal; The second textured nonmagnetic layer comprises a second nonmagnetic transition metal; A magnesium oxide-coated dielectric layer is located between the first textured nonmagnetic layer and the second textured nonmagnetic layer; A reference layer is located between the first texture-destructive nonmagnetic layer and the second texture-destructive nonmagnetic layer; A free layer, located between the first texture-damped nonmagnetic layer and the second texture-damped nonmagnetic layer; and A spinel layer is located between the reference layer and the free layer, and includes a polycrystalline spinel material having a (001) texture along an axial direction extending between the reference layer and the free layer.

2. The magnetoresistive memory device according to claim 1, wherein the reference layer and the free layer have a (001) texture.

3. The magnetoresistive memory device of claim 2, wherein the grains of the free layer are epitaxially aligned with the grains of the spinel layer across the interface between the free layer and the spinel layer.

4. The magnetoresistive memory device according to claim 3, wherein: The magnesium oxide-coated dielectric layer comprises grains with a (001) texture; The grains of the free layer are epitaxially aligned with the grains of the magnesium oxide-covered dielectric layer at the interface between the free layer and the magnesium oxide-covered dielectric layer; and The grains of the reference layer are aligned with the grains of the spinel layer across the interface between the reference layer and the spinel layer.

5. The magnetoresistive memory device according to claim 1, the magnetoresistive memory device further comprising a covering ferromagnetic layer, the covering ferromagnetic layer comprising a polycrystalline ferromagnetic material having a (001) texture.

6. The magnetoresistive memory device according to claim 5, wherein: The magnesium oxide-coated dielectric layer is located between the free layer and the coated ferromagnetic layer; The magnesium oxide-coated dielectric layer comprises grains with a (001) texture; and The grains of the ferromagnetic coating are epitaxially aligned with the grains of the magnesium oxide dielectric layer across the interface between the magnesium oxide dielectric layer and the ferromagnetic coating.

7. The magnetoresistive memory device according to claim 1, wherein: The first nonmagnetic transition metal and the second nonmagnetic transition metal are independently selected from tungsten, ruthenium, tantalum, niobium, molybdenum, and rhenium; and Each of the first texture-destructive nonmagnetic layer and the second texture-destructive nonmagnetic layer has a thickness in the range of 0.2 nm to 1 nm.

8. The magnetoresistive memory device according to claim 1, wherein the spinel layer has a molecular formula M x Q y O z , where 0.95 < x < 1.05, 1.95 < y < 2.05 and 3.95 < z < 4.05, and M and Q are different metals.

9. The magnetoresistive memory device of claim 8, wherein the spinel layer comprises a material selected from MgAl2O4, ZnAl2O4, SiMg2O4, SiZn2O4, MgGa2O4, a certain fraction of at least one metal element obtained therefrom being replaced by another metal element while retaining the crystal structure, and oxygen-deficient derivatives thereof.

10. The magnetoresistive memory device according to claim 8, wherein the spinel layer has a molecular formula of Mg x Al y O z , where 0.95 < x < 1.05, 1.95 < y < 2.05 and 3.95 < z < 4.

05.

11. The magnetoresistive memory device of claim 10, wherein the spinel layer comprises MgAl2O4.

12. The magnetoresistive memory device of claim 1, further comprising a synthetic antiferromagnetic (SAF) structure located between the first electrode and the reference layer, wherein the first texture-destructive nonmagnetic layer is located between the SAF structure and the reference layer.

13. The magnetoresistive memory device according to claim 1, wherein: The spinel layer includes a dielectric tunneling barrier layer having a thickness in the range of 0.5 nm to 1.2 nm; and The magnetoresistive memory device includes a spin-transfer torque magnetoresistive memory device.

14. The magnetoresistive memory device according to claim 1, wherein: The spinel layer has a thickness in the range of 1.5 nm to 3 nm; and The magnetoresistive memory device includes a voltage-controlled magnetic anisotropic magnetoresistive memory device.

15. The magnetoresistive memory device according to claim 1, wherein: The magnesium oxide-coated dielectric layer has a thickness in the range of 0.02 nm to 2 nm; The free layer comprises a CoFeB layer or a CoFe layer having a thickness in the range of 0.5 nm to 2 nm; and The reference layer includes a CoFeB layer or a CoFe layer having a thickness in the range of 0.8 nm to 1.2 nm.

16. A method of forming a magnetoresistive memory device, the method comprising: A first electrode is formed above the substrate; A magnetic tunnel junction stack is deposited on top of the first electrode, wherein the magnetic tunnel junction stack comprises: a first texture-destructive nonmagnetic layer containing a first nonmagnetic transition metal, a reference layer containing a first amorphous ferromagnetic material, a spinel layer containing an amorphous spinel material, a free layer containing a second amorphous ferromagnetic material, a magnesium oxide-covered dielectric layer containing grains with (001) texture, and a second texture-destructive nonmagnetic layer containing a second nonmagnetic transition metal. An annealing process is performed to induce solid-phase epitaxial crystallization of the materials of the free layer, the spinel layer, and the reference layer using a magnesium oxide-coated dielectric layer as a crystallization template layer, thereby converting the amorphous spinel material into a polycrystalline spinel material with a (001) texture along an axial direction perpendicular to the interface between the spinel layer and the free layer; and A second electrode is formed above a portion of the magnetic tunnel junction stack before or after the annealing process; and The reference layer is located between the first texture-damped nonmagnetic layer and the second texture-damped nonmagnetic layer.

17. The method of claim 16, wherein: The solid-phase epitaxy transforms each of the reference layer and the free layer into a polycrystalline ferromagnetic material layer with a (001) texture; The grains in the free layer are epitaxially aligned with the grains in the magnesium oxide-covered dielectric layer during the solid-phase epitaxy. The grains in the spinel layer are epitaxially aligned with the grains in the free layer during the solid-phase epitaxy; and The grains in the reference layer are epitaxially aligned with the grains in the spinel layer in the solid-phase epitaxy.

18. The method according to claim 16, wherein the spinel layer has the molecular formula Mg x Al y O z , where 0.95 < x < 1.05, 1.95 < y < 2.05 and 3.95 < z < 4.

05.

19. The method of claim 16, wherein each of the first texture-destroying nonmagnetic layer and the second texture-destroying nonmagnetic layer prevents the propagation of crystal orientation of the material across it during the solid-phase epitaxial crystallization.

20. The method of claim 16, wherein: The magnetic tunneling stack further includes a covering ferromagnetic layer, which comprises additional amorphous ferromagnetic material in contact with the magnesium oxide covering dielectric layer; and The solid-phase epitaxial crystallization transforms the additional amorphous ferromagnetic material into a polycrystalline ferromagnetic material with a (001) texture.

21. A spin-orbit torque (SOT) magnetoresistive memory device, the SOT magnetoresistive memory device comprising: electrode; A non-magnetic heavy metal SOT layer, wherein the non-magnetic heavy metal SOT layer is spaced apart from the electrode; and A vertical magnetic tunneling junction stack, wherein the vertical magnetic tunneling junction stack is located between the electrode and the SOT layer, the vertical magnetic tunneling junction stack comprising: The first textured non-magnetic layer comprises a first non-magnetic transition metal; The second textured nonmagnetic layer comprises a second nonmagnetic transition metal; A magnesium oxide dielectric layer, wherein the magnesium oxide dielectric layer is located between the first textured nonmagnetic layer and the second textured nonmagnetic layer; A reference layer is located between the first texture-destructive nonmagnetic layer and the second texture-destructive nonmagnetic layer; A free layer, located between the first texture-damped nonmagnetic layer and the second texture-damped nonmagnetic layer; and A spinel layer is located between the reference layer and the free layer, and includes a polycrystalline spinel material having a (001) texture along an axial direction extending between the reference layer and the free layer.

22. The SOT magnetoresistive memory device of claim 21, wherein the reference layer and the free layer have a (001) texture.

23. The SOT magnetoresistive memory device of claim 22, wherein the grains of the free layer are epitaxially aligned with the grains of the spinel layer across the interface between the free layer and the spinel layer.

24. The SOT magnetoresistive memory device according to claim 23, wherein: The magnesium oxide dielectric layer comprises grains with a (001) texture; The grains of the free layer are epitaxially aligned with the grains of the magnesium oxide dielectric layer at the interface between the magnesium oxide dielectric layer and the free layer; and The grains of the reference layer are aligned with the grains of the spinel layer across the interface between the reference layer and the spinel layer.

25. The SOT magnetoresistive memory device according to claim 21, wherein: The first texture-destructive non-magnetic layer is located above the SOT layer; The in-plane magnetized ferromagnetic layer is located above the first textured, non-magnetic layer; The magnesium oxide dielectric layer is located above the first textured, non-magnetic layer. A non-magnetic metal layer is located above the in-plane magnetized ferromagnetic layer and the magnesium oxide dielectric layer; The free layer is located above the non-magnetic metal layer; The spinel layer is located above the free layer; The reference layer is located above the spinel layer; The second texture-breaking non-magnetic layer is located above the reference layer; and The electrode is located above the second texture-damped non-magnetic layer.

26. The SOT magnetoresistive memory device according to claim 21, wherein: The first texture-destructive non-magnetic layer is located above the SOT layer; The free layer is located above the first texture-damaged non-magnetic layer; The spinel layer is located above the free layer; The magnesium oxide dielectric layer is located above the spinel layer; The reference layer is located above the magnesium oxide dielectric layer; The second texture-breaking non-magnetic layer is located above the reference layer; and The electrode is located above the second texture-damped non-magnetic layer.

27. The SOT magnetoresistive memory device according to claim 21, wherein: The first nonmagnetic transition metal and the second nonmagnetic transition metal are independently selected from tungsten, ruthenium, tantalum, niobium, molybdenum, and rhenium; and Each of the first texture-destructive nonmagnetic layer and the second texture-destructive nonmagnetic layer has a thickness in the range of 0.2 nm to 1 nm.

28. The SOT magnetoresistive memory device according to claim 21, wherein the spinel layer has a molecular formula M x Q y O z , where 0.95 < x < 1.05, 1.95 < y < 2.05 and 3.95 < z < 4.05, and M and Q are different metals.

29. The SOT magnetoresistive memory device of claim 28, wherein the spinel layer comprises a material selected from: MgAl2O4, ZnAl2O4, SiMg2O4, SiZn2O4, MgGa2O4, a certain fraction of at least one metal element obtained therefrom being replaced by another metal element while retaining the crystal structure, and oxygen-deficient derivatives thereof.

30. The SOT magnetoresistive memory device according to claim 28, wherein the spinel layer has a chemical formula of Mg x Al y O z , where 0.95 < x < 1.05, 1.95 < y < 2.05, and 3.95 < z < 4.

05.

31. The SOT magnetoresistive memory device of claim 30, wherein the spinel layer comprises MgAl2O4.

32. The SOT magnetoresistive memory device of claim 21, further comprising a synthetic antiferromagnetic (SAF) structure located between the electrode and the reference layer, wherein the first texture-destructive nonmagnetic layer is located between the SAF structure and the reference layer.

33. The SOT magnetoresistive memory device of claim 21, wherein the SOT layer is electrically connected to two terminals of the SOT magnetoresistive memory device.

34. The SOT magnetoresistive memory device according to claim 21, wherein: The SOT layer has a thickness in the range of 5nm to 10nm; and The SOT layer contains Pt, Ta, W, Hf, Ir, CuBi, CuIr, AuPt, AuW, PtPd, or PtMgO.

35. The SOT magnetoresistive memory device according to claim 21, wherein: The magnesium oxide dielectric layer has a thickness in the range of 0.5 nm to 1 nm; The free layer comprises a CoFeB layer or a CoFe layer having a thickness in the range of 0.2 nm to 0.8 nm; and The reference layer includes a CoFeB layer or a CoFe layer having a thickness in the range of 0.5 nm to 2 nm.

36. A method for forming a spin-orbit torque (SOT) magnetoresistive memory device, the method comprising: A non-magnetic heavy metal SOT layer is formed on top of the substrate; A magnetic tunneling layer stack is deposited on top of the SOT layer, wherein the magnetic tunneling layer stack comprises: a first texture-destructive nonmagnetic layer containing a first nonmagnetic transition metal, a reference layer containing a first amorphous ferromagnetic material, a spinel layer containing an amorphous spinel material, a free layer containing a second amorphous ferromagnetic material, a magnesium oxide dielectric layer containing grains having a (001) texture, and a second texture-destructive nonmagnetic layer containing a second nonmagnetic transition metal. An annealing process is performed to induce solid-phase epitaxial crystallization of the materials of the free layer, the spinel layer and the reference layer using a magnesium oxide dielectric layer as a crystallization template layer, so as to convert the amorphous spinel material into a polycrystalline spinel material having a (001) texture along an axial direction perpendicular to the interface between the spinel layer and the free layer. as well as An electrode is formed above a portion of the magnetic tunnel junction stack before or after the annealing process; and The reference layer is located between the first texture-damped nonmagnetic layer and the second texture-damped nonmagnetic layer.

37. The method of claim 36, wherein: The solid-phase epitaxy transforms each of the reference layer and the free layer into a polycrystalline ferromagnetic material layer with a (001) texture; The grains in the free layer are epitaxially aligned with the grains in the magnesium oxide dielectric layer during the solid-phase epitaxy. The grains in the spinel layer are epitaxially aligned with the grains in the free layer during the solid-phase epitaxy; and The grains in the reference layer are epitaxially aligned with the grains in the spinel layer in the solid-phase epitaxy.

38. The method according to claim 36, wherein the spinel layer has the formula Mg x Al y O z , where 0.95 < x < 1.05, 1.95 < y < 2.05 and 3.95 < z < 4.

05.

39. The method of claim 36, wherein each of the first texture-destroying nonmagnetic layer and the second texture-destroying nonmagnetic layer prevents the propagation of the crystal orientation of the material across it during the solid-phase epitaxial crystallization.

40. The method of claim 36, wherein the magnetic tunneling stack further comprises an in-plane ferromagnetic layer between the first texture-disrupted nonmagnetic layer and the magnesium oxide dielectric layer.

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