Composition of a memory cell containing a chalcogenide compound, its structure, its manufacturing method and its operating method

Abstract

An object of the present invention is to provide a component for stable operation of a memory element including a chalcogenide compound, a memory structure suitable for the component, a method for manufacturing the component, and a method for operating the component. To achieve the above object, the present invention can provide a memory array having a crosspoint structure, the memory array comprising: a first electrode line and a second electrode line intersecting each other; and a selection memory element formed of a chalcogenide compound, which is arranged at each intersection of the first electrode line and the second electrode line. The first electrode line is formed on a substrate. A first functional electrode can be formed between the first electrode line and the selection memory element. A second functional electrode can be formed between the second electrode line and the selection memory element. The first functional electrode can be formed as a line along the first electrode line.

Description

Technical Field

[0001] The present invention provides a material composition, a structure of a memory cell, and an algorithm for improving drift for improving the stable operation and characteristics of a memory cell, wherein the memory cell includes a two-terminal selector element that performs the function of selecting a memory cell in a memory array or a selection memory element that simultaneously performs the function of storing a logic state and the function of selecting a memory cell. Background Art

[0002] Due to the recent explosive growth of the data server market and the need to develop new AI semiconductors, the importance of non-volatile memory continues to increase.

[0003] Among various nonvolatile memories, phase-change random access memory (PRAM) utilizes the properties of chalcogenides, whose phase changes back and forth between an amorphous state and a crystalline state in response to applied heat. Recently, a cross-point memory has been developed and commercialized. In this structure, a memory array is formed by arranging and connecting memory cells. The cells include a chalcogenide compound with a changed phase and a two-terminal switching selector that exhibits a sharp increase in current flow at the intersection of electrodes arranged in the horizontal and vertical directions when a voltage equal to or greater than a predetermined voltage is applied.

[0004] A memory device having a cross-point structure requires a two-terminal selector, and through the two-terminal selector, a desired memory cell can be selected for reading and writing among a plurality of memory cells. Many of the two-terminal selectors are chalcogenides.

[0005] In addition, in order to form a cross-point structure as described above, a phase change material for storing a logic state and a two-terminal switching selector for selecting a memory cell are connected to form a memory cell, and the recent U.S. Patent No. 10,134,470 describes a memory device having a cross-point structure and an operating method of the memory device, which utilizes a memory cell including a single chalcogenide compound layer, which is used as a two-terminal switching selector and a memory at the same time by using a chalcogenide instead of a phase change material.

[0006] In order to manufacture a memory array having a cross-point structure using memory cells including a selection memory element (in which both logic state storage and selector functions are performed in a single chalcogen compound layer), it is necessary to form intersecting electrode lines (bit lines, word lines) and pillars including the selection memory element, which is a chalcogen compound, located at the intersections of the electrode lines. However, due to the low rigidity of chalcogen compounds, the process for forming the pillars including chalcogen compounds presents many difficulties. Therefore, there is a need for a structure for the selection memory element and a suitable process for the structure to facilitate more efficient and cost-effective manufacture of a memory device having a cross-point structure using the selection memory element, which is a chalcogen compound.

[0007] In addition, similar to the memory cell 1S1P including a two-terminal selector and a phase change memory element, the memory cell 1S including the selection memory element represents a logic state divided into a set state (the set state is a low resistance state) and a reset state (the reset state is a high resistance state).

[0008] The current change according to the voltage in the memory cell 1S or 1S1P is Figure 1 , where the memory cell in the set state only flows a low current when current is applied, but at the threshold voltage V th_set or higher, the current increases sharply, which indicates that it is turned on. The memory cell in the reset state is also at the threshold voltage V th_reset or higher, and shows a sharp increase in current.

[0009] In order to determine this logical state of the memory cell, as Figure 1 As shown, the threshold voltage V th_set The threshold voltage V th_reset Apply a read voltage V within the read window RW within the range between reading The current flowing is measured to determine whether the selected memory cell is in the set state or the reset state.

[0010] However, over time, the threshold voltage of a memory cell 1S1P including a two-terminal selector and a phase-change memory element composed of a chalcogenide compound, or a memory cell 1S including a selection memory element, gradually increases due to the material's characteristics. This phenomenon, known as drift, causes a change in the read window, making read errors more likely. To address this drift problem, a chalcogenide compound composition that is relatively less susceptible to drift and thus stabilizes the read window is required. Furthermore, a stable reading method for memory cells experiencing drift is also required. Summary of the Invention

[0011] Technical issues

[0012] An object of the present invention is to provide a composition for stably operating and manufacturing a memory cell including a selection memory element or a two-terminal selector composed of a chalcogenide compound, a memory structure, a manufacturing method, and an operating method thereof.

[0013] Technical Solution

[0014] To achieve the stated purpose, a first aspect of the present invention may provide a composition for selecting a memory element, wherein, in terms of atomic ratio, Ge is in the range of 5at% to 20at%, As is in the range of 10at% to 30at%, Se is in the range of 50at% or greater, S is in the range of 0.5at% or greater, and Si is in the range of greater than 0 to less than or equal to 1at%.

[0015] In addition, the second aspect of the present invention can provide a memory array having a cross-point structure, the cross-point structure comprising: a first electrode line and a second electrode line intersecting each other, and a selection memory element arranged at each intersection of the first electrode line and the second electrode line and being a chalcogen compound, wherein the memory array comprises: the first electrode line, the first electrode line being formed on a substrate; a first functional electrode, the first functional electrode being formed between the first electrode line and the selection memory element; and a second functional electrode, the second functional electrode being formed between the second electrode line and the selection memory element, wherein the first functional electrode is formed as a line along the first electrode line.

[0016] In a method for manufacturing a memory array having a cross-point structure including the structure proposed in the second aspect, the third aspect of the present invention can provide a manufacturing method including the following steps: (a) depositing a first electrode layer on a substrate; (b) depositing a first functional electrode layer on the first electrode layer; (c) etching the first electrode layer and the first functional electrode layer together to form a first electrode line and a first functional electrode line; (d) depositing a first ILD layer on the substrate on which the first electrode line and the first functional electrode line are formed; (e) a first planarization step of planarizing the first ILD layer to form a first surface, wherein at least a portion of the upper surface of the first functional electrode line is exposed between the planarized first ILD layers when viewed from the upper surface; (f) depositing a second interlayer dielectric (ILD) layer on the first surface; (g) a hole forming step of forming a hole on the second ILD layer by etching, wherein the hole is formed on the first functional electrode line; and (h) depositing a chalcogen compound constituting the selection memory element on the second ILD layer in which the hole is formed to form the selection memory element in the hole.

[0017] In addition, in a method for initializing a memory cell including a two-terminal selector or selection memory as a chalcogenide compound, a fourth aspect of the present invention can provide a method for initializing a memory cell including the following steps: (a) applying an initialization voltage to the memory cell; (b) determining whether the memory cell is turned on; and (c) terminating the initialization when the memory cell is turned on, and increasing the initialization voltage and repeating steps (a) and (b) when the memory cell is not turned on, wherein the initialization is terminated when the increased initialization voltage exceeds a first voltage, wherein the first initialization voltage first applied from the initialization voltage is less than or equal to the maximum threshold voltage of the memory cell in the set state before drift, and the first voltage is within a drift read window range, which is a voltage range between the minimum threshold voltage of the memory cell expected to be in the reset state after the drift and the maximum threshold voltage of the memory cell in the set state.

[0018] Beneficial effects

[0019] Since the memory element including the chalcogenide compound according to the present invention can be stably operated, the applicability of the memory element to various fields can be increased. In addition, since operational errors in the memory element including the chalcogenide compound can be reduced, the accuracy of the electronic device including the memory element can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a graph showing a change in current according to voltage in a memory cell including a selected memory element or a two-terminal selector.

[0021] Figure 2 is a graph showing a change in current according to voltage in a memory cell including a selected memory element or a two-terminal selector.

[0022] Figure 3 is a graph schematically showing the correlation between the coordination number of a chalcogen compound and the drift.

[0023] Figure 4 is a diagram showing a structure of a memory cell including a selection memory element according to a conventional technique.

[0024] Figure 5 is a diagram showing a structure of a memory cell including a selection memory element according to an embodiment of the present invention.

[0025] Figure 6 is a diagram illustrating a structure of a memory cell including a selection memory element according to another embodiment of the present invention.

[0026] Figure 7is a diagram showing a comparison between the structure of a memory cell including a selection memory element according to a conventional art and the structure of a memory cell including a selection memory element according to the present invention.

[0027] Figure 8 is a process diagram describing a method for manufacturing a memory cell including a selection memory element according to conventional technology.

[0028] Figure 9 is a process diagram describing a method for manufacturing a memory cell including a selection memory element according to the present invention.

[0029] Figure 10 are process diagrams describing a method for fabricating a memory cell including a selection memory element according to an embodiment of the present invention.

[0030] Figure 11 is a process diagram describing a method for fabricating a memory cell including a selection memory element according to another embodiment of the present invention.

[0031] Figure 12 is a graph showing threshold voltage distribution of a memory cell including a selection memory element or a two-terminal selector.

[0032] Figure 13 is a graph illustrating threshold voltage initialization of a memory cell including a selection memory element or a two-terminal selector.

[0033] Figure 14 is a graph showing the initialization steps of a memory cell including selecting a memory element or a two-terminal selector. DETAILED DESCRIPTION

[0034] Hereinafter, the configuration and operation of the embodiments of the present invention will be described with reference to the accompanying drawings. In the following description of the present invention, when it is determined that a detailed description of related known functions or configurations may unnecessarily obscure the main purpose of the present invention, the detailed description will be omitted. In addition, when a part is referred to as "including" any component, unless otherwise specified, it means that the part may also include other components, rather than excluding other components.

[0035] According to the present invention, a composition for selecting a memory element can be provided, wherein, in terms of atomic ratio, Ge is in the range of 5at% to 20at%, As is in the range of 10at% to 30at%, Se is in the range of 50at% or more, S is in the range of 0.5at% or more, and Si is in the range of greater than 0 to less than or equal to 1at%.

[0036] When memory cells read logical states in a memory array having a cross-point structure including selected memory elements, the probability of determining an error is reduced because the difference between the threshold voltage of a memory cell in a set state and the threshold voltage of a memory cell in a reset state (i.e., a read window) is stable.

[0037] However, due to the characteristics of the chalcogenide compound used in selecting the memory element, the chalcogenide compound has a problem of exhibiting a drift phenomenon, in which the threshold voltage of the memory cell in the set state and the threshold voltage of the memory cell in the reset state both increase over time, thereby changing the read window.

[0038] Therefore, after a predetermined period of time, Figure 1 The threshold voltage in is changed to Figure 2 The threshold voltage V in the set state is shown th_set_d and the threshold voltage V in the reset state th_reset_d , and the read voltage V set according to the initial read window RW reading After drifting, it may be located in the read window RW D In addition, the probability of errors in the reading step increases.

[0039] This drift phenomenon can be controlled according to the composition of the chalcogenide, and Figure 3 The 1 / drift (y-axis) of the selected memory element (the inverse of the threshold voltage change according to the drift) is shown according to the average coordination number of the chalcogen element (x-axis). Figure 3 As shown, the smaller the average coordination number of chalcogens on the periodic table, the larger the 1 / drift value. That is, drift is reduced and the read window becomes larger. Specifically, the smaller the atomic number of the chalcogen, the greater the effect. Therefore, considering the above situation, the use of a chalcogen compound containing Se and S is preferred. In particular, when Se and S are mixed and used, the performance and manufacturing suitability of the manufacturing selective memory can be met. Therefore, a chalcogen compound containing 50 at% or more of Se and 0.5 at% or more of S is preferably a chalcogen. Specifically, the S content is more preferably 1 at% to 2 at%.

[0040] In addition, the chalcogenide compound for the selective memory may also include a reduced amount of Group 4 elements or Group 5 elements, representatively, such Group 4 elements and Group 5 elements are Ge and As, respectively, wherein 5at% to 20at% Ge may be included and 10at% to 30at% As may be included.

[0041] Furthermore, when S is included, the rigidity of the selection memory element decreases, so that there may be difficulties in the manufacturing process of manufacturing a memory cell including the selection memory element. Therefore, in order to supplement this rigidity, 1 at % or less of Si may be included.

[0042] In addition, a trace amount of Group 3 elements can improve drift, among which In is typically effective. In addition to In, B, Al, Ga, and Tl can also be effective. The content of Group 3 elements is preferably 0 at% to 15 at%.

[0043] Examples of the composition of such chalcogen compounds are shown in the table below.

[0044] [Table 1]

[0045] serial number In (at%) Ge (at%) As (at%) Se (at%) S (at%) Si (at%) 1 0.1 10.0 27.0 52.0 10.4 0.5 2 0.5 20.0 15.5 55.0 8.5 0.5 3 4.0 15.5 15.0 60.0 5.0 0.5 4 10.0 18.0 15.0 55.0 1.0 1.0 5 15.0 10.0 10.0 63.5 0.7 0.8

[0046] When the content of chalcogen increases, the average coordination number decreases, thereby improving the characteristics of the selective memory. On the contrary, the rigidity of the material decreases, which makes it difficult to form a pattern and may cause cleaning damage. Although there are usually slight differences depending on the material, when Se or S is used instead of Te, the drift value becomes smaller, but the rigidity is further reduced. To overcome the above problems, Si is included in the composition, but it still needs to be supplemented.

[0047] To overcome this problem, the present invention proposes a structure for a selection memory cell including a selection memory element as a chalcogenide compound, and a method for manufacturing the selection memory cell.

[0048] The present invention can provide a memory array with a cross-point structure, which cross-point structure includes: a first electrode line and a second electrode line intersecting each other, and a selection memory element arranged at each intersection of the first electrode line and the second electrode line and being a chalcogen compound, wherein the memory array with a cross-point structure includes: a first electrode line formed on a substrate; a first functional electrode formed between the first electrode line and the selection memory element; and a second functional electrode formed between the second electrode line and the selection memory element, wherein the first functional electrode is formed as a line along the first electrode line.

[0049] Generally, a memory array having a cross-point structure using a selection memory element as a chalcogenide compound is made by forming a pillar 41 in which, as shown in FIG. Figure 4 As shown, the first functional electrode 21 , the selection memory element 30 , and the second functional electrode 22 are sequentially stacked between the intersecting electrode lines 11 and 12 .

[0050] However, when forming pillars comprising functional electrodes as described above, the height of the pillars increases, thereby increasing the aspect ratio (height / width) of the pillars. When the aspect ratio of the pillars increases as described above, the pillars comprising chalcogenides, which have poor rigidity, are damaged or have reduced accuracy during processing, and there is a significant risk of damage during cleaning operations. Therefore, it is necessary to reduce the overall height of the pillars to reduce the aspect ratio.

[0051] Furthermore, compared to forming pillars by forming a chalcogenide layer having poor rigidity and then etching the layer, the pillars are preferably manufactured by a damascene process of filling the formed grooves, and for this purpose, it is advantageous not to include functional electrodes in the pillars in the process.

[0052] Therefore, if Figure 5 As shown, the present invention provides a structure in which the first functional electrode line 23 is formed as a line along the first electrode line 11 first formed on the substrate, and the memory element 30 is selected to be formed as a pillar on the first functional electrode line 23, and then the second functional electrode line 24 is formed as a line along the second electrode line 12 again.

[0053] In this structure, the height of the pillars comprising the selective memory element (which is a chalcogenide with poor rigidity) is reduced, thereby reducing the aspect ratio of the pillars comprising the chalcogenide, thereby preventing process defects and reduced accuracy. Furthermore, since the layer forming the pillars is composed of a single layer of the chalcogenide compound constituting the selective memory element, it is also suitable for application to damascene processes.

[0054] In addition, traditionally, Figure 7 As shown in (a), the first functional electrode 21 is formed into a columnar shape, so that there is a high possibility of current leakage due to the first functional electrode crossing the defect of the insulator, but in the present invention, as shown in Figure 7 As shown in (b), the possibility of the first functional electrode line 23 crossing the insulator is fundamentally blocked, so that there is no possibility of current leakage due to the functional electrode.

[0055] In addition, in the present invention, Figure 6 As shown, it can also be a structure as follows: in this structure, the first functional electrode line 23 is formed along the first electrode line 11, the memory element 30 is selected to be formed as a column on the first functional electrode line 23, and then the second functional electrode 22 is formed as a column behind the selection memory element 30, and the second electrode line 12 is formed.

[0056] In this case, since the pillar 42 composed of the selection memory element 30 and the second functional electrode 22 can also be formed by the damascene process, process defects and the like can be prevented, and there will be no problem. Figure 7 The current leakage shown in (a) is possible.

[0057] According to the present invention, the first functional electrode and the second functional electrode are located between the first electrode and the second electrode intersecting each other and the selection memory element, and such functional electrodes should be used to improve the characteristics of the selection memory while having the characteristics of a conductive material (including a material that has conductivity only under certain conditions), and preferably, have the function of a diffusion barrier layer as an element between the two electrodes and the selection memory element.

[0058] Thus, the functional electrode may be composed of carbon, oxides, nitrides, silicon oxides, borides, or combinations thereof.

[0059] The carbon may be amorphous carbon or graphene, and the oxide may be amorphous carbon such as TiO x 、TaO x , HfO x 、ZrO x 、AlO x 、ZnO x 、SiO x 、RuO x , PtO x The silicon oxide may be a silicon oxide including Si among the above metal oxides, the nitride may be TiN, TaN or CN, and the boride may be CB, TiB, TaB, etc.

[0060] Specifically, the first functional electrode and the second functional electrode according to the present invention may be amorphous carbon, and the thickness may be between to within the range.

[0061] Amorphous carbon is suitable for use as a diffusion barrier between a metal line and a selective memory element and has excellent electrical conductivity, so it is preferably used as a material for a functional electrode. If the thickness is too thin, it cannot sufficiently serve as a diffusion barrier, and if the thickness is too thick, the resistance between the selective memory element and the electrode increases, which is not preferable. Therefore, the appropriate thickness is between to and, more preferably, within the range of to within the range.

[0062] In addition, the first functional electrode and the second functional electrode according to the present invention may be oxide, nitride, silicon oxide, boride or a combination thereof, and the thickness may be between to within the range.

[0063] Oxides, nitrides, silicon oxides and borides are suitable non-conductive materials for use as diffusion barriers, but if they are too thick, there is a problem of increased resistance. Therefore, the appropriate thickness is between to and more preferably, within the range of to within the range.

[0064] In addition, the present invention may provide a memory array having a cross-point structure, the cross-point structure including a selection memory element in which a first functional electrode or a second functional electrode is composed of two layers, wherein a first layer of the two layers is in contact with the selection memory element, and a second layer of the two layers is in contact with the first electrode or the second electrode, the first layer is composed of oxide, silicon oxide, nitride, boride or a combination thereof, and has a thickness of to The second layer is amorphous carbon and has a thickness of to within the range.

[0065] The first layer of the functional electrode is made of a ceramic material such as oxide, which can more faithfully act as a diffusion barrier by contacting the selected memory device, and the second layer in contact with the electrode is formed of amorphous carbon, making it possible to reduce resistance. At this time, the thickness of the first layer is between to More preferably, within the range of to The thickness of the second layer is within the range of to More preferably, within the range of to within the range.

[0066] By forming the functional electrodes as multiple layers rather than a single layer as described above, the advantages of each material can be combined.

[0067] In addition, in a memory array having a cross-point structure including a selection memory element as described above, the composition of the selection memory element may be a chalcogen compound in which, in terms of atomic ratio, Ge is in the range of 5 at % to 25 at %, As is in the range of 10 at % to 30 at %, Se is in the range of 50 at % or greater, S is in the range of 0.5 at % or greater, and Si is in the range of greater than 0 to less than or equal to 1 at %.

[0068] In addition, the selection memory element may be a chalcogenide further including at least one element from the group consisting of B, Al, In, Ga, and Tl, with an atomic ratio ranging from greater than 0 to less than or equal to 15 at %.

[0069] Hereinafter, a method for manufacturing a memory array having a cross-point structure having the composition and structure described above will be described.

[0070] According to the present invention, a method for manufacturing a memory array having a cross-point structure including a selection memory element can be provided, the method comprising the following steps: (a) depositing a first electrode layer on a substrate; (b) depositing a first functional electrode layer on the first electrode layer; (c) etching the first electrode layer and the first functional electrode layer together to form a first electrode line and a first functional electrode line; (d) depositing a first interlayer dielectric (ILD) layer on the substrate on which the first electrode line and the first functional electrode line are formed; (e) a first planarization step of planarizing the first ILD layer to form a first surface, wherein at least a portion of the upper surface of the first functional electrode line is exposed between the planarized first ILD layers when viewed from the upper surface; (f) depositing a second interlayer dielectric (ILD) layer on the first surface; (g) a hole forming step of forming a hole in the second ILD layer by etching, wherein the hole is formed on the first functional electrode line; and (h) depositing a chalcogen compound constituting the selection memory element on the second ILD layer having the hole formed therein to form the selection memory element in the hole.

[0071] Here, the first ILD layer may be an oxide, and the second ILD layer may be a nitride. The first ILD layer may be formed of a general insulating material such as silicon oxide or aluminum oxide, while the second ILD layer having a large contact area with the selected memory device as a chalcogen compound may be formed of a stable nitride such as TiN, TaN, or CN, thereby having low reactivity to reduce the possibility of reacting with the selected memory element.

[0072] In addition, a method for manufacturing a memory array having a cross-point structure including selection memory elements can be provided, the method further comprising the following steps: after step (h), (i) a second planarization step of planarizing the deposited chalcogen compound layer to the same height as that of the second ILD layer to form a second surface, wherein the selection memory elements are independently exposed between the second ILD layers when viewed from the upper surface; (j) depositing a second functional electrode layer on the second surface; (k) depositing a second electrode layer on the second functional electrode layer; and (l) etching the second functional electrode layer and the second electrode layer together to form second functional electrode lines and second electrode lines.

[0073] As another method, a method for manufacturing a memory array having a cross-point structure including selection memory elements may be provided, the method further comprising the following steps: after step (h), (m) a third planarization step of planarizing the deposited chalcogen compound layer to a height lower than that of the second ILD layer to allow the chalcogen compound layer to be removed from surfaces other than holes, and forming a third surface, wherein the selection memory elements are independently exposed between the second ILD layers when viewed from the top surface, and the height of the selection memory elements is lower than that of the second ILD layer when viewed from a side cross-section; (n) depositing a second functional electrode layer on the third surface; (o) a fourth planarization step of planarizing the second functional electrode layer to a height the same as that of the second ILD layer to allow the second functional electrode layer to be removed from surfaces other than holes, and forming a fourth surface, wherein the second functional electrodes are independently exposed in the second ILD layer; (p) depositing a second electrode layer on the fourth functional electrode layer; and (q) etching the second electrode layer to form second electrode lines.

[0074] An example of a conventional general method for manufacturing a memory array having a cross-point structure is Figure 8 . In a conventional method, a first electrode layer 111, a first functional electrode layer 211, a chalcogenide layer 311 constituting a selection memory element, and a second functional electrode layer 221 are sequentially deposited and formed (step 1), and all of them are simultaneously etched to form a wall 412 consisting of the first functional electrode line 212, the chalcogenide line 312, the second functional electrode line 222, and the first electrode line 112 (step 2). A first ILD layer 611 is stacked on the wall 412 (step 3) and flattened to form a first flattened surface 611a exposing the upper surface 222a of the second functional electrode line 222 (step 4). Thereafter, a second electrode layer 121 is deposited (step 5) and etched to form the second electrode line 122. At this time, etching is performed along the second electrode line 122 to the first functional electrode 213 to form a pillar 413 consisting of the first functional electrode 213, the selection memory element 313, and the second functional electrode 223 (step 6). Thereafter, a second ILD layer 621 is deposited on the pillars to allow for filling of the second ILD layer between the pillars (step 7).

[0075] In the process described above, during the two etching steps in steps 2 and 6, the chalcogenide layer 311 is easily damaged and forms high walls 412 and pillars 413 that are not supported by the surroundings. Moreover, due to the poor rigidity of chalcogenide compounds, the walls 412 and pillars 416 with such high aspect ratios may be damaged or have reduced accuracy during the process.

[0076] To overcome the above problems, the present invention proposes a method for manufacturing a memory array having a cross-point structure using a damascene process.

[0077] When passing Figure 9 Describing the manufacturing method according to the present invention in more detail, a first electrode layer 131 is deposited on a substrate, and a first functional electrode layer 231 is deposited again on the first electrode layer 131. The first electrode layer 131 and the first functional electrode layer 231 are then etched together to form first electrode lines 132 and first functional electrode lines 232. A first ILD layer 631 is deposited on the thus-formed first electrode lines 132 and first functional electrode lines 232, and a first planarization step is performed. In this first planarization step, the first ILD layer 631 is planarized to form a first surface 632a. When viewed from above, the upper surface 232a of the first functional electrode line 232 is exposed between the planarized first ILD layers 632. A second ILD layer 641 is deposited on the thus-formed first surface 632a. Holes 711 are formed in the second ILD layer 641 by etching, and holes 711 are also formed in the upper surface 232a of the first functional electrode line 232. On the second ILD layer 641 including the hole 711 thus formed, a chalcogen layer 321 constituting a selection memory element is deposited to fill the hole with a chalcogen compound, thereby forming a selection memory element 322 .

[0078] By forming the selection memory element 322 in the hole as described above, the pillar can be stably formed in the second ILD layer 641 despite the poor rigidity of the chalcogenide.

[0079] Thereafter, the second functional electrodes and the second electrode lines can be formed by two methods.

[0080] First, refer to Figure 10 A method of forming the second functional electrode as a line along the second electrode line is described. Figure 9 The chalcogenide layer 321 deposited in the process is planarized to the same height as the second ILD layer 641 to form a second surface 641a. When viewed from the top, the upper surfaces 322a of the selected memory elements 322 are independently exposed between the second ILD layers. A second functional electrode layer 241 is then deposited on the second surface 641a. A second electrode layer 141 is deposited on the second functional electrode layer 241 and then etched together to form second functional electrode lines 242 and second electrode lines 142, ultimately forming a cross-point structure.

[0081] The cross-point memory array thus formed has the following characteristics: Figure 5The shape shown, wherein the first functional electrode line 232 and the second functional electrode line 242 are formed as lines along the first electrode line 132 and the second electrode line 142, respectively, and the selection memory element 322 is formed in a columnar shape at the point where the first functional electrode line 232 and the second functional electrode line 242 intersect.

[0082] Another approach involves the second functional electrode forming a pillar structure together with the select memory element, which will be Figure 11 Provide a description.

[0083] Figure 11 The chalcogenide layer 311 deposited in the substrate is planarized to a height lower than that of the second ILD layer 641. This planarization operation is called an etch-back operation, and by etching back, the chalcogenide layer 321 is removed from the surface except for the hole 712. When viewed from the top surface, the upper surface 322b of the selected memory element 322 is independently exposed, wherein the height of the upper surface 322b is lower than that of the second ILD layer 641, forming a third surface 641b. The hole 712 still remains on the selected memory element 322. The second functional electrode layer 251 is deposited again on the third surface 641b to form a second functional electrode 252 in the hole 712. Thereafter, the second electrode layer 151 is deposited and then etched to form the second electrode line 152 for finishing.

[0084] The cross-point memory array thus formed has the following characteristics: Figure 6 The shape shown, wherein the first functional electrode line 232 is formed as a line along the first electrode line 132 , and the second functional electrode 252 extends over the selection memory element 322 to form a pillar 420 .

[0085] By the damascene process of filling the hole with the chalcogen compound, a process in which the selective memory element as the chalcogen compound is erected or etched without a supporting layer on the side is prevented, thereby preventing damage to the selective memory device and preventing defects from occurring.

[0086] In addition, due to the characteristics of the material, the threshold voltage of the memory cell 1S1P including a two-terminal selector and a phase change memory element, or the memory cell 1S including a selection memory element, shifts in a gradually increasing direction. The threshold voltage distribution LRS of the memory cells in the set state and the threshold voltage distribution HRS of the memory cells in the reset state are represented by solid lines, and these threshold voltage distributions LRS and HRS increase over time due to a drift phenomenon and become the threshold voltage distributions LRS_D and HRS_D represented by dashed lines.

[0087] When the threshold voltage is changed as described above, the reading voltage V readingThe read window in which the logic state of the memory cell can be effectively read changes from RW1 before the drift to RW2 after the drift. This change is particularly problematic as Figure 2 As shown, because the threshold voltage of the memory cell in the set state gradually increases, the memory cell in the set state may be erroneously read as being in the reset state.

[0088] In order to prevent such errors from occurring during operation, it is necessary to return a memory cell in a set state that has experienced drift over time to an initial state before the drift.

[0089] To this end, in a method for initializing a memory cell including a two-terminal selector or selection memory as a chalcogenide compound, the present invention provides a method for initializing a memory cell, the method comprising the following steps: (a) applying an initialization voltage to the memory cell; (b) determining whether the memory cell is turned on; and (c) terminating the initialization when the memory cell is turned on, and increasing the initialization voltage and repeating steps (a) and (b) when the memory cell is not turned on, wherein the initialization is terminated when the increased initialization voltage exceeds a first voltage, wherein the first initialization voltage first applied from the initialization voltage is less than or equal to the maximum threshold voltage of the memory cell in the set state before drift, and the first voltage is within the drift read window range, which is the voltage range between the minimum threshold voltage of the memory cell expected to be in the reset state after drift and the maximum threshold voltage of the memory cell expected to be in the set state after drift.

[0090] The above method is an initialization method of returning the threshold voltage of a memory cell in a set state to a state before drift before a reading step of determining whether the memory cell is in a set state or reset.

[0091] The threshold voltage of the memory cell 1S1P including a two-terminal selector and a phase-change memory element or the memory cell 1S including a selection memory element returns to the threshold voltage of the memory cell in the initial set state after the memory cell is turned on exceeding the threshold voltage, regardless of whether the memory cell is in the set state or the reset state. Figure 13 shows such an initialization, wherein the initialization voltage V is applied pr After the memory cell is turned on, the threshold voltage V in the voltage-current curve 1030 of the memory cell in the set state after the drift has occurred is th_set_d Initialized to the threshold voltage V in the voltage-current curve 1010 of the memory cell in the set state before drifting th_set .

[0092] Therefore, when all memory cells in the set state are turned on and initialized before the memory cells are read, read errors caused by changes in the read window due to drift can be reduced. The above initialization method is needed to stably maintain the read window of cells that drift.

[0093] Reference Figure 14 , the initialization method according to the present invention will be described in more detail.

[0094] First, the first initialization voltage V pre1 is applied to a memory cell that has drifted, and determines whether the memory cell is turned on.

[0095] When the memory cell is turned on, the initialization stops. When the memory cell is not turned on, the initialization voltage is increased and the initialization voltage V is applied again. pre2 , and again determine whether the memory cell is turned on.

[0096] When gradually increasing the initialization voltage (V pre1 →V pre2 →V pre3 ...→V pre_n ) while determining whether the memory cell is turned on, thereby all memory cells in the set state are turned on and initialized.

[0097] If the memory cells are in the reset state and therefore not turned on, the initialization process is terminated when the increased initialization voltage exceeds the first voltage V1 and the first voltage V1 is within the drift read window range RW2, which is a voltage range between the minimum threshold voltage V41 of the memory cells expected to be in the reset state after the drift and the maximum threshold voltage V32 of the memory cells expected to be in the set state after the drift. Therefore, since the initialization voltage is greater than the maximum threshold voltage V32 in the set state, all memory cells in the set state can be turned on, and since it does not exceed the minimum threshold voltage V41 of the memory cells that are stably in the reset state, the memory cells in the reset state are prevented from being turned on, and the memory cells in the reset state are not initialized.

[0098] The initialization voltage used to initialize a memory cell in a set state according to the initialization method of the present invention is only slightly higher than the threshold voltage of the memory cell, so that the load applied to the memory cell during the initialization process can be very small. If the initialization is performed using an excessively high voltage, the memory cell will suddenly turn on, causing a large current to flow immediately, which may damage the memory cell.

[0099] At this time, the first initialization voltage V pre1It may be the minimum threshold voltage V11 of the memory cell in the set state before drifting.

[0100] By gradually increasing the applied voltage from the minimum possible threshold voltage of the memory cell, the load applied to the memory cell due to the initialization process can be minimized.

[0101] In addition, in step (c), the initialization voltage may be increased by 5 mV to 200 mV at a time.

[0102] If the initialization voltage is increased too much at a time, the current flowing in the cell to be turned on may be too large, and if it is increased too little, it is not preferred because the time required for the initialization process increases. Therefore, the preferred voltage increase is 5mV to 200mV each time, more preferably, 20mV to 60mV.

[0103] Furthermore, the first voltage is within a drift read window, and a difference between the first voltage and an expected maximum threshold voltage of the memory cell in the set state after drifting can be within a range of 0.50 to 0.95 relative to the drift read window.

[0104] exist Figure 14 Preferably, the first voltage V1 is within the drift read window range RW2 and is close to the minimum threshold voltage V41 of the memory cells expected to be in the reset state after drift, so as to initialize all memory cells in the set state whose threshold voltages are abnormally high (which is possible).

[0105] For this reason, it is preferred that the difference A between the first voltage V1 and the maximum threshold voltage V32 of the memory cell in the set state expected after drift is in the range of 0.50 to 0.95 when the entire drift read window range RW2 is 1. When the first voltage V1 is close to the maximum threshold voltage V32 of the memory cell in the set state after drift due to a value less than 0.50, it is not preferred because the memory cell in the set state having an abnormally large threshold voltage may not be initialized, and when it is as close as possible but too close to the minimum threshold voltage V41 of the memory cell in the reset state, it is also not preferred because the cell in the reset state may be initialized.

[0106] Therefore, the difference A between the first voltage V1 and the expected maximum threshold voltage V32 of the memory cell in the set state after drift divided by the entire drift read window range RW2 is preferably in the range of 0.50 to 0.95, more preferably in the range of 0.75 to 0.90.

Claims

1. A method of initializing a memory cell comprising a two-terminal selector or select memory as a chalcogenide, the method comprising the steps of: (a) applying an initialization voltage to the memory cell; (b) determining whether the memory cell is turned on; as well as (c) when the memory cell is turned on, terminating the initialization, and when the memory cell is not turned on, increasing the initialization voltage and repeating steps (a) and (b), wherein the initialization is terminated when the increased initialization voltage exceeds the first voltage, wherein the first initialization voltage first applied from the initialization voltage is less than or equal to the maximum threshold voltage of the memory cell in the set state before drifting, and The first voltage is within a drift read window, which is a voltage range between a minimum threshold voltage of a memory cell expected to be in a reset state after the drift and the maximum threshold voltage of the memory cell expected to be in the set state after the drift.

2. The method according to claim 1, wherein The first initialization voltage is a minimum threshold voltage of the memory cell in the set state before the drifting.

3. The method according to claim 1, wherein In step (c), the initialization voltage is increased by 5 mV at a time to 200 mV.

4. The method according to claim 1, wherein A difference between the first voltage and an expected maximum threshold voltage of the memory cell in a set state after the drift is in a range of 0.50 to 0.95 relative to the drift read window.

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