Capacitor and resistor structures based on gate material and methods of forming the same

Abstract

A capacitor or resistor structure is disclosed in which at least one of the capacitor or resistor structure can be formed simultaneously with the formation of a field effect transistor by patterning a gate dielectric layer into a gate electrode and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or resistor strip. Contacts are then formed to the capacitor or resistor structure. Prior to patterning the capacitor or resistor contacts, sidewall spacers can be formed on the gate electrode to reduce damage to the underlying capacitor or resistor layer.

Description

[0001] Related applications

[0002] This application claims priority to U.S. non-provisional application No. 17 / 006,228, filed August 28, 2020, and U.S. non-provisional application No. 17 / 006,265, filed August 28, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to the field of semiconductor devices, and more specifically to capacitor and resistor structures based on gate materials and methods for manufacturing the same. Background Technology

[0004] Passive components, such as capacitor and resistor structures, can be combined with transistors to provide a variety of circuits. The manufacture of capacitor and resistor structures requires many processing steps, which contribute to the process complexity and overall cost of semiconductor die manufacturing. Summary of the Invention

[0005] According to one aspect of this disclosure, a semiconductor structure is provided comprising a capacitor structure located on a semiconductor substrate including a substrate semiconductor layer. The capacitor structure includes: a first electrode including a first substrate semiconductor portion of the substrate semiconductor layer; a first node dielectric located on a top surface of the first substrate semiconductor portion of the substrate semiconductor layer; a second electrode including a first semiconductor plate and located on the top surface of the first node dielectric; a second node dielectric located on the top surface of the first semiconductor plate; a third electrode including a stack of a second semiconductor plate and a main metal plate; a trench laterally surrounding the third electrode; a peripheral stack laterally surrounding the third electrode, wherein the peripheral stack includes a peripheral semiconductor plate and a peripheral metal plate, and wherein the peripheral semiconductor plate contacts a peripheral portion of the top surface of the second node dielectric, comprises the same material as the second semiconductor plate, and is laterally spaced from the second semiconductor plate; and at least one contact-level dielectric layer extending laterally over the third electrode and the peripheral stack.

[0006] According to another aspect of the present disclosure, a method of forming a semiconductor structure including a capacitor structure on a semiconductor substrate including a substrate semiconductor layer is provided. The method includes forming a first stack including a first node dielectric and a first semiconductor plate on a top surface of a first substrate semiconductor portion of the substrate semiconductor layer; forming a second stack including a second node dielectric and a semiconductor sheet over the first stack; forming a metal sheet over the second stack and over a peripheral portion of a top surface of the first semiconductor plate; dividing the metal sheet and the semiconductor sheet into an inner layer stack surrounded by a moat trench and a peripheral stack surrounding the moat trench, wherein sidewalls of the layer stack and sidewalls of the peripheral stack are physically exposed in the moat trench; forming at least one contact level dielectric layer directly on the sidewalls of the inner layer stack and the sidewalls of the peripheral stack; and forming a contact via structure through the at least one contact level dielectric layer on the layer stack and on the peripheral stack, wherein: the inner layer stack includes a main semiconductor plate and a main metal plate; the peripheral stack includes a peripheral semiconductor plate and a peripheral metal plate; the main semiconductor plate and the peripheral semiconductor plate are patterned portions of the semiconductor sheet; and the main metal plate and the peripheral metal plate are patterned portions of the metal sheet.

[0007] According to yet another aspect of the present disclosure, a semiconductor structure including a resistor structure on a semiconductor substrate including a substrate semiconductor layer is provided. The resistor structure includes: a first resistor isolation dielectric on a top surface of a first substrate semiconductor portion of the substrate semiconductor layer; a strip of semiconductor material on a top surface of the first resistor isolation dielectric; a first resistor contact assembly including a first semiconductor plate including an opening therein and a first metal plate extending through the opening in the first semiconductor plate and contacting a first region of a top surface of the strip of semiconductor material; a second resistor contact assembly including a second semiconductor plate including an opening therein and a second metal plate extending through the opening in the second semiconductor plate and contacting a second region of the top surface of the strip of semiconductor material; and a peripheral stack including a peripheral semiconductor plate and a peripheral metal plate and electrically isolated from the strip of semiconductor material, wherein the peripheral semiconductor plate includes a same material as the first semiconductor plate and the second semiconductor plate, and the peripheral metal plate includes a same material as the first metal plate and the second metal plate.

[0008] According to yet another aspect of the present disclosure, a method of forming a semiconductor structure including a resistor structure on a semiconductor substrate including a substrate semiconductor layer is provided. The method includes forming a first stack including a first resistor isolation dielectric and a strip of semiconductor material on a top surface of the first substrate semiconductor portion of the substrate semiconductor layer; forming a second stack including a second resistor isolation dielectric and a sheet of semiconductor over the first stack, wherein the second stack includes openings therethrough, and a portion of a top surface of the strip of semiconductor material is physically exposed at a bottom of each of the openings in the second stack; forming a sheet of metal over the second stack and on the physically exposed portion of the top surface of the strip of semiconductor material; and dividing the sheet of metal and the sheet of semiconductor into patterned portions including a first resistor contact assembly and a second resistor contact assembly. In one embodiment, the first resistor contact assembly includes a first sheet of semiconductor including openings therein and a first sheet of metal extending through the openings in the first sheet of semiconductor and contacting a first region of the top surface of the strip of semiconductor material; and the second resistor contact assembly includes a second sheet of semiconductor including openings therein and a second sheet of metal extending through the openings in the second sheet of semiconductor and contacting a second region of the top surface of the strip of semiconductor material. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1A is a schematic vertical cross-sectional view of a first exemplary structure after forming a first isolation dielectric layer and a first semiconductor material layer according to the first embodiment of the present disclosure.

[0010] FIG. 1B is a top-down view of the first exemplary structure taken along the vertical plane B-B' of FIG. 1A

[0011] FIG. 2A is a schematic vertical cross-sectional view of the first exemplary structure after forming a shallow isolation trench according to the first embodiment of the present disclosure.

[0012] FIG. 2B is a top-down view of the first exemplary structure taken along the vertical plane B-B' of FIG. 2A

[0013] FIG. 3A is a schematic vertical cross-sectional view of the first exemplary structure after forming a shallow isolation structure according to the first embodiment of the present disclosure.

[0014] FIG. 3B is a top-down view of the first exemplary structure taken along the vertical plane B-B' of FIG. 3A

[0015] FIG. 4A ​​​is a schematic vertical cross-sectional view of the first exemplary structure after forming a second isolation dielectric layer and a second semiconductor material layer according to the first embodiment of the disclosure.

[0016] FIG. 4B is a top-down view of the first exemplary structure taken along the vertical plane B-B' of FIG. 4A

[0017] FIG. 5A is a schematic vertical cross-sectional view of the first exemplary structure after forming a second node dielectric and a semiconductor sheet according to the first embodiment of the disclosure.

[0018] FIG. 5B is a top-down view of the first exemplary structure taken along the vertical plane B-B' of FIG. 5A

[0019] FIG. 6A is a schematic vertical cross-sectional view of the first exemplary structure after forming a metal material layer and a dielectric cap layer according to the first embodiment of the disclosure.

[0020] FIG. 6B is a top-down view of the first exemplary structure taken along the vertical plane B-B' of FIG. 6A

[0021] FIG. 7A is a schematic vertical cross-sectional view of the first exemplary structure after patterning the dielectric cap layer, the metal material layer, the first semiconductor plate, and the gate semiconductor material portion, and after forming source and drain extension regions according to the first embodiment of the disclosure.

[0022] FIG. 7B is a top-down view of the first exemplary structure taken along the vertical plane B-B' of FIG. 7A

[0023] FIG. 8A is a schematic vertical cross-sectional view of the first exemplary structure after forming dielectric capacitor spacers, dielectric gate spacers, and source and drain regions according to the first embodiment of the disclosure.

[0024] FIG. 8B is a top-down view of the first exemplary structure taken along the vertical plane B-B' of FIG. 8A

[0025] FIG. 9A is a schematic vertical cross-sectional view of the first exemplary structure after forming a moat trench that patterns the stack of the semiconductor sheet and the metal plate into a main semiconductor plate, a main metal plate, a peripheral semiconductor plate, and a peripheral metal plate according to the first embodiment of the disclosure.

[0026] ​​​​​FIG. 9B It is along FIG. 9A A top view of the first exemplary structure taken by the vertical plane BB′.

[0027] FIG. 10A This is a schematic vertical cross-sectional view of a first exemplary structure after the formation of at least one contact-level dielectric layer according to a first embodiment of the present disclosure.

[0028] FIG. 10B It is along FIG. 10A A top view of the first exemplary structure taken by the vertical plane BB′.

[0029] FIG. 11A This is a schematic vertical cross-sectional view of a first exemplary structure after the formation of the contact via structure according to a first embodiment of the present disclosure.

[0030] FIG. 11B It is along FIG. 11A A top view of the first exemplary structure taken by the vertical plane BB′.

[0031] FIG. 12A This is a schematic vertical cross-sectional view of an alternative configuration of a first exemplary structure after the formation of the second node dielectric and semiconductor sheet, according to a first embodiment of the present disclosure.

[0032] FIG. 12B It is along FIG. 12A A top view of the first exemplary structure taken by the vertical plane BB′.

[0033] FIG. 13A This is a schematic vertical cross-sectional view of an alternative configuration of a first exemplary structure after the formation of a trench, according to a first embodiment of the present disclosure, wherein the trench patternes a stack of semiconductor wafers and metal plates into a main semiconductor plate, a main metal plate, a peripheral semiconductor plate, and a peripheral metal plate.

[0034] FIG. 13B It is along FIG. 13A A top view of an alternative configuration of the first exemplary structure, taken from the vertical plane BB′.

[0035] FIG. 14A This is a schematic vertical cross-sectional view of an alternative configuration of a first exemplary structure after the formation of a contact via structure according to a first embodiment of the present disclosure.

[0036] FIG. 14B It is along FIG. 14A A top view of the first exemplary structure taken by the vertical plane BB′.

[0037] FIG. 15Ais a schematic vertical cross-sectional view of a second exemplary structure after forming a first isolation dielectric layer and a first semiconductor material layer according to the first embodiment of the present disclosure.

[0038] FIG. 15B is a top-down view of the first exemplary structure taken along the vertical plane B-B' of FIG. 15A

[0039] FIG. 16A is a schematic vertical cross-sectional view of a second exemplary structure after forming a shallow isolation trench according to the second embodiment of the present disclosure.

[0040] FIG. 16B is a top-down view of the second exemplary structure taken along the vertical plane B-B' of FIG. 16A

[0041] FIG. 17A is a schematic vertical cross-sectional view of a second exemplary structure after forming a shallow isolation structure according to the second embodiment of the present disclosure.

[0042] FIG. 17B is a top-down view of the second exemplary structure taken along the vertical plane B-B' of FIG. 17A

[0043] FIG. 18A is a schematic vertical cross-sectional view of a second exemplary structure after forming a second isolation dielectric layer and a second semiconductor material layer according to the second embodiment of the present disclosure.

[0044] FIG. 18B is a top-down view of the second exemplary structure taken along the vertical plane B-B' of FIG. 18A

[0045] FIG. 19A is a schematic vertical cross-sectional view of a second exemplary structure after forming a second resistor isolation dielectric and a semiconductor sheet according to the second embodiment of the present disclosure.

[0046] FIG. 19B is a top-down view of the second exemplary structure taken along the vertical plane B-B' of FIG. 19A

[0047] FIG. 20A is a schematic vertical cross-sectional view of a second exemplary structure after forming a metal material layer and a dielectric cap layer according to the second embodiment of the present disclosure.

[0048] FIG. 20B is a top-down view of the second exemplary structure taken along the vertical plane B-B' of FIG. 20A

[0049] FIG. 21A ​​​​​​is a schematic vertical cross-sectional view of a second exemplary structure after patterning a dielectric cap layer, a metal material layer, and a gate semiconductor material portion, and after forming source and drain extension regions, according to the second embodiment of the present disclosure.

[0050] FIG. 21B is a top-down view of the second exemplary structure, taken along the vertical plane B-B' of FIG. 21A

[0051] FIG. 22A is a schematic vertical cross-sectional view of a second exemplary structure after forming dielectric resistor spacers, dielectric gate spacers, and source and drain regions, according to the second embodiment of the present disclosure.

[0052] FIG. 22B is a top-down view of the second exemplary structure, taken along the vertical plane B-B' of FIG. 22A

[0053] FIG. 23A is a schematic vertical cross-sectional view of a second exemplary structure after forming a moat trench that patterns the layer stack of semiconductor sheet, metal sheet, and dielectric cap sheet into a resistor contact assembly and a peripheral stack, according to the second embodiment of the present disclosure.

[0054] FIG. 23B is a top-down view of the second exemplary structure, taken along the vertical plane B-B' of FIG. 23A

[0055] FIG. 24A is a schematic vertical cross-sectional view of a second exemplary structure after forming at least one contact level dielectric layer, according to the second embodiment of the present disclosure.

[0056] FIG. 24B is a top-down view of the second exemplary structure, taken along the vertical plane B-B' of FIG. 24A

[0057] FIG. 25A is a schematic vertical cross-sectional view of a second exemplary structure after forming a contact via structure, according to the second embodiment of the present disclosure.

[0058] FIG. 25B is a top-down view of the second exemplary structure, taken along the vertical plane B-B' of FIG. 25A DETAILED DESCRIPTION

[0059] ​​​​​As discussed above, the present disclosure relates to gate material-based capacitor structures and resistor structures and methods of manufacturing the same, aspects of which are described below. Embodiments of the present disclosure can be used to form capacitor structures and resistor structures that incorporate a conductive layer used to form a gate structure of an adjacent field effect transistor. The field effect transistors, capacitors, and resistors can be used in any suitable semiconductor device, such as a driver circuit for a three-dimensional NAND memory device.

[0060] The drawings are not drawn to scale. Where a single instance of an element is illustrated in a figure, multiple instances of the element can be repeated unless explicitly described or otherwise clearly indicated otherwise. Numerical designations such as “first,” “second,” and “third” are merely used to identify like elements and different numerical designations can be employed throughout the specification and claims of the present disclosure. The term “at least one” element means all possibilities including the possibility of a single element and the possibility of multiple elements.

[0061] Like reference numbers indicate like elements or similar elements. Unless otherwise specified, elements with the same reference numbers are assumed to have the same composition and the same function. Unless otherwise indicated, “contact” between elements means direct contact between elements that provides a shared edge or surface of the elements. Two or more elements are “separated” from each other if they are not in direct contact with each other or with each other. As used herein, a first element positioned “on” a second element can be positioned on an outer side of a surface of the second element or on an inner side of the second element. As used herein, a first element is “directly” positioned on a second element if there is physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is “electrically connected to” a second element if there is an electrically conductive path between the first element and the second element that is comprised of at least one electrically conductive material. As used herein, a “prototype” structure or “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component thereof.

[0062] As used herein, a “layer” refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have a scope that is less than the scope of an underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform structure having a thickness that is less than the thickness of the structure. For example, a layer can be positioned between or at any pair of horizontal planes between a top surface and a bottom surface of a structure or a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, or can have one or more layers thereon, over and / or below.

[0063] Reference FIGS. 1A-1BAccording to a first exemplary structure of a first embodiment of the present disclosure includes a substrate that includes a substrate semiconductor layer 10. The substrate 8 can be a semiconductor substrate that includes a semiconductor material at least at an upper portion thereof. The substrate 8 can be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate that includes a top semiconductor (e.g., silicon) layer (which corresponds to the substrate semiconductor layer 10), a buried insulating layer (not shown), and a handle substrate. In one embodiment, the substrate 8 can be a commercially available semiconductor wafer, such as a silicon wafer.

[0064] The provided substrate semiconductor layer 10 can include a semiconductor material. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0 x 10 -6 S / cm to 1.0 x 10 5 S / cm. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0 x 10 -6 S / cm to 1.0 x 10 5 S / cm, and capable of producing a doped material having electrical conductivity in the range from 1.0 S / cm to 1.0 x 10 5 S / cm upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds holes to a valence band within a band structure or an n-type dopant that adds electrons to a conduction band within a band structure. As used herein, an “electrically conductive material” refers to a material having electrical conductivity greater than 1.0 x 10 5 S / cm. As used herein, an “insulator material” or “dielectric material” refers to a material having electrical conductivity less than 1.0 x 10 -6 S / cm. As used herein, a “heavily doped semiconductor material” refers to a semiconductor material that is doped with an electrical dopant at a sufficiently high atomic concentration to become an electrically conductive material (i.e., have electrical conductivity greater than 1.0 x 10 5 S / cm) when formed as a crystalline material or in the case of being converted to a crystalline material (e.g., starting from an initial amorphous state) by an annealing process. A “doped semiconductor material” can be a heavily doped semiconductor material, or can be a semiconductor material that includes electrical dopants at a concentration in the range from 1.0 x 10 -6 S / cm to 1.0 x 10 5Semiconductor materials with electrical dopant concentrations (i.e., p-type and / or n-type dopant) in the range of S / cm. "Intrinsic semiconductor material" refers to a semiconductor material undoped with electrical dopants. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. Doped semiconductor materials can be semiconductor or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material comprising at least one metallic element. All conductivity measurements were performed under standard conditions.

[0065] Typically, the substrate semiconductor layer 10 may comprise any semiconductor material known in the art. For example, single-crystal silicon, silicon-germanium alloy, polycrystalline silicon, III-V semiconductor materials, III-VI semiconductor materials, or any other semiconductor material may be used for the substrate semiconductor layer 10. In one embodiment, the substrate semiconductor layer 10 may comprise single-crystal silicon and may include a doped well in the upper portion of a single-crystal silicon wafer or an epitaxial single-crystal silicon layer grown on the top surface of a single-crystal silicon wafer. In one embodiment, the provided substrate semiconductor layer 10 may include an atomic concentration of 1.0 × 10⁻⁶. 14 / cm 3 Up to 1.0×10 18 / cm 3 The dopant is of a first conductivity type (which may be p-type or n-type) within the range, but smaller and larger dopant concentrations may also be used. The substrate semiconductor layer 10 includes a first substrate semiconductor portion 10C located in a first device region (where a capacitor structure is subsequently formed) and a second substrate semiconductor portion 10T located in a second device region (where a field-effect transistor is subsequently formed).

[0066] In one embodiment, the first substrate semiconductor portion 10C can be appropriately doped by implanting a dopant into the first substrate semiconductor portion 10C. For example, an electrically conductive dopant of a first conductivity type or an electrically conductive dopant of a second conductivity type opposite to the first conductivity type can be implanted into the first substrate semiconductor portion 10C by performing a patterned ion implantation process. In one embodiment, the surface region of the first substrate semiconductor portion 10C may include an atomic concentration of 5.0 × 10⁻⁶. 19 / cm 3 Up to 2.0×10 21 / cm 3 An electrostatic dopant within a certain range is used to make the implanted surface region of the first substrate semiconductor portion 10C conductive. The conductive region of the first substrate semiconductor portion 10C includes a first electrode of a capacitor structure to be subsequently formed. The conductive region of the first substrate semiconductor portion 10C may be limited to a surface region with a thickness in the range of 10 nm to 200 nm, or it may occupy the entire volume of the first substrate semiconductor portion 10C.

[0067] A first isolation dielectric layer 30L can be formed over the entire top surface of the substrate semiconductor layer 10. The first isolation dielectric layer 30L can be formed over each of the first substrate semiconductor portion 10C and the second substrate semiconductor portion 10T of the substrate semiconductor layer 10. The first isolation dielectric layer 30L includes at least one dielectric material that can be used as a gate dielectric, and is therefore also referred to as a gate dielectric layer. The first isolation dielectric layer 30L can include silicon oxide, silicon nitride, and / or a dielectric metal oxide such as aluminum oxide, hafnium oxide, lanthanum oxide, tantalum pentoxide, etc. The first isolation dielectric layer 30L can be formed by thermal oxidation of the semiconductor material of the substrate semiconductor layer 10, and / or can be formed by depositing a high quality dielectric material such as a dielectric metal oxide, silicon nitride, and / or silicon oxide using chemical vapor deposition or atomic layer deposition. The thickness of the first isolation dielectric layer 30L can be in a range from 1 nm to 20 nm, such as from 2 nm to 12 nm and / or from 4 nm to 8 nm, although lesser and greater thicknesses can also be employed.

[0068] A first semiconductor material layer 40L can be deposited over and directly on the first isolation dielectric layer 30L. The first semiconductor material layer 40L can include a doped semiconductor material having a first conductivity type or a second conductivity type. In one embodiment, the first semiconductor material layer 40L can include amorphous silicon, polysilicon, or a silicon-germanium alloy. In one embodiment, the first semiconductor material layer 40L can be electrically conductive. The first semiconductor material layer 40L can be deposited using chemical vapor deposition. The first semiconductor material layer 40L can be doped in situ with electrical dopants during deposition of the first semiconductor material layer 40L, or can be doped non-in situ by performing a low energy ion implantation process after deposition of an intrinsic semiconductor material. The thickness of the first semiconductor material layer 40L can be in a range from 20 nm to 200 nm, such as from 40 nm to 60 nm, although lesser and greater thicknesses can also be employed.

[0069] Referring to FIG. 2A and FIG. 2B The first semiconductor material layer 40L and the first isolation dielectric layer 30L can be patterned, e.g., by applying and patterning a photoresist layer to form discrete patterned photoresist material portions over regions of the first substrate semiconductor portion 10C and additional patterned photoresist material portions over each region of the second substrate semiconductor portion 10T. An anisotropic etching process can be performed to etch unmasked portions of the first semiconductor material layer 40L, the first isolation dielectric layer 30L, and the upper portion of the substrate semiconductor layer 10. Shallow isolation trenches 11 are formed laterally surrounding the patterned portions of the first semiconductor material layer 40L, the first isolation dielectric layer 30L, and the upper portion of the substrate semiconductor layer 10. The shallow isolation trenches 11 can be interconnected to each other as a single continuous volume, as shown in FIG. 3B, or can be formed as discrete shallow isolation trenches 11, as shown in FIG. 3C. The shallow isolation trenches 11 can be formed to a depth in a range from 1 nm to 20 nm, such as from 2 nm to 12 nm and / or from 4 nm to 8 nm, although lesser and greater depths can also be employed. FIG. 2AThe photoresist layer can be removed, e.g., by ashing. The bottom boundaries of the first substrate semiconductor portion 10C and the second substrate semiconductor portion 10T can lie in a horizontal plane that includes the bottom surfaces of the shallow isolation trenches 11.

[0070] The patterned portions of the substrate semiconductor layer 10 include the first substrate semiconductor portion 10C and the second substrate semiconductor portion 10T. In other words, the pattern in the patterned photoresist layer can be selected such that the remaining portions of the substrate semiconductor layer 10 include the first substrate semiconductor portion 10C and the second substrate semiconductor portion 10T. In one embodiment, the first substrate semiconductor portion 10C and the second substrate semiconductor portion 10T can optionally include vertically tapered and horizontally straight sidewalls that extend laterally along a horizontal direction. For example, the first substrate semiconductor portion 10C and the second substrate semiconductor portion 10T can include a respective pair of sidewalls that extend laterally along a first horizontal direction hd1 and a respective pair of sidewalls that extend laterally along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. In general, the first substrate semiconductor portion 10C can have any horizontal cross-sectional shape, such as a polygonal shape, a circular polygon, a circle, an ellipse, or any two-dimensional closed curve shape. The second substrate semiconductor portion 10T can have a rectangular horizontal cross-sectional shape, which facilitates the formation of field effect transistors thereon.

[0071] The patterned portions of the first isolation dielectric layer 30L include first node dielectrics (i.e., first capacitor dielectrics) 30 formed on top surfaces of the first substrate semiconductor portion 10C and gate dielectrics 38 formed on respective ones of the second substrate semiconductor portion 10T. The patterned portions of the first semiconductor material layer 40L include first semiconductor plates 40 and gate semiconductor material portions 49. The first semiconductor plates 40 can be formed on top surfaces of the first node dielectrics 30. The gate semiconductor material portions 49 can be formed on top surfaces of respective ones of the gate dielectrics 38. The first semiconductor plates 40 can function as second electrodes of the capacitor structures of one embodiment of the present disclosure. Thus, a first stack of the first node dielectrics 30 and the first semiconductor plates 40 can be formed. A bottom surface of the first semiconductor plate 40 can coincide with a perimeter of a top surface of the first node dielectric 30. Sidewalls of the first semiconductor plate 40 and the first node dielectric 30 can vertically coincide. As used herein, first and second surfaces “vertically coincide” if the second surface is above or below the first surface and if there is a vertical plane that includes the first and second surfaces. The vertical plane can or can not have a curvature in a horizontal cross-sectional view.

[0072] Reference is made to FIG. 3A and FIG. 3BAt least one dielectric material can be deposited in the shallow isolation trench 11. The at least one dielectric material can include an optional diffusion barrier liner material, such as a silicon nitride liner material, and a planarizable dielectric fill material, such as an undoped silicate glass or a doped silicate glass. The at least one dielectric material can fill the entire volume of the shallow isolation trench 11. By a planarization process, excess portions of the at least one dielectric material can be removed from above the horizontal plane including the top surfaces of the first semiconductor plate 40 and the gate semiconductor material portion 49. For example, a chemical mechanical planarization process can be employed to remove excess portions of the at least one dielectric material from above the horizontal plane including the top surfaces of the first semiconductor plate 40 and the gate semiconductor material portion 49. The remaining portions of the at least one dielectric material filling the volume of the shallow isolation trench 11 constitute a shallow trench isolation (STI) structure 20. The shallow trench isolation structure 20 laterally surrounds each of the first substrate semiconductor portion 10C and the second substrate semiconductor portion 10T, the first node dielectric 30 and the gate dielectric 38, and each of the first semiconductor plate 40 and the gate semiconductor material portion 49. In one embodiment, each sidewall of the first substrate semiconductor portion 10C, the second substrate semiconductor portion 10T, the first node dielectric 30, the gate dielectric 38, the first semiconductor plate 40, and the gate semiconductor material portion 49 can contact the shallow trench isolation structure 20. In one embodiment, the top surfaces of the first semiconductor plate 40 and the gate semiconductor material portion 49 can lie in the same horizontal plane as the top surface of the shallow trench isolation structure 20.

[0073] Referring to FIG. 4A and FIG. 4B The second isolation dielectric layer 50L and the second semiconductor material layer 60L can be deposited over the first semiconductor plate 40 and the gate semiconductor material portion 49 as continuous material layers. The second isolation dielectric layer 50L can include any dielectric material that can function as a node dielectric for a capacitor (i.e., as a capacitor dielectric). In one embodiment, the second isolation dielectric layer 50L includes silicon oxide, silicon nitride, and / or a dielectric metal oxide. In one embodiment, the second isolation dielectric layer 50L can include a dielectric metal oxide having a dielectric constant greater than 7.9. Generally, the higher the dielectric constant of the second isolation dielectric layer 50L, the greater the capacitance of the second electrode including the first semiconductor plate 40 and the third electrode subsequently formed by patterning the second semiconductor material layer 60L. The thickness of the second isolation dielectric layer 50L can be in a range from 1 nm to 20 nm, such as from 2 nm to 12 nm and / or from 4 nm to 10 nm, although lesser and greater thicknesses can also be employed. The second isolation dielectric layer 50L can or can not include the same material as the first node dielectric 40. The second isolation dielectric layer 50L can or can not have the same thickness as the first node dielectric 40.

[0074] A second semiconductor material layer 60L can be deposited over the first isolation dielectric layer 50L and directly on the second isolation dielectric layer. The second semiconductor material layer 60L can include a doped semiconductor material having a first conductivity type or a second conductivity type. In one embodiment, the second semiconductor material layer 60L can include amorphous silicon, polysilicon, or a silicon-germanium alloy. In one embodiment, the second semiconductor material layer 60L can be electrically conductive. The second semiconductor material layer 60L can be deposited using chemical vapor deposition. The second semiconductor material layer 60L can be doped with electrical dopants in situ during deposition of the second semiconductor material layer 60L, or can be doped ex situ by performing a low-energy ion implantation process after deposition of the intrinsic semiconductor material. The thickness of the second semiconductor material layer 60L can be in a range from 5 nm to 50 nm, such as from 10 nm to 20 nm, although lesser and greater thicknesses can also be employed.

[0075] Referring to FIG. 5A and FIG. 5B A photoresist layer 67 can be applied over the second semiconductor material layer 60L and can be lithographically patterned to cover a central portion of the area of the first substrate semiconductor portion 10C in top view (i.e., plan view). The perimeter of the patterned portion of the photoresist layer 67 can be laterally offset inward from the perimeter of the top surface of the first substrate semiconductor portion 10C. At least one etching process can be performed to remove unmasked portions of the second semiconductor material layer 60L and the second isolation dielectric layer 50L. In one embodiment, the at least one etching process can include a first etching process that etches unmasked portions of the second semiconductor material layer 60L selectively to a material of the second isolation dielectric layer 50L, and a second etching process that etches unmasked portions of the second isolation dielectric layer 50L selectively to a material of the first semiconductor plate 40. As used herein, removal of a first material is “selective to” a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the “selectivity” of the first material with respect to the removal process of the second material.

[0076] The first etching process and / or the second etching process can include at least one anisotropic etching process (such as a reactive ion etching process) or an isotropic etching process (such as a wet etching process). For example, a wet etching process employing hot trimethyl-2-hydroxyethylammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH) can be performed to remove unmasked portions of the second semiconductor material layer 60L during the first etching process, and a wet etching process employing an etchant that etches the dielectric material of the second isolation dielectric layer 50L can be used to remove unmasked portions of the second isolation dielectric layer 50L. The remaining patterned portions of the second semiconductor material layer 60L include a semiconductor sheet 60S, and the remaining patterned portions of the second isolation dielectric layer 50L include a second node dielectric 50. The second stack of the second node dielectric 50 and the semiconductor sheet 60S can be formed over the first stack of the first node dielectric 30 and the first semiconductor plate 40. A perimeter of a bottom surface of the semiconductor sheet 60S can coincide with a perimeter of a top surface of the second node dielectric 50. Sidewalls of the second node dielectric 50 and the semiconductor sheet 60S can vertically coincide.

[0077] Referring to FIG. 6A and FIG. 6B A metal material layer 70L and a dielectric cap layer 80L can be deposited over the second stack of the second node dielectric 50 and the semiconductor sheet 60S, the gate semiconductor material portions 49, and the shallow trench isolation structures 20. The metal material layer 70L includes a metal material, such as a transition metal, an intermetallic alloy of at least two transition metals, a conductive nitride of at least one transition metal, a silicide of at least one transition metal, or a combination, stack, or alloy thereof. The metal material can or can not include a metal element that forms a metal silicide with the semiconductor material of the gate semiconductor material portions 49. For example, at least one metal element within the metal material layer 70L can include Al, Ti, Co, W, Ta, Ni, Mo, or a conductive nitride or silicide thereof. The metal material layer 70L can be deposited by chemical vapor deposition or physical vapor deposition. The thickness of the metal material layer 70L can be in a range of 10 nm to 100 nm, although lesser and greater thicknesses can also be employed.

[0078] The dielectric cap layer 80L includes a dielectric capping material that is resistant to diffusion of metal ions and impurity ions. For example, the dielectric cap layer 80L can include silicon nitride. The dielectric cap layer 80L can be deposited by, for example, chemical vapor deposition. The thickness of the dielectric cap layer 80L can be in a range of 10 nm to 60 nm, although lesser and greater thicknesses can also be employed.

[0079] Referring to FIG. 7A and FIG. 7BA photoresist layer (not shown) can be applied over the dielectric cap layer 80L and can be photopatterned to cover the areas over a portion of the first substrate semiconductor portion 10C and the gate regions of the transistors subsequently formed over the second substrate semiconductor portion 10T. In one embodiment, the area of the patterned portion of the photoresist layer over the first substrate semiconductor portion can include the entire area of the second node dielectric 50 and the second stack of semiconductor sheet 60S. In one embodiment, the perimeter of the patterned portion of the photoresist layer over the first substrate semiconductor portion 10C can be laterally offset outward from the sidewalls of the second stack of the second node dielectric 50 and the semiconductor sheet 60S by a finite lateral spacing, which can be in the range of 10 nm to 200 nm, although smaller and larger spacings can also be employed. In one embodiment, the perimeter of the patterned portion of the photoresist layer over the first substrate semiconductor portion 10C can be laterally offset inward from the closed perimeter of the portions of the shallow trench isolation structure 20 laterally surrounding and contacting the first substrate semiconductor portion 10C. The lateral offset distance can be in the range of 10 nm to 200 nm, although smaller and larger spacings can also be employed. Each patterned portion of the photoresist layer over a respective one of the second substrate semiconductor portions 10T can laterally traverse a central portion of the respective one of the second substrate semiconductor portions 10T. The width of each patterned portion of the photoresist layer can correspond to the gate length of the respective field effect transistor subsequently formed.

[0080] An anisotropic etching process can be performed to transfer the pattern in the photoresist layer through each of the dielectric cap layer 80L, the metal material layer 70L, the first semiconductor plate 40, and the gate semiconductor material portion 49 by performing an anisotropic etching process. The anisotropic etching process can include a non-selective reactive ion etching process that etches the materials of the dielectric cap layer 80L, the metal material layer 70L, and the materials of the first semiconductor plate 40 and the gate semiconductor material portion 49. The etching process can stop on the materials of the first node dielectric 30 and the gate dielectric 38.

[0081] The patterned portions of the dielectric cap layer 80L include a dielectric cap sheet 80S formed over the first substrate semiconductor portion 10C and a dielectric gate cap 88 formed across a respective one of the second substrate semiconductor portions 10T. The patterned portions of the metal material layer 70L include a metal sheet 70S formed over the first substrate semiconductor portion 10C and a metal gate electrode 78 formed across a respective one of the second substrate semiconductor portions 10T. The peripheral portions of the first semiconductor plate 40 are trimmed by an anisotropic etching process. The second stack of the second node dielectric 50 and the semiconductor sheet 60S is encapsulated by the metal sheet 70S and the first semiconductor plate 40, and is preferably not etched by the anisotropic etching process. Each patterned portion of the gate semiconductor material portion 49 includes a semiconductor gate electrode 48. The first node dielectric 30 and the gate dielectric 38 can act as etch stop structures for the anisotropic etching process. The first node dielectric 30 can cover the entire top surface of the first substrate semiconductor portion 10C, and the gate dielectric 38 can cover the entire top surface of a respective one of the second substrate semiconductor portions 10T.

[0082] The sidewalls of the dielectric cap sheet 80S, the metal sheet 70S, and the first semiconductor plate 40 can be vertically coincident with one another. Each combination of the semiconductor gate electrode 48 and the metal gate electrode 78 constitutes a composite gate electrode (48, 78). The sidewalls of each successive group of the semiconductor gate electrode 48, the metal gate electrode 78, and the dielectric gate cap 88 can be vertically coincident with one another. Each successive combination of the semiconductor gate electrode 48, the metal gate electrode 78, and the dielectric gate cap 88 constitutes a gate stack (38, 78, 88).

[0083] Electrical dopants can be implanted into regions of the second substrate semiconductor portions 10T that are not masked by the gate stacks (38, 78, 88) to form source and drain extension regions (7, 9). The source and drain extension regions (7, 9) can include a source extension region 7 formed on one side of a respective composite gate electrode (48, 78), and a drain extension region 9 formed on the other side of the respective composite gate electrode (48, 78). In one embodiment, if CMOS transistors are to be formed, a masking ion implantation process can be employed to form a first subset of source and drain extension regions (7, 9) having p-type doping, and to form a second subset of source and drain extension regions (7, 9) having n-type doping. A mask can optionally cover the first substrate semiconductor portion 10C to avoid implanting the capacitor region of the substrate.

[0084] Reference is made to FIG. 8A and FIG. 8BThe dielectric material layer can be conformally deposited over the first exemplary structure and can be anisotropically etched using sidewall spacer etching to remove horizontally extending portions of the dielectric material layer. The dielectric material layer includes at least one dielectric material, such as silicon nitride and / or silicon oxide. In one embodiment, the dielectric material layer can include a layer stack of a silicon nitride layer and a silicon oxide layer. Each remaining portion of the dielectric material layer includes a vertical portion laterally surrounding a sidewall of the respective layer stack. For example, the dielectric capacitor spacer 52 can laterally surround a layer stack including the first semiconductor plate 40, the second node dielectric 50, the semiconductor sheet 60S, the metal sheet 70S, and the dielectric cap sheet 80S. The dielectric capacitor spacer 52 can contact sidewalls of the first semiconductor plate 40, the metal sheet 70S, and the dielectric cap sheet 80S, and can be laterally spaced apart from the second node dielectric 50 and the semiconductor sheet 60S. The dielectric gate spacer (i.e., sidewall spacer) 58 can laterally surround, and can contact, a sidewall of a gate stack including the semiconductor gate electrode 48, the metal gate electrode 78, and the dielectric gate cap 88. A lateral thickness of the dielectric capacitor spacer 52 and each dielectric gate spacer 58 can be in a range of 15 nm to 120 nm, such as 30 nm to 60 nm, although smaller and larger lateral thicknesses can also be employed.

[0085] The anisotropic etching process that removes the horizontal portions of the dielectric material layer laterally etches portions of the first node dielectric 30 and the gate dielectric 38 that are not masked by the dielectric capacitor spacer 52 or the dielectric gate spacer 58. Accordingly, a sidewall of the remaining portion of the first node dielectric 30 can be vertically coincident with a bottom periphery of the outer sidewall of the dielectric capacitor spacer 52. The dielectric capacitor spacer 52 laterally surrounds and contacts the first semiconductor plate 40, which serves as a second electrode of the capacitor structure. A sidewall of each remaining portion of the gate dielectric 38 can be vertically coincident with a bottom periphery of the outer sidewall of the respective overlying dielectric gate spacer 58. Further, a bottom surface of the dielectric capacitor spacer 52 contacts a top surface of the first node dielectric 30 at a peripheral portion. In one embodiment, a top edge of each sidewall of the first node dielectric 30 can be coincident with the bottom periphery of the outer sidewall of the dielectric capacitor spacer 52. The dielectric capacitor spacer 52 laterally surrounds and contacts sidewalls of the metal sheet 70S and the dielectric cap sheet 80S.

[0086] An electrical dopant can be implanted into regions of the second substrate semiconductor portion 10T not masked by the gate stack (38, 78, 88) or the dielectric gate spacer 58 to form source and drain regions (17, 19). The source and drain regions (17, 19) can include a source region 17 formed on one side of a respective composite gate electrode (48, 78), and a drain region 19 formed on the other side of the respective composite gate electrode (48, 78). In one embodiment, if CMOS transistors are to be formed, a masking ion implantation process can be employed to form a first subset of source and drain regions (17, 19) having p-type doping, and to form a second subset of source and drain regions (17, 19) having n-type doping. Implanted portions of the source and drain extension regions (7, 9) can be incorporated into a respective one of the source and drain regions (17, 19). Field effect transistors are formed in regions including or overlying the second substrate semiconductor portion 10T. A mask can optionally cover the first substrate semiconductor portion 10C to avoid implanting the capacitor region of the substrate.

[0087] A field effect transistor can be formed on the second substrate semiconductor portion 10T of the substrate semiconductor layer 10. Each field effect transistor can include a gate dielectric 38 and a semiconductor gate electrode 48, which is a patterned portion of the gate semiconductor material portion 49. Each gate dielectric 38 includes the same material as the first node dielectric 30 and has the same thickness as that first node dielectric. In one embodiment, one or more of the semiconductor gate electrodes 48 can include the same material as the first semiconductor plate 40 and have the same thickness as that first semiconductor plate. In one embodiment, each field effect transistor can include a metal gate electrode 78 that includes the same material as the metal sheet 70S and has the same thickness as that metal sheet.

[0088] Reference is made to FIG. 9A and FIG. 9BA photoresist layer 177 can be applied over the first exemplary structure and can be lithographically patterned to form a moat-shaped opening within the area of the metal sheet 70S. A moat-shaped opening refers to an opening having an inner periphery and an outer periphery that is laterally offset outward from the inner periphery and does not contact the inner periphery. In one embodiment, the outer periphery of the moat-shaped opening can be laterally recessed inward from the sidewalls of the metal sheet 70S in a plan view (i.e., top view). In one embodiment, the outer periphery of the moat-shaped opening in the photoresist layer can be uniformly offset inward from the sidewalls of the metal sheet 70S by a uniform lateral offset distance, which can be in a range of 20 nm to 200 nm, such as 40 nm to 100 nm, although smaller and larger lateral offset distances can also be employed. The inner periphery of the moat-shaped opening can be laterally offset inward from the outer periphery of the moat-shaped opening by a width of the moat-shaped opening. The width of the moat-shaped opening can be in a range of 20 nm to 200 nm, such as 40 nm to 100 nm, although smaller and larger widths can also be employed. In one embodiment, the width of the moat-shaped opening can be uniform by the moat-shaped opening being uniform. The shape of the moat-shaped opening can be the shape of a rectangular frame or any other polygonal frame, the shape of a ring, or any two-dimensional shape that includes a hole therein.

[0089] An anisotropic etching process can be performed to remove portions of the dielectric cap sheet 80S, the metal sheet 70S, and the semiconductor sheet 60S that are not masked by the photoresist layer 177. The second node dielectric 50 can serve as a stop structure for the anisotropic etching process. For example, the anisotropic etching process can include a selective etching step that includes a first anisotropic etching step that selectively etches a material of the dielectric cap sheet 80S with respect to a material of the metal sheet 70S, a second anisotropic etching step that selectively etches the material of the metal sheet 70S with respect to a material of the semiconductor sheet 60S, and a third anisotropic etching step that selectively etches the semiconductor material of the semiconductor sheet 60S with respect to a material of the second node dielectric 50. The moat trench 79 is formed by the anisotropic etching process in a volume of the materials of the dielectric cap sheet 80S, the metal sheet 70S, and the semiconductor sheet 60S that is etched therefrom.

[0090] Due to the relatively thin semiconductor sheet 60S and the second node dielectric 50, a separate selective etching step can be used to etch the moat trench 79 that is different from the selective etching step used to form the FIG. 7A and FIG. 7BThe composite gate electrode (48, 78) and the stack of the first semiconductor sheet 40, the dielectric cap sheet 80S, and the metal sheet 70S are shown. This reduces the chance that the moat trench 79 etch step will punch through the second node dielectric 50 and cause a short in the capacitor region. In addition, the moat trench 79 is preferably entirely within the area of the first semiconductor sheet 40, the dielectric cap sheet 80S, and the metal sheet 70S. In this case, during the etch step shown FIG. 7A and FIG. 7B and FIG. 9A and FIG. 9B During the etch step shown, no portion of the first semiconductor sheet 40, the dielectric cap sheet 80S, and the metal sheet 70S is etched twice. This reduces the likelihood of etch-induced defects that can occur in regions etched twice during separate etch steps.

[0091] Each of the dielectric cap sheet 80S, the metal sheet 70S, and the semiconductor sheet 60S is divided into an inner material portion and an outer material portion by the anisotropic etching process. Specifically, the dielectric cap sheet 80S is divided into a main dielectric cap 80 located inside the moat trench 79 and a peripheral dielectric cap 82 located outside the moat trench 79. Each metal sheet 70S is divided into a main metal sheet 70 located inside the moat trench 79 and a peripheral metal sheet 72 located outside the moat trench 79. The semiconductor sheet 60S is divided into a main semiconductor sheet 60 located inside the moat trench 79 and a peripheral semiconductor sheet 62 located outside the moat trench 79.

[0092] Generally, after the dielectric capacitor spacer 52 and the dielectric gate spacer 58 are formed, the combination of the dielectric cap sheet 80S, the metal sheet 70S, and the semiconductor sheet 60S is divided by the moat trench 79 into an inner layer stack (60, 70, 80) and a peripheral stack 201. The moat trench 79 is laterally surrounded by the inner layer stack (60, 70, 80) and is laterally surrounded by the peripheral stack 201. The sidewalls of the inner layer stack (60, 70, 80) and the sidewalls of the peripheral stack 201 are physically exposed to the moat trench 79.

[0093] The inner layer stack (60, 70, 80) includes the main semiconductor sheet 60, the main metal sheet 70, and the main dielectric cap 80. The peripheral stack 201 includes the peripheral semiconductor sheet 62, the peripheral metal sheet 72, and the peripheral dielectric cap 82. The main semiconductor sheet 60 and the peripheral semiconductor sheet 62 are patterned portions of the semiconductor sheet 60S. The main metal sheet 70 and the peripheral metal sheet 72 are patterned portions of the metal sheet 70S. The main dielectric cap 80 and the peripheral dielectric cap 82 are patterned portions of the dielectric cap sheet 80S.

[0094] A dual capacitor structure is formed over the first substrate semiconductor portion 10C. The first substrate semiconductor portion 10C serves as a first electrode of the capacitor structure, the first semiconductor plate 40 serves as a second electrode of the capacitor structure, and the main semiconductor plate 60 serves as part of a third electrode of the capacitor structure. The first node dielectric 30 is between and contacts each of the first substrate semiconductor portion 10C and the first semiconductor plate 40. The second node dielectric 50 can be on a top surface of the first semiconductor plate 40 and can contact a bottom surface of the main semiconductor plate 60, which is a second semiconductor plate that serves as part of the third electrode of the capacitor structure. The third electrode can include a stack of the main semiconductor plate 60 and the main metal plate 70.

[0095] In one embodiment, the first electrode of the first substrate semiconductor portion 10C and the third electrode of the main semiconductor plate 60 can be electrically connected to each other to provide a two-terminal capacitor structure. Alternatively, the first, second, and third electrodes can be connected to different nodes of other semiconductor devices, such as field effect transistors formed over the second substrate semiconductor portion 10T, to provide a series connection of two capacitors. The first capacitor includes the first node (i.e., capacitor) dielectric 30 between the first electrode including the first substrate semiconductor portion 10C and the second electrode including the first semiconductor plate 40. The second capacitor includes the second node (i.e., capacitor) dielectric 50 between the second electrode including the first semiconductor plate 40 and the third electrode (60, 70) including the main semiconductor plate 60 and the main metal plate 70. Thus, the first semiconductor plate 40 acts as an electrode for both capacitors.

[0096] The peripheral stack 201 provides electrical contact to the second electrode including the first semiconductor plate 40. In particular, the peripheral stack 201 includes a peripheral semiconductor plate 62, a peripheral metal plate 72, and a peripheral dielectric cap 82. The peripheral semiconductor plate 62 contacts a peripheral portion of a top surface of the second node dielectric 50, includes the same material as the main semiconductor plate 60, and is laterally spaced apart from the main semiconductor plate 60 by a moat trench 79. The photoresist layer 177 can then be removed, e.g., by ashing.

[0097] Reference is made to FIG. 10A and FIG. 10BAt least one contact level dielectric material can be deposited over the interior layer stack (60, 70, 80), the peripheral stack 201, and the field effect transistor to form at least one contact level dielectric layer 90. Thus, the at least one contact level dielectric layer 90 can laterally extend over the third electrode (60, 70) and the peripheral stack 201 and include a downward protruding portion that fills the moat trench 79 and contacts the second node dielectric 50. In one embodiment, the at least one contact level dielectric layer 90 can include an optional dielectric liner 90A and a planarization dielectric layer 90B that includes a planarizable dielectric material. For example, the dielectric liner 90A can include a dielectric diffusion barrier material such as silicon nitride and the planarization dielectric layer 90B can include an undoped silicate glass or a doped silicate glass. The thickness of the dielectric liner 90A can be in a range from 4 nm to 20 nm, although lesser and greater thicknesses can also be employed.

[0098] The downward protruding portion of the at least one contact level dielectric layer fills the moat trench 79. Generally, the peripheral stack 201 includes an opening defined by an inner wall (which can be an outer sidewall of the moat trench 79) and laterally surrounds the third electrode (60, 70) and is laterally spaced apart from the third electrode (60, 70). In one embodiment, each outer sidewall of the peripheral stack 201 can be vertically coincident with a respective sidewall of the second electrode that includes the first semiconductor plate 40. The downward protruding portion of the at least one contact level dielectric layer 90 can be formed directly on a surface of the second node dielectric 50, which can be a top surface or a recessed horizontal surface of the second node dielectric 50. The downward protruding portion of the at least one contact level dielectric layer 90 can be formed directly on sidewalls of the layer stack (60, 70, 80) and sidewalls of the peripheral stack 201. The downward protruding portion of the at least one contact level dielectric layer 90 can be in contact with a top surface of the second node dielectric 50 and can be vertically spaced apart from the second electrode that includes the first semiconductor plate 40 by the second node dielectric 50.

[0099] Referring to FIG. 11A and FIG. 11BUsing photolithography and etching, contact vias are etched through at least one contact-level dielectric layer 90 and a second node dielectric 50. The contact vias are then filled with conductive contact via structures (92, 94, 96, 97, 98, 99). The contact via structures extend through at least one contact-level dielectric layer 90 to contact the corresponding node of a capacitor structure or field-effect transistor. The contact via structures (92, 94, 96, 97, 98, 99) may include a first contact via structure 92 contacting a first electrode including a first substrate semiconductor portion 10C, a second contact via structure 94 contacting a peripheral metal plate 72 electrically connected to a second electrode including a first semiconductor plate 40, and a third contact via structure 96 contacting a main metal plate 70 as part of a third electrode (60, 70). Although each of the three capacitor contact via structures (92, 94, 96) has three... FIG. 11A As shown, but only one, two, or four or more of each of the capacitor contact via structures (92, 94, 96) may exist. Furthermore, if three or more of each type of capacitor contact via structure (92, 94, 96) are present, each type of capacitor contact via structure may be arranged in rows extending along a first horizontal direction hd1 and a second horizontal direction hd2, or arranged in a random pattern. Further, the contact via structures (92, 94, 96, 97, 98, 99) may include a source contact via structure 97 contacting the corresponding source region 17, a drain contact via structure 99 contacting the corresponding drain region 19, and a gate contact via structure 98 contacting one of the corresponding composite gate electrodes (48, 78).

[0100] refer to FIG. 12A and FIG. 12B The pattern of the photoresist layer 67 can be changed to achieve the desired effect. FIG. 5A and FIG. 5B The first exemplary structure shown derives alternative configurations of the first exemplary structure. Specifically, the pattern of the photoresist layer can be modified such that at least one edge of the patterned photoresist layer 67 lies above the top surface of the shallow trench isolation structure 20. Furthermore, the photoresist layer includes an opening (e.g., a slit) 67A above the shallow trench isolation structure 20. [Executable] FIG. 5A and FIG. 5BThe etching process is used to pattern the second isolation dielectric layer 50L and the second semiconductor material layer 60L into a second stack of the second node dielectric 50 and the semiconductor wafer 60S. The second stack of the second node dielectric 50 and the semiconductor wafer 60S has a periphery that covers and contacts a portion of the shallow trench isolation structure 20. In one embodiment, a first segment of the periphery of the second stack of the second node dielectric 50 and the semiconductor wafer 60S may cover and contact a portion of the shallow trench isolation structure 20, and a second segment of the periphery of the second stack of the second stack of the second node dielectric 50 and the semiconductor wafer 60S may contact the top surface of the first semiconductor plate 40. In another embodiment, the entire periphery of the second stack of the second node dielectric 50 and the semiconductor wafer 60S may cover and contact a portion of the shallow trench isolation structure 20. The periphery of the second stack of the second node dielectric 50 and the semiconductor wafer 60S above a portion of the shallow trench isolation structure 20 includes an opening (e.g., a slit) 560. Typically, the shallow trench isolation structure laterally surrounds the first substrate semiconductor portion 10C. A portion of the second node dielectric 50 and a portion of the semiconductor sheet 60S may be overlaid and may contact the top surface of the shallow trench isolation structure 20.

[0101] refer to FIG. 13A and FIG. 13B Executable FIGS. 6A-9B The processing steps are to form a field-effect transistor and to form an inner layer stack (60, 70, 80) and a peripheral stack 201. The trench 79 preferably has an area overlapping with the shallow trench isolation structure 20. The main metal plate 70 and the main dielectric cap 80 fill the opening 560 to leave a groove 80G in the top of the main dielectric cap 80. The top of the main metal plate 70 is recessed below the groove 80G.

[0102] refer to FIG. 14A and FIG. 14B Executable FIGS. 10A-11Bprocessing steps to form at least one contact level dielectric layer 90 and various contact via structures (94, 96, 97, 98, 99). A portion of the second node dielectric 50 and a portion of the peripheral stack 201 overlie and contact a top surface of the shallow trench isolation structure 20. In one embodiment, a subset of the contact via structures, such as the third contact via structure 96, can be formed over and within the area of the shallow trench isolation structure 20. Further, the first contact via structure 92 can be optionally omitted in this embodiment. Further, the main semiconductor plate 60 and the second node dielectric 50 are removed in the opening 560 location underneath the third contact via structure 96. In this case, the main metal plate 70 extends downward through the opening 560 from which the main semiconductor plate 60 and the second node dielectric 50 are removed, and contacts the shallow trench isolation structure 20. The third contact via structure 96 is formed through the main dielectric cap 80 in the location of the recess 80G and the opening 560. In this alternative embodiment, the heights (i.e., depths) of all of the contact via structures (94, 96, 98) are similar. For example, the bottoms of the contact via structures (94, 96, 98) are located in the plate P-P' and their tops are coplanar with the top of the dielectric layer 90. This improves process margins during etching of the contact vias because the contact vias have similar heights (i.e., depths) and are simultaneously entered during deposition of the contact via structures (94, 96, 98) with similar heights (i.e., depths).

[0103] Reference FIGS. 1A-14B And according to various embodiments of the present disclosure, a semiconductor structure is provided that includes a capacitor structure located on a semiconductor substrate that includes a substrate semiconductor layer 10. The capacitor structure includes: a first electrode that includes a first substrate semiconductor portion 10C of the substrate semiconductor layer 10; a first node dielectric 30 located on a top surface of the first substrate semiconductor portion 10C of the substrate semiconductor layer 10; a second electrode that includes a first semiconductor plate 40 and is located on a top surface of the first node dielectric 30; a second node dielectric 50 located on a top surface of the first semiconductor plate 40; a third electrode (60, 70) that includes a stack of a main semiconductor plate 60 and a main metal plate 70; a moat trench 79 laterally surrounding the third electrode (60, 70); a peripheral stack 201 laterally surrounding the third electrode (60, 70), wherein the peripheral stack 201 includes a peripheral stack 201 that includes a peripheral semiconductor plate 62 and a peripheral metal plate 72, and wherein the peripheral semiconductor plate 62 contacts a peripheral portion of a top surface of the second node dielectric 50, includes the same material as the main semiconductor plate 60, and is laterally spaced apart from the main semiconductor plate 60; and at least one contact level dielectric layer 90 laterally extending over the third electrode (60, 70) and the peripheral stack 201.

[0104] In one embodiment, the at least one contact-level dielectric layer 90 includes a downward protruding portion that fills the moat trench 79 and contacts the second node dielectric 50 exposed in the moat trench 79. The downward protruding portion of the at least one contact-level dielectric layer 90 is vertically spaced apart from the second electrode by the second node dielectric 50. In one embodiment, each outer sidewall of the peripheral stack 201 vertically coincides with a respective sidewall of the second electrode.

[0105] In one embodiment, the dielectric capacitor spacer 52 laterally surrounds and contacts the second electrode (embodied as the first semiconductor plate 40) and the peripheral stack 201, and contacts a peripheral portion of the top surface of the first node dielectric 30. In one embodiment, a top edge of a sidewall of the first node dielectric 40 coincides with a bottom periphery of an outer sidewall of the dielectric capacitor spacer 52.

[0106] In one embodiment, the peripheral metal plate 72 includes the same metal material as the main metal plate 70; and the peripheral stack 201 includes a peripheral dielectric cap 82 that contacts a top surface of the peripheral metal plate 72.

[0107] In one embodiment, the shallow trench isolation structure 20 laterally surrounds the first substrate semiconductor portion 10C. An entire bottom periphery of the first node dielectric 30 can be in contact with a top surface of the substrate semiconductor portion 10C, and can be laterally offset inward from an inner periphery of a portion of the shallow trench isolation structure 20 that laterally surrounds the first substrate semiconductor portion 10C.

[0108] In one embodiment, the shallow trench isolation structure 20 laterally surrounds the first substrate semiconductor portion 10C. A portion of the second node dielectric 50 and a portion of the peripheral stack 201 overlie and contact a top surface of the shallow trench isolation structure 20.

[0109] In one embodiment, the semiconductor structure includes a field effect transistor located on the second substrate semiconductor portion 10T of the substrate semiconductor layer 10 and including a gate dielectric 38 that includes the same material as the first node dielectric 30 and has the same thickness as the first node dielectric. In one embodiment, the field effect transistor includes: a semiconductor gate electrode 48 that includes the same material as the first semiconductor plate 40 and has the same thickness as the first semiconductor plate; and a metal gate electrode 78 that includes the same material as each of the main metal plate 70 and the peripheral metal plate 72 and has the same thickness as each of the main metal plate and the peripheral metal plate.

[0110] In one embodiment, the semiconductor structure further includes: a first contact via structure 92 extending through the at least one contact level dielectric layer 90 and electrically contacting the first electrode 10C; a second contact via structure 94 extending through the at least one contact level dielectric layer 90 and contacting the second electrode 40 through the peripheral metal plate 72; and a third contact via structure 96 extending through the at least one contact level dielectric layer 90 and contacting the third electrode (60, 70).

[0111] In one embodiment, the first electrode 10C, the first node dielectric 30, and the second electrode 40 form a first capacitor, while the second electrode 40, the second node dielectric 50, and the third electrode (60, 70) form a second capacitor.

[0112] Reference is made to FIG. 15A and FIG. 15B , which show a third exemplary structure according to a second embodiment of the present disclosure. By forming a first isolation dielectric layer 30L and a first semiconductor material layer 140L over the substrate semiconductor layer 10, the second exemplary structure can be derived from the first exemplary structure of FIG. 1A and FIG. 1B . The first semiconductor material layer 140L includes a semiconductor material having a suitable resistivity (i.e., inverse of resistivity) for use as a resistor element. For example, the electrical conductivity of the first semiconductor material layer 140L can be in the range of 1.0 x 10 -6 S / cm to 1.0 x 10 3 S / cm, which corresponds to a resistivity range of 1.0 x 10 -3 Ohm-cm to 1.0 x 10 6 Ohm-cm. The resistivity of the semiconductor material in the first semiconductor material layer 140L can be controlled by selecting a substrate semiconductor material (such as polysilicon or a silicon-germanium alloy) for the first semiconductor material layer 140L, and by doping the first semiconductor material layer 140L with electrical dopants at a suitable atomic concentration, which may, for example, be in the range of 1.0 x 10 12 / cm 3 to 1.0 x 10 19 / cm 3The first semiconductor material layer 140L can have a thickness in the range of 20 nm to 200 nm, such as 60 nm to 100 nm, although smaller and larger atomic concentrations can also be employed. The first semiconductor material layer 140L can have a thickness in the range of 20 nm to 200 nm, such as 60 nm to 100 nm, although smaller and larger thicknesses can also be employed. Different portions of the first semiconductor material layer 140L can be doped differently. For example, portions of the first semiconductor material layer 140L that are to be used as semiconductor gate electrodes can be doped with a higher dopant concentration than portions of the first semiconductor material layer 140L that are to be used as resistor elements. Furthermore, portions of the first semiconductor material layer 140L that are to be used as resistor elements can have a different dopant concentration than other portions, depending on the target value of the resistivity of the respective resistor element.

[0113] The substrate semiconductor layer 10 comprises first substrate semiconductor portions 10R located in a first device area in which the resistor structures are subsequently formed and second substrate semiconductor portions 10T located in a second device area in which field effect transistors are subsequently formed. Each first substrate semiconductor portion 10R on which a respective resistor element is subsequently formed can have a linear shape that can provide a high aspect ratio, a serpentine shape, or any straight, curved, or compound shape.

[0114] In one embodiment, the first semiconductor material layer 140L can be formed as an intrinsic semiconductor material layer or a layer with a low level of electrical doping. In this case, the first exemplary structure can be formed simultaneously with the formation of the second exemplary structure by providing a suitable doping to a portion of the first semiconductor material layer 140L and using such doped portion as the first semiconductor material layer 40L of the first exemplary structure.

[0115] With reference to FIG. 16A and FIG. 16B The first semiconductor material layer 140L and the first isolation dielectric layer 30L can be patterned, e.g., by applying and patterning a photoresist layer, to form discrete patterned photoresist material portions over each area of the first substrate semiconductor portions 10R and additional patterned photoresist material portions over each area of the second substrate semiconductor portions 10T. An anisotropic etching process can be performed to etch unmasked portions of the first semiconductor material layer 140L, the first isolation dielectric layer 30L, and the upper portion of the substrate semiconductor layer 10. Shallow isolation trenches 11 are formed that laterally surround the patterned portions of the first semiconductor material layer 140L, the first isolation dielectric layer 30L, and the upper portion of the substrate semiconductor layer 10. The shallow isolation trenches 11 can be interconnected to each other as a single continuous volume. The photoresist layer can be subsequently removed, e.g., by ashing. The bottom boundaries of the first substrate semiconductor portions 10R and the second substrate semiconductor portions 10T can lie in a horizontal plane that includes the bottom surfaces of the shallow isolation trenches 11.

[0116] The patterned portions of the substrate semiconductor layer 10 include first substrate semiconductor portions 10R and second substrate semiconductor portions 10T. In other words, the pattern in the patterned photoresist layer can be selected such that the remaining portions of the substrate semiconductor layer 10 include the first substrate semiconductor portions 10R and the second substrate semiconductor portions 10T. In one embodiment, the first substrate semiconductor portions 10R and the second substrate semiconductor portions 10T can optionally include vertically tapered and horizontally straight sidewalls that extend laterally along a horizontal direction. For example, the first substrate semiconductor portions 10R and the second substrate semiconductor portions 10T can include a respective pair of sidewalls that extend laterally along a first horizontal direction hd1 and a respective pair of sidewalls that extend laterally along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. In general, the first substrate semiconductor portions 10R can have any horizontal cross-sectional shape that can provide a high aspect ratio. The first substrate semiconductor portions 10R can have the shape of a rectangular strip, a serpentine strip, or any strip that can extend laterally (with or without variations) in the propagation direction. The aspect ratio of each first substrate semiconductor portion 10R can be in the range of 2 to 1,000, although smaller and larger aspect ratios can also be employed. The second substrate semiconductor portions 10T can have a rectangular horizontal cross-sectional shape that facilitates the formation of field effect transistors thereon.

[0117] The patterned portions of the first isolation dielectric layer 30L include first resistor isolation dielectrics 130 formed on top surfaces of respective first substrate semiconductor portions 10R, and gate dielectrics 38 formed on respective ones of the second substrate semiconductor portions 10T. The patterned portions of the first semiconductor material layer 140L include semiconductor material strips 140 and gate semiconductor material portions 49. The semiconductor material strips 140 can be formed on top surfaces of respective first resistor isolation dielectrics 130. The gate semiconductor material portions 49 can be formed on top surfaces of respective ones of the gate dielectrics 38. Portions of the semiconductor material strips 140 can function as resistor elements of the resistor structures of the second embodiment of the present disclosure. Accordingly, a first stack of the first resistor isolation dielectrics 130 and the semiconductor material strips 140 can be formed on each first substrate semiconductor portion 10R. A perimeter of a bottom surface of the semiconductor material strips 140 can coincide with a perimeter of a top surface of the underlying first resistor isolation dielectric 130. Sidewalls of the semiconductor material strips 140 and the first resistor isolation dielectrics 130 can vertically coincide.

[0118] Reference is made to FIG. 17A and FIG. 17BAt least one dielectric material can be deposited in the shallow isolation trench 11. The at least one dielectric material can include an optional diffusion barrier liner material, such as a silicon nitride liner material, and a planarizable dielectric fill material, such as an undoped silicate glass or a doped silicate glass. The at least one dielectric material can fill the entire volume of the shallow isolation trench 11. By a planarization process, excess portions of the at least one dielectric material can be removed from above the horizontal plane that includes the top surfaces of the semiconductor material strip 140 and the gate semiconductor material portion 49. For example, a chemical mechanical planarization process can be employed to remove excess portions of the at least one dielectric material from above the horizontal plane that includes the top surfaces of the semiconductor material strip 140 and the gate semiconductor material portion 49. The remaining portions of the at least one dielectric material that fill the volume of the shallow isolation trench 11 constitute a shallow trench isolation (STI) structure 20. The shallow trench isolation structure 20 laterally surrounds the first substrate semiconductor portion 10R and the second substrate semiconductor portion 10T, the first resistor isolation dielectric 130 and the gate dielectric 38, and the semiconductor material strip 140 and the gate semiconductor material portion 49. In one embodiment, each sidewall of the first substrate semiconductor portion 10R, the second substrate semiconductor portion 10T, the first resistor isolation dielectric 130, the gate dielectric 38, the semiconductor material strip 140 and the gate semiconductor material portion 49 can contact the shallow trench isolation structure 20. In one embodiment, the top surfaces of the semiconductor material strip 140 and the gate semiconductor material portion 49 can be located in the same horizontal plane as the top surface of the shallow trench isolation structure 20.

[0119] Referring to FIG. 18A and FIG. 18B The second isolation dielectric layer 50L and the second semiconductor material layer 60L can be deposited over the semiconductor material strip 140 and the gate semiconductor material portion 49 as a continuous layer of material. The second isolation dielectric layer 50L can include any dielectric material that can be used as a resistor isolation dielectric, i.e., any dielectric material that can be used as an electrical isolation material. In one embodiment, the second isolation dielectric layer 50L includes silicon oxide, silicon nitride and / or a dielectric metal oxide. The thickness of the second isolation dielectric layer 50L can be in the range of 1 nm to 20 nm, such as 2 nm to 12 nm and / or 4 nm to 10 nm, although lesser and greater thicknesses can also be employed. The second isolation dielectric layer 50L can or can not include the same material as the first resistor isolation dielectric 130. The second isolation dielectric layer 50L can or can not have the same thickness as the first resistor isolation dielectric 130.

[0120] The second semiconductor material layer 60L can be deposited over the first isolation dielectric layer 50L and directly on the second isolation dielectric layer. The second semiconductor material layer 60L can be the same as the first exemplary structure (e.g., can comprise polysilicon). Alternatively, if the capacitor structure in the first exemplary structure is not fabricated at the same time as the formation of the second exemplary structure, the second semiconductor material layer 60L can comprise any semiconductor material, and can be un-doped, P-doped, or n-doped. In one embodiment, the second semiconductor material layer 60L can be electrically conductive. In another embodiment, the second semiconductor material layer 60L can be semiconductive. The second semiconductor material layer 60L can be deposited using chemical vapor deposition. The second semiconductor material layer 60L can be un-doped, can be doped in situ with electrical dopants during deposition of the second semiconductor material layer 60L, or can be doped non-in situ by performing a low energy ion implantation process after deposition of the intrinsic semiconductor material. The thickness of the second semiconductor material layer 60L can be in a range from 20 nm to 200 nm, such as from 60 nm to 100 nm, although lesser and greater thicknesses can also be employed.

[0121] Referring to FIG. 19A and FIG. 19B A photoresist layer (not shown) can be applied over the second semiconductor material layer 60L, and can be lithographically patterned to cover an area including the entire set of first substrate semiconductor portions 10R that are laterally enclosed within the perimeter of the shallow trench isolation structure 20 in a top view (i.e., plan view). The outer perimeter of the patterned portion of the photoresist layer can be laterally offset outward from the perimeter of the shallow trench isolation structure 20 that laterally surrounds the set of first substrate semiconductor portions 10R. In one embodiment, the entire outer perimeter of the patterned portion of the photoresist layer can be located within the area of the shallow trench isolation structure, such that the outer perimeter of the patterned portion of the photoresist layer does not overlie any of the first substrate semiconductor portions 10R.

[0122] According to aspects of the disclosure, the photoresist layer can be patterned to provide a pair of openings over an end portion of each semiconductor material stripe 140. In other words, one opening in the photoresist layer is formed over a first end portion of each semiconductor material stripe 140, and another opening in the photoresist layer is formed over a second end portion of each semiconductor material stripe 140. The area of the openings in the photoresist layer corresponds to the area in which electrical contacts to the underlying semiconductor material stripe 140 are subsequently formed. In one embodiment, the location of the openings in the photoresist layer can be offset from the end of a respective one of the semiconductor material stripes 140 to increase the nearest neighbor distance between the openings in the photoresist layer and to reduce pattern failure in the photoresist layer during a lithographic patterning process. For example, if the semiconductor material stripes 140 extend laterally along a first horizontal direction hd1 and are spaced apart along a second horizontal direction hd2, the openings in the photoresist layer to adjacent semiconductor material stripes 140 that are offset along the second horizontal direction hd2 can be laterally offset along the first horizontal direction hd1 to increase the distance between the openings of adjacent pairs and to reduce the probability of electrical shorting between subsequently formed contact structures.

[0123] At least one etching process can be performed to remove unmasked portions of the second semiconductor material layer 60L and the second isolation dielectric layer 50L. In one embodiment, the at least one etching process can include a first etching process that is selective to the material of the second semiconductor material layer 60L to etch unmasked portions of the second semiconductor material layer 60L, and a second etching process that is selective to the material of the semiconductor material stripes 140 to etch unmasked portions of the second isolation dielectric layer 50L.

[0124] The first etching process and / or the second etching process can include at least one anisotropic etching process (such as a reactive ion etching process) or an isotropic etching process (such as a wet etching process). For example, a wet etching process employing hot trimethyl-2-hydroxyethylammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH) can be performed to remove unmasked portions of the second semiconductor material layer 60L during the first etching process, and a wet etching process employing an etchant that etches the dielectric material of the second isolation dielectric layer 50L can be used to remove unmasked portions of the second isolation dielectric layer 50L. The remaining patterned portions of the second semiconductor material layer 60L include semiconductor sheets 160, and the remaining patterned portions of the second isolation dielectric layer 50L include second resistor isolation dielectrics 150. The second stack of second resistor isolation dielectrics 150 and semiconductor sheets 160 can be formed over the first stack of first resistor isolation dielectrics 130 and semiconductor material strips 140. A perimeter of a bottom surface of the semiconductor sheets 160 can coincide with a perimeter of a top surface of the second resistor isolation dielectrics 150. Sidewalls of the second stack of second resistor isolation dielectrics 150 and semiconductor sheets 160 can vertically coincide.

[0125] The stack of second resistor isolation dielectrics 150 and semiconductor sheets 160 can be formed on top surfaces of the semiconductor material strips 140. Each top surface of the semiconductor material strips 140 can contact a bottom surface of the second resistor isolation dielectrics 150. A pair of openings 161 in the second stack of second resistor isolation dielectrics 150 and semiconductor sheets 160 can be formed over each semiconductor material strip 140. The top surface of the semiconductor material strips 140 can be physically exposed at a bottom of each opening 161 by the second stack of second resistor isolation dielectrics 150 and semiconductor sheets 160. In one embodiment, if there are N semiconductor material strips 140 on top of the second stack of second resistor isolation dielectrics 150 and semiconductor sheets 160, the total number of openings 161 through the second stack of second resistor isolation dielectrics 150 and semiconductor sheets 160 can be 2N.

[0126] Reference is made to FIG. 20A and FIG. 20BA metal material layer 70L and a dielectric cap layer 80L can be deposited over the second stack of resistor isolation dielectric 150 and semiconductor sheet 160, gate semiconductor material portion 49, and shallow trench isolation structure 20. The metal material layer 70L in the second exemplary structure includes any of the materials that can be used for the metal material layer 70L in the first exemplary structure, and can have the same thickness as in the first exemplary structure. The metal material layer 70L includes a downward protruding portion that extends vertically through the opening 161 in the second stack of resistor isolation dielectric 150 and semiconductor sheet 160 and contacts a top surface of a respective one of the semiconductor material strips 140.

[0127] The dielectric cap layer 80L includes a dielectric capping material that is resistant to diffusion of metal ions and impurity ions. For example, the dielectric cap layer 80L can include silicon nitride. The dielectric cap layer 80L can be deposited by, for example, chemical vapor deposition. The thickness of the dielectric cap layer 80L can be in a range of 10 nm to 60 nm, although lesser and greater thicknesses can also be employed.

[0128] Referring to FIG. 21A and FIG. 21B A photoresist layer (not shown) can be applied over the dielectric cap layer 80L and can be lithographically patterned to cover an area over the second stack of resistor isolation dielectric 150 and semiconductor sheet 160, and each gate region of a transistor subsequently formed over the second substrate semiconductor portion 10T. In one embodiment, the area of the patterned portion of the photoresist layer over the second stack of resistor isolation dielectric 150 and semiconductor sheet 160 can include the entire area of the second stack of resistor isolation dielectric 150 and semiconductor sheet 160. In one embodiment, the perimeter of the patterned portion of the photoresist layer over the second stack of resistor isolation dielectric 150 and semiconductor sheet 160 can be laterally offset outward from the sidewalls of the second stack of resistor isolation dielectric 150 and semiconductor sheet 160 by a finite lateral spacing, which can be in a range of 10 nm to 200 nm, although lesser and greater spacings can also be employed. Thus, the perimeter of the patterned portion of the photoresist layer over the second stack of resistor isolation dielectric 150 and semiconductor sheet 160 can be laterally offset outward from the closed perimeter laterally surrounding and contacting the portion of the shallow trench isolation structure 20 of the first substrate semiconductor portion 10R. Each patterned portion of the photoresist layer over a respective one of the second substrate semiconductor portions 10T can laterally traverse a central portion of the respective one of the second substrate semiconductor portions 10T. The width of each patterned portion of the photoresist layer can correspond to the gate length of the respective field effect transistor subsequently formed.

[0129] An anisotropic etch process can be performed to transfer the pattern in the photoresist layer through each of the dielectric cap layer 80L, the metal material layer 70L, and the gate semiconductor material portions 49 by performing an anisotropic etch process such as a RIE process that stops on silicon oxide or a dielectric metal oxide material within the first resistor isolation dielectric 130 and the gate dielectric 38. The semiconductor material strips 140 are covered by the photoresist layer pattern, and by the second stack of the second resistor isolation dielectric 150 and the semiconductor sheet 160, and thus are not etched at this processing step.

[0130] The patterned portions of the dielectric cap layer 80L include a dielectric cap sheet 180S formed over the second stack of the second resistor isolation dielectric 150 and the semiconductor sheet 160, and include a dielectric gate cap 88 formed across a respective one of the second substrate semiconductor portions 10T. The patterned portions of the metal material layer 70L include a metal sheet 170S formed over the second stack of the second resistor isolation dielectric 150 and the semiconductor sheet 160, and include a metal gate electrode 78 formed across a respective one of the second substrate semiconductor portions 10T. The second stack of the second resistor isolation dielectric 150 and the semiconductor sheet 160 is encapsulated by the metal sheet 170S, the semiconductor material strips 140, and the shallow trench isolation structures 20, and is not etched by the anisotropic etch process. Each patterned portion of the gate semiconductor material portions 49 includes a semiconductor gate electrode 48. The first resistor isolation dielectric 130 and the gate dielectric 38 can function as etch stop structures for the anisotropic etch process. The first resistor isolation dielectric 130 can cover a respective first substrate semiconductor portion 10R, and the gate dielectric 38 can cover an entire top surface of a respective one of the second substrate semiconductor portions 10T.

[0131] The sidewalls of the dielectric cap sheet 180S and the metal sheet 170S can be vertically coincident with each other. Each combination of the semiconductor gate electrode 48 and the metal gate electrode 78 constitutes a composite gate electrode (48, 78). The sidewalls of each successive group of the semiconductor gate electrode 48, the metal gate electrode 78, and the dielectric gate cap 88 can be vertically coincident with each other. Each successive combination of the semiconductor gate electrode 48, the metal gate electrode 78, and the dielectric gate cap 88 constitutes a gate stack (38, 78, 88).

[0132] An electrical dopant can be implanted into regions of the second substrate semiconductor portion 10T not masked by the gate stack (38, 78, 88) to form source and drain extension regions (7, 9). The source and drain extension regions (7, 9) can include a source extension region 7 formed on one side of a respective composite gate electrode (48, 78), and a drain extension region 9 formed on the other side of the respective composite gate electrode (48, 78). In one embodiment, if CMOS transistors are formed, a masked ion implantation process can be employed to form a first subset of source and drain extension regions (7, 9) having p-type doping, and to form a second subset of source and drain extension regions (7, 9) having n-type doping.

[0133] Referring to FIG. 22A and FIG. 22B A dielectric material layer can be conformally deposited over the second exemplary structure, and can be anisotropically etched using sidewall spacer etching to remove horizontally extending portions of the dielectric material layer. The dielectric material layer includes at least one dielectric material, such as silicon nitride and / or silicon oxide. In one embodiment, the dielectric material layer can include a layer stack of a silicon nitride layer and a silicon oxide layer. Each remaining portion of the dielectric material layer includes a vertical portion laterally surrounding sidewalls of a respective layer stack. For example, a dielectric resistor spacer 152 can laterally surround a layer stack including the first resistor isolation dielectric 130, the semiconductor material strip 140, the second resistor isolation dielectric 150, the semiconductor sheet 160, the metal sheet 170S, and the dielectric cap sheet 180S. The dielectric resistor spacer 152 can contact sidewalls of the metal sheet 170S and the dielectric cap sheet 180S, and can be laterally spaced apart from the second resistor isolation dielectric 150, the semiconductor sheet 160, and the semiconductor material strip 140 by the metal sheet 170S. A dielectric gate spacer 58 can laterally surround and can contact sidewalls of a gate stack including the semiconductor gate electrode 48, the metal gate electrode 78, and the dielectric gate cap 88. The lateral thickness of the dielectric resistor spacer 152 and each dielectric gate spacer 58 can be in a range of 15 nm to 120 nm, such as 30 nm to 60 nm, although smaller and larger lateral thicknesses can also be employed.

[0134] The anisotropic etch process that removes the horizontal portions of the dielectric material layers laterally etches portions of the gate dielectric 38 that are not masked by the dielectric gate spacers 58. The sidewalls of each remaining portion of the gate dielectric 38 can be vertically coincident with the bottom periphery of the outer sidewall of the respective overlying dielectric gate spacer 58. In addition, the entire bottom surface of the dielectric resistor spacer 152 can contact the top surface of the shallow trench isolation structure 20. The dielectric resistor spacer 152 laterally surrounds and contacts the sidewalls of the metal sheet 170S and the dielectric cap sheet 180S. The semiconductor material strips (i.e., resistor strips) 140 are not damaged during the sidewall spacer (58, 152) etch because they are covered by the overlying layers and are not exposed during the sidewall spacer etch.

[0135] Electrical dopants can be implanted into regions of the second substrate semiconductor portion 10T that are not masked by the gate stack (38, 78, 88) or the dielectric gate spacers 58 to form source and drain regions (17, 19). The source and drain regions (17, 19) can include source regions 17 formed on one side of the respective composite gate electrode (48, 78) and drain regions 19 formed on the other side of the respective composite gate electrode (48, 78). In one embodiment, if CMOS transistors are fabricated, a masking ion implantation process can be employed to form a first subset of source and drain regions (17, 19) having p-type doping and to form a second subset of source and drain regions (17, 19) having n-type doping. The implanted portions of the source and drain extension regions (7, 9) can be incorporated into a respective one of the source and drain regions (17, 19). Field effect transistors are formed in the regions that include or overlie the second substrate semiconductor portion 10T.

[0136] Accordingly, field effect transistors can be formed on the second substrate semiconductor portion 10T of the substrate semiconductor layer 10. Each field effect transistor can include a gate dielectric 38 and a semiconductor gate electrode 48 that is a patterned portion of the gate semiconductor material portion 49. Each gate dielectric 38 includes the same material as and has the same thickness as the first resistor isolation dielectric 130. In one embodiment, one or more of the semiconductor gate electrodes 48 can include the same material as and have the same thickness as the semiconductor material strips 140. In one embodiment, each field effect transistor can also include a metal gate electrode 78 that includes the same material as and has the same thickness as the metal sheet 170S.

[0137] Reference is made to FIG. 23A and FIG. 23BThe photoresist layer 177 can be applied over the second exemplary structure and can be lithographically patterned to form openings within regions enclosed by the sidewalls of the metal sheet 170S, and a plurality of discrete patterned photoresist material portions 177A laterally surrounding the openings within regions of the metal sheet 170S. The sidewalls of the openings in the photoresist layer can be laterally offset inwardly from the sidewalls of the metal sheet 170S formed at the processing step of FIG. 21A and FIG. 21B The sidewalls of the metal sheet 170S formed at the processing step of

[0138] An anisotropic etch process can be performed to remove portions of the dielectric cap sheet 180S, the metal sheet 170S, and the semiconductor sheet 160 that are not masked by the photoresist layer 177. The second resistor isolation dielectric 150 can act as a stop structure for the anisotropic etch process. For example, the anisotropic etch process can include a first anisotropic etch step that etches the material of the dielectric cap sheet 180S, a second anisotropic etch step that etches the material of the metal sheet 170S, and a third anisotropic etch process that etches the semiconductor material of the semiconductor sheet 160 selectively to the material of the second resistor isolation dielectric 150. Thus, the semiconductor material strips (i.e., resistor strips) 140 are also not exposed during this etch step.

[0139] The trenches 179 laterally surrounding discrete patterned portions of the dielectric cap sheet 180S, the metal sheet 170S, and the semiconductor sheet 160 can be formed by an anisotropic etching process from the volume of material etching the dielectric cap sheet 180S, the metal sheet 170S, and the semiconductor sheet 160.

[0140] Each of the dielectric cap sheet 180S, the metal sheet 170S, and the semiconductor sheet 160 is divided by the anisotropic etching process into the resistor contact assemblies (101A, 101B) laterally surrounded by the trenches 179 and the peripheral stacks 101P laterally surrounding the trenches 179. Thus, by etching the sidewall spacers (58, 152) followed by the etching forming the resistor contact assemblies (101A, 101B), the likelihood of etching damage to the semiconductor material strips 140 is reduced. The reduced damage to the strips 140 reduces the variation in resistance between different strips 140, which can provide the ability to reduce the size of the strips 140 without negatively affecting their resistance. The resistor structure layout also makes the gate electrode RIE optimization easier because the step height difference between the layers is reduced. Furthermore, the resistor contact assemblies (101A, 101B) do not have sidewall spacers. Finally, the virtual stacks of portions of the dielectric cap sheet 180S, the metal sheet 170S, and the semiconductor sheet 160 can be omitted from the space between pairs of the resistor contact assemblies (101A, 101B) and replaced by the trenches 179 located between the resistor contact assemblies (101A, 101B).

[0141] The resistor contact assemblies (101A, 101B) include first resistor contact assemblies 101A formed on the first end portions of each semiconductor material strip 140 and second resistor contact assemblies 101B formed on the second end portions of each semiconductor material strip 140. The first resistor contact assemblies 101A and the second resistor contact assemblies 101B can be formed on each semiconductor material strip 140. The photoresist layer 177 can be subsequently removed, for example, by ashing.

[0142] The dielectric cap sheet 180S is divided into first dielectric caps 180A over first end portions of respective semiconductor material strips 140, second dielectric caps 180B over second end portions of respective semiconductor material strips 140, and a peripheral dielectric cap 180P outside the trench 179. Each metal sheet 170S is divided into first metal plates 170A over first end portions of respective semiconductor material strips 140, second metal plates 170B over second end portions of respective semiconductor material strips 140, and a peripheral metal plate 170P outside the trench 179. The semiconductor sheet 160 is divided into first semiconductor plates 160A over first end portions of respective semiconductor material strips 140, second semiconductor plates 160B over second end portions of respective semiconductor material strips 140, and a peripheral semiconductor plate 160P outside the trench 179.

[0143] Generally, after the dielectric resistor spacers 152 and the dielectric gate spacers 58 are formed, the combination of the dielectric cap sheet 180S, the metal sheet 170S, and the semiconductor sheet 160 is divided by the trench 179 into the resistor contact assemblies (101A, 101B) and the peripheral stack 101P. The trench 179 laterally surrounds each of the resistor contact assemblies (101A, 101B) and is laterally surrounded by the peripheral stack 101P. All sidewalls of the resistor contact assemblies (101A, 101B) and the inner sidewall of the peripheral stack 201 are physically exposed to the trench 179.

[0144] Each first resistor contact assembly 101A includes a stack of a first semiconductor plate 160A, a first metal plate 170A, and a first dielectric cap 180A. Each second resistor contact assembly 101B includes a stack of a second semiconductor plate 160B, a second metal plate 170B, and a second dielectric cap 180B. The peripheral stack 101P includes a peripheral semiconductor plate 160P, a peripheral metal plate 170P, and a peripheral dielectric cap 180P. The first semiconductor plate 160A, the second semiconductor plate 160B, and the peripheral semiconductor plate 160P are patterned portions of the semiconductor sheet 160. The first metal plate 170A, the second metal plate 170B, and the peripheral metal plate 170P are patterned portions of the metal sheet 170S. The first dielectric cap 180A, the second dielectric cap 180B, and the peripheral dielectric cap 180P are patterned portions of the dielectric cap sheet 180S.

[0145] The trench 179 can laterally surround each of the first and second resistor contact assemblies 101 A, 101B and can be laterally surrounded by the peripheral stack 101P. In one embodiment, each first resistor contact assembly 101 A can include a first semiconductor plate 160A including an opening therein and a first metal plate 170A extending through the opening in the first semiconductor plate 160A and contacting a top surface of a first region of a respective semiconductor material stripe 140, and each second resistor contact assembly 101B can include a second semiconductor plate 160B including an opening therein and a second metal plate 170B extending through the opening in the second semiconductor plate 160B and contacting a top surface of a second region of a respective semiconductor material stripe 140. The peripheral stack 101P includes a peripheral semiconductor plate 160P and a peripheral metal plate 170P and is electrically isolated from the semiconductor material stripes 140. The peripheral semiconductor plate 160P includes the same material as the first and second semiconductor plates 160A, 160B, and the peripheral metal plate 170P includes the same material as the first and second metal plates 170A, 170B.

[0146] Referring to FIG. 24A and FIG. 24B The at least one contact level dielectric material can be deposited over the second resistor isolation dielectric 150, the resistor contact assemblies (101 A, 101B), the peripheral stack 101P, and the field effect transistors to form at least one contact level dielectric layer 90. The at least one contact level dielectric layer 90 can laterally extend over the second resistor isolation dielectric 150, the resistor contact assemblies (101 A, 101B), the peripheral stack 101P, and the field effect transistors and include a downwardly protruding portion that fills the trench 179 and contacts the second resistor isolation dielectric 150. In one embodiment, the at least one contact level dielectric layer 90 can include a dielectric liner 90A and a planarized dielectric layer 90B including a planarizable dielectric material. For example, the dielectric liner 90A can include a dielectric diffusion barrier material such as silicon nitride and the planarized dielectric layer 90B can include an undoped silicate glass or a doped silicate glass. The thickness of the dielectric liner 90A can be in a range of 4 nm to 20 nm, although lesser and greater thicknesses can also be employed.

[0147] The downward protruding portion of the at least one contact level dielectric layer fills the trench 179. Typically, the peripheral stack 101P includes an opening defined by an inner sidewall (which can be an outer sidewall of the trench 179) and laterally surrounds and is laterally spaced apart from the resistor contact assembly (101A, 101B). The downward protruding portion of the at least one contact level dielectric layer 90 can be formed directly on a surface of the second resistor isolation dielectric 150, which can be a top surface or a recessed horizontal surface of the second resistor isolation dielectric 150. The downward protruding portion of the at least one contact level dielectric layer 90 can be formed directly on sidewalls of the resistor contact assembly (101A, 101B) and inner sidewalls of the peripheral stack 101P. The downward protruding portion of the at least one contact level dielectric layer 90 can be in contact with a top surface of the second resistor isolation dielectric 150 and can be vertically spaced apart from the semiconductor material strip 140 by the second resistor isolation dielectric 150.

[0148] Referring to FIG. 25A and FIG. 25B The contact via structures (192, 194, 97, 98, 99) can be formed through the at least one contact level dielectric layer 90 on a respective node of a resistor structure or a field effect transistor. The contact via structures (192, 194, 97, 98, 99) include first contact via structures 192 that contact a respective first metal plate 170A and second contact via structures 194 that contact a respective second metal plate 170B. While only a single respective contact via structure (192, 194) is shown in FIG. 25A contacting one respective resistor contact assembly (101A, 101B), in alternative configurations, two or more respective contact via structures (192, 194) can contact one respective resistor contact assembly (101A, 101B). Further, the contact via structures (192, 194, 97, 98, 99) can include source contact via structures 97 that contact a respective source region 17, drain contact via structures 99 that contact a respective drain region 19, and gate contact via structures 98 that contact a respective one of the composite gate electrodes (48, 78).

[0149] Referring to FIGS. 15A-25BAnd according to various embodiments of the present disclosure, a semiconductor structure is provided that includes a resistor structure on a semiconductor substrate that includes a substrate semiconductor layer 10. The resistor structure includes: a first resistor isolation dielectric 130 on a top surface of a first substrate semiconductor portion 10R of the substrate semiconductor layer 10; a semiconductor material strip 140 on a top surface of the first resistor isolation dielectric 130; a first resistor contact assembly 101A that includes a first semiconductor plate 160A that includes an opening therein and a first metal plate 170A that extends through the opening in the first semiconductor plate 160A and contacts a top surface of a first region of the semiconductor material strip 140; a second resistor contact assembly 101B that includes a second semiconductor plate 160B that includes an opening therein and a second metal plate 170B that extends through the opening in the second semiconductor plate 160B and contacts a top surface of a second region of the semiconductor material strip 140; and a peripheral stack 101P that includes a peripheral semiconductor plate 160P and a peripheral metal plate 170P and is electrically isolated from the semiconductor material strip 140, where the peripheral semiconductor plate 160P includes the same material as the first semiconductor plate 160A and the second semiconductor plate 160B, and the peripheral metal plate 170P includes the same material as the first metal plate 170A and the second metal plate 170B.

[0150] In one embodiment, the resistor structure includes a second resistor isolation dielectric 150 that contacts a top surface of the semiconductor material strip 140, a bottom surface of the first semiconductor plate 160A, and a bottom surface of the second semiconductor plate 160B. In one embodiment, the second resistor isolation dielectric 150 contacts a bottom surface of the peripheral semiconductor plate 160P.

[0151] In one embodiment, the second resistor isolation dielectric 150 contacts sidewalls of the first metal plate 170A, sidewalls of the second metal plate 170B, and sidewalls of the peripheral metal plate 170P. In one embodiment, the resistor structure includes: an additional first resistor isolation dielectric 130 on a top surface of an additional first substrate semiconductor portion 10R and laterally spaced apart from the first resistor isolation dielectric 130 by a shallow trench isolation structure 20; and an additional semiconductor material strip 140 (e.g., another strip 140 spaced apart from the first strip 140 along a second horizontal direction hd2) on a top surface of the additional first resistor isolation dielectric 130, laterally spaced apart from the semiconductor material strip 140 by the shallow trench isolation structure 20, and contacting a bottom surface of the second resistor isolation dielectric 150.

[0152] In one embodiment, a bottom surface of the first metal plate 170A contacts a top surface of the first semiconductor plate 160A; and a sidewall of the first metal plate 170A vertically coincides with an outer sidewall of the first semiconductor plate 160A. In one embodiment, the peripheral stack 101P includes an opening extending from a top surface of the peripheral stack 101P to a bottom surface of the peripheral stack 101P, where the first resistor contact assembly 101A and the second resistor contact assembly 101B are located within the opening in the peripheral stack 101P. The dielectric resistor spacer 152 can laterally surround and can contact an outer sidewall of the peripheral stack 101P. However, the first resistor contact assembly 101A and the second resistor contact assembly 101B do not have a dielectric resistor spacer on their respective sidewalls.

[0153] The at least one contact-level dielectric layer 90 laterally extends over the first resistor contact assembly 101A, the second resistor contact assembly 101B, and the peripheral stack 101P, and includes a downwardly-protruding portion that protrudes into the opening in the peripheral stack 101P. In one embodiment, the downwardly-protruding portion of the at least one contact-level dielectric layer 90 contacts a sidewall of the first resistor contact assembly 101A, a sidewall of the second resistor contact assembly 101B, an inner sidewall of the peripheral stack 101P, and an outer sidewall of the dielectric resistor spacer 152.

[0154] In one embodiment, the semiconductor structure includes a field effect transistor located on the second substrate semiconductor portion 10T of the substrate semiconductor layer 10 and including a gate dielectric 38 that includes the same material as the first resistor isolation dielectric 130 and has the same thickness as the first resistor isolation dielectric. In one embodiment, the field effect transistor includes a semiconductor gate electrode 48 that includes the same material as the semiconductor material strip 140 and has the same thickness as the semiconductor material strip. In one embodiment, the field effect transistor includes a metal gate electrode 78 that includes the same material as each of the first metal plate 170A and the second metal plate 170B and has the same thickness as each of the first metal plate and the second metal plate.

[0155] Various processing steps of the present disclosure can be employed to provide capacitor structures and / or resistor structures concurrently with the formation of field effect transistors. Gate material is used as a component of the capacitor structures and / or resistor structures. In one embodiment, the capacitor structures and / or resistor structures can be formed on the same semiconductor substrate as the transistors. At least one of the capacitor or resistor structures can be formed concurrently with the formation of the field effect transistors by patterning the gate dielectric layer into gate dielectric and into first node dielectric or first resistor isolation dielectric, and by patterning the semiconductor layer into gate electrode and into second electrode of the capacitor or resistor strip. Contacts are then formed to the capacitor or resistor structures. Prior to patterning the capacitor or resistor contacts, sidewall spacers can be formed on the gate electrode to reduce etch damage to the underlying capacitor or resistor layers.

[0156] While specific preferred embodiments are mentioned, it is to be understood that the present disclosure is not limited thereto. Those skilled in the art will perceive modifications and alterations to the disclosed embodiments, and these modifications and alterations are intended to fall within the scope of the present disclosure. Compatibility is assumed among all embodiments that are not alternatives to each other. Unless explicitly stated otherwise, the word "comprising" or "including" contemplates all embodiments where the words "consisting essentially of or the words "consisting of are substituted for the word "comprising" or "including." Embodiments are shown in the present disclosure employing particular structures and / or configurations, it is to be understood that the present disclosure can be practiced in any other compatible structure and / or configuration that is functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise deemed impossible by one of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims

1. A semiconductor structure comprising a capacitor structure on a semiconductor substrate comprising a substrate semiconductor layer, wherein the capacitor structure comprises: a first electrode comprising a first substrate semiconductor portion of the substrate semiconductor layer; a first node dielectric on a top surface of the first substrate semiconductor portion of the substrate semiconductor layer; a second electrode comprising a first semiconductor plate on a top surface of the first node dielectric; a second node dielectric on a top surface of the first semiconductor plate; a third electrode comprising a stack of a main semiconductor plate and a main metal plate; a moat trench laterally surrounding the third electrode; a peripheral stack laterally surrounding the third electrode, wherein the peripheral stack comprises a peripheral semiconductor plate and a peripheral metal plate, and wherein the peripheral semiconductor plate contacts a peripheral portion of the top surface of the second node dielectric, comprises a same material as the main semiconductor plate, and is laterally spaced apart from the main semiconductor plate; and at least one contact level dielectric layer laterally extending over the third electrode and the peripheral stack.

2. The semiconductor structure of claim 1, wherein the at least one contact level dielectric layer comprises a downward protruding portion that fills the moat trench and contacts the second node dielectric exposed in the moat trench.

3. The semiconductor structure of claim 2, wherein the downward protruding portion of the at least one contact level dielectric layer is vertically spaced apart from the second electrode by the second node dielectric.

4. The semiconductor structure of claim 2, wherein each outer sidewall of the peripheral stack vertically coincides with a respective sidewall of the second electrode.

5. The semiconductor structure of claim 4, further comprising a dielectric capacitor spacer laterally surrounding and contacting the second electrode and the peripheral stack, and contacting a peripheral portion of the top surface of the first node dielectric.

6. The semiconductor structure of claim 5, wherein a top edge of a sidewall of the first node dielectric coincides with a bottom perimeter of an outer sidewall of the dielectric capacitor spacer.

7. The semiconductor structure of claim 1, wherein: the peripheral metal plate comprises a same metallic material as the main metal plate; and the peripheral stack comprises a peripheral dielectric cap contacting a top surface of the peripheral metal plate.

8. The semiconductor structure of claim 1, further comprising a shallow trench isolation structure laterally surrounding the first substrate semiconductor portion, wherein an entire bottom perimeter of the first node dielectric contacts the top surface of the substrate semiconductor portion and is laterally offset inward from an inner perimeter of a portion of the shallow trench isolation structure laterally surrounding the first substrate semiconductor portion. ​ 9. The semiconductor structure of claim 1, further comprising a shallow trench isolation structure laterally surrounding the first substrate semiconductor portion, wherein a portion of the second node dielectric and a portion of the peripheral stack overlie and contact a top surface of the shallow trench isolation structure.

10. The semiconductor structure of claim 1, further comprising a field effect transistor on a second substrate semiconductor portion of the substrate semiconductor layer and comprising a gate dielectric comprising a same material as the first node dielectric and having a same thickness as the first node dielectric.

11. The semiconductor structure of claim 10, wherein the field effect transistor comprises: a semiconductor gate electrode comprising a same material as the first semiconductor plate and having a same thickness as the first semiconductor plate; and a metal gate electrode comprising a same material as and having a same thickness as each of the main metal plate and the peripheral metal plate.

12. The semiconductor structure of claim 1, further comprising: a first contact via structure extending through the at least one contact level dielectric layer and contacting the first electrode; a second contact via structure extending through the at least one contact level dielectric layer and electrically contacting the second electrode through the peripheral metal plate; and a third contact via structure extending through the at least one contact level dielectric layer and contacting the third electrode.

13. The semiconductor structure of claim 12, wherein: the first electrode, the first node dielectric, and the second electrode form a first capacitor; and the second electrode, the second node dielectric, and the third electrode form a second capacitor.

14. A method of forming a semiconductor structure comprising a capacitor structure on a semiconductor substrate comprising a substrate semiconductor layer, the method comprising: forming a first stack comprising a first node dielectric and a first semiconductor plate on a top surface of a first substrate semiconductor portion of the substrate semiconductor layer; forming a second stack comprising a second node dielectric and a semiconductor sheet over the first stack; forming a metal sheet over the second stack and over a peripheral portion of a top surface of the first semiconductor plate; dividing the metal sheet and the semiconductor sheet into an inner layer stack surrounded by a moat trench and a peripheral stack surrounding the moat trench, wherein sidewalls of the inner layer stack and sidewalls of the peripheral stack are physically exposed in the moat trench; forming at least one contact level dielectric layer directly on the sidewalls of the inner layer stack and the sidewalls of the peripheral stack; and forming a contact via structure through the at least one contact level dielectric layer on the inner layer stack and on the peripheral stack, wherein: the inner layer stack comprises a main semiconductor plate and a main metal plate; the peripheral stack comprises a peripheral semiconductor plate and a peripheral metal plate; the main semiconductor plate and the peripheral semiconductor plate are patterned portions of the semiconductor sheet; and the main metal plate and the peripheral metal plate are patterned portions of the metal sheet. ​ The main metal plate and the peripheral metal plate are patterned portions of the metal sheet.

15. The method of claim 14, wherein the moat trench laterally surrounds a third electrode, the third electrode comprising the main semiconductor plate and the main metal plate.

16. The method of claim 15, wherein the at least one contact level dielectric layer comprises a downwardly projecting portion that fills the moat trench.

17. The method of claim 16, wherein the downwardly projecting portion of the at least one contact level dielectric layer is formed directly on a surface of the second node dielectric.

18. The method of claim 14, further comprising: depositing a layer of metal material over the semiconductor sheet; patternizing the layer of metal material into the metal sheet; and forming a dielectric capacitor spacer laterally surrounding the metal sheet on sidewalls of the metal sheet, wherein after forming the dielectric capacitor spacer, the metal sheet and the semiconductor sheet are divided into the inner layer stack and the peripheral stack.

19. The method of claim 14, further comprising: forming an isolation dielectric layer over the first and second substrate semiconductor portions of the substrate semiconductor layer; forming a first semiconductor material layer over the isolation dielectric layer; patternizing the isolation dielectric layer and the first semiconductor material layer, wherein a patternized portion of the isolation dielectric layer comprises the first node dielectric and a gate dielectric formed on the second substrate semiconductor portion, and a patternized portion of the first semiconductor material layer comprises the first semiconductor plate and a gate semiconductor material portion; and forming a field effect transistor over the second substrate semiconductor portion, the field effect transistor comprising a patternized portion of the gate dielectric and the gate semiconductor material portion.

20. The method of claim 19, further comprising: depositing a layer of metal material over the gate semiconductor material portion and over the semiconductor sheet; and patternizing the layer of metal material, the gate semiconductor material portion, and the first semiconductor plate by performing an etching process, wherein: a patternized portion of the layer of metal material comprises a metal gate electrode and the metal sheet; a patternized portion of the gate semiconductor material portion comprises a semiconductor gate electrode; and a peripheral portion of the first semiconductor plate is removed by the etching process.

21. A semiconductor structure comprising a resistor structure on a semiconductor substrate comprising a substrate semiconductor layer, wherein the resistor structure comprises: a first resistor isolation dielectric on a top surface of a first substrate semiconductor portion of the substrate semiconductor layer; a semiconductor material strip on a top surface of the first resistor isolation dielectric; a first resistor contact assembly comprising a first semiconductor plate including an opening therein and a first metal plate extending through the opening in the first semiconductor plate and contacting a first region of a top surface of the semiconductor material strip; a second resistor contact assembly comprising a second semiconductor plate including an opening therein and a second metal plate extending through the opening in the second semiconductor plate and contacting a second region of the top surface of the semiconductor material strip; and a peripheral stack comprising a peripheral semiconductor plate and a peripheral metal plate and electrically isolated from the semiconductor material strip, wherein the peripheral semiconductor plate comprises the same material as the first semiconductor plate and the second semiconductor plate, and the peripheral metal plate comprises the same material as the first metal plate and the second metal plate.

22. The semiconductor structure of claim 21, wherein the resistor structure further comprises a second resistor isolation dielectric contacting a top surface of the semiconductor material strip, a bottom surface of the first semiconductor plate, and a bottom surface of the second semiconductor plate.

23. The semiconductor structure of claim 22, wherein the second resistor isolation dielectric contacts a bottom surface of the peripheral semiconductor plate.

24. The semiconductor structure of claim 22, wherein the second resistor isolation dielectric contacts sidewalls of the first metal plate, sidewalls of the second metal plate, and sidewalls of the peripheral metal plate.

25. The semiconductor structure of claim 22, wherein the resistor structure further comprises: an additional first resistor isolation dielectric on a top surface of an additional first substrate semiconductor portion and laterally spaced apart from the first resistor isolation dielectric by a shallow trench isolation structure; and an additional semiconductor material strip on a top surface of the additional first resistor isolation dielectric, laterally spaced apart from the semiconductor material strip by the shallow trench isolation structure, and contacting a bottom surface of the second resistor isolation dielectric.

26. The semiconductor structure of claim 21, wherein: a bottom surface of the first metal plate contacts a top surface of the first semiconductor plate; and sidewalls of the first metal plate vertically coincide with outer sidewalls of the first semiconductor plate.

27. The semiconductor structure of claim 21, wherein the peripheral stack comprises an opening extending from a top surface of the peripheral stack to a bottom surface of the peripheral stack, wherein the first resistor contact assembly and the second resistor contact assembly are located within the opening in the peripheral stack.

28. The semiconductor structure of claim 27, further comprising a dielectric resistor spacer laterally surrounding and contacting outer sidewalls of the peripheral stack, wherein the first resistor contact assembly and the second resistor contact assembly do not have a dielectric resistor spacer on their respective sidewalls. ​ ​ 29. The semiconductor structure of claim 28, further comprising at least one contact level dielectric layer laterally extending over the first resistor contact assembly, the second resistor contact assembly, and the peripheral stack, and including a downwardly projecting portion that projects into the opening in the peripheral stack.

30. The semiconductor structure of claim 29, wherein the downwardly projecting portion of the at least one contact level dielectric layer contacts sidewalls of the first resistor contact assembly, sidewalls of the second resistor contact assembly, inner sidewalls of the peripheral stack, and outer sidewalls of the dielectric resistor spacers.

31. The semiconductor structure of claim 21, further comprising a field effect transistor on a second substrate semiconductor portion of the substrate semiconductor layer and including a gate dielectric comprising the same material as and having the same thickness as the first resistor isolation dielectric.

32. The semiconductor structure of claim 31, wherein the field effect transistor includes a semiconductor gate electrode comprising the same material as and having the same thickness as the semiconductor material strip.

33. The semiconductor structure of claim 32, wherein the field effect transistor further includes a metal gate electrode comprising the same material as and having the same thickness as each of the first metal plate and the second metal plate.

34. A method of forming a semiconductor structure including a resistor structure on a semiconductor substrate including a substrate semiconductor layer, the method comprising: forming a first stack including a first resistor isolation dielectric and a semiconductor material strip on a top surface of a first substrate semiconductor portion of the substrate semiconductor layer; forming a second stack including a second resistor isolation dielectric and a semiconductor sheet over the first stack, wherein the second stack includes openings therethrough, and a portion of a top surface of the semiconductor material strip is physically exposed at a bottom of each of the openings in the second stack; forming a metal sheet over the second stack and on the physically exposed portion of the top surface of the semiconductor material strip; dividing the metal sheet and the semiconductor sheet into patterned portions including a first resistor contact assembly and a second resistor contact assembly.

35. The method of claim 34, wherein: the first resistor contact assembly includes a first semiconductor plate including an opening therein and a first metal plate extending through the opening in the first semiconductor plate and contacting a first region of a top surface of the semiconductor material strip; and the second resistor contact assembly includes a second semiconductor plate including an opening therein and a second metal plate extending through the opening in the second semiconductor plate and contacting a second region of the top surface of the semiconductor material strip.

36. The method of claim 35, wherein: ​ Splitting the metal sheet and the semiconductor sheet into the patterned portions includes forming trenches through the metal sheet and the semiconductor sheet; and the trenches laterally surround the first and second resistor contact assemblies and are laterally surrounded by a peripheral stack, which is another patterned portion of the metal sheet and the semiconductor sheet.

37. The method of claim 36, further comprising forming at least one contact level dielectric layer in the trenches and over the first resistor contact assembly, the second resistor contact assembly, and the peripheral stack, wherein the at least one contact level dielectric layer is formed directly on sidewalls of the first and second semiconductor slabs.

38. The method of claim 34, further comprising: depositing a layer of metal material over the semiconductor sheet; patternizing the layer of metal material into the metal sheet; and forming a dielectric resistor spacer laterally surrounding the metal sheet on sidewalls of the metal sheet, wherein: the first and second resistor contact assemblies have no dielectric resistor spacer on their respective sidewalls; and splitting the metal sheet and the semiconductor sheet into the patterned portions occurs after forming the dielectric resistor spacer.

39. The method of claim 34, further comprising: forming an isolation dielectric layer over the first and second substrate semiconductor portions of the substrate semiconductor layer; forming a first semiconductor material layer over the isolation dielectric layer; and patternizing the isolation dielectric layer and the first semiconductor material layer, wherein a patternized portion of the isolation dielectric layer includes the first resistor isolation dielectric and at least one additional first resistor isolation dielectric, and a patternized portion of the first semiconductor material layer includes the semiconductor material strip and at least one additional semiconductor material strip, wherein: the second resistor isolation dielectric is formed on a top surface of each of the at least one additional semiconductor material strip; the patternized portion of the isolation dielectric layer includes a gate dielectric formed on the second substrate semiconductor portion of the substrate semiconductor layer; and the patternized portion of the first semiconductor material layer includes a gate semiconductor material portion.

40. The method of claim 39, further comprising: depositing a layer of metal material over the gate semiconductor material portion and over the semiconductor sheet; patternizing the layer of metal material and the gate semiconductor material portion by performing an etching process; and forming a field effect transistor over the second substrate semiconductor portion, the field effect transistor including the gate dielectric and patternized portions of the gate semiconductor material portion and the layer of metal material; wherein: the patternized portion of the layer of metal material includes a metal gate electrode and the metal sheet; and the patternized portion of the gate semiconductor material portion includes a semiconductor gate electrode.

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