A clock synchronization method and device

Abstract

A clock synchronization method and device are used to solve the problem of inaccurate time synchronization. The method includes: a first device sends first data, adds a timestamp to the first data, and determines the position of the data corresponding to the timestamp in the first data, and the first time of sending the data corresponding to the timestamp; determines the transmission delay generated by the data at the position during the format conversion process; sends a first message to the second device, the first message indicates the time after compensation for the first time; receives a second message sent by the second device at a third time; sends a third message containing the third time to the second device, so that the second device performs clock synchronization. The method pre-compensates for the determined transmission delay, effectively solves the impact of data format conversion of the transmitted data on clock synchronization, and improves the accuracy of time synchronization.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a clock synchronization method and device. Background Art

[0002] In order to improve the data transmission efficiency, the data sender and receiver need to synchronize the data clock. At present, the clock synchronization between devices is mainly based on the precision clock synchronization protocol standard (IEEE1588 protocol) of network measurement and control system.

[0003] like Figure 1 As shown in the figure, the specific clock synchronization process between the data sender and the data receiver is as follows:

[0004] When the data sending direction transmits data to the data receiving direction, the data sending direction sends a synchronization (sync) message carrying data to the data receiving direction, and the data receiving direction records the receiving time T2 of receiving the sync message. Then, the data sending direction sends a follow-up (follow_up) message carrying the real time T1 of data sending to the data receiving direction, and the data receiving direction obtains the T1 in the follow_up message. After receiving the Sync message, the data receiving direction sends a delay request (Delay_req) message to the data sending direction, and records the sending time T3 of sending the Delay_req message. After receiving the Delay_Req message, the data sending direction records the accurate receiving time T4 of the Delay_Req message, and then sends a delay response (Delay_Resp) message carrying T4 to the data receiving direction, and the data receiving direction obtains the T4 in the Delay_Resp message. Thus, the data receiver determines the time difference between the data sender and the data receiver and the path delay of the data transmission process based on the four time points T1, T2, T3 and T4 based on the IEEE1588 protocol. The data receiver implements clock synchronization between the data sender and the data receiver based on the determined time difference and path delay.

[0005] However, in communication services, when the data sender performs data transmission, it is often necessary to process the data format of the transmission data. For example, when the data sender and the data receiver use a clock data recovery (CDR) system to perform data transmission, forward error correction coding (FEC) is generally used to process the data format of the transmission data. However, the change of the data format of the transmission data will produce a large delay jitter.

[0006] The existing technology is currently unable to achieve accurate clock synchronization between the data sender and the data receiver when the data format is changed, thereby reducing the data transmission efficiency between the data sender and the data receiver. Summary of the invention

[0007] The embodiments of the present application provide a clock synchronization method and device for solving the problem of inaccurate clock synchronization when processing data formats in the prior art.

[0008] In a first aspect, an embodiment of the present application provides a clock synchronization method, which is used in a network environment consisting of a first device, a conversion device, and a second device, wherein the conversion device is used to convert the format of first data of the first device to obtain second data, and send the second data to the second device, including:

[0009] The first device sends the first data, adds a timestamp to the first data, and determines the data position of the data corresponding to the timestamp in the first data, as well as the first time of sending the data corresponding to the timestamp; the first device determines the transmission delay generated by the data at the data position during the format conversion process based on the data position; the first device sends a first message to the second device, the first message is used to indicate a second time, and the second time is the time after the first time is compensated according to the transmission delay; the first device receives the second message sent by the second device at a third time; the first device sends a third message to the second device, the third message includes the third time, so that the second device synchronizes the clock with the first device based on the second time, the third time and the fourth time of sending the second message.

[0010] Based on this scheme, during the communication transmission process, the first device determines the transmission delay generated in the process of data format conversion for the transmission data and the first time of sending the data with a timestamp recorded in the first data, and then indicates the second time for clock synchronization to the second device based on the transmission delay and the first time. The second time is the time after compensating the first time based on the transmission delay, so that the second device performs clock synchronization according to the compensated sending time, effectively solving the delay jitter generated in the process of data format conversion for the transmission data, the impact on clock synchronization, and improving the accuracy of time synchronization.

[0011] In a possible implementation, the first message includes the first time and the transmission delay, so that the second device compensates the first time according to the transmission delay to obtain a second time; or the first message includes the second time.

[0012] In a possible implementation, the first message is a follow_up message; the second message is a delay request Delay_req message; and the third message is a delay response Delay_Resp message.

[0013] In a possible implementation manner, during the transmission of the second data, a relative position between an alignment mark in the second data and data in the second data remains unchanged.

[0014] In a second aspect, an embodiment of the present application provides a clock synchronization method, which is used in a network environment consisting of a first device, a conversion device, and a second device, wherein the conversion device is used to convert the format of first data of the first device to obtain second data, and send the second data to the second device, including:

[0015] The second device receives the second data sent by the conversion device; the second device receives the first message sent by the first device, the first message is used to indicate the second time; the second time is the time after compensating the first time according to the transmission delay, the transmission delay is the data with a timestamp in the first data generated during the format conversion process, and the first time is the sending time of the data corresponding to the timestamp sent by the first device; the second device sends a second message to the first device at a fourth time; the second device receives the third message sent by the first device, the third message includes the third time when the first device receives the second message; the second device synchronizes the clock with the first device according to the second time, the third time and the fourth time.

[0016] Based on this solution, during the communication transmission process, the second device receives a first message indicating a second time sent by the first device, and the second time is the time after compensating the first time according to the transmission delay, so that the second device performs clock synchronization according to the compensated transmission time, effectively solving the delay jitter generated during the data format conversion process of the transmitted data, the impact on the clock synchronization, and improving the accuracy of time synchronization.

[0017] In a possible implementation, before the second device performs clock synchronization with the first device according to the second time, the third time and the fourth time, it also includes: the second device determines the second time according to the transmission delay included in the first message and the first time.

[0018] In a possible implementation, the first message is a follow_up message; the second message is a delay request Delay_req message; and the third message is a delay response Delay_Resp message.

[0019] In a possible implementation manner, during the transmission of the second data, a relative position between an alignment mark in the second data and data in the second data remains unchanged.

[0020] In a third aspect, an embodiment of the present application provides a clock synchronization method, which is used in a network environment consisting of a first device, a conversion device, and a second device, wherein the conversion device is used to convert the format of first data of the first device to obtain second data, and send the second data to the second device, including:

[0021] The second device receives the second data sent by the conversion device; the second device determines the transmission delay generated by the data with a timestamp in the second data during the format conversion process; the second device receives the first message sent by the first device, and the first message includes the first time; the second device sends a second message to the first device at a fourth time; the second device receives the third message sent by the first device, and the third message includes the third time when the first device receives the second message; the second device synchronizes the clock with the first device according to the first time, the transmission delay, the third time and the fourth time.

[0022] Based on this solution, during the communication transmission process, the second device determines the transmission delay caused by the data format conversion process, and then compensates the first time received from the first device according to the transmission delay to obtain the second time, thereby performing clock synchronization according to the second time, effectively solving the impact of data format processing on clock synchronization during transmission data, and improving the accuracy of time synchronization.

[0023] In a possible implementation, the second device compensates the first time according to the transmission delay to obtain a second time; the second device performs clock synchronization with the first device according to the second time, the third time, and the fourth time.

[0024] In a possible implementation, the first message is a follow_up message; the second message is a delay request Delay_req message; and the third message is a delay response Delay_Resp message.

[0025] In a possible implementation manner, during the transmission of the second data, a relative position between an alignment mark in the second data and data in the second data remains unchanged.

[0026] In a fourth aspect, an embodiment of the present application provides a communication device, which has the functions of implementing the devices in the first to third aspects of the above embodiments. The functions can be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units or modules corresponding to the above functions.

[0027] In a possible implementation, the communication device may be the first device in the first aspect described above, or a component that can be used for the first device, such as a chip or a chip system or a circuit, and the communication device may include: a transceiver and a processor. The processor may be configured to support the communication device to perform the corresponding functions of the first device described above, and the transceiver is used to support communication between the communication device and other devices (such as a second device). Optionally, the communication device may also include a memory, which may be coupled to the processor and stores program instructions and data necessary for the communication device. The transceiver may be an independent receiver, an independent transmitter, a transceiver with integrated transceiver functions, or an interface circuit.

[0028] In another possible implementation, the communication device may be the second device in the second aspect or the third aspect, or a component that can be used for the second device, such as a chip or a chip system or a circuit, and the communication device may include: a transceiver and a processor. The processor may be configured to support the communication device to perform the corresponding functions of the second device above, and the transceiver is used to support the communication device and other devices (such as the first device) The communication device may also include a memory, which may be coupled to the processor, which stores the necessary program instructions and data for the communication device. Among them, the transceiver may be an independent receiver, an independent transmitter, a transceiver with integrated transceiver functions, or an interface circuit.

[0029] In a fifth aspect, an embodiment of the present application provides a communication device for implementing the above-mentioned first aspect or any one of the methods in the first aspect.

[0030] In a possible implementation manner, when the communication device is a first device, it may include: a processing unit and a communication unit:

[0031] The communication unit is used to send the first data;

[0032] The processing unit is used to add a timestamp to the first data, determine a data position of the data corresponding to the timestamp in the first data, and a first time of sending the data corresponding to the timestamp; and determine, according to the data position, a transmission delay generated by the data at the data position during the format conversion process;

[0033] The communication unit is used to send a first message to the second device, where the first message is used to indicate a second time, and the second time is the time after the first time is compensated according to the transmission delay; receive a second message sent by the second device at a third time; and send a third message to the second device, where the third message includes the third time, so that the second device synchronizes the clock with the first device according to the second time, the third time and the fourth time of sending the second message.

[0034] In a sixth aspect, an embodiment of the present application provides a communication device for implementing the above-mentioned second aspect or any one of the methods in the second aspect.

[0035] In a possible implementation manner, when the communication device is a second device, it may include: a processing unit and a communication unit:

[0036] The communication unit is configured to receive second data sent by a conversion device; receive a first message sent by the first device, the first message being used to indicate a second time; the second time being the time after the first time is compensated according to a transmission delay, the transmission delay being generated during a format conversion process of the data with a timestamp in the first data, the first time being the time when the first device sends the data corresponding to the timestamp; send a second message to the first device at a fourth time; receive a third message sent by the first device, the third message including a third time when the first device receives the second message;

[0037] The processing unit is configured to perform clock synchronization with the first device according to the second time, the third time and the fourth time.

[0038] In a seventh aspect, an embodiment of the present application provides a communication device for implementing the above-mentioned third aspect or any one of the methods in the third aspect.

[0039] In a possible implementation manner, when the communication device is a second device, it may include: a processing unit and a communication unit:

[0040] The communication unit is used to receive second data sent by the conversion device;

[0041] The processing unit is used to determine the transmission delay of the data with the timestamp in the second data during the format conversion process;

[0042] The communication unit is used to receive a first message sent by the first device, the first message including the first time; send a second message to the first device at a fourth time; receive a third message sent by the first device, the third message including the third time when the first device receives the second message; and perform clock synchronization with the first device based on the first time, the transmission delay, the third time and the fourth time.

[0043] In an eighth aspect, an embodiment of the present application provides a communication system, the communication system comprising a first device and a second device. The first device can be used to perform any aspect of the first aspect; or perform any method of the first aspect;

[0044] The second device is used to execute any one of the second aspect or the third aspect; or is used to execute any one of the methods in the first aspect or the third aspect.

[0045] In a ninth aspect, the present application provides a chip system, including a processor. Optionally, it may also include a memory, the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the communication device equipped with the chip system executes any one of the first to third aspects above; or executes any one of the methods in the first to third aspects above.

[0046] In the tenth aspect, an embodiment of the present application provides a computer storage medium, which stores instructions. When the computer storage medium is run on a communication device, the communication device executes any one of the above-mentioned first to third aspects; or executes any one of the above-mentioned first to third aspects.

[0047] In the eleventh aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a communication device, enables the communication device to execute any one of the first to third aspects above; or execute any one of the methods of the first to third aspects above. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a schematic diagram of message transmission between an existing IEEE1588-based sending device and a receiving device;

[0049] Figure 2 A schematic diagram of a timestamp marking method in an existing data transmission process;

[0050] Figure 3A schematic diagram of a system architecture provided for an embodiment of the present application;

[0051] Figure 4 A schematic diagram of a time synchronization method provided in an embodiment of the present application;

[0052] Figure 5 A schematic diagram of determining transmission delay by performing FEC encoding provided in an embodiment of the present application;

[0053] Figure 6 A schematic diagram of compensation for the sending time T1 provided in an embodiment of the present application;

[0054] Figure 7 A schematic diagram of a flow chart corresponding to another clock synchronization method provided in an embodiment of the present application;

[0055] Figure 8 A schematic diagram of the structure of a first device provided in an embodiment of the present application;

[0056] Fig. 9 A schematic diagram of the structure of a second first device provided in an embodiment of the present application;

[0057] Fig.10 A schematic diagram of the structure of the first second device provided in an embodiment of the present application;

[0058] Fig.11 A schematic diagram of the structure of a second device provided in an embodiment of the present application;

[0059] Fig.12 A schematic diagram of the structure of a third second device provided in an embodiment of the present application;

[0060] Fig.13 A schematic structural diagram of the fourth second device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0061] The present application will be described in detail below with reference to the accompanying drawings.

[0062] In the communication service, when the data sender performs data transmission, in order to improve the data transmission efficiency and reduce the bit error rate, it is often necessary to convert the data format of the transmission data. For example, when the data sender and the data receiver use the CDR / Retimer system to perform data transmission, the FEC encoding technology is generally used to convert the data format of the transmission data. The data format conversion of the transmission data will generate a large delay jitter, wherein the delay jitter generated by the data format conversion is referred to as transmission delay in the embodiment of the present application.

[0063] For example, Figure 2As shown, it is assumed that during data transmission, the data at position A in the transmission data is used as the reference of the timestamp, that is, the sending device uses the sending time of the data at position A as the sending time of the transmission data.

[0064] Case 1: Data transmitted from the first device to the second device does not need to be converted into a data format.

[0065] For example, if the first device directly sends the data to be transmitted to the second device, the first device sends a sync message carrying the transmitted data to the second device, adds a timestamp to the transmitted data, and determines the data position of the data corresponding to the timestamp in the transmitted data and the first time of sending the data corresponding to the timestamp. The second device records the time of receiving the sync message as 1:10 (i.e., time T2).

[0066] Assuming that the first device determines that the sending time of the location A data is 1:00, the first device determines that the timestamp to be inserted into the follow_up message is 1:00 according to the sending time 1:00, that is, after the first device determines the sending time of the location A data, it generates a timestamp according to the sending time and carries the timestamp in the follow_up message. The first device sends the follow_up message to the second device. The second device receives the follow_up message and obtains the timestamp 1:00 (i.e., time T1) in the follow_up message.

[0067] Therefore, the second device can obtain the sum of the time difference Offset between the first device and the second device and the network transmission delay Delay according to the following formula 1 and the known T1 and T2. T2-T1=offset+Delay Formula 1

[0068] Wherein, by substituting T1 as 1:00 and T2 as 1:10 into the above formula 1, it can be determined that the sum of the Offset and the Delay is 10.

[0069] Among them, the "time stamp in the transmission data" described in the embodiment of the present application actually means that the first device generates a voucher document (i.e., a timestamp) after determining the sending time of the data at the location A, and the sending time of the data at the location A can be known through the timestamp. Further, the first device can record the voucher document (i.e., the timestamp) in the follow_up message, and send the follow_up message to the second device, so that the second device can obtain the sending time of the data at the location A.

[0070] It should be noted that the above explanation of "adding a timestamp to the transmission data" is not intended to be a limitation of the embodiments of the present application. In the communication transmission process, timestamps are often used to determine or prove the time when certain events occur, so those skilled in the art can understand the meaning of "adding a timestamp to the transmission data by the first device" in the embodiments of the present application.

[0071] Case 2: data transmitted from the first device to the second device needs to be converted into a data format.

[0072] For example, the first device sends a sync message carrying the transmission data to the second device through a conversion device (for example, the conversion device is a CDR / Retimer), wherein the transmission data undergoes data format conversion in the conversion device.

[0073] The first device determines the sending time of the transmission data (i.e., the data at the position A). Assuming that the sending time of the transmission data is 1:00, the first device determines that the timestamp to be inserted into the follow_up message is 1:00 according to the sending time 1:00. Then, the first device sends the follow_up message to the second device. The second device receives the follow_up message and obtains the timestamp 1:00 (i.e., time T1) in the follow_up message.

[0074] However, the transmission delay will occur when the data format conversion of the transmission data is performed by the conversion device. Assume that the transmission delay caused by the conversion device for the transmission data is 5 minutes. Therefore, the second device records the time of receiving the sync message as 1:15 (i.e., time T2).

[0075] Therefore, the second device can obtain the sum of the time difference Offset between the first device and the second device and the network transmission delay Delay according to the above formula 1 and the known T1 and T2.

[0076] Wherein, by substituting T1 as 1:00 and T2 as 1:15 into the above formula 1, it can be determined that the sum of the Offset and the Delay is 15.

[0077] Obviously, through the introduction of the above situation 1 and situation 2, it can be known that the sum of the Offset and the Delay determined in situation 2 is not the actual sum of the Offset and the Delay in the data transmission process between the first device and the second device. Therefore, the clock synchronization between the second device and the first device based on the Offset and Delay obtained in situation 2 will produce a large error and cannot achieve accurate clock synchronization.

[0078] Therefore, when the data to be transmitted needs to be processed in a data format, the prior art cannot accurately achieve clock synchronization between the first device and the second device, thereby reducing the data transmission efficiency between the first device and the second device.

[0079] FEC Algorithm port Check bit Uncertain transmission delay (ns) (528，514) 25 140 5.6 (528，514) 100 140 1.4 (544，514) 50 300 6 (544，514) 100 300 3 (544，514) 200 300 1.5 (544，514) 400 300 0.75

[0080] Table 1 Uncertain transmission delay caused by FEC coding

[0081] Among them, in order to solve the above problems, the embodiment of the present application provides a clock synchronization method. The technical solution of the embodiment of the present application can be applied to various communication systems, such as: long term evolution (LTE) system, worldwide interoperability for microwave access (WiMAX) communication system, future fifth generation (5G) system, such as new generation wireless access technology (NR), and future communication systems, such as 6G system.

[0082] Taking the 5G system (also known as the New Radio system) as an example, specifically, in order to accurately solve the problem of transmission delay caused by the data format conversion process, the transmission delay caused by the data format conversion of the transmission data is determined in the embodiment of the present application, and the transmission delay is compensated to the sending time of the first device sending data to the second device, such as the sending time T1. Through this method, when the second device performs clock synchronization with the first device, the sending time T1 used for clock synchronization is the compensated time, which has eliminated the transmission delay caused by the data format conversion of the transmission data, thereby effectively solving the impact of the data format conversion process of the transmission data on clock synchronization and improving the accuracy of time synchronization.

[0083] It should be noted that the time synchronization in the embodiments of the present application may also be referred to as clock synchronization.

[0084] Figure 3 Schematic diagram of a system architecture applicable to the embodiment of the present application. Figure 3 As shown, the system architecture includes one or more first devices 301, such as gNB, eNodeB or WLAN access point, one or more second devices 302, one or more conversion devices 303 (such as CDR / Retimer), and a core network 304.

[0085] In an embodiment of the present application, the first device 301 may include: a base transceiver station (Base TransceiverStation), a wireless transceiver, a basic service set (Basic Service Set, BSS), an extended service set (Extended Service Set, ESS), NodeB, eNodeB, gNB, etc.

[0086] The system architecture may include several different types of first devices 301, such as a macro base station, a micro base station, etc. The first device 301 may apply different wireless technologies, such as a cell wireless access technology or a WLAN wireless access technology.

[0087] The second device 302 may be a device with a wireless transceiver function, which may be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; may also be deployed on the water surface (such as a ship, etc.); may also be deployed in the air (such as an airplane, a balloon, and a satellite, etc.). The terminal device may be a mobile phone, a tablet computer, a computer with a wireless transceiver function, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal device in industrial control, a wireless terminal device in self-driving, a wireless terminal device in remote medical, a wireless terminal device in smart grid, a wireless terminal device in transportation safety, a wireless terminal device in smart city, a wireless terminal device in smart home, etc.

[0088] The core network device 304 can be a mobility management entity (MME) in an LTE system, or an access and mobility management function (AMF) network element and a session management function (SMF) network element in a 5G communication system, without specific limitation.

[0089] In the present application, the main Figure 3 The system architecture shown is used as an example for description, but is not limited to this.

[0090] The communication systems to which the above system architecture is applicable include but are not limited to: wideband code division multiple access (WCDMA) mobile communication system, evolved universal terrestrial radio access network (E-UTRAN) system, long term evolution (LTE) system, future fifth generation (5G) system, such as new radio access technology (NR), and future communication systems such as 6G system.

[0091] Some of the terms used in the embodiments of the present application are explained below for easier understanding.

[0092] 1) FEC is a coding technology, an error control method, and a method to increase the credibility of data communication. It mainly refers to the technology of encoding the signal according to a certain algorithm before it is sent to the transmission channel, adding redundant codes with the characteristics of the signal itself, and decoding the received signal according to the corresponding algorithm at the receiving end, so as to find out the error code generated in the transmission process and correct it.

[0093] 2) IEEE 1588 Precision Clock Synchronization Protocol for Network Measurement and Control Systems, referred to as Precision Timing Protocol (PTP), the main principle of which is to periodically calibrate and synchronize the clocks of all nodes in the network through a synchronization signal, so that the Ethernet-based distributed system can achieve precise synchronization, and has the characteristics of easy configuration, fast convergence, and low network bandwidth and resource consumption. Among them, the IEEE 1588 clock synchronization technology described in the embodiments of the present application can be applied to any multicast network.

[0094] 3) Messages are the data units exchanged and transmitted in the network, that is, the data blocks that a station wants to send at one time. Messages contain the complete data information to be sent, and their length is very inconsistent, unlimited and variable.

[0095] Among them, in the IEEE1588 time synchronization system, the messages mainly include sync synchronization messages, follow_up follow-up messages, delay_req delay request messages, delay_resp delay response messages, etc. The sync synchronization message is periodically sent from the master clock and contains a timestamp used to accurately describe the estimated sending time of the data packet sent by the master clock, wherein the estimated sending time is not the actual sending time.

[0096] The follow_up message is sent from the master clock after determining the real sending time of the sync message, and includes a time T1 used to accurately describe the real sending time T1 of the sync message sent by the master clock. The slave clock can determine the time difference (T2-T1) between the master clock and the slave clock according to the receiving time T2 of the sync message and the real sending time T1 in the follow_up message.

[0097] However, the time difference calculated at this time includes the delay caused by network transmission, so the Delay_Req message is used to define the network transmission delay.

[0098] The Delay_Req message is sent by the slave clock after the slave clock receives the Sync message. Like the Sync message, the sending slave clock records the accurate sending time T3 of the Delay_Req message, and the receiving master clock records the accurate receiving time T4 of the Delay_Req message. After receiving the Delay_Req message, the master clock records the accurate receiving time T4 of the Delay_Req message, and then carries T4 in the Delay_Resp message sent to the slave clock, and notifies the slave clock of T4 through the Delay_Resp message, so that the slave clock can calculate the network delay and clock error.

[0099] 4) Reed-solomon codes (RS) are a type of forward error correction channel coding that is effective for polynomials generated by correcting oversampled data. When the receiver correctly receives enough points, it can recover the original polynomial, even if many points on the received polynomial are distorted by noise interference.

[0100] 5) Retimer chip: It is mainly used to reconstruct the signal through the internal clock when the signal passes through the Retimer, so as to increase the signal transmission energy, and then continue to transmit, which can reduce the signal jitter.

[0101] 6) Timestamp is a complete and verifiable data that can indicate that a piece of data existed at a specific point in time. It mainly provides users with electronic evidence to prove the time when certain data of the user was generated.

[0102] Generally speaking, a timestamp is an encrypted credential document that consists of three parts: a summary of the file to be timestamped; the date and time the certification unit receives the file; and the certification unit's digital signature.

[0103] In addition, the term "at least one" in the embodiments of the present application refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. The following at least one item (items) or similar expressions refer to any combination of these items, including any combination of single items (items) or plural items (items). For example, at least one item (items) of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0104] Unless otherwise specified, ordinal numbers such as "first" and "second" in the embodiments of the present application are used to distinguish multiple objects and are not used to limit the order, timing, priority or importance of multiple objects.

[0105] In addition, the terms "including" and "having" in the embodiments, claims and drawings of the present application are not exclusive. For example, a process, method, system, product or device including a series of steps or modules is not limited to the listed steps or modules, and may also include steps or modules that are not listed.

[0106] Through the introduction of the above application scenarios in the embodiments of the present application, the process of clock synchronization based on the IEEE1588 protocol is specifically introduced below for the situation where data format conversion is required for transmitted data.

[0107] Among them, when the embodiment of the present application performs clock synchronization, the main method is to compensate the transmission delay generated during the data format conversion process of the data into the sending time, and then perform clock synchronization according to the compensated sending time. According to the different execution devices for compensation, it can be divided into multiple situations, which are introduced below.

[0108] Among them, it is assumed that the data at position A in the transmitted data is used as a reference in the embodiment of the present application, and for the convenience of subsequent introduction, the sending time of the first device sending data to the second device is represented as T1, the receiving time of the second device receiving the data is T2, the transmission delay caused by the data format conversion of the data is Δt, the data without data format processing is referred to as the first data, and the data obtained after the data format processing of the first data is referred to as the second data.

[0109] Compensation execution device 1: The first device compensates the transmission time T1 according to the transmission delay Δt generated in the process of performing data format conversion on the transmission data.

[0110] like Figure 4 As shown, when the execution device for compensation is the first device, the step of performing clock synchronization in the present application includes:

[0111] S400: The first device sends first data to the conversion device, and records the sending time T1 of sending the first data.

[0112] Among them, since the data at position A in the transmission data is used as a reference in the embodiment of the present application, it can be understood that the sending time T1 is specifically the time when the first device sends the data at position A in the first data.

[0113] Optionally, the first device may carry the first data via a sync message, that is, the first device sends a sync message carrying the first data to the conversion device.

[0114] S401: The conversion device performs data format conversion on the first data to generate second data.

[0115] S402: The conversion device sends the second data to a second device.

[0116] S403: The second device receives the second data and records the time T2 when the second data is received.

[0117] Among them, since the data at position A in the transmitted data is used as a reference in the embodiment of the present application, it can be understood that the receiving time T2 is specifically the time when the data at position A in the second data is received by the second device.

[0118] S404: The first device determines a delay jitter Δt generated in a data format conversion process according to the first data and the second data.

[0119] Further, the first device may determine the Δt according to a data transmission rate of the first data and a data transmission rate of the second data.

[0120] The first device may determine a data transmission rate of the first data according to the first data to be sent, and the first device may determine a transmission rate of the second data according to a rule for data conversion performed by the conversion device.

[0121] Optionally, in the embodiment of the present application, the first device may determine the transmission delay Δt according to a transmission rate of the first data and a transmission rate of the second data.

[0122] Among them, because the data at position A in the transmitted data is used as a reference in the embodiment of the present application, the Δt determined by the first device is the difference between the sending time of the data at position A in the first data and the sending time of the data at position A in the second data.

[0123] Exemplarily, in the embodiment of the present application, the data format conversion of the first data implemented by the FEC technology is selected for detailed introduction. It should be noted that other methods that can change the data format are also applicable to the embodiment of the present application.

[0124] like Figure 5As shown, it is assumed that, during the data transmission process, when the first device and the second device perform data transmission, the clock synchronization is performed based on the 3000th bit of the transmitted data. The first data format is RS (528, 514), and the data transmission rate based on the 100GE port is 4*25.78125Gbps; the second data format is RS (544, 514), and the data transmission rate based on the 100GE port is 4*26.5625Gbps; and the first data and the second data have the same sending start bit, for example, the first data start bit and the second data start bit are both bit0, then the delay jitter of the first data start bit and the second data start bit is 0.

[0125] Among them, the delay jitter caused by data format conversion of the 3000th bit of the transmission data can be determined according to the following formula 2.

[0126] Δt(bitX)=(A) / Y(Gbps)-(A) / Z(Gbps) Formula 2

[0127] In the above formula 2, Y (Gbps) represents the data transmission rate of the first data, Z (Gbps) represents the data transmission rate of the second data, X represents the bit used as the timestamp reference, and A represents the number of bits corresponding to the bits 0 to X. For example, when the bit is bit0, A represents data with a length of 1 bit; when the bit is bit1, A represents data with a length of 2 bits; when the bit is bit3000, A represents data with a length of 3001 bits; Δt represents the delay jitter caused by the data format conversion of the first data.

[0128] Therefore, based on the above formula 2, it can be obtained that Δt(bit3000)=(3001) / 4 / 25.78125Gbps-(3001) / 4 / 26.5625Gbps=0.855ps.

[0129] It should be noted that, in addition to the above-mentioned method for determining the transmission delay caused by the data format conversion during the transmission data, any method for determining the transmission delay caused by the transmission data format conversion applicable to the embodiments of the present application falls within the scope of protection of the present application.

[0130] Furthermore, the first device also determines the direction of the Δt, that is, whether the Δt is positive or negative, so as to determine whether the delay is increased or reduced after the data format processing according to the direction of the Δt.

[0131] S405: The first device compensates the T1 according to Δt to obtain the second time T1′.

[0132] Among them, if the direction of Δt is right, that is, Δt is a positive value, it means that Δt is the transmission delay increased based on the first data sending, and T1′=T1+Δt; if the direction of Δt is left, that is, Δt is a negative value, it means that Δt is the transmission delay reduced based on the first data sending, and T1′=T1-Δt.

[0133] For example, Figure 6 As shown, when the transmission data sent by the first device to the second device needs to be converted into a data format, assuming that the transmission delay Δt determined by the first device is increased by 5ns, the first device sends a sync message to the second device through the conversion device at 1:00 (i.e., T1). The second device receives the sync message at 1:15 (i.e., T2).

[0134] The first device compensates the T1 according to the Δt to obtain the T1′, that is, T1′=1:00+0:05=1:05.

[0135] Similarly, when the transmission data sent by the first device to the second device needs to be converted into a data format, assuming that the first device determines that the generated transmission delay Δt is reduced by 2ns, the first device sends a sync message to the second device through the conversion device at 1:02 (i.e., T1). The second device receives the sync message at 1:00 (i.e., T2).

[0136] The first device compensates the T1 according to the Δt to obtain the T1′, that is, T1′=1:02-0:02=1:00.

[0137] S406: The first device sends a first message (eg, a follow_up message) to the second device, wherein the first message is used to indicate the second time T1′.

[0138] Optionally, in the embodiment of the present application, the above step S404 can be omitted, that is, the first device does not need to compensate the T1 according to the Δt to obtain the second time T1′. The first device can directly carry the T1 and the Δt in the first message and send it to the second device, so that after the second device obtains the first message, it can determine T1′ according to the T1 and the Δt in the first message.

[0139] S407: The second device receives the first message, and obtains the T1′ in the first message.

[0140] Optionally, if the information carried in the first message is the T1 and the Δt, after the second device obtains the first message, it determines T1′ by itself according to the T1 and the Δt in the first message.

[0141] S408: The second device sends a second message (eg, a Delay_Req message) to the first device, and records a sending time T3 of the second message.

[0142] S409: The first device receives the second message and records the time T4 when the second message is received.

[0143] S410: The first device sends a third message (eg, a delay_resp message) to the second device, where the third message includes the T4.

[0144] S411, the second device receives the third message, and obtains the T4 in the third message.

[0145] S412: The second device performs clock synchronization with the first device according to T1′, T2, T3, and T4.

[0146] For example, in the embodiment of the present application, when the first device and the second device achieve time synchronization through the IEEE1588 protocol, it is necessary to determine the time difference Offset and the path transmission delay Delay between the first device and the second device, so that the second device can achieve time synchronization with the first device based on the calculated time difference Offset and the path transmission delay Delay.

[0147] The second device performs calculation according to the following formula 3 and formula 4:

[0148] T2-T1=offset+Delayms Formula 3

[0149] T4-T3=-offset+Delaysm Formula 4

[0150] Among them, T2 in Formula 3 represents the time when the second device receives the transmission data sent by the first device, T1 represents the time when the first device actually sends the transmission data, offset represents the time difference between the devices during the communication between the first device and the second device, and Delayms represents the network path transmission delay when the first device transmits data to the second device.

[0151] In Formula 4, T3 represents the time when the second device sends a delay request message to the first device, T4 represents the time when the first device receives the delay request message, -offset represents the time difference between the devices during the communication and transmission process between the second device and the first device, and Delaysm represents the network path transmission delay when the second device transmits data to the first device.

[0152] Because the transmission data to be sent has undergone data format conversion, the Δt still exists. Then, the sending time of the transmission data calculated by the second device by substituting it into Formula 3 should be the compensated time, that is, T1′.

[0153] After the second device substitutes T1′, T2, T3, and T4 into Formula 3 and Formula 4, Formula 5 can be obtained.

[0154] Offset=[(T2-T1′)-(T4-T3)-(Delayms-Delaysm)] / 2 Formula 5

[0155] Among them, a transmission delay Δt will also be generated during the actual data transmission process. Since the T1 is compensated in advance according to the Δt in the embodiment of the present application, the interference of the Δt on the clock synchronization can be reduced when the clock synchronization is performed later in the embodiment of the present application.

[0156] For example, when output transmission is performed in the prior art, Offset includes Δt, as shown in the following formula 6:

[0157] Offset=[(T2-T1)-(T4-T3)-(Delayms+Δt-Delaysm)] / 2 Formula 6

[0158] The Offset obtained in this application is shown in the following formula 7:

[0159] Offset=[(T2-T1′)-(T4-T3)-(Delayms+Δt-Delaysm)] / 2 Formula 7

[0160] Furthermore, since T1′=T1+Δt, according to the above formula 7, the Offset obtained by the present application is:

[0161] Offset=[(T2-T1+Δt)-(T4-T3)-(Delayms+Δt-Delaysm)] / 2

[0162] =[(T2-T1)-(T4-T3)-(Delayms-Delaysm)] / 2

[0163] Therefore, the embodiment of the present application can ensure that the clock of the second device is accurately synchronized without any other precision loss by compensating the sending time T1.

[0164] Furthermore, in an embodiment of the present application, when the first device transmits data to the second device, the alignment mark (AM) in the data and the data in the second data remain unchanged relative to each other during the transmission process, that is, the first device transparently transmits the data to be transmitted to the second device.

[0165] Among them, when the transmitted data undergoes data format conversion, the network path transmission delay mainly includes the path delay d and the transmission delay Δt generated during the data format conversion process. When the first device transparently transmits the transmission data to the second device, the relative position of the data in the FEC codeword is fixed, so the path delay d is also fixed. Therefore, during the data transmission process, only the fixed path delay d of the path transmission needs to be determined, so that the accuracy of the second device in synchronizing the clock of the first device can be effectively guaranteed.

[0166] It should be noted that in the embodiments of this application Figure 4 In the interactive process shown, the order of certain steps is not limited, for example, S404 can be executed before S402.

[0167] Compensation execution device 2: The second device compensates the sending time T1 according to the transmission delay Δt generated in the data format conversion process of the data.

[0168] like Figure 7 As shown, when the execution device for compensation is the second device, the step of performing clock synchronization in the present application includes:

[0169] S700: The first device sends first data to the conversion device, and records the time T1 of sending the first data.

[0170] S701: The conversion device performs data format processing on the first data to generate second data.

[0171] S702: The conversion device sends the second data to a second device.

[0172] S703: The second device receives the second data and records the time T2 when the second data is received.

[0173] S704: The second device determines a transmission delay generated during a format conversion process of the data of the second data recording timestamp.

[0174] Optionally, in the embodiment of the present application, after the second device obtains the second data, it can determine the first data according to the data format conversion rule of the conversion device and the second data, and then determine the transmission delay Δt according to the first data and the second data.

[0175] The specific method of determining the transmission delay Δt is described in S404 above, which will not be described in detail here.

[0176] Furthermore, the first device also determines the direction of the Δt, that is, whether the Δt is positive or negative, so as to determine whether the delay is increased or reduced after the data format processing according to the direction of the Δt.

[0177] S705: The first device sends a first message (eg, a follow_up message) to the second device, wherein the first message is used to indicate the T1.

[0178] S706: The second device receives the first message, and obtains the T1 in the first message.

[0179] S707: The second device compensates the T1 according to the Δt to determine a compensated T1′.

[0180] S708: The second device sends a second message (eg, a Delay_Req message) to the first device, and records a sending time T3 of the second message.

[0181] S709: The first device receives the second message and records the time T4 when the second message is received.

[0182] S710: The first device sends a third message (eg, a delay_resp message) to the second device, where the third message includes the T4.

[0183] S711: The second device receives the third message, and obtains the T4 in the third message.

[0184] S712: The second device performs clock synchronization with the first device according to T1′, T2, T3, and T4.

[0185] The specific clock synchronization method is detailed in the above step S412 and will not be described in detail here.

[0186] It should be noted that in the embodiments of this application Figure 7 In the interactive process shown, the order of certain steps is not limited. For example, S704 can be executed before S702.

[0187] Through the above introduction to the scheme of the present application, it can be understood that in order to realize the above functions, the above-mentioned implementation devices include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present invention can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0188] Based on the above embodiments, Figure 8 As shown, a first device for clock synchronization provided by the present application includes a processor 800 , a memory 801 and a communication interface 802 .

[0189] The processor 800 is responsible for managing the bus architecture and general processing, and the memory 801 can store data used by the processor 800 when performing operations. The transceiver communication interface 802 is used to receive and send data under the control of the processor 800 to perform data communication with the memory 801.

[0190] The processor 800 may be a central processing unit (CPU), a network processor (NP) or a combination of a CPU and a NP. The processor 800 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The memory 701 may include various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0191] The processor 800, the memory 801 and the communication interface 802 are interconnected. Optionally, the processor 800, the memory 801 and the communication interface 802 can be interconnected via a bus 803; the bus 803 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0192] Specifically, the processor 800 is used to read the program in the memory 801 and execute:

[0193] Send the first data, add a timestamp to the first data, and determine the data position of the data corresponding to the timestamp in the first data, as well as the first time of sending the data corresponding to the timestamp; determine the transmission delay generated by the data at the data position during the format conversion process according to the data position; send a first message to the second device, the first message is used to indicate a second time, and the second time is the time after compensating the first time according to the transmission delay; receive a second message sent by the second device at a third time; send a third message to the second device, the third message includes the third time, so that the second device synchronizes the clock with the first device according to the second time, the third time and the fourth time of sending the second message.

[0194] In a possible implementation method, the first message includes the first time and the transmission delay, so that the second device compensates the first time according to the transmission delay to obtain the second time; or the first message includes the second time.

[0195] In a possible implementation, the first message is a follow_up message; the second message is a delay request Delay_req message; and the third message is a delay response Delay_Resp message.

[0196] In a possible implementation method, during the transmission of the second data, a relative position between an alignment mark in the second data and data in the second data remains unchanged.

[0197] like Fig. 9As shown, the present invention provides a first device for clock synchronization, the device comprising: a processing unit 900 and a communication unit 901:

[0198] The communication unit 901 is used to send the first data;

[0199] The processing unit 900 is used to add a timestamp to the first data, and determine a data position of the data corresponding to the timestamp in the first data, and a first time of sending the data corresponding to the timestamp; and determine, according to the data position, a transmission delay generated by the data at the data position during the format conversion process;

[0200] The communication unit 901 is used to send a first message to the second device, where the first message is used to indicate a second time, and the second time is the time after the first time is compensated according to the transmission delay; receive a second message sent by the second device at a third time; and send a third message to the second device, where the third message includes the third time, so that the second device synchronizes the clock with the first device according to the second time, the third time and the fourth time of sending the second message.

[0201] like Fig.10 As shown, an embodiment of the present application further provides a second clock synchronization device, which includes a processor 1000, a memory 1001 and a communication interface 1002.

[0202] The processor 1000 is responsible for managing the bus architecture and general processing, and the memory 1001 can store data used by the processor 1000 when performing operations. The transceiver communication interface 1002 is used to receive and send data under the control of the processor 1000 to perform data communication with the memory 1001.

[0203] The processor 1000 may be a central processing unit (CPU), a network processor (NP) or a combination of a CPU and a NP. The processor 1000 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The memory 1001 may include various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0204] The processor 1000, the memory 1001 and the communication interface 1002 are interconnected. Optionally, the processor 1000, the memory 1001 and the communication interface 1002 can be interconnected via a bus 1003; the bus 1003 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.10 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0205] Specifically, the processor 1000 is used to read the program in the memory 1001 and execute:

[0206] Receive second data sent by a conversion device; receive a first message sent by the first device, the first message is used to indicate a second time; the second time is the time after compensating the first time according to a transmission delay, the transmission delay is generated during the format conversion process of the data with a timestamp in the first data, and the first time is the sending time of the data corresponding to the timestamp sent by the first device; send a second message to the first device at a fourth time; the second device receives a third message sent by the first device, the third message includes a third time when the first device receives the second message; and perform clock synchronization with the first device according to the second time, the third time and the fourth time.

[0207] In a possible implementation manner, the processor 1000 is further configured to:

[0208] The second device determines the second time according to the transmission delay included in the first message and the first time.

[0209] In a possible implementation, the first message is a follow_up message; the second message is a delay request Delay_req message; and the third message is a delay response Delay_Resp message.

[0210] In a possible implementation manner, during the transmission of the second data, a relative position between an alignment mark in the second data and data in the second data remains unchanged.

[0211] like Fig.11 As shown, the present invention provides a second device for clock synchronization, the device comprising: a processing unit 1100 and a communication unit 1101:

[0212] The communication unit 1101 is configured to receive second data sent by a conversion device; receive a first message sent by the first device, the first message being used to indicate a second time; the second time being the time after the first time is compensated according to a transmission delay, the transmission delay being generated during a format conversion process of the data with a timestamp in the first data, the first time being the time when the first device sends the data corresponding to the timestamp; send a second message to the first device at a fourth time; receive a third message sent by the first device, the third message including a third time when the first device receives the second message;

[0213] The processing unit 1100 is configured to perform clock synchronization with the first device according to the second time, the third time, and the fourth time.

[0214] like Fig.12As shown, an embodiment of the present application further provides another clock-synchronized second device, which includes a processor 1200 , a memory 1201 , and a communication interface 1202 .

[0215] The processor 1200 is responsible for managing the bus architecture and general processing, and the memory 1201 can store data used by the processor 1200 when performing operations. The transceiver communication interface 1202 is used to receive and send data under the control of the processor 1200 to perform data communication with the memory 1201.

[0216] The processor 1200 may be a central processing unit (CPU), a network processor (NP) or a combination of a CPU and a NP. The processor 1200 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The memory 1201 may include various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0217] The processor 1200, the memory 1201 and the communication interface 1202 are interconnected. Optionally, the processor 1200, the memory 1201 and the communication interface 1202 can be interconnected via a bus 1203; the bus 1203 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.12 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0218] Specifically, the processor 1200 is used to read the program in the memory 1201 and execute:

[0219] Receive second data sent by a conversion device; determine a transmission delay generated by the data with a timestamp in the second data during the format conversion process; receive a first message sent by the first device, the first message including the first time; send a second message to the first device at a fourth time; receive a third message sent by the first device, the third message including a third time when the first device receives the second message; and synchronize the clock with the first device based on the first time, the transmission delay, the third time and the fourth time.

[0220] In a possible implementation manner, the processor 1200 is further configured to:

[0221] The second device compensates the first time according to the transmission delay to obtain a second time; the second device performs clock synchronization with the first device according to the second time, the third time, and the fourth time.

[0222] In a possible implementation, the first message is a follow_up message; the second message is a delay request Delay_req message; and the third message is a delay response Delay_Resp message.

[0223] In a possible implementation manner, during the transmission of the second data, a relative position between an alignment mark in the second data and data in the second data remains unchanged.

[0224] like Fig.13 As shown, another first clock synchronization device provided by the present invention includes: a processing unit 1300 and a communication unit 1301:

[0225] The communication unit 1301 is used to receive second data sent by the conversion device;

[0226] The processing unit 1300 is used to determine the transmission delay of the data with the timestamp in the second data during the format conversion process;

[0227] The communication unit 1301 is used to receive a first message sent by the first device, the first message including the first time; send a second message to the first device at a fourth time; receive a third message sent by the first device, the third message including the third time when the first device receives the second message; and perform clock synchronization with the first device based on the first time, the transmission delay, the third time and the fourth time.

[0228] In some possible implementations, various aspects of the clock synchronization method provided by an embodiment of the present invention may also be implemented in the form of a program product, which includes a program code. When the program code is run on a computer device, the program code is used to enable the computer device to execute the steps of the clock synchronization method according to various exemplary embodiments of the present invention described in this specification.

[0229] The program product may adopt any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. Examples of readable storage media in one implementation of the present application embodiment (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0230] The program product for clock synchronization according to an embodiment of the present invention may be a portable compact disk read-only memory (CD-ROM) and include program code, and may be run on a server device. However, the program product of the present invention is not limited thereto, and in this document, a readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with information transmission, an apparatus or a device.

[0231] The readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, wherein the readable program code is carried. Such propagated data signals may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination of the above. The readable signal medium may also be any readable medium other than a readable storage medium, which may transmit, propagate, or transfer a program for use by or in conjunction with a periodic network action system, apparatus, or device.

[0232] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0233] Program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device.

[0234] The embodiment of the present application also provides a computing device readable storage medium for the clock synchronization method, that is, the content is not lost after power failure. The storage medium stores a software program, including program code, and when the program code is run on the computing device, the software program can implement any of the clock synchronization solutions in the embodiment of the present application when read and executed by one or more processors.

[0235] The present application is described above with reference to the block diagrams and / or flow charts showing the methods, devices (systems) and / or computer program products according to the embodiments of the present application. It should be understood that a block of the block diagram and / or flow chart diagram and a combination of blocks of the block diagram and / or flow chart diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer and / or other programmable data processing device to produce a machine, so that the instructions executed by the computer processor and / or other programmable data processing device create a method for implementing the functions / actions specified in the block diagram and / or flow chart block.

[0236] Accordingly, the present application may also be implemented with hardware and / or software (including firmware, resident software, microcode, etc.). Furthermore, the present application may take the form of a computer program product on a computer-usable or computer-readable storage medium, which has a computer-usable or computer-readable program code implemented in the medium, for use by an instruction execution system or in conjunction with an instruction execution system. In the context of the present application, a computer-usable or computer-readable medium may be any medium that may contain, store, communicate, transmit, or convey a program for use by an instruction execution system, device, or apparatus, or in conjunction with an instruction execution system, device, or apparatus.

[0237] Although the present application has been described in conjunction with specific features and embodiments thereof, it is obvious that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely exemplary illustrations of the present application as defined by the appended claims, and are deemed to have covered any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, a person skilled in the art may make various modifications and variations to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A clock synchronization method, used in a network environment consisting of a first device, a conversion device and a second device, wherein the conversion device is used to convert the format of first data of the first device to obtain second data, and send the second data to the second device, characterized in that: The method includes: The first device sends the first data, adds a timestamp to the first data, and determines a data position of data corresponding to the timestamp in the first data, and a first time of sending the data corresponding to the timestamp; The first device determines, according to the data position, a transmission delay generated during format conversion of the data at the data position; The first device sends a first message to the second device, where the first message is used to indicate a second time, where the second time is a time after the first time is compensated according to the transmission delay; The first device receives a second message sent by the second device at a third time; The first device sends a third message to the second device, where the third message includes the third time, so that the second device performs clock synchronization with the first device according to the second time, the third time, and a fourth time of sending the second message; The first device determines, according to the data position, a transmission delay generated by the data at the data position during the format conversion process, including: The first device determines a transmission delay generated by the data at the data location during a format conversion process according to the data location, a data transmission rate of the first data, and a data transmission rate of the second data.

2. The method according to claim 1, characterized in that: The first message is used to indicate a second time, including: The first message includes the first time and the transmission delay, so that the second device compensates the first time according to the transmission delay to obtain a second time; or The first message includes the second time.

3. The method according to claim 1 or 2, characterized in that: The first message is a follow_up message; the second message is a delay request Delay_req message; and the third message is a delay response Delay_Resp message.

4. The method according to claim 1 or 2, characterized in that: During the transmission of the second data, the relative position of the alignment mark in the second data and the data in the second data remains unchanged.

5. A clock synchronization method, used in a network environment consisting of a first device, a conversion device and a second device, wherein the conversion device is used to convert the format of first data of the first device to obtain second data, and send the second data to the second device, characterized in that: The method includes: The second device receives the second data sent by the conversion device; The second device receives a first message sent by the first device, where the first message is used to indicate a second time; the second time is a time after the first time is compensated according to a transmission delay, where the transmission delay is generated during a format conversion process of the data with a timestamp in the first data, and the transmission delay is determined by a data transmission rate of the first data and a data transmission rate of the second data, and the first time is a sending time of the data corresponding to the timestamp sent by the first device; The second device sends a second message to the first device at a fourth time; The second device receives a third message sent by the first device, where the third message includes a third time when the first device receives the second message; The second device performs clock synchronization with the first device according to the second time, the third time and the fourth time.

6. The method according to claim 5, characterized in that Before the second device performs clock synchronization with the first device according to the second time, the third time and the fourth time, the second device further includes: The second device determines the second time according to the transmission delay included in the first message and the first time.

7. The method according to claim 5 or 6, characterized in that: The first message is a follow_up message; the second message is a delay request Delay_req message; and the third message is a delay response Delay_Resp message.

8. The method according to claim 5 or 6, characterized in that: During the transmission of the second data, the relative position of the alignment mark in the second data and the data in the second data remains unchanged.

9. A clock synchronization method, used in a network environment consisting of a first device, a conversion device and a second device, wherein the conversion device is used to convert the format of first data of the first device to obtain second data, and send the second data to the second device, characterized in that: The method includes: The second device receives the second data sent by the conversion device; The second device determines a transmission delay generated during format conversion of the data with the timestamp in the second data; The second device receives a first message sent by the first device, where the first message includes a first time, and the first time is a sending time when the first device sends the data corresponding to the timestamp; The second device sends a second message to the first device at a fourth time; The second device receives a third message sent by the first device, where the third message includes a third time when the first device receives the second message; The second device performs clock synchronization with the first device according to the first time, the transmission delay, the third time, and the fourth time; The second device determines a transmission delay generated during a format conversion process of the data with a timestamp in the second data, including: The second device determines, according to the data transmission rate of the first data and the data transmission rate of the second data, a transmission delay generated during the format conversion process of the data with a timestamp in the second data.

10. The method according to claim 9, characterized in that The second device performs clock synchronization with the first device according to the first time, the transmission delay, the third time and the fourth time, including: The second device compensates the first time according to the transmission delay to obtain a second time; The second device performs clock synchronization with the first device according to the second time, the third time, and the fourth time.

11. The method according to claim 9 or 10, characterized in that: The first message is a follow_up message; the second message is a delay request Delay_req message; and the third message is a delay response Delay_Resp message.

12. The method according to claim 9 or 10, characterized in that: During the transmission of the second data, the relative position of the alignment mark in the second data and the data in the second data remains unchanged.

13. A communication device, characterized in that: include: a processing unit and a communication unit; The communication unit is used to send first data; The processing unit is used to add a timestamp to the first data, determine a data position of the data corresponding to the timestamp in the first data, and a first time of sending the data corresponding to the timestamp; and determine, according to the data position, a transmission delay generated by the data at the data position during the format conversion process; The communication unit is used to send a first message to a second device, where the first message is used to indicate a second time, where the second time is a time after the first time is compensated according to the transmission delay; receiving a second message sent by the second device at a third time; Sending a third message to the second device, where the third message includes the third time, so that the second device performs clock synchronization with the first device according to the second time, the third time, and a fourth time of sending the second message; The processing unit is specifically used for: The transmission delay of the data at the data position during the format conversion process is determined based on the data position, the data transmission rate of the first data, and the data transmission rate of the second data, wherein the second data is obtained by format conversion of the first data by a conversion device.

14. A communication device, characterized in that: include: a processing unit and a communication unit; The communication unit is used to receive second data sent by the conversion device; receiving a first message sent by a first device, where the first message is used to indicate a second time; The second time is a time after compensating the first time according to a transmission delay, the transmission delay is generated during a format conversion process of data with a timestamp in the first data, the transmission delay is determined by a data transmission rate of the first data and a data transmission rate of the second data, and the first time is a sending time of the data corresponding to the timestamp sent by the first device; Sending a second message to the first device at a fourth time; receiving a third message sent by the first device, the third message including a third time when the first device receives the second message; The processing unit is configured to perform clock synchronization with the first device according to the second time, the third time and the fourth time.

15. A communication device, characterized in that: include: a processing unit and a communication unit; The communication unit is used to receive second data sent by the conversion device; The processing unit is used to determine the transmission delay of the data with the timestamp in the second data during the format conversion process; The communication unit is configured to receive a first message sent by a first device, where the first message includes a first time, where the first time is a sending time when the first device sends the data corresponding to the timestamp; Sending a second message to the first device at a fourth time; receiving a third message sent by the first device, the third message including a third time when the first device receives the second message; performing clock synchronization with the first device according to the first time, the transmission delay, the third time and the fourth time; The processing unit is specifically used for: According to the data transmission rate of the first data and the data transmission rate of the second data, the transmission delay generated by the data with a timestamp in the second data during the format conversion process is determined, and the second data is obtained after the first data sent by the first device is format converted by the conversion device.

16. A communication device, characterized in that: include: one or more processors; Memory; one or more programs; The one or more programs are stored in the memory, and the one or more programs include instructions. When the instructions are executed by the processor, the communication device executes the method according to any one of claims 1 to 4.

17. A communication device, characterized in that: include: one or more processors; Memory; one or more programs; The one or more programs are stored in the memory, and the one or more programs include instructions. When the instructions are executed by the processor, the communication device executes the method according to any one of claims 5 to 12.

18. A clock synchronization system, characterized in that: include: A first device, a second device, and a conversion device; The first device is used to execute the method according to any one of claims 1 to 4; The second device is used to execute the method according to any one of claims 5 to 12; The conversion device is used to convert the format of the first data of the first device to obtain second data, and send the second data to the second device.

19. A computer-readable storage medium, characterized in that: The method comprises computer instructions, which, when executed on a first device, cause the first device to execute the method as claimed in any one of claims 1 to 4.

20. A computer-readable storage medium, characterized in that: The method comprises computer instructions, which, when executed on a second device, cause the second device to execute the method as claimed in any one of claims 5 to 12.

Images