Memory access method and device, computing device and storage medium

Abstract

The present invention provides a memory access method and apparatus, a computing device, and a storage medium, wherein the memory access method includes: determining a target operator, splitting the target operator according to a preset parameter quantity to obtain a split operator, determining memory resources of multiple parameters in the split operator, determining first memory block information and second memory block information of the determined parameters according to the memory resources, generating a target information set according to the first memory block information and the second memory block information, wherein the target information set includes target memory block information, determining a memory access instruction set according to the target information set, and accessing memory according to the memory access instruction set. By determining the first memory block information and the second memory block information according to the memory resources of multiple parameters in the split operator, and generating and determining the memory access instruction set according to the first memory block information and the second memory block information to access the memory, instruction density is improved.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a memory access method. Background Art

[0002] At present, the number of parameters in deep neural networks is getting larger and larger, reaching tens of megabytes or even hundreds of megabytes. Even after quantization, the number of parameters is still very large, which poses a great challenge to the bandwidth design of the NPU, making it difficult for the NPU bandwidth to keep up with its computing speed, which greatly limits the reasoning ability of the NPU.

[0003] The memory (cache) design of existing NPUs is generally designed to be divided into multiple blocks (memory blocks), and then the read and write operations on each memory block are mutually exclusive in time and cannot be performed at the same time. Therefore, the NPU also uses a pipeline design similar to that of modern CPUs to provide a solution. At the same time, in order to reduce the length of instructions, only the memory block IDs for instruction synchronization are allowed to synchronize different instruction queues. In this way, the software must make full use of this feature when generating instructions, and split the operator parameter loading instructions and operator calculation instructions as much as possible to ensure the pipeline writing and reading of neural network parameters on different memory blocks. The existing method NPU has a low instruction parallel density, so that the reasoning ability of the NPU is low. Summary of the Invention

[0004] In view of this, the present invention provides a memory access method. One or more embodiments of the present invention also relate to a memory access device, a computing device, a computer-readable storage medium, and a computer program to address technical deficiencies in the prior art.

[0005] According to a first aspect of the present invention, there is provided a memory access method, comprising:

[0006] Determine the target operator, and split the target operator according to the preset parameter amount to obtain the split operator;

[0007] Determine the memory resources for multiple parameters in the split operator;

[0008] Determine first memory block information and second memory block information with parameters according to the memory resource;

[0009] generating a target information set according to the first memory block information and the second memory block information, wherein the target information set includes target memory block information;

[0010] A memory access instruction set is determined according to the target information set, and the memory is accessed according to the memory access instruction set.

[0011] In a possible implementation, splitting the target operator according to the preset parameter amount to obtain the split operator includes:

[0012] The target operator is split according to the preset parameter quantity of the computing unit of the target hardware to obtain the split operators.

[0013] In one possible implementation, determining memory resources for multiple parameters in a split operator includes:

[0014] Allocate at least one memory block resource for each parameter in the split operator.

[0015] In one possible implementation, determining the first memory block information and determining the second memory block information of the parameter according to the memory resource includes:

[0016] Generate a first mask and first identification information according to the memory block resources corresponding to each parameter in the split operator, wherein the bits in the first mask correspond to the memory block resources;

[0017] A second mask and second identification information corresponding to each parameter is generated according to the memory block resources corresponding to the parameter.

[0018] In a possible implementation, generating a target information set according to the first memory block information and the second memory block information includes:

[0019] Traverse the second mask, calculate the first mask and the current second mask according to the preset rules, and obtain the target memory block information;

[0020] When the traversal is completed, all target memory block information constitutes a target information set.

[0021] In one possible implementation, determining a memory access instruction set according to a target information set includes:

[0022] Traverse the target information set and determine the target memory block according to the target memory block information;

[0023] Generate instruction information according to the target memory block;

[0024] Generate memory access instructions according to instruction information;

[0025] When the traversal is completed, all memory access instructions constitute a memory access instruction set.

[0026] In one possible implementation, accessing memory according to a memory access instruction set includes:

[0027] The execution identifier of the memory access instruction at a set position in the memory access instruction set is configured into the computing instruction, so that the memory is accessed based on the memory access instruction in the memory access instruction set.

[0028] According to a second aspect of the present invention, there is provided a memory access device, comprising:

[0029] A splitting module is configured to determine a target operator and split the target operator according to a preset parameter to obtain a split operator;

[0030] a resource allocation module configured to determine memory resources for a plurality of parameters in a split operator;

[0031] an information determination module, configured to determine first memory block information and second memory block information with determined parameters according to memory resources;

[0032] a target information determination module, configured to generate a target information set based on the first memory block information and the second memory block information, wherein the target information set includes target memory block information;

[0033] The instruction generation module is configured to determine a memory access instruction set according to target memory block information and access the memory according to the memory access instruction set.

[0034] According to a third aspect of the present invention, there is provided a computing device comprising:

[0035] memory and processor;

[0036] The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the above-mentioned memory access method are implemented.

[0037] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, which stores computer-executable instructions, and when the instructions are executed by a processor, the steps of the above-mentioned memory access method are implemented.

[0038] According to a fifth aspect of the present invention, a computer program is provided, wherein when the computer program is executed in a computer, the computer is caused to execute the steps of the above-mentioned memory access method.

[0039] The present invention provides a memory access method and device, wherein the memory access method includes: determining a target operator, splitting the target operator according to a preset parameter quantity to obtain a split operator, determining memory resources of multiple parameters in the split operator, determining first memory block information and second memory block information of the determined parameters according to the memory resources, generating a target information set according to the first memory block information and the second memory block information, wherein the target information set includes target memory block information, determining a memory access instruction set according to the target information set, and accessing memory according to the memory access instruction set. By determining the first memory block information and the second memory block information of the determined parameters by the memory resources of multiple parameters in the split operator, generating and determining the memory access instruction set according to the first memory block information and the second memory block information to access the memory, the instruction density is improved, thereby improving the reasoning capability of the NPU. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is a flow chart of a memory access method provided by an embodiment of the present invention;

[0041] Figure 2 This is a queue diagram of a memory access method provided by an embodiment of the present invention;

[0042] Figure 3 This is a flow chart of a processing process of a memory access method provided by an embodiment of the present invention;

[0043] Figure 4 It is a structural diagram of a memory access device provided by an embodiment of the present invention;

[0044] Figure 5 It is a structural block diagram of a computing device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The following description sets forth numerous specific details to facilitate a thorough understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific implementations disclosed below.

[0046] The terms used in one or more embodiments of the present invention are for the purpose of describing specific embodiments only and are not intended to limit one or more embodiments of the present invention. The singular forms "a", "an", "the" used in one or more embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used in one or more embodiments of the present invention refers to and includes any or all possible combinations of one or more associated listed items.

[0047] It should be understood that although the terms first, second, etc. may be used to describe various information in one or more embodiments of the present invention, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of one or more embodiments of the present invention, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0048] First, the terms involved in one or more embodiments of this specification are explained.

[0049] Mask: A mask is a string of binary codes that performs a bitwise AND operation on the target field to mask the current input bit.

[0050] Memory: It is one of the important components of a computer, also known as internal memory and main memory. It is used to temporarily store calculation data in the CPU and exchange data with external memory such as hard disk.

[0051] Embedded neural network processor (NPU): adopts the "data-driven parallel computing" architecture and is particularly good at processing massive multimedia data such as videos and images.

[0052] A data structure is a collection of data elements that have one or more specific relationships with each other.

[0053] ID (Identity document) is an abbreviation for various proprietary terms such as identity card identification number, account number, unique code, exclusive number, industrial design, country abbreviation, legal term, universal account, decoder, software company, etc.

[0054] A linked list is a non-continuous and non-sequential storage structure on a physical storage unit. The logical order of data elements is achieved through the link order of pointers in the linked list.

[0055] In this invention specification, a memory access method is provided. The invention specification also relates to a memory access device, a computing device, and a computer-readable storage medium, which are described in detail one by one in the following embodiments.

[0056] See also Figure 1 , Figure 1 A flowchart of a memory access method provided according to an embodiment of the present invention is shown, which specifically includes the following steps.

[0057] Step 102: Determine the target operator, and split the target operator according to preset parameters to obtain split operators.

[0058] In a possible implementation, splitting the target operator according to the preset parameter amount to obtain the split operator includes:

[0059] The target operator is split according to the preset parameter quantity of the computing unit of the target hardware to obtain the split operators.

[0060] For example, see Figure 2 , create an empty queue Q, whose required element e is a data structure S, which contains an integer n and n pairs of masks and ids. The operator is split according to the minimum parameter quantity required by the calculation unit of the NPU operator. For example, the calculation unit is divided into block granularity along the channel direction. In this way, the original operator can be divided into multiple corresponding operators according to the minimum granularity along the channel direction, and the corresponding parameter quantities are also divided accordingly. This can change the original operator calculation process from loading large parameters and calculating large operators to a continuous pipeline operation of loading multiple small parameters and calculating small operators. The process of loading the parameters of the next small operator is parallel to the calculation of the current small operator.

[0061] Step 104: Determine memory resources for multiple parameters in the split operator.

[0062] In one possible implementation, determining memory resources for multiple parameters in a split operator includes:

[0063] Allocate at least one memory block resource for each parameter in the split operator.

[0064] Continuing with the previous example, we allocate integer multiples of memory blocks to the parameters of the split operators, and try to allocate different memory blocks to the parameters of each operator. Two linked lists are used here to manage memory blocks: linked list A is used to store available memory blocks, and linked list B is used to store allocated memory blocks. Linked list A uses the principle of alternating first-order allocation. Once the memory in A is insufficient, the oldest used memory node is released from B in a timely manner and inserted into A according to the memory offset size. If possible, it is merged with adjacent nodes. If the memory in A is still insufficient, the process is repeated until the allocation is successful or the entire memory is insufficient and a failure is returned.

[0065] Step 106: Determine first memory block information and second memory block information with parameters according to the memory resource.

[0066] In one possible implementation, determining the first memory block information and determining the second memory block information of the parameter according to the memory resource includes:

[0067] A first mask and first identification information are generated according to the memory block resources corresponding to each parameter in the split operator, wherein bits in the first mask correspond to the memory block resources.

[0068] A second mask and second identification information corresponding to each parameter is generated according to the memory block resources corresponding to the parameter.

[0069] Continuing with the previous example, a mask and an ID (syncid) are calculated based on the memory blocks allocated by the operator parameters. Each bit of the mask corresponds to a memory block. The corresponding bits of used memory blocks are marked as 1, and unused bits are marked as 0. The ID represents the identifier of the first memory block used among the total number of memory blocks. The mask and ID corresponding to the current operator parameters are calculated.

[0070] Step 108: Generate a target information set based on the first memory block information and the second memory block information, wherein the target information set includes target memory block information.

[0071] In a possible implementation, the method includes generating a target information set based on the first memory block information and the second memory block information, including:

[0072] Traverse the second mask, calculate the first mask and the current second mask according to the preset rules, and obtain the target memory block information.

[0073] When the traversal is completed, all target memory block information constitutes a target information set.

[0074] Continuing with the above example, instantiate another mask r equal to mask, instantiate an object s of S, initially with n being 0, and traverse each pair of mask and id in each element of queue Q from front to back. If the current operator's mask is bitwise ANDed with each mask of the traversed element e to obtain c, if c is not 0, then add a pair of mask and id to s, assign mask to c, and assign id to the last id in element e. n in s is increased by 1, and r and c are bitwise ANDed to obtain a new r. At the same time, the head of queue Q becomes the next element of e. After traversing Q, if n in s is still 0, then add the current operator's mask and id to s, and set n in s to 1. Otherwise, if r is not 0, merge r into the mask in s that is immediately adjacent to r.

[0075] Step 110: Determine a memory access instruction set according to the target information set, and access the memory according to the memory access instruction set.

[0076] In one possible implementation, determining a memory access instruction set according to a target information set includes:

[0077] Traverse the target information set and determine the target memory block according to the target memory block information.

[0078] Generates instruction information based on the target memory block.

[0079] Generate memory access instructions based on instruction information.

[0080] When the traversal is completed, all memory access instructions constitute a memory access instruction set.

[0081] Continuing with the above example, we traverse the mask and id in s, calculate the memory block corresponding to the mask, convert it into the corresponding offset and size in the parameter, and use the id as the instruction synchronization id to generate the load instruction corresponding to the parameter part.

[0082] In one possible implementation, accessing memory according to a memory access instruction set includes:

[0083] The execution identifier of the memory access instruction at a set position in the memory access instruction set is configured into the computing instruction, so that the memory is accessed based on the memory access instruction in the memory access instruction set.

[0084] Continuing with the above example, we configure the last id in s to the corresponding calculation instruction and generate the calculation instruction. This ensures that the current calculation instruction depends on the previous corresponding split and load instruction.

[0085] The present invention provides a memory access method, which includes: determining a target operator, splitting the target operator according to a preset parameter quantity to obtain a split operator, determining memory resources of multiple parameters in the split operator, determining first memory block information and second memory block information for determining the parameters according to the memory resources, generating a target information set according to the first memory block information and the second memory block information, wherein the target information set includes target memory block information, determining a memory access instruction set according to the target information set, and accessing memory according to the memory access instruction set. By determining the first memory block information and the second memory block information for determining the parameters by using the memory resources of multiple parameters in the split operator, and generating a memory access instruction set according to the first memory block information and the second memory block information to access the memory, instruction density is improved, thereby improving the reasoning capability of an NPU.

[0086] See also Figure 3 , Figure 3 A flowchart of a processing process of a memory access method provided by an embodiment of the present invention is shown, which specifically includes the following steps.

[0087] Step 302: Create a queue.

[0088] Step 304: Take out the operators that need parameters in the network layer and put them into the queue.

[0089] Step 306: Split the operator according to the minimum parameter amount.

[0090] Step 308: Allocate a memory block for the split operator.

[0091] Step 310: Calculate the mask and identifier corresponding to the memory block.

[0092] Step 312: traverse the mask of the operator in the queue, generate the element corresponding to the memory block, insert the element into the tail of the queue, and update the head of the queue.

[0093] Step 314: traverse the mask of the elements of the current memory block and generate corresponding load instructions and calculation instructions of the split operator.

[0094] Step 316: Check whether the split operator is traversed. If yes, go to step 318; if not, go to step 308.

[0095] Step 318: Check whether the network layer traversal is complete. If so, go to step 320; if not, go to step 304.

[0096] Step 320: End.

[0097] The present invention provides a memory access method, which traverses the mask of the operator in the queue, generates the element corresponding to the memory block, inserts the element into the tail of the queue, updates the head of the queue, traverses the mask of the element of the current memory block, generates the corresponding load instruction and the calculation instruction of the split operator, thereby improving the instruction density and thus improving the reasoning ability of the NPU.

[0098] Corresponding to the above method embodiment, the present invention also provides a memory access device embodiment, Figure 4 FIG1 shows a schematic diagram of the structure of a memory access device provided by an embodiment of the present invention. Figure 4 As shown, the device includes:

[0099] The splitting module 402 is configured to determine a target operator and split the target operator according to a preset parameter to obtain split operators.

[0100] The resource allocation module 404 is configured to determine memory resources for multiple parameters in the split operator.

[0101] The information determining module 406 is configured to determine first memory block information and second memory block information of a parameter according to the memory resource.

[0102] The target information determination module 408 is configured to generate a target information set according to the first memory block information and the second memory block information, wherein the target information set includes target memory block information.

[0103] The instruction generation module 410 is configured to determine a memory access instruction set according to the target memory block information, and access the memory according to the memory access instruction set.

[0104] Optionally, the splitting module 402 is further configured to:

[0105] The target operator is split according to the preset parameter quantity of the computing unit of the target hardware to obtain the split operators.

[0106] Optionally, the resource allocation module 404 is further configured to:

[0107] Allocate at least one memory block resource for each parameter in the split operator.

[0108] Optionally, the information determination module 406 is further configured to:

[0109] A first mask and first identification information are generated according to the memory block resources corresponding to each parameter in the split operator, wherein bits in the first mask correspond to the memory block resources.

[0110] A second mask and second identification information corresponding to each parameter is generated according to the memory block resources corresponding to the parameter.

[0111] Optionally, the target information determination module 408 is further configured to:

[0112] Traverse the second mask, calculate the first mask and the current second mask according to the preset rules, and obtain the target memory block information.

[0113] When the traversal is completed, all target memory block information constitutes a target information set.

[0114] Optionally, the instruction generation module 410 is further configured to:

[0115] Traverse the target information set and determine the target memory block according to the target memory block information.

[0116] Generates instruction information based on the target memory block.

[0117] Generate memory access instructions based on instruction information.

[0118] When the traversal is completed, all memory access instructions constitute a memory access instruction set.

[0119] Optionally, the instruction generation module 410 is further configured to:

[0120] The execution identifier of the memory access instruction at a set position in the memory access instruction set is configured into the computing instruction, so that the memory is accessed based on the memory access instruction in the memory access instruction set.

[0121] The present invention provides a memory access device, which determines a target operator, splits the target operator according to a preset parameter quantity to obtain a split operator, determines memory resources of multiple parameters in the split operator, determines first memory block information and second memory block information for determining the parameters according to the memory resources, generates a target information set according to the first memory block information and the second memory block information, wherein the target information set includes target memory block information, determines a memory access instruction set according to the target information set, and accesses memory according to the memory access instruction set. By determining the first memory block information and the second memory block information for determining the parameters according to the memory resources of multiple parameters in the split operator, and generating a memory access instruction set according to the first memory block information and the second memory block information to access the memory, the instruction density is improved, thereby improving the reasoning capability of the NPU.

[0122] The above is a schematic scheme of a memory access device of this embodiment. It should be noted that the technical scheme of the memory access device and the technical scheme of the above-mentioned memory access method are of the same concept. For details not described in detail in the technical scheme of the memory access device, please refer to the description of the technical scheme of the above-mentioned memory access method.

[0123] Figure 5 The block diagram of a computing device 500 according to one embodiment of the present invention is shown. Components of the computing device 500 include, but are not limited to, a memory 510 and a processor 520. The processor 520 is connected to the memory 510 via a bus 530, and a database 550 is used to store data.

[0124] The computing device 500 also includes an access device 540 that enables the computing device 500 to communicate via one or more networks 560. Examples of such networks include a public switched telephone network (PSTN), a local area network (LAN), a wide area network (WAN), a personal area network (PAN), or a combination of communication networks such as the Internet. The access device 540 may include one or more of any type of network interface (e.g., a network interface card (NIC)), whether wired or wireless, such as an IEEE 802.11 wireless local area network (WLAN) wireless interface, a Worldwide Interoperability for Microwave Access (Wi-MAX) interface, an Ethernet interface, a universal serial bus (USB) interface, a cellular network interface, a Bluetooth interface, a near field communication (NFC) interface, and the like.

[0125] In one embodiment of the present invention, the above components of the computing device 500 and Figure 5 Other components not shown in the figure may also be connected to each other, for example, via a bus. Figure 5 The computing device structure block diagram shown is only for the purpose of illustration, and is not intended to limit the scope of the present invention. Those skilled in the art can add or replace other components as needed.

[0126] Computing device 500 can be any type of stationary or mobile computing device, including a mobile computer or mobile computing device (e.g., a tablet computer, a personal digital assistant, a laptop computer, a notebook computer, a netbook computer, etc.), a mobile phone (e.g., a smartphone), a wearable computing device (e.g., a smartwatch, smart glasses, etc.), or other types of mobile devices, or a stationary computing device such as a desktop computer or PC. Computing device 500 can also be a mobile or stationary server.

[0127] The processor 520 is configured to execute the following computer executable instructions, which implement the steps of the above-mentioned memory access method when executed by the processor.

[0128] The above is a schematic solution of a computing device of this embodiment. It should be noted that the technical solution of the computing device and the technical solution of the above-mentioned memory access method are of the same concept. For details not described in detail in the technical solution of the computing device, please refer to the description of the technical solution of the above-mentioned memory access method.

[0129] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, which implement the steps of the above-mentioned memory access method when executed by a processor.

[0130] The above is a schematic scheme of a computer-readable storage medium of this embodiment. It should be noted that the technical scheme of this storage medium and the technical scheme of the above-mentioned memory access method are based on the same concept. For details not described in detail in the technical scheme of the storage medium, please refer to the description of the technical scheme of the above-mentioned memory access method.

[0131] An embodiment of the present invention further provides a computer program, wherein when the computer program is executed in a computer, the computer is caused to execute the steps of the above-mentioned memory access method.

[0132] The above is an illustrative solution of a computer program of this embodiment. It should be noted that the technical solution of the computer program and the technical solution of the above-mentioned memory access method are of the same concept. For details not described in detail in the technical solution of the computer program, please refer to the description of the technical solution of the above-mentioned memory access method.

[0133] The foregoing description describes specific embodiments of the present invention. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0134] Computer instructions include computer program code, which may be in source code form, object code form, executable files, or some intermediate form. Computer-readable media may include any entity or device capable of carrying computer program code, recording media, USB flash drives, removable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signals, telecommunications signals, and software distribution media. It should be noted that the content of computer-readable media may be appropriately expanded or reduced based on the requirements of legislation and patent practice within a jurisdiction. For example, in some jurisdictions, based on legislation and patent practice, computer-readable media does not include electric carrier signals or telecommunications signals.

[0135] It should be noted that for the aforementioned method embodiments, for ease of description, they are all expressed as a series of action combinations. However, those skilled in the art should be aware that the present invention is not limited by the order of the actions described, because according to the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0136] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0137] The preferred embodiments disclosed above are intended only to illustrate the present invention. The alternative embodiments do not exhaustively describe all details, nor do they limit the present invention to specific embodiments. Obviously, numerous modifications and variations are possible based on the present invention. These embodiments are selected and described in detail to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A memory access method, characterized in that: include: Determine a target operator, and split the target operator according to a preset parameter to obtain split operators; Determining memory resources for a plurality of parameters in the split operator; determining first memory block information according to the memory resource and determining second memory block information of the parameter; generating a target information set according to the first memory block information and the second memory block information, wherein the target information set includes target memory block information; Determining a memory access instruction set according to the target information set, and accessing a memory according to the memory access instruction set; The determining of memory resources for the plurality of parameters in the split operator comprises: allocating at least one memory block resource to each parameter in the split operator; The determining the first memory block information and the determining the second memory block information of the parameter according to the memory resource includes: Generate a first mask and first identification information according to the memory block resource corresponding to each parameter in the split operator, wherein the bits in the first mask correspond to the memory block resource; Generate a second mask and second identification information corresponding to each parameter according to the memory block resource corresponding to the parameter; Generating a target information set according to the first memory block information and the second memory block information includes: Traversing the second mask, calculating the first mask and the current second mask according to a preset rule to obtain the target memory block information; When the traversal is completed, all the target memory block information constitutes the target information set.

2. The method according to claim 1, characterized in that The step of splitting the target operator according to the preset parameter amount to obtain a split operator includes: The target operator is split according to preset parameter quantities of a computing unit of the target hardware to obtain split operators.

3. The method according to claim 1, characterized in that The determining of the memory access instruction set according to the target information set includes: Traversing the target information set, and determining a target memory block according to the target memory block information; generating instruction information according to the target memory block; generating a memory access instruction according to the instruction information; When the traversal is completed, all the memory access instructions constitute the memory access instruction set.

4. The method according to claim 3, characterized in that Accessing the memory according to the memory access instruction set includes: The execution identifier of the memory access instruction at a set position in the memory access instruction set is configured into the computing instruction, so that the memory is accessed based on the memory access instruction in the memory access instruction set.

5. A memory access device comprising: a splitting module configured to determine a target operator and split the target operator according to a preset parameter to obtain split operators; a resource allocation module, configured to determine memory resources for a plurality of parameters in the split operator; an information determining module, configured to determine first memory block information and second memory block information of the parameter according to the memory resource; a target information determination module, configured to generate a target information set according to the first memory block information and the second memory block information, wherein the target information set includes target memory block information; an instruction generation module, configured to determine a memory access instruction set according to the target memory block information, and access the memory according to the memory access instruction set; The resource allocation module is further configured to allocate at least one memory block resource to each parameter in the split operator; The information determination module includes: Generate a first mask and first identification information according to the memory block resource corresponding to each parameter in the split operator, wherein the bits in the first mask correspond to the memory block resource; Generate a second mask and second identification information corresponding to each parameter according to the memory block resource corresponding to the parameter; Generating a target information set according to the first memory block information and the second memory block information includes: Traversing the second mask, calculating the first mask and the current second mask according to a preset rule to obtain the target memory block information; When the traversal is completed, all the target memory block information constitutes the target information set.

6. A computing device comprising: memory and processor; The memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor, the steps of the memory access method described in any one of claims 1 to 4 are implemented.

7. A computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions, when executed by a processor, implement the steps of the memory access method according to any one of claims 1 to 4.

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