Method and system for translating virtual addresses in a virtual memory based system

Abstract

An information processing system and method for converting a virtual address to a real address, comprising: a processor for processing data; a memory device for storing data; and a memory controller configured to control access to the memory device, wherein the processor is configured to send a page directory base address and a plurality of memory offsets from the processor to the memory controller in response to a request to convert a first virtual address to a second physical address. The memory controller is configured to: read a first-level page directory table from the memory device using the page directory base address and the first-level memory offset; combine the first-level page directory table with the second-level memory offset; and read a second-level page directory table from the memory device using the first-level page directory table and the second-level memory offset.

Description

Background Art

[0001] The present disclosure relates generally to data processing, and more particularly to methods, apparatus, and systems for optimizing address translation in computer systems.

[0002] Memory management manages data stored in a computer, including overseeing the retrieval and storage of data from memory in a computer, among other tasks. Memory management is often a key factor in the overall system performance of a computer. Computer systems typically include physical memory for storing applications and data. Modern computers often rely on memory management techniques known as virtual memory management to improve performance and provide greater flexibility in the design of computers and the underlying architectures on which they are premised.

[0003] Using a virtual memory system, the underlying hardware that implements the computer's memory system is effectively hidden from the computer's software. A relatively large virtual memory space is typically used for such a computer, in which a computer program executed on the computer uses an address pointing to a location in the virtual memory space to access the memory system. However, the physical memory devices in the computer are accessed via "real" addresses that are directly mapped to specific memory locations in the physical memory devices. Hardware and / or software in the computer are provided to perform "address translation" to map the virtual memory addresses of the virtualized address space to real addresses in the physical memory space. In this way, whenever a computer program on the computer attempts to access memory using a virtual address, the computer converts the virtual address into a corresponding real address, so that the appropriate location in the appropriate physical device mapped to the virtual address can be accessed. Summary of the invention

[0004] The present disclosure is provided to help understand computer systems, computer architectures, processors, memory systems, and methods of converting virtual addresses in computer systems, but is not intended to limit the present disclosure or the present invention. The present disclosure is directed to those of ordinary skill in the art. It should be understood that the various aspects and features of the present disclosure may be advantageously used alone in some cases, or in combination with other aspects and features of the present disclosure in other cases. Therefore, computer systems, architectures, processors, and methods of operating the same may be varied and modified to achieve different effects.

[0005] In one or more embodiments, an information processing system is disclosed. The information system in the embodiment includes a processor for processing data; one or more memory devices having multiple locations for storing data, each location having a physical address; and a memory controller, preferably local to the memory device, configured to control read and write access to the memory device. In one aspect, in response to a request to convert a first virtual address into a second address (preferably a physical address), the processor is configured to send a page directory base address and multiple memory offsets from the processor to the memory controller, wherein the multiple memory offsets include at least a first-level memory offset and a second-level memory offset. The memory controller in one or more aspects is configured to: receive a page directory base address and multiple memory offsets from the processor; read a first-level page directory table from one or more memory devices using the page directory base address and the first-level memory offset; combine the first-level page directory table with the second-level memory offset; and read a second-level page directory table from one or more memory devices using the first-level page directory table and the second-level memory offset.

[0006] The memory controller is configured in one or more embodiments to send a page table entry (PTE) to a processor, wherein the PTE contains a translation of a first virtual address to a second address. The system in the embodiment is also configured to send a memory row containing the address of the page table entry (PTE) from the memory controller to the processor, and wherein the processor is also configured to extract the page table entry (PTE) from the memory row containing the address of the page table entry (PTE). On the one hand, in response to determining that all multiple memory offsets have been combined with multiple page directory tables, the memory controller is configured to send a page table entry (PTE) to the processor. The processor in the embodiment is configured to combine a page directory base address and a first-level offset, and send multiple memory offsets to the memory controller together with the combined page directory base address and the first-level memory offset.

[0007] The memory controller is also configured in one aspect to obtain a memory row containing an address of a first-level page directory table from one or more memory devices. The memory controller is also configured to extract the address of the first-level page directory table from the memory row containing the address of the first-level page directory table in one or more embodiments. The system in the embodiment is also configured to send the memory row containing the address of the first-level page directory table from the memory controller to the processor, and the processor is also configured to extract the address of the first-level page directory table from the memory row containing the address of the first-level page directory table. In one or more embodiments, the memory controller is also configured to obtain a memory row containing the address of the second-level page directory table from one or more memory devices. The memory controller in the embodiment is configured to extract the address of the second-level page directory table from the memory row containing the address of the second-level page directory table. The system in one or more aspects is configured to send the memory row containing the address of the second-level page directory table from the memory controller to the processor, and the processor is configured to extract the address of the second-level page directory table from the memory row containing the address of the second-level page directory table. The memory controller in one or more embodiments is further configured to combine the third level memory offset with the second level page directory table and read the third level page directory table from the memory using the third level memory offset and the second level page directory table.

[0008] In one or more embodiments, in response to the memory controller receiving the page directory base address and the memory offset, the memory controller is configured to control all memory read operations to the multiple page directory tables stored in the memory, and the system is configured so that all memory read operations to the multiple page directory tables stored in the memory are initiated in the memory controller. The system is optionally configured so that all memory offsets are sent from the processor to the memory controller together. And on the one hand, the memory controller is configured to combine the page directory base address and the first-level memory offset. In an embodiment, the system is configured to respond to the request for conversion, only the memory line containing the address of the PTE is sent to the processor, and no page directory table is sent from the memory controller to the processor. The request for conversion in one or more embodiments includes a nested conversion with a guest virtual address and a host virtual address.

[0009] A computing system in one or more embodiments is also disclosed. In one or more aspects, the computing system includes a processor; one or more memory devices having multiple locations for storing the data, each location having a physical address; a memory controller local to the one or more memory devices, the memory controller controlling read and write access to the one or more memory devices; and a computer-readable storage medium including program instructions that, when executed by the processor, in response to a request to convert a first virtual address to a second address, cause the processor to send a page directory base address and multiple memory offsets from the processor to the memory controller, wherein the multiple memory offsets include at least a first level memory offset and a second level memory offset. In an embodiment, the computer system also includes a computer-readable storage medium comprising program instructions which, when executed by a memory controller, in response to a request to convert a first virtual address to a second address, cause the memory controller to: receive a page directory base and a plurality of memory offsets from a processor; read a first level page directory table from the memory device using the page directory base and the first level memory offsets; combine the first level page directory table with the second level memory offsets; read a second level page directory table from a memory using the first level page directory table and the second level memory offsets; and send a page table entry (PTE) to the processor.

[0010] In one aspect, program instructions in a computing system, when executed by a memory controller, cause the memory controller to send a page table entry (PTE) to a processor in response to determining that all of the plurality of memory offsets have been combined with a plurality of page directory tables. In one embodiment, program instructions of a computing system, when executed by a processor, cause the processor to combine a page directory base offset and a first-level memory offset, and send the plurality of memory offsets together with the combined page directory base offset and first-level memory offset to a memory controller. In one or more aspects, the program instructions, when executed by the processor, cause the processor to transmit all of the plurality of memory offsets together from the processor to the memory controller in response to the request to convert the first virtual address to the second address. In one or more embodiments, the computing system further includes programming instructions that, when executed in response to the request to convert the first virtual address to the second address, cause the memory controller to send only a memory row containing an address of the PTE to the processor, and no page directory table is sent from the memory controller to the processor.

[0011] A method for translating addresses by a system having multiple page directory tables stored in a memory is also disclosed. In response to a request to translate a first address into a second address, a page directory base address and multiple memory offsets are sent from a processor to a memory controller, wherein the multiple memory offsets include at least a first-level memory offset and a second-level memory offset; a first-level page directory table is read from a memory by the memory controller using the page directory base address and the first-level memory offset; the second-level memory offset and the first-level page directory table are combined by and in the memory controller; a second-level page directory table is read from a memory by the memory controller using the first-level page directory table and the second-level memory offset; and a page table entry (PTE) is sent from the memory controller to the processor. In one aspect, the method further includes sending all of the multiple memory offsets together from the processor to the memory controller, and sending only the memory line containing the address of the PTE from the memory controller to the processor without sending the page directory table. In one embodiment, the method involves a base page translation, and in one aspect, the translation request involves a base page translation, wherein the page directory table forms part of a base tree.

[0012] The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of exemplary embodiments of the invention, as illustrated in the accompanying drawings, wherein like reference numerals generally refer to the same parts of exemplary embodiments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] When read in conjunction with the provided drawings, the various aspects, features, and embodiments of computer systems, computer architectures, processors, memory systems, and methods of operation thereof will be better understood. For the purpose of illustrating aspects, features, and / or various embodiments of computer systems, computer architectures, processors, and methods of operation thereof, embodiments are provided in the accompanying drawings, but the claims should not be limited to the precise arrangements, structures, features, aspects, components, systems, circuits, embodiments, or devices shown, and the arrangements, structures, subcomponents, features, aspects, methods, processes, circuits, embodiments, and devices shown may be used alone or in combination with other arrangements, structures, components, subcomponents, systems, features, aspects, circuits, embodiments, methods, and devices.

[0014] Figure 1 is a functional block diagram illustrating a computer system according to an embodiment of the present disclosure.

[0015] Figure 2A An example of a computing environment is depicted.

[0016] Figure 2B Another example of a computing environment is depicted.

[0017] Figure 3A An example of a hierarchical conversion mechanism is depicted.

[0018] Figure 3B An example of an index into an advanced translation table is depicted.

[0019] Figure 4 Another example of a hierarchical conversion mechanism according to an embodiment of the present disclosure is depicted.

[0020] Figure 5 A block diagram of a processor and memory controller of an embodiment undergoing translation of a virtual address is shown.

[0021] Figure 6 A block diagram of a processor and memory controller of another embodiment undergoing translation of virtual addresses is shown.

[0022] Figure 7 A flow chart illustrating an embodiment of a method of translating a virtual address into a physical address is shown. DETAILED DESCRIPTION

[0023] The following description is made to illustrate the general principles of the present invention and is not meant to limit the inventive concept claimed herein. In the following specific embodiments, many details are set forth to provide an understanding of information processing systems including computer systems, computer architectures, processors, memory systems, and their operating methods, which include methods for performing address translation, however, those skilled in the art will appreciate that different and many embodiments of information processing systems including computer systems, computer architectures, processors, memory systems, and their operating methods can be practiced without those specific details, which include methods and structures for performing address translation, and the claims and disclosures should not be limited to the embodiments, subcomponents, features, processes, methods, aspects, features, or details specifically described and shown herein. In addition, the specific features described herein may be used in combination with each of the other described features in various possible combinations and permutations.

[0024] Unless expressly defined otherwise herein, all terms are to be given their broadest possible interpretation, including the meanings implied in the specification and as understood by those skilled in the art and / or as defined in dictionaries, treatises, etc. It must also be noted that, as used in the specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless otherwise indicated, and that when used in this specification, the terms "include" and / or "comprise" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0025] The following discussion omits or only briefly describes conventional features of information processing systems including processors, microprocessor systems, memory systems, and their architectures, which are obvious to those skilled in the art. It is assumed that those skilled in the art are familiar with the general architectures of processors and memory systems and / or devices and their operations. It may be noted that numbered elements are numbered according to the accompanying drawings in which the element is introduced, and may be referenced by that number in subsequent drawings.

[0026] In data and information processing systems, there are a large number of accesses to data stored in various memory systems including main memory. Access to memory in a virtualized memory system typically requires an address translation from a virtual address (VA) to a real address (RA). Due to the frequency of memory access requests in a computer, address translation can have a significant impact on overall system performance. Therefore, it is desirable to minimize the amount of time to provide address translations. The present disclosure addresses this problem through systems and techniques that reduce the amount of time to provide address translations. In one or more embodiments, a system and process for accelerating base page translations (RPTs) are disclosed, and specifically, RPT table traversals are accelerated by reducing data exchanges between a processor (CPU) and a memory including a memory controller (MC) during a table traversal translation process.

[0027] A feature of virtual addressing is that the computer does not have to include storage for the entire virtual memory space in the physical memory device in the main memory of the computer. Instead, lower-level storage such as disk drives and other mass storage devices can be used as supplementary storage, where memory addresses are grouped into "pages" that are exchanged ("paging") between the main memory and the supplementary storage as required. When the processing system uses paging, the low-order bits of the virtual address are retained and directly used as the low-order bits of the actual physical address, and the high-order bits can be considered as corresponding to or mapped to the keyword or index of one or more address translation tables of the physical address. The memory referenced by such a range can be referred to as a page. The page size can be in the size range of, for example, from 4 kilobytes to 16 gigabytes.

[0028] Address translation in a virtual memory system is typically incorporated with access to various address translation data structures. One such structure, called a page table, includes multiple entries that map virtual addresses to real addresses in a page-by-page manner, and includes one or more page table entries (PTEs). Using virtual addressing, a processor can access memory using a physical address resulting from translating a virtual address (VA) into a physical or real address (RA).

[0029] The number of entries in the page table required to map all the memory address spaces used by the computer can be large, and the entries need to be stored in gigabyte / terabyte-sized main memory (random access memory) rather than in dedicated memory associated with the processor, which slows down access to these entries residing in main storage. In order to speed up address translation and reduce the latency of obtaining address translation, a high-speed memory associated with the processor, called a translation lookaside buffer (TLB), is typically used to cache recently used entries for rapid access by the computer. The TLB is a data structure for caching page table entries that map virtual addresses (VA) to physical addresses or real addresses (RA). For each memory access, the VA is presented to the TLB, and if the TLB hits, i.e., the VA of the memory access matches an entry in the TLB, then the TLB provides the real address (RA) to the processor. Finding a mapping or match in a given TLB provides rapid conversion between virtual addresses and physical addresses.

[0030] No mapping or match is found for the virtual address in a given TLB indicating that the page table should be checked, and in one or more embodiments, a table walk through multiple tables and levels will need to be performed to convert the virtual address to a real address in physical memory. If the address does not hit in the TLB, in one or more embodiments, a translation process involving a more expensive hardware processor or software processor is invoked to handle the translation, and the page table entry is loaded and inserted into the TLB so that the address will hit in the TLB and the memory access can proceed. The TLB is typically associated with a processor (CPU) and may be local to the processor (CPU).

[0031] There are several conventional methods to convert virtual addresses into real addresses in physical memory. Base page translation (RPT) is a base tree-based method for converting virtual addresses (VA) into real addresses (RA) in virtual memory-based systems. The tree structure page table (e.g., base address translation) method uses a tree structure in memory. The root of the tree is identified by the physical address in the memory, and the bits from the virtual address are used as indexes at each level of the tree until the page table entry is found. Although the final page table entry (PTE) found in the tree structure is cached in the TLB, the middleware at each level is typically cached in the page traversal cache (PWC). In a typical RPT conversion, it is necessary to "traverse" multiple levels of the base tree in order to obtain the converted physical or real address (RA). In a typical configuration, this traversal process is completely managed by the processor (CPU) and may take a long time due to the large amount of exchanges between the processor (CPU) and the memory controller (MC).

[0032] Address translation generally occurs in data or information processing environments, and more specifically, generally occurs in processor-based systems and / or computerized environments. Figure 1 1 is a functional block diagram illustrating a computer system 150 in which embodiments of the present disclosure may be practiced. System 150 includes an example of automated computing machinery in the form of computer 152.

[0033] Computer 152 may include at least one processor 156 or central processing unit (“CPU”) and random access memory 168 (“RAM”) connected to processor 156 and other components of computer 152 via a high-speed memory bus 166 and bus adapter 158 .

[0034] Although processor 156 is shown as being coupled to RAM 168 via front side bus 162, bus adapter 158, and high speed memory bus 166, persons of ordinary skill in the art will recognize that such a configuration is merely an exemplary implementation and that other configurations may be utilized to couple processor 156 to other components of system 150. In some embodiments, processor 156 may support direct peripheral connections, such as a Peripheral Component Interconnect Express ("PCIe") connection, or the like.

[0035] The operating system 154 may be stored in the RAM 168 of the computer 152. Operating systems useful in computers configured for operation of a processor may include UNIX™, Linux™, Microsoft Windows™, AIX™, IBM's z / OST™, and other operating systems known to those of ordinary skill in the art. In addition to the operating system 154 being located in the RAM 168, other components such as data processing applications may be stored in the RAM 168. In addition, the software and other components may be stored in non-volatile storage, such as on a disk drive 170.

[0036] Computer 152 may include a disk drive adapter 172 coupled to processor 156 and other components of computer 152 through expansion bus 160 and bus adapter 158. Disk drive adapter 172 may connect non-volatile data storage in the form of disk drive 170 to computer 152. Disk drive adapters may include integrated drive electronics ("IDE") adapters, small computer system interface ("SCSI") adapters, and other adapters known to those of ordinary skill in the art. Non-volatile computer memory may also be implemented as an optical drive, electrically erasable programmable read-only memory (so-called "EEPROM" or "flash" memory), a RAM drive, and other memories known to those of ordinary skill in the art.

[0037] The computer 152 may include one or more input / output ("I / O") adapters 178. The I / O adapters 178 may implement user-oriented input / output through, for example, software drivers and computer hardware to control output to a display device such as a computer display screen, and user input from user input devices 181 such as a keyboard and mouse. The computer 152 may include a video adapter 209, which is an example of an I / O adapter specifically designed for graphics output to a display device 180 such as a display screen or computer monitor. The video adapter 209 is connected to the processor 156 through a high-speed video bus 164, a bus adapter 158, and a front-side bus 162 (which may also be a high-speed bus). The I / O adapters 178 may also include COMM and driver adapters. The I / O adapters 178 may also be PCI Express, where all I / O are connected.

[0038] The computer 152 may include a communications adapter 167 for data communications with other computers 182 and for data communications with the data communications network 100. Such data communications may be performed serially through an RS-232 connection, through an external bus such as a universal serial bus ("USB"), through a data communications network such as an IP data communications network, and in other ways known to those of ordinary skill in the art. The communications adapter 167 may implement the hardware level of data communications by which one computer sends data communications to another computer, either directly or through the data communications network 174. Examples of communications adapters 167 may include modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications, and 802.11 adapters for wireless data communications.

[0039] Figure 1 The arrangement of computers and other devices shown in is for explanation and not limitation. Data processing systems useful according to various embodiments of the present disclosure may include additional servers, routers, other devices, and peer-to-peer architectures. The networks in such data processing systems may support many data communication protocols, including, for example, TCP (Transmission Control Protocol), IP (Internet Protocol), HTTP (Hypertext Transfer Protocol), WAP (Wireless Access Protocol), HDTP (Handheld Device Transport Protocol), and other protocols known to those of ordinary skill in the art. In addition to Figure 1 Various embodiments of the present disclosure may be implemented on a variety of hardware platforms in addition to those shown in FIG.

[0040] refer to Figure 2AAn example of a computing environment for incorporating and using one or more aspects of translation capabilities is described. In one example, computing environment 100 includes a processor (central processing unit - CPU) 102, which includes at least one memory management unit (MMU) / translation lookaside buffer (TLB) portion 104 and a cache 106. Processor 102 is communicatively coupled to a memory portion 108 having a cache 110, and to an input / output (I / O) portion 112. I / O portion 112 is communicatively coupled to external I / O devices 114, which may include, for example, data input devices, sensors and / or output devices, such as displays.

[0041] The memory management unit 104 is used to manage the memory portion 108, including facilitating access to the memory. To improve address translation, the memory management unit in one embodiment utilizes a translation lookaside buffer (TLB). The TLB is a cache of previously translated addresses. Therefore, when a request for a memory access including an address to be translated is received, the TLB is first checked. If the address and its translation are in the TLB, no translation is required. Otherwise, the received virtual address is translated.

[0042] Figure 2B Another embodiment of a computing environment for incorporating and using one or more aspects of the present invention is depicted in . In this example, computing environment 150 includes server 152, which includes, for example, one or more virtual machines 154, one or more central processors (e.g., central processing units) 156, at least one hypervisor 158, and input / output subsystem 160. The virtual machines and hypervisor are included in memory 162.

[0043] In this embodiment, each virtual machine is capable of hosting a guest operating system 168 and can execute one or more applications 170. An operating system or application running in a virtual machine appears to have access to the entire complete system, but in reality, only a portion of it is available.

[0044] CPU 156 (e.g., central processing unit) is a physical processor resource that can be allocated to a virtual machine. For example, virtual machine 154 includes one or more logical processors, each logical processor representing all or a portion of a physical processor 156 that can be dynamically allocated to a virtual machine. Similar to CPU 102, CPU 156 includes at least one MMU / TLB portion and at least one cache. Virtual machine 154 is managed by a hypervisor 158, such as, for example, PowerVM provided by International Business Machines Corporation.

[0045] The input / output subsystem 160 directs the flow of information between devices and memory (also referred to herein as main memory or primary storage). It is coupled to the server, as it may be part of the server or separate from it. The I / O subsystem relieves the central processor from the task of communicating directly with the I / O devices coupled to the server, and allows data processing to proceed simultaneously with I / O processing.

[0046] Address translation in a virtual memory system is typically incorporated with access to various address data structures. One such structure, called a page table, includes multiple entries that map virtual addresses to real addresses in a page-by-page manner. The format and information included in a page table entry depends on the architecture and / or specific type of translation configured for the system. A page table entry located by traversing a hierarchical page table typically includes various information, including at least a portion of a real address used to access physical memory.

[0047] The address received for translation may include virtual address bits and one or more offsets, including a page offset. The virtual address bits are sent to the TLB, which attempts to match the virtual address bits with a real page number stored in the TLB. If the TLB finds an entry containing a real page number that matches the virtual address bits, it provides the physical address. The physical address is used to address a page in physical memory. The page bits or page offset are used to access an address relative to the beginning of the page.

[0048] In one embodiment, if no match is found (TLB miss), the address translation system obtains the physical address from the page table by performing a page walk after the TLB miss. The virtual address resolution system may also load the obtained physical address into one or more of the arrays of the TLB. In addition, in one or more embodiments, one or more steps of the page walk are also installed in an array of a page walk cache (PWC). That is, when a page walk is performed, various intermediate entries of the page walk may be saved as page directory entries in the PWC. The page walk steps cached in the PWC array allow the processing system to perform subsequent page walks faster because it does not have to perform the cached page walk steps, and / or the page walk does not need to start from scratch.

[0049] Base page translation (RPT) is a common and popular method of memory virtualization, in which a base tree is used to translate the effective / virtual address space into real / physical addresses. RPT is an example of a hierarchical translation table mechanism. The hierarchy of tables is called dynamic address translation (DAT) tables, and for RPT, these tables are called base tables. For the RPT process, a base tree (i.e., base table) is stored in a physical address space (e.g., main memory), and the root of the tree (also known as the page directory base address) is stored in a register in a processor (CPU). The base page table is, in one embodiment, a hierarchical data structure, for example, that specifies a mapping between a virtual page number and a real page number, a virtual page number and a virtualized real page number, or a virtualized real page number and a real page number.

[0050] To perform a base page table walk (RPT) to convert a virtual address into a real address in physical memory, the processor starts at the root or base address of the base tree and uses a set of bits from the virtual address as an offset into a page directory entry or table. The page directory entry at the specified offset points to the next level page directory entry or table. Another set of bits from the virtual address is used to index into this entry / table and pick the next page directory entry / table to be used. The process continues until the last set of bits is used to find a page table entry (PTE) in the page table. In current systems, this traversal process through the table is completely managed by the processor CPU and can take a long time due in part to the large amount of exchanges between the CPU and the memory controller (MC).

[0051] One or more embodiments are disclosed for accelerating RPT table traversal by increasing the responsibilities and operations performed by a memory controller during the table traversal process. In one or more embodiments, a memory controller (MC) performs the entire table traversal, reducing the number of exchanges between the CPU and the memory / memory controller (MC). In one embodiment, the memory controller performs the entire table traversal, and the final page table entry (PTE) and all intermediate addresses in the base tree conversion are sent from the memory controller or sent back to the processor (CPU). This method reduces latency and allows the base tree to be cached, for example, in a page traversal cache (PWC) or in a processor (CPU). In another embodiment, the memory controller (MC) performs the entire table traversal, and only the final page table entry (PTE) is sent back from the memory controller to the processor (CPU). The method reduces latency and eliminates the page traversal cache (PWC), and in one aspect eliminates the page traversal cache (PWC) for host conversion. In one or more embodiments, the final PTE entry containing the desired conversion is available at the processor (CPU) faster than the existing methods allow.

[0052] refer to Figure 3AAn example of base page translation is described. In this example, a translation table 404 is provided for translating addresses of virtual memory 402 into real addresses. The origin of the highest order translation table of the hierarchical translation table 404 is provided, for example, by a control register (CR3) 406. An effective or virtual address 408 is used to index into each table of the hierarchical translation table 404 to determine the source address of the next table until, for example, a page table entry (PTE) having a page address 409 of physical memory 410 is located. In an example where the translation mechanism utilizes a DAT table, an effective address is a virtual address having multiple indices or offsets for indexing into the translation table.

[0053] Figure 3B Another example of an RPT is shown, for example, during a table walk through a base table, where the highest level translation table of the hierarchy is "indexed" by a high portion 408a of an effective or virtual address 408 to locate a Table 1 entry 412a for locating the next translation table (Table 2). That is, entry 412a in Table 1 includes the source address of Table 2. Similarly, a next portion 408b of the effective or virtual address 408 is used to index into Table 2 to find a Table 2 entry 412b having a source address of Table 3. A next portion 408c of the effective or virtual address 408 is used to index into Table 3 to find a Table 3 entry 412c having a source address of a page table 414a. A next portion 408d of the effective or virtual address 408 is used to index into a page table 414a to locate a page table entry 412d having an address of a physical memory page 416. In one embodiment, the origin of the translation table hierarchy may include a table selector field for determining which hierarchy of translation tables to initiate a translation. Therefore, translation may require only a subset of the hierarchy (where effective addresses are restricted to include a predetermined number of most significant bits having a zero value). Translation using fewer tables will be faster than translation using more tables.

[0054] Figure 4 A block diagram of another example of an RPT process is shown, in which a virtual address space is translated to a physical address using a base tree, for example, by performing a table walk through multiple levels of the base tree. Figure 5 and Figure 6 A block diagram of data exchange between a processor (CPU) 156 and a memory 162 and between the processor 156 and a memory controller 161 is shown, wherein the memory controller 161 is associated with and local to the memory 162. In one or more embodiments, the memory 162 includes one or more memory cards (not shown), wherein each memory card has a memory controller 161 and one or more DRAMs (not shown) to store data. Figure 4 , 5In the examples of 6, 48-bit addressing is used as an example for description purposes, not as a limitation of the illustrative embodiments. The conversion process can be practiced with an addressing system of any size (bit width) in the manner described herein, and is contemplated within the scope of the exemplary embodiments.

[0055] exist Figure 4 , 5 In the examples of and 6, the lowest 16 bits 408e of the 48-bit virtual address are the page offset (assuming 64KB pages) and provide an address to locate the desired translated real address on the page in memory. The next 8 bits 408d are the offset into the page table, while the next three 8-bit sets 408c, 408b, and 408a are offsets to different page directory levels. To perform a table walk, portions of the virtual address 408 are sent by the processor (CPU) 156 to the memory controller (MC) 161 along with the page directory base address 420 (which is also referred to as the page directory root 420). Specifically, typically, all of the upper portion of the virtual address 408, except for the page offset bits (e.g., page bits 408e), are sent by the processor (CPU) 156 to the memory controller 161. Figure 4 , 5 In the examples of 6, page directory 1-offset 408a, page directory 2-offset 408b, page directory 3-offset 408c and page table offset 408d, and page directory root or base address 420, are respectively as shown in FIG. Figure 5 and Figure 6 570 and 670 are sent to the memory controller 161. That is, in one or more embodiments, at the beginning of the translation, the page directory entry 1 (PDE1) is sent by the CPU 156 to the memory controller 161, and the page directory entry 1 refers to the page directory base address 420 plus the page directory 1-offset 408a, and the offsets are, for example, 408b, 408c, and 408d, as shown in 570 and 670. In other words, in one embodiment, all offsets (408a, 408b, 408c, and 408d) are sent together, and in one aspect, are sent together with the page directory base address 420, or are sent sequentially together with the page directory base address 420, and are sent from the processor 156 to the memory controller 161 via the bus between the processor (CPU) 156 and the memory 162. New instructions are used to send page directory 2-offset 408b, page directory 3-offset 408c, and page table offset 408d, as well as page directory 1-offset 408a and page directory base address 420, as in the previous conversion method, page directory 1-offset 408a and page directory root or base address 420 are initially sent by processor 156 to memory controller 161 before and without sending other offsets 408b, 408c, or 408d.

[0056] The page directory root or base address 420 is provided by the operating system, and in one aspect, the page directory base address 420 is based on the thread of the virtual address being translated. According to an embodiment, to perform a table walk, the page directory 1-offset 408a is added by the memory controller 161 to the page directory base address 420 in the memory controller 161, and as Figure 4 A memory access is performed as shown at 425 in to read this memory location. In one aspect, memory fetch 425 utilizes memory controller 161 to obtain information and data from a DRAM located on a memory card. Page directory base address 420 is used to identify the address of a table or directory, and page directory 1-offset 408a is used as an index into the table identified by page directory base address 420. The entry in the table, such as the memory location identified by the address at the entry in the table, contains the base address of a level 2 page directory entry for translation, such as page directory table 2 address 430. Memory fetch 425 in one or more embodiments obtains more than the index entry of the translation table from memory, and in one aspect obtains information to be stored in one or more caches (e.g., L2 / L3 caches) associated with the processor. According to one embodiment, where the translation intermediary is stored in processor 156, and in one aspect is stored in a page walk cache (PWC) in processor 156, Figure 5 A PDE1 response 572 is sent from the memory controller 161 to the processor (CPU) 156. The PDE1 response 572 in one aspect includes the information obtained from the memory at 425, and in another aspect includes the page directory table 2 address. In one or more embodiments, the page directory table 2 address is stored in the PWC, and in one aspect, the page directory table 2 address is stored in the PWC by the processor 156.

[0057] Continuing the translation, the page directory 2-offset 408b is added to the directory base address (page directory table 2 address) 430 in and by the memory controller 161, and as Figure 4 A memory access is performed as shown at 435 to read the memory location. In one aspect, memory fetch 435 utilizes memory controller 161 to obtain information and data from a DRAM located on a memory card. Page Directory Table 2 Address 430 is used to identify the address of a table or directory, and Page Directory 2-Offset 408b is used as an index into the table identified by Page Directory Base Address 430. The memory location contains the base address of a level 3 page directory entry for translation, such as address 440 of Page Directory Table 3. Memory fetch 435 in one or more embodiments obtains more than index entries of a translation table from memory, and in one aspect obtains information to be stored in one or more caches (e.g., L2 / L3 caches) associated with a processor. According to one embodiment, where the translation intermediary is stored in the processor and in one aspect in a page walk cache (PWC), Figure 5 The PDE2 response 574 in is sent from the memory controller 161 to the processor (CPU) 156. The PDE2 response 574 in one aspect includes the information obtained from the memory at 435 and in another aspect includes the page directory table 3 address. In one or more embodiments, the page directory table 3 address is stored in the PWC and is stored in the PWC by the processor 156 in one aspect.

[0058] Continuing the translation further, if the translated virtual address 408 has additional offset bits sent to the memory controller 161, the page directory 3-offset 408c is added by the memory controller 161 to the directory base address (page directory table 3 address) 440 in the memory controller 161, and as Figure 4 A memory access is performed as shown at 445 to read the memory location. In one aspect, memory fetch 445 utilizes memory controller 161 to obtain information and data from a DRAM located on a memory card. Page table 3 address 440 is used to identify the address of a table or directory, and page directory 3-offset 408c is used as an index into the table identified by page directory base address 440. The memory location contains the base address of the page table offset entry used for the translation, such as page table address 450. Memory fetch 445 in one or more embodiments obtains more than the index entry of the translation table from memory, and in one aspect obtains information to be stored in one or more caches (e.g., L2 / L3 caches) associated with the processor. According to one embodiment, where the translation agent is stored in the processor and in one aspect is stored in a page walk cache (PWC), Figure 5 A PDE3 response 576 in is sent from memory controller 161 to processor (CPU) 156. PDE3 response 576 in one aspect includes information retrieved from memory at 445 and in another aspect includes a page table address. In one or more embodiments, the page table address is stored in the PWC and in one aspect is stored in the PWC by processor 156.

[0059] Continuing further along the page table traversal to obtain the address translation, the memory controller 161 adds the page table offset 408d to the directory base address (page table address) 450 in the memory controller 161, and Figure 4 A memory access is performed as shown at 455 to obtain a page table entry (PTE) 460. In one aspect, memory fetch 455 obtains information and data from a DRAM located on the memory card using memory controller 161. Page table address 450 is used to identify the address of a table or directory, and page table offset 408d is used as an index into the table identified by page table address 450. The memory location contains the page table entry 460 for translation. Figure 5The PTE response 578 in is sent from the memory controller 161 to the processor (CPU) 156. Similarly, in Figure 6 During the translation process of , PTE response 678 is sent from memory controller 161 to processor (CPU) 156. PTE responses 578 and 678 include information obtained from memory at 455 on the one hand, and include page table entry (PTE) 460 on the other hand. In one or more embodiments, page table entry (PTE) 460 is stored in the TLB and is stored in the TLB by processor 156 on the one hand.

[0060] In one or more embodiments, Figure 5 and Figure 6 As shown, all offsets to the directory table are sent from the processor to the memory controller along with the page base root directory, preferably at the start of the table walk process, and preferably sent together. The memory controller, rather than the processor, performs the table walk in one or more embodiments, for example, the memory controller adds the offsets to the base table / directory, and the memory access is issued from the memory controller. That is, the memory controller will read the memory, such as DRAM, and add the offsets. Figure 5 and Figure 6 In both methods, the memory controller rather than the processor (CPU) performs the pointer chasing process during the conversion.

[0061] exist Figure 6 In an embodiment, only the last memory line access (e.g., the memory line access containing the page table entry (PTE) 460) is sent back to the processor and is preferably stored in a TLB in the processor. Figure 6 In an embodiment of the present invention, intermediate memory accesses (e.g., intermediate memory accesses containing intermediate directories 430, 440, and 450) are not sent back to the processor, and the intermediate directories are not stored in any page walk cache (PWC). Figure 5 In an embodiment of the present invention, one or more intermediate memory accesses (e.g., one or more intermediate memory accesses including page directory table 2 entry / address 430, page directory table 3 entry / address 440, and page directory table entry / address 450) and preferably in addition to Figure 4 All intermediate memory accesses except the page table entry 460 in are sent from the memory controller 161 to the processor 156. The intermediate directory entries 430, 440 and 450 contained in the intermediate memory accesses sent back to the processor may be stored in one or more page walk caches (PWCs), while the page table entries (PTEs) may be stored in the TLB. For example, Figure 3B The intermediate entries (412a, 412b and 412c) of the conversion or table traversal shown in are sent back to the processor and are preferably stored in the PWC, while the entries from Figure 3B The page table entry 412d of the translation or table walk shown in is sent back to the processor and stored in the TLB. Figure 5 The embodiments show that all intermediate translations (e.g., base tables or directories) are sent back to the processor, but it will be appreciated that less than all intermediate memory accesses and any combination of intermediate memory accesses (e.g., intermediate directory entries) may be sent back to the processor and, in one aspect, may be stored in one or more page walk caches (PWCs).

[0062] exist Figure 6 In an embodiment, in the case where the memory controller is saturated with requests, the latency of processing the conversion can be compared to Figure 5 The embodiment reduces because only the PTE response 678 is sent back to the processor. Figure 6 Embodiments should complete translations (table walks) faster, but the processor does not have the benefit of intermediate page table directories stored in a page walk cache (PWC). Therefore, whether intermediate translations are saved in the PWC is a matter of design choice, including whether to include a cache or whether the cache is large enough to store intermediate directory translations in order to reduce future table walk latency.

[0063] In a typical modern microprocessor, the processor adds the offset to a base address directory in the processor, the processor sends the base address and offset (e.g., base address 420 + offset 408a, or base address 430 + offset 408b) to the memory to get the next base address, and a response (e.g., a memory access result) is sent back to the processor. Such a memory access exchange is on the order of 300 cycles, so in order to traverse a system with such a configuration, Figure 4 A table walk of will take on the order of 1200 cycles. Figure 2B In the virtualized environment shown, where the client operating system implements a base page translation tree on top of the hypervisor's base page table, a single client translation may require multiple memory swaps between the processor and memory, such as 24 memory swaps for a total of 7200 cycles. In embodiments where the translation is performed in the memory controller, those memory access exchanges between the processor and memory are eliminated, reducing the latency involved in the table traversal process. There are still memory accesses to obtain information residing in the memory, but those memory accesses are controlled by a local memory controller and are typically on the same card as the memory device (e.g., DRAM). In other words, memory fetch requests are not issued from the processor and do not have to traverse the bus between the processor and the memory.

[0064] The benefit of both approaches is that the number of round trips between the processor and the memory / memory controller is reduced. The system and conversion process according to these embodiments does not incur multiple round trips between the processor and the memory / memory controller, and therefore does not incur the latency associated with traversing the bus between the processor 156 and the memory 162 for these memory accesses. For example, in Figure 6 In the embodiment of , there is preferably one memory access request 670 sent by the processor 156 to the memory controller 161, and one response 678 sent back from the memory controller 161 to the processor 156, such as a memory access line containing a page table entry. It can be expected that according to typical techniques, a single response returned by the memory controller to the processor will take longer than one of multiple memory accesses, such as 500 cycles, because there will be multiple accesses to memory as the memory controller traverses the translations of the various tables / directories. However, a single exchange between the processor and the memory controller will reduce the overall latency of traversing the base tree, such as to obtain the translation (PTE 460).

[0065] Figure 5 The conversion process shown in FIG. 1 may consume the same bandwidth as the existing table traversal process in one or more embodiments and is faster than Figure 6 The translation process takes longer, but still reduces latency over the prior art while having the benefit of storing intermediate addresses (intermediate tables / directories) in the page walk cache in the processor. The intermediate addresses of the intermediate tables and directories are sent from the memory controller back to the processor for subsequent use. Figure 6 Can be slower than Figure 5 , but it may not be obvious. Consider that sending each of the intermediate responses (e.g., PDE response 572, PDE2 response 574, and PDE3 response 576) in one embodiment will take approximately 60-70 cycles, but will be less than the 300 cycles to perform each round-trip exchange between the processor and the memory. In one or more embodiments, the memory controller can be aware of the presence or absence of intermediate addresses in the CPU cache (e.g., in the page walk table (PWC)), and in one or more aspects, the memory controller can send only the required memory lines. In this way, the benefits of caching intermediate addresses (e.g., of the intermediate table / directory) in the page walk cache (PWC) are retained, but the performance of caching intermediate addresses in the last level page walk cache (PWC) will be improved. Figure 4 The latency of any table traversal that misses in the page directory table 3 address 440).

[0066] although Figure 5 and Figure 6 The embodiment of the address translation process in FIG. 1 shows a single-stage translation, such as a single-stage translation of a virtual address to a real address, but Figure 5 and Figure 6 The address translation process and its combination can also be used for nested translation. In nested translation, for example, Figure 2B In the case of a virtual machine hosting a guest as shown, there will be multiple RPT levels where the guest process uses a base translation running on the host running the base translation. The guest translation will have intermediate translations, such as PDE2, PDE3, and PTE addresses, and PDE2, PDE3, and PTE addresses are associated with each memory access of the guest (PDE2, PDE3, and PTE at the host level). By utilizing various guest and host level translations Figure 5 and Figure 6 The conversion process can further reduce the delay in the conversion. Nested conversion can also be used Figure 5 and Figure 6 For example, intermediate information used for host translation (such as page walk cache and / or TLB entries) will not be stored as Figure 6 As shown in the process section, intermediate information (such as entries in the page traversal cache) will be stored for clients, such as Figure 5 As shown in the process of . That is, the intermediates are not stored for the host translation memory access, the intermediates are stored for the guest translation memory access. By utilizing this hybrid approach for nested address translation, the footprint is reduced by not storing any intermediate information for the host translation (e.g., no intermediate directory addresses) but storing the intermediate information for the guest translation to create the appearance of only one level of translation. The reduction in footprint can offset any loss caused by not storing the host's intermediate addresses due to area reduction, power reduction, and better utilization of the TLB for the guest translations that continue to be cached. For example, in a virtualized system where the guest runs on the host, under the existing process, 18 PWC entries and 6 TLB entries may need to be stored for one nested translation, while using the hybrid (combined) approach, only 3 PWC entries and six TLBs will be stored, thereby saving processor area reduction and power reduction.

[0067] Figure 7 is an exemplary flow chart according to one embodiment, which illustrates and describes one or more methods of processing data, including, in one embodiment, processing address translations, such as base page translations (RPTs), according to one or more embodiments of the present disclosure. More specifically, the disclosed method, in one aspect, is directed to performing a table walk preferably with a memory controller to obtain an address translation. Although method 700 is described for convenience and not to limit the present disclosure to include a series and / or multiple steps, it should be understood that the process need not be performed as a series of steps, and / or the steps need not be performed in a manner related to Figure 7Rather, the processes may be integrated and / or one or more steps may be performed together, concurrently, or the steps may be performed in the order disclosed or in an alternate order.

[0068] Figure 7 The method 700 in the embodiment relates to processing data in an information processing system, and more specifically to processing address translation, such as converting virtual addresses to real addresses in a virtualized memory system, including processing nested address translation in an embodiment. In the information processing system, a processor processes an instruction including a request to load data from a memory. Typically, a request or instruction to load data from a memory includes a virtual address to a location in the memory where the required data is located, and those virtual addresses need to be converted to real addresses in a physical memory device. At 705, a request for address translation is made. The request for address translation can come from an instruction that is decoded and issued to the processor. At 710, the processor sends a base address directory and a virtual address offset to a memory controller. In one or more embodiments, at 710, the processor sends all virtual memory offsets together to the memory controller, preferably together with the base address directory. In one embodiment, at 710, the processor adds the first-level virtual address to the base address directory and sends the combined base address directory and the first-level offset to the memory controller with the remaining virtual memory offset. It will be appreciated that all virtual memory offsets except the page bits, eg, all virtual address bits except the address bits that specify a location on a memory page, may be sent from the processor to the memory controller.

[0069] At 715, in one embodiment, the memory controller adds the offset sent by the processor to the base directory. In the first instance of address translation, at 715, the first level offset is added to the base directory. In the instance where the processor adds the first level offset to the base directory, the memory controller does not perform the combination. At 720, the memory controller accesses the memory for the memory row indicated by the base address and the offset. In one or more embodiments, the memory controller combines or adds the offset to the directory table, for example, using the offset and the current directory table or base address to find and obtain the next directory table. If this is a first level memory translation, the memory controller accesses the memory for the memory row indicated by the base address and the first level offset. As described above, the offset bits represent an index into the directory table on the one hand, and at 720 the memory controller accesses the memory for the memory row corresponding to the entry in the directory table. In one embodiment, the memory row read by the memory controller contains the address of the next directory table. In one or more embodiments, when the memory row read from the memory may contain a data block including more than the directory table address, the memory controller extracts the address of the next directory table.

[0070] At 730, a determination is made as to whether the translation process is saving the intermediate base directory address. If the system is saving the intermediate directory table address (730: YES), then at 735, the memory line accessed by the memory controller at 720 is sent back to the processor. In one aspect, at 735, the entire memory line is sent back to the processor, or in one or more embodiments, the intermediate directory table address is sent back to the processor. At 740, the intermediate directory table address is saved in a page walk cache in the processor. In one aspect, when the memory line sent back to the processor has more data than just the directory table address, the processor extracts the address of the intermediate directory table address and saves it in the page walk cache. The process after 740 continues to 750.

[0071] At 730, if it is determined that the intermediate directory table is not saved (730: No), the process continues to 750, where it is determined whether there is any additional offset in the virtual address received by the memory controller. Figure 6 , the process will proceed from 730 to 750, skipping steps 735 and 740. If it is determined at 750 that there is an additional offset to the virtual address (750: Yes), the process returns to step 715, where the memory controller adds the offset to the directory table. In the instance where the process returns to process step 715, the directory table to which the next level offset is added (indexed to) is the directory table at the address returned from the memory access at 720, and in one aspect, is the directory table at the address specified by the entry identified in the previous directory table. The memory controller thereafter proceeds to 720, where the memory controller again accesses (reads) the memory, this time the memory row containing the next directory table. The process continues with steps 715, 720, 730, 735, and 740 until there is no longer a virtual address offset at 750 (750: No). In other words, process 700 continues until the table traversal is completed at 750.

[0072] If there are no more virtual address offsets at 750 (750: No), the table walk is complete and at 755, the memory line from the memory access at 720 is sent to the processor. In one embodiment, a page table entry (PTE) may be extracted from the memory line read at 720 and the PTE may be sent to the processor. At 760, the PTE is saved in a TLB in the processor. In the event that the memory line sent back to the processor at 755 contains more than the PTE, at 760, the processor extracts the PTE and stores it in the TLB. Future requests for this address translation should hit the TLB.

[0073] Although the above-described illustrative embodiments are preferably implemented in hardware (such as in units and circuits of a processor), various aspects of the illustrative embodiments may also be implemented in software. For example, it will be understood that Figure 7 Each block of the flowchart illustration in the flowchart illustration and the combination of blocks in the flowchart illustration can be implemented by computer program instructions. These computer program instructions can be provided to a processor or other programmable data processing device to produce a machine, so that the instructions executed on the processor or other programmable data processing device create components for implementing the functions specified in one or more blocks of the flowchart. These computer program instructions can also be stored in a computer-readable memory or storage medium, which can guide the processor or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory or storage medium produce an article of manufacture including instruction components that implement the functions specified in one or more blocks of the flowchart.

[0074] Therefore, the blocks of the flowchart illustration support a combination of components for performing the specified functions, a combination of steps for performing the specified functions, and program instruction components for performing the specified functions. It will also be understood that each block of the flowchart illustration and the combination of blocks in the flowchart illustration can be implemented by a computer system based on special-purpose hardware that performs the specified functions or steps, or by a combination of special-purpose hardware and computer instructions.

[0075] One or more embodiments of the present disclosure may be systems, methods, and / or computer program products. A computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform various aspects of the present disclosure.

[0076] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove on which instructions are recorded, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be interpreted as a temporary signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (e.g., a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0077] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium in the corresponding computing / processing device.

[0078] The computer-readable program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as "C" programming languages ​​or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, an electronic circuit including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions to personalize the electronic circuit by utilizing the state information of the computer-readable program instructions, so as to perform various aspects of the present disclosure.

[0079] Various aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustration and / or block diagram and the combination of blocks in the flowchart illustration and / or block diagram can be implemented by computer-readable program instructions.

[0080] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create components for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can guide the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable storage medium with instructions stored therein includes an article of manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0081] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, so that a series of operating steps are performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0082] The flow charts and block diagrams in the accompanying drawings illustrate the architecture, functions and operations of possible implementations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each frame in the flow chart or block diagram may represent a module, segment or portion of an instruction, which includes one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the frame may not occur in the order marked in the figure. For example, depending on the functions involved, two frames shown in succession may be executed substantially simultaneously, or these frames may sometimes be executed in reverse order. It will also be noted that each frame illustrated in the block diagram and / or flow chart and the combination of frames in the block diagram and / or flow chart may be implemented by a dedicated hardware-based system that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

[0083] In addition, the system according to various embodiments may include a processor and logic integrated with the processor and / or executable by the processor, which is configured to perform one or more of the process steps described herein. By integrated, it is meant that the processor has logic embedded therein as hardware logic, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc. By executable by the processor, it is meant that the logic is hardware logic; software logic, such as a part of firmware, an operating system, a part of an application; etc., or some combination of hardware and software logic, which is accessible by the processor and is configured to cause the processor to perform a certain function when executed by the processor. The software logic can be stored on local and / or remote memory of any memory type, as is known in the art. Any processor known in the art, such as a software processor module and / or a hardware processor, such as an ASIC, FPGA, a central processing unit (CPU), an integrated circuit (IC), a graphics processing unit (GPU), etc., can be used.

[0084] The corresponding structures, materials, actions and equivalents of all parts or steps plus function elements in the following claims are intended to include any structure, material or action for performing functions in combination with other claimed elements as specifically claimed. The description of the embodiments of the present disclosure has been presented for the purpose of illustration and description, but it is not intended to be exhaustive or limited to the embodiments in the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present disclosure. The embodiments and examples are selected and described in order to best explain the principles and practical applications of the present disclosure, and to enable other persons of ordinary skill in the art to understand the various embodiments of the present disclosure with various modifications, which are suitable for the specific purposes contemplated.

[0085] The programs described herein are identified based on the applications in which they are implemented in the specific embodiments of the present disclosure. However, it should be understood that any specific program naming herein is used only for convenience, and therefore the present invention should not be limited to use in any specific application identified and / or implied by such naming.

[0086] It is clear that the various features of the foregoing systems and / or methods may be combined in any manner, resulting in multiple combinations from the description presented above.

[0087] It will also be appreciated that embodiments of the present disclosure may be provided as a service deployed on behalf of a customer to provide services on demand.

[0088] The description of various embodiments of the present disclosure has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An information processing system, comprising: A processor for processing data; one or more memory devices having a plurality of locations for storing the data, each location having a physical address; a memory controller configured to control read and write access to the one or more memory devices; Wherein, in response to a request to convert a first virtual address into a second address, the processor is configured to: combining a page directory base address and a first level memory offset; and sending a second level memory offset along with a combined page directory base address and a first level memory offset from the processor to the memory controller; and The memory controller is configured as follows: receiving from the processor the second level memory offset along with the combined page directory base address and the first level memory offset; reading a first level page directory table from the one or more memory devices using the page directory base address and the first level memory offset; combining the first level page directory table with the second level memory offset; and A second level page directory table is read from the one or more memory devices using the first level page directory table and the second level memory offset. 2 . The information handling system of claim 1 , wherein the memory controller is configured to send a page table entry (PTE) to the processor, wherein the PTE contains a translation of the first virtual address to the second address.

3. The information handling system of claim 1 , wherein the system is further configured to send a memory row containing an address of a page table entry (PTE) from the memory controller to the processor, and wherein the processor is further configured to extract the page table entry (PTE) from the memory row containing the address of the page table entry (PTE). 4 . The information handling system of claim 1 , wherein in response to determining that all memory offsets have been combined with a page directory table, the memory controller is configured to send a page table entry (PTE) to the processor. 5 . The information handling system of claim 1 , wherein the memory controller is local to the one or more memory devices and is further configured to obtain a memory line containing an address of the first level page directory table from the one or more memory devices. 6 . The information handling system of claim 5 , wherein the memory controller is further configured to extract the address of the first level page directory table from the memory row containing the address of the first level page directory table.

7. The information processing system of claim 5 , wherein the system is further configured to send the memory row containing the address of the first-level page directory table from the memory controller to the processor, and wherein the processor is further configured to extract the address of the first-level page directory table from the memory row containing the address of the first-level page directory table.

8. The information handling system of claim 1, wherein the memory controller is local to the one or more memory devices and is further configured to obtain a memory line containing an address of the second level page directory table from the one or more memory devices. 9 . The information handling system of claim 8 , wherein the memory controller is further configured to extract the address of the second-level page directory table from the memory row containing the address of the second-level page directory table.

10. The information processing system of claim 8, wherein the system is configured to send the memory row containing the address of the second-level page directory table from the memory controller to the processor, and the processor is further configured to extract the address of the second-level page directory table from the memory row containing the address of the second-level page directory table.

11. The information processing system of claim 1 , wherein in response to the memory controller receiving the page directory base address and the memory offset, the memory controller is configured to control all memory read operations for the multiple page directory tables stored in the memory, and the system is configured so that all memory read operations for the multiple page directory tables stored in the memory are initiated in the memory controller.

12. The information handling system of claim 1, wherein the system is configured such that all memory offsets are sent together from the processor to the memory controller.

13. The information handling system of claim 1, wherein a memory controller is configured to combine the page directory base address and a first level memory offset.

14. The information handling system of claim 1, wherein the memory controller is further configured to combine a third-level memory offset with the second-level page directory table, and read the third-level page directory table from a memory using the third-level memory offset and the second-level page directory table.

15. The information handling system of claim 1, wherein the system is configured to send only a memory line containing an address of a page table entry to the processor in response to the request for translation, and none of the page directory tables are sent from the memory controller to the processor.

16. The information handling system of claim 1, wherein the translated request comprises a nested translation having a guest virtual address and a host virtual address.

17. A computing system comprising: A processor for processing data; one or more memory devices having a plurality of locations for storing the data, each location having a physical address; a memory controller, local to the one or more memory devices, the memory controller controlling read and write access to the one or more memory devices; A computer-readable storage medium including program instructions that, when executed by the processor, in response to a request to convert a first virtual address to a second address, cause the processor to: Combine page directory base address and first level memory offset; as well as sending a second level memory offset from the processor to the memory controller along with a combined page directory base address and the first level memory offset; as well as A computer-readable storage medium including program instructions that, when executed by the memory controller, in response to the request to translate the first virtual address to the second address, cause the memory controller to: receiving from the processor the second level memory offset along with the combined page directory base address and the first level memory offset; reading a first level page directory table from the one or more memory devices using the page directory base address and the first level memory offset; combining the first level page directory table with the second level memory offset; reading a second level page directory table from a memory using the first level page directory table and the second level memory offset; as well as A page table entry PTE is sent to the processor.

18. The computing system of claim 17, further comprising program instructions that, when executed by the memory controller, cause the memory controller to send the page table entry (PTE) to the processor in response to determining that all of the plurality of memory offsets have been combined with the plurality of page directory tables.

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