High-performance and area-efficient synaptic memory cell structure

Abstract

A synaptic memory system includes: synaptic memory cells disposed at the intersection of axons and dendritic lines, each synaptic memory cell including a plurality of analog memory devices, each synaptic memory cell being configured to store weight values ​​according to the output level of a write signal, the plurality of analog memory devices being combined to form each synaptic memory cell; a write portion configured to write the weight values ​​to each synaptic memory cell and including a write driver and an output controller, the write driver being configured to output the write signal to each synaptic memory cell, the output controller being configured to control the output level of the write signal of the write driver; and a read driver configured to read the weight values ​​stored in the synaptic memory cells.

Description

Technical Field

[0001] This invention relates to a high-performance and area-efficient synaptic memory cell structure. In particular, this invention provides a system and method for operating the synaptic memory cell structure. Background Technology

[0002] Analog memories, with their continuously controllable resistance and capacitance, are commonly used as memory devices to store synaptic weights in neural network systems. For good performance in a neural network system, synaptic memory cells preferably have high resolution. Many memory devices have low resolution or small dynamic range. Due to the device characteristics and noise margins of these memory devices, it is difficult to improve them. Some memory devices have a rectangular shape, which has a large aspect ratio unsuitable for integration into array blocks. Therefore, there is a need in the art to address the aforementioned problems. Summary of the Invention

[0003] From a first aspect, the present invention provides a synaptic memory system, comprising: a plurality of synaptic memory cells disposed at intersections of a plurality of axons and a plurality of dendritic lines, each synaptic memory cell including a plurality of analog memory devices, each synaptic memory cell configured to store a weight value according to an output level of a write signal, the weight value to be stored in each synaptic memory cell being one of at least three different values, the plurality of analog memory devices being combined to constitute each synaptic memory cell; a write portion configured to write the weight value to each synaptic memory cell, the write portion including a write driver and an output controller, the write driver being configured to output the write signal to a target synaptic memory cell, the target synaptic memory cell being one of the synaptic memory cells, the target synaptic memory cell being selected to store the weight value, the output controller being configured to control the output level of the write signal of the write driver; and a read driver configured to read the weight value stored in the synaptic memory cell.

[0004] In another aspect, the present invention provides an apparatus including a synaptic memory system, wherein the synaptic memory system comprises: a plurality of synaptic memory cells disposed at intersections of a plurality of axons and a plurality of dendritic lines, each synaptic memory cell including a plurality of analog memory devices, each synaptic memory cell being configured to store a weight value according to an output level of a write signal, the weight value to be stored in each synaptic memory cell being one of at least three different values, the plurality of analog memory devices being combined to form each synaptic memory cell; a write portion configured to write the weight value to each synaptic memory cell, the write portion including a write driver and an output controller, the write driver being configured to output the write signal to a target synaptic memory cell, the target synaptic memory cell being one of the synaptic memory cells selected to store the weight value, the output controller being configured to control the output level of the write signal of the write driver; and a read driver configured to read the weight value stored in the synaptic memory cell.

[0005] In another aspect, the present invention provides a method for operating a synaptic memory system, the synaptic memory system comprising: a plurality of synaptic memory cells disposed at intersections of a plurality of axons and a plurality of dendritic lines, each synaptic memory cell including a plurality of analog memory devices; a write portion including a write driver and an output controller; and a set of read drivers; the method comprising: storing weight values ​​by the synaptic memory cells of the system according to the output level of a write signal, the stored weight values ​​being one of at least three different values; writing the weight values ​​into the synaptic memory cells by the write portion, the writing comprising: outputting the write signal to the synaptic memory cell selected to store the weight values ​​by the write driver, and controlling the output level of the write signal of the write driver by the output controller; and reading the weight values ​​stored in the synaptic memory cells by the read drivers.

[0006] According to one aspect of the present invention, a synaptic memory system is provided. The system includes a plurality of synaptic memory cells, a write section, and a read driver. The plurality of synaptic memory cells are disposed at the intersections of a plurality of axial synapses and a plurality of dendritic synapses. Each synaptic memory cell includes a plurality of analog memory devices. Each synaptic memory cell is configured to store a weight value based on the output level of a write signal. The weight value to be stored in each synaptic memory cell is one of at least three different values. The plurality of analog memory devices are combined to constitute each synaptic memory cell. The write section is configured to write the weight value to each synaptic memory cell. The write section includes a write driver and an output controller. The write driver is configured to output a write signal to a target synaptic memory cell. The target synaptic memory cell is one of the synaptic memory cells. The target synaptic memory cell is selected to store the weight value. The output controller is configured to control the output level of the write signal of the write driver. The read driver is configured to read the weight value stored in the synaptic memory cell.

[0007] According to another aspect of the present invention, an apparatus comprising the above-described synaptic memory system is provided. Attached Figure Description

[0008] The invention will now be described by way of example only with reference to preferred embodiments, as shown in the following figures:

[0009] Figure 1 A synaptic memory with a cross-shaped array is shown according to a first exemplary embodiment of the present invention.

[0010] Figure 2 A synaptic memory system according to a first exemplary embodiment is shown.

[0011] Figure 3 A timing diagram illustrating the timing of the signal output is shown.

[0012] Figure 4 Synaptic memory and synaptic memory units are shown, each unit consisting of multiple memory devices.

[0013] Figure 5A An exemplary structure of an analog memory composed of MRAM is shown. Figure 5B It shows Figure 5A The analog memory stores the state of the maximum (or minimum) value. Figure 5C It shows Figure 5A The analog memory stores the state of the minimum (or maximum) value.

[0014] Figure 6 It shows Figures 5A to 5C The analog memory shown is an exemplary configuration for each memory device in the synaptic memory cell.

[0015] Figure 7 An example of a device including a neural synaptic core system is shown. Detailed Implementation

[0016] In the following, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the present invention is not limited to the exemplary embodiments given below, and can be implemented with various modifications within the scope of the invention. Furthermore, the drawings used herein are for illustrative purposes and do not show actual dimensions.

[0017] First exemplary embodiment

[0018] Figure 1 A synaptic memory 100 with a cross-shaped array according to a first exemplary embodiment of the present invention is depicted.

[0019] The hardware implementation of a neuromorphic system can include synaptic memory, neuronal bodies, and network connections with axons and dendrites. For example... Figure 1 As shown, the synaptic memory 100 may include synaptic memory units 10 disposed / placed at all intersections of all axons (axonal lines) 20 and all dendrites (dendritic lines) 30. Each synaptic memory unit 10 may be configured to store a synaptic weight value indicating the weight of the synaptic connection of the corresponding synaptic memory unit 10. Note that axons 20 correspond to the corresponding axons of the preneurons, and dendrites 30 correspond to the corresponding dendrites of the postneurons.

[0020] The memory device of the synaptic memory cell 10 may be non-volatile random access memory (NVRAM), which is analog memory. The synaptic memory cell 10 will be described in detail later.

[0021] Figure 2 A synaptic memory system 1 according to a first exemplary embodiment is depicted.

[0022] like Figure 2 As shown, the synaptic memory system 1 may include a synaptic memory 100, a write driver 40, a write line selector 45, a read driver 50, a read driver selector 150, a weight evaluator 70, a weight encoder 80, and a write pulse generator 90. Note that the synaptic memory system 1 may be a neuromorphic system on silicon. The synaptic memory system 1 is an example of the claimed synaptic memory system.

[0023] Here, as referenced above Figure 1 The synaptic memory 100 has a cross-shaped array of axons 20 and dendrites 30, and includes synaptic memory cells 10 arranged at all intersections of axons 20 and dendrites 30.

[0024] A write driver (synaptic memory cell driver) 40 is connected to the synaptic memory 100. The write driver 40 can be configured to write synaptic weight values ​​to the corresponding synaptic memory cells 10 in response to a learning operation input or a recognition operation input. Specifically, the write driver 40 can apply voltage to a prong 20 selected by a write line selector 45, which selects the prong 20 to which the write driver 40 applies voltage. For example, the write line selector 45 switches the selected prongs 20 in a predetermined order at a certain timing. In this example, the weight encoder 80 controls the write driver 40 and the write line selector 45 to apply voltage to the synaptic memory cells 10 located on the prongs 20 selected by the write line selector 45 according to the switching timing of the write line selector 45. This allows synaptic weight values ​​to be written to all synaptic memory cells 10 located on each prong by a pair of write drivers 40 and write line selectors 45.

[0025] Dendrite 30 is connected to a dendrite driver (not shown), which selects a target dendrite from the dendrite 30 and uses this target dendrite to write or read synaptic weight values ​​during a write operation or a read operation. The dendrite driver can selectively apply voltage to the dendrite 30. This allows the dendrite driver to identify (multiple) target dendrites. Specifically, during a write operation of the synaptic weight value, the dendrite driver sets one of the dendrites 30 to ground (GND) and sets the other dendrites 30 to high impedance (Hi-Z). A write line selector 45 selects one of the axons 20 connected to the write driver 40 to apply a voltage to it. Thus, the synaptic weight value is written to the synaptic memory cell 10 at the intersection of the dendrite 30 set to GND and the axon 20 to which the write driver 40 applies the voltage. The write driver 40 receives pulse signals for controlling output timing. A drive voltage (VDD) is applied to the write driver 40. Note that the write driver 40 is configured to control the voltage applied to the synaptic memory cell 10.

[0026] A read driver 50 is connected to the synaptic memory 100. The read driver 50 can be configured to read synaptic weight values ​​from the synaptic memory cells 10 in response to an identification operation input. Specifically, a dendrite driver (not shown) sets the dendrite 30 used for reading the synaptic weight values ​​to the GND state and sets the other dendrites 30 to the Hi-Z state. A read driver selector 150 selects or enables the read driver 50 corresponding to the axon 20 to apply voltage to it. This results in the reading of synaptic weight values ​​from the synaptic memory cells 10 at the intersection of the dendrite 30 set to the GND state and the axon 20 to which voltage is applied by the read driver 50. In the synaptic weight value reading operation, a total synaptic weight value is read for each dendrite 30 set to the GND state. The total synaptic weight value is the sum of the synaptic weight values ​​of the individual synaptic memory cells 10 on the axon 20 to which voltage is applied.

[0027] The weight evaluator 70 can use the neuronal output signal from the dendrite 30 to evaluate the current synaptic weight value and determine the next synaptic weight value. Specifically, the weight calculator 70 compares the neuronal output signal obtained from the dendrite 30 with the expected output signal given as input to the learning operation and calculates the next synaptic weight value, which is used to update the current synaptic weight value stored in the synaptic memory unit 10.

[0028] The weight encoder 80 can encode the next synaptic weight value calculated by the weight evaluator 70. The weight encoder 80 controls the drive voltage of the write driver 40 based on the next synaptic weight value calculated by the weight evaluator 70. This enables the write driver 40 to control the voltage applied to the synaptic memory cell 10.

[0029] The write pulse generator 90 can perform modulation processing, such as pulse width modulation and pulse quantity (or frequency) modulation. In other words, the write pulse generator 90 can generate and output a pulse signal based on the encoded value generated by the weight encoder 80. This pulse signal, along with the drive voltage controlled by the weight encoder 80, enables the write driver 40 to update the current synaptic weight value stored in the synaptic storage unit 10.

[0030] To update the current synaptic weight value, several methods can be applied, such as (i) adding the gap between the current synaptic weight value and the next synaptic weight value to the current synaptic weight value, and (ii) resetting the current synaptic weight to the minimum value, thereby writing the next synaptic weight value.

[0031] For example, method (i) can be applied to update the synaptic weight value by reducing the synaptic weight value. That is, in the NVRAM used as the synaptic memory cell 10, the stored value can be reduced by applying a voltage with the opposite polarity to the voltage applied to increase the stored value, and the amount of reduction of the stored synaptic weight value can be controlled by the value of the power supply voltage.

[0032] In method (i), several levels can be set regarding the output value of the write driver 40 to control the synaptic weight value. For example, the levels are "driver common level," "set threshold level," and "reset threshold level." The driver common level is the voltage level when the write driver 40 is in a turned-off (inactive) state. The synaptic memory cell 10 is configured to maintain the current weight value if the output of the write driver 40 is between the set threshold level and the reset threshold level, or in a high impedance (Hi-Z) state, and the voltage applied to the dendrite 30 is at the driver common level. The set threshold level (i.e., the positive threshold level) is the voltage level at or above which a write operation increasing the synaptic weight value can be performed. The reset threshold level (i.e., the negative threshold level) is the voltage level at or below which a write operation decreasing the synaptic weight value can be performed. The output value of the write driver 40 is an example of the output level that is claimed to be protected.

[0033] refer to Figure 3 The above method will be described in more detail. Figure 3 This is a timing diagram showing the timing of signal outputs from write driver 40, the timing of signal outputs from read driver 50, and the timing of state transitions in synaptic memory cell 10.

[0034] (1) First, from time t1 to time t2 (segment t1-t2), the write driver 40 applies a voltage below the reset threshold level to one of the synaptic memory cells 10 (target cell), causing the write driver 40 to set the target cell to a reset state (a specific decrement value). That is, a write operation to reduce the synaptic weight value is performed. The value to be decremented in the target cell depends on the amount by which the voltage applied by the write driver 40 drops below the reset threshold level. In this timeline, this operation is performed in state "Reset 1".

[0035] (2) Next, from time t2 to time t3 (segment t2-t3), the write driver 40 applies a voltage higher than the set threshold level to the target cell, causing the write driver 40 to set the target cell to a set state (a certain increment value). That is, a write operation that increases the synaptic weight value is performed. The increment value in the target cell depends on the amount by which the voltage applied by the write driver 40 exceeds the set threshold level. In this timeline, this operation is performed in state "Set 1".

[0036] (3) Next, from time t4 to time t5 (segment t4 to t5), the read driver 50 applies a voltage between the driver common level and the set threshold level to the target cell, causing the read driver 50 to set the target cell to the read state. That is, the synaptic weight value read operation is performed. If the target cell read in this state is the same as the target cell written in the "Set 1" state, then the value to be read at this point corresponds to the synaptic weight value updated in step (2) above. In this timeline, this operation is performed in the state "Read 1".

[0037] (4) Next, from time t6 to time t7 (segment t6 to t7), the write driver 40 applies a voltage below the reset threshold level to the target cell, causing the write driver 40 to set the target cell to another reset state to achieve another decremented value. That is, a write operation to reduce the synaptic weight value is performed. In this timeline, this operation is performed in state "Reset 2".

[0038] (5) Next, from time t8 to time t9 (segment t8 to t9), the read driver 50 applies a voltage between the driver common level and the set threshold level to the target cell, causing the read driver 50 to set the target cell to another read state. That is, a synaptic weight value read operation is performed. If the target cell read in this state is the same as the target cell written in the "Reset 2" state, then the value to be read at this time corresponds to the synaptic weight value updated in step (4) above. In this timeline, this operation is performed in state "Read 2".

[0039] (6) During periods other than t1-t2, t2-t3, and t6-t7, the target cell is set to a high impedance (Hi-Z) state relative to the write driver 40, meaning that no write operation is performed during these periods. Furthermore, during periods other than t4-t5 and t8-t9, the target cell is set to a high impedance state relative to the read driver 50, meaning that no read operation is performed during these periods.

[0040] When the write driver 40 is in the off state, the applied voltage of the synaptic memory cell 10 is between the set threshold level and the reset threshold level or a high impedance state, and the synaptic memory cell 10 maintains the current weight value. This prevents write operations on the synaptic weight value.

[0041] In response to the output signal from the write driver 40, the applied voltage moves from the driver common level to the set threshold level or above, or to the reset threshold level or below.

[0042] When the voltage applied by the write driver 40 exceeds a set threshold level, the synaptic weight value is updated to increase. The amount of increase depends on how much the voltage applied by the write driver 40 exceeds the set threshold level. In other words, by adjusting the voltage applied by the write driver 40, i.e., by selecting the write level to control the amount of excess, the increment of the synaptic weight value can be controlled.

[0043] When the voltage applied by the write driver 40 drops below the reset threshold level, the synaptic weight value is updated to decrease. The amount of decrease depends on how much the voltage applied by the write driver 40 drops below the reset threshold level. In other words, by adjusting the voltage applied by the write driver 40, i.e., by selecting the write level, the amount of decrease is controlled, thus enabling control over the amount of decrease in the synaptic weight value.

[0044] Note that if the applied voltage is within the range between the set threshold level and the reset threshold level, the synaptic weight value is maintained. In other words, write operations on the synaptic memory cell 10 are not performed. The read driver 50 reads the synaptic weight value from the synaptic memory cell 10 by applying a voltage within this range to the synaptic memory cell 10.

[0045] The following is a description of the synaptic memory unit 10.

[0046] Non-volatile random access memory (NVRAM) as analog memory can be used as synaptic memory cell 10. Analog memory has the characteristic that its resistance and capacitance can be continuously controlled. Examples of NVRAM include flash memory, ferroelectric random access memory (FeRAM), magnetoresistive random access memory (MRAM), phase-change random access memory (PRAM), and resistive random access memory (ReRAM).

[0047] Writing data to the NVRAM is performed by applying a voltage or current to the NVRAM. The NVRAM can store data using a state change of the corresponding synaptic memory cell 10 in response to the applied voltage or current. Note that the state change used to record data depends on the structure of the NVRAM. For example, state changes can include changes in electrical state, changes in magnetic state, and changes in phase.

[0048] The degree of state change can vary depending on the magnitude of the applied voltage or current (i.e., voltage or current value). This allows NVRAM to store continuous values ​​(analog values) or multiple values ​​(discrete values). Note that NVRAM can store and retain values ​​as one of at least three different (non-digital) values. In other words, NVRAM can be used as analog memory. In the example shown in the figure, synaptic memory cell 10 is constructed of NVRAM such that controlling the voltage or current value applied to the NVRAM can control the synaptic weight values ​​stored in synaptic memory cell 10. Specifically, if a voltage value is used to control the write operation, a larger voltage value allows the NVRAM to store a larger synaptic weight value. This adjustment of voltage (current) can be done after the synaptic memory system 1 (described later) is manufactured. Note that whether to use a voltage value or a current value to control the write operation on the NVRAM can be determined based on the characteristics of the NVRAM, such as the type of state change for data recording and the width, speed, or precision of the state change depending on the voltage or current value.

[0049] Incidentally, in order to achieve good performance as a neural network system, it is desirable for the synaptic memory cell 100 to have a resolution step size greater than sufficient. However, many memory devices have rather low resolution or small dynamic range, and it is difficult to improve them due to device characteristics and noise margins.

[0050] Therefore, in this embodiment, multiple memory devices with low resolution or small dynamic range (or both) are combined into a single synaptic memory (synaptic memory unit 10). More preferably, different amplitudes can be assigned to each device so that the overall dynamic range can be increased.

[0051] Figure 4 Synaptic memory 100 and synaptic memory unit 10 are depicted, each of which consists of multiple memory devices.

[0052] In the figure, m memory devices 11 are combined to form a synaptic memory cell 10. It is assumed that the memory devices 11 included in a synaptic memory cell 10 have identical device characteristics. Furthermore, it is assumed that each memory device 11 has n resolution steps.

[0053] Since a synaptic memory cell 10 consists of m memory devices 11, m rows of dendrites corresponding to each memory device 11 are connected in a synaptic memory cell 10. These m rows constitute a set of dendrites 30.

[0054] Each of the m lines constituting a set of dendrites 30 is assigned a number in the range of 0 to (m-1). When it is necessary to distinguish the memory devices 11 constituting the synaptic memory unit 10 from one another, each memory device 11 is hereinafter labeled with the number of the line connected to that memory device 11, such as memory device 11(0), memory device 11(1)..., memory device 11(m-2) and memory device 11(m-1).

[0055] Figure 4 The overall resolution of the synaptic memory cell 10 shown is determined by a combination of the dynamic ranges of multiple memory devices 11. For example, the overall resolution of the synaptic memory cell 10 is represented by an exponential scale using the resolution (n) of the memory devices 11, where n is the base. Thus, each memory device 11 is assigned a different amplitude. More specifically, assuming the resolution of the synaptic memory cell 10 is an m-bit value, memory device 11(0) represents the first bit, memory device 11(1) represents the second bit, ..., memory device 11(m-2) represents the (m-1)th bit, and memory device 11(m-1) represents the m-th bit.

[0056] To obtain the overall resolution of the synaptic memory cell 10, the converter 12(k-1) (k = 1, 2, ..., m) converts the current from each line constituting a set of dendrites 30 according to the bits expressed by the corresponding memory device 11. More specifically, the current from the line connected to the memory device 11(0) is multiplied by one (or n). 0 The current from the line connected to memory device 11(1) multiplied by n (or n 1 ), ..., the current from the line connected to memory device 11(m-2) multiplied by n m-2 And the current from the line connected to memory device 11(m-1) multiplied by n m-1 Therefore, the output from each line can represent a bit of the corresponding memory device 11(k-1) (k = 1, 2, ..., m) that forms part of the resolution value of the synaptic memory cell 10 as a whole.

[0057] Then, adder 13 sums the currents from these lines. As described above, the output current from each line has been converted according to the number of bits of resolution of the synaptic memory cell 10, and therefore summing these currents allows for a current corresponding to the overall resolution of the synaptic memory cell 10. The current-to-voltage converter (IVC) 14 then converts the output value into a voltage, which is then converted from analog to digital by analog-to-digital converter (ADC) 15. The resulting digital value is output as an output signal from the merged dendrite 35.

[0058] Figure 7An example of a device 1010 including a neural synaptic core system 1000 is described.

[0059] like Figure 7 As shown, the synaptic memory system 1 can be provided on a device 1010 such as a computer. In the example shown, multiple neural synaptic core systems 1000 are disposed on a chip 1001, such as a semiconductor chip. The chip 1001 is then mounted on the device 1010.

[0060] Each neural synaptic core system 1000 includes a synaptic memory system 1 and a neuronal body 700. The neuronal body 700 performs neuronal operations. Specifically, the neuronal body 700 obtains the product of synaptic weight values ​​and input values ​​based on a total current sensed by a current sensor. The total current sensed by the current sensor can represent the product of synaptic weight values ​​and input values ​​stored in the synaptic memory unit 10 at the intersection of a selected axon 20 and a set of dendrites 30. The neuronal body 700 then outputs a neuronal output corresponding to the total current value.

[0061] Here, the neural synaptic core system 1000 is interconnected via pre-drive axons 25. The synaptic storage system 1 is connected to the pre-neuron via the pre-drive axons 25. The neuronal body 700 is part of the post-neuron, and its output is connected to the pre-drive axons 25 of the synaptic storage system 1 in the same or other neural synaptic core systems 1000. The synaptic storage system 1 receives output signals from the pre-neuron to accumulate the weight values ​​of the synapses activated via its axons 20. If the accumulated value of the synaptic weight values ​​multiplied by the input values ​​from the axons 20 (or pre-drive axons 25) reaches a predetermined threshold, the neuronal body 700 outputs a signal at the pre-drive axon 25 as the neuronal output of the post-neuron.

[0062] Second exemplary embodiment

[0063] Figure 5A An exemplary structure of an analog memory composed of MRAM is shown. Figure 5B It shows Figure 5A The analog memory stores the state of the value "0". Figure 5C It shows Figure 5A The analog memory stores the state of the value "1".

[0064] The analog memory 16 includes a free layer 161 and a pinned layer 162. The free layer 161 is planar and includes a fixed region 161a at its ends and a data region 161b between the fixed regions 161a. The pinned layer 162 is deposited on a corresponding fixed region 161a at the ends of the free layer 161.

[0065] When excited by the pinned layer 162, the two fixed regions 161a have magnetic fields in opposite directions.

[0066] Due to the influence of fixed region 161a, the magnetic field of data region 161b can be the same as the magnetic field of either fixed region 161a, or it can partially include the magnetic fields of both fixed regions 161a. The boundary where the magnetic field of data region 161b changes is called domain wall 161c.

[0067] When the fixed region 161a is activated by the pinned layer 162, the position of the domain wall 161c moves within the data region 161b between the fixed regions 161a. Analog values ​​are stored based on the position of the domain wall 161c.

[0068] Therefore, in order to increase the dynamic range of the analog memory 16 configured as described above, it is necessary to increase the length that the domain walls 161c can move as much as possible. In other words, the length of the data region 161b ( Figure 5A The length A in the equation needs to be as long as possible. In other words, the distance between the two fixed regions 161a needs to be as long as possible.

[0069] Meanwhile, when writing to memory, domain wall 161C, as Figure 5B and Figure 5C As shown, when moving between two fixed regions 161a, the current (or electron movement per unit time) exceeding a certain threshold amount increases from greater than... Figure 3 The voltage at which the threshold level is set or reset is affected. The direction of electron movement (opposite to the current direction) is... Figure 5B and Figure 5C As shown in the diagram, the amount of movement of the domain wall 161c depends on the current (the amount of electrons moving per unit time). Therefore, the number of recorded value stages in the memory over its entire range is related to the domain wall 161c. Figure 5B The magnetic domain walls move to Figure 5C The length of the data region 161b of the magnetic domain walls is proportional. Therefore, Figure 5A The length A of the device 16 should be maximized. On the other hand, the recording current is proportional to the cross-sectional area of ​​the storage device perpendicular to the flowing current. Therefore, Figure 5A The width b of the device 16 should be minimized to reduce recording current and thus power consumption. For these reasons, the analog memory 16, which has a large dynamic range and sufficient storage value resolution at low power consumption, will have a large aspect ratio. Figure 5A (The ratio of a to b).

[0070] refer to Figures 5A to 5C The structure of analog memory 16 explained is for illustrative purposes only. However, many analog memories actually exhibit large aspect ratios, which allows them to have large dynamic ranges and many small steps.

[0071] Assuming reference Figure 4 Each of the memory devices 11 of the synaptic memory units 10 explained is referenced Figures 5A to 5C The analog memory 16 is explained.

[0072] Figure 6 It shows Figures 5A to 5C The analog memory 16 shown is an exemplary configuration for each memory device 11 in the synaptic memory unit 10.

[0073] exist Figure 6 In the example shown, the plurality of memory devices 11 (analog memory 16) in each synaptic memory unit 10 are configured such that their long sides (along...) Figure 5A The sides of the synaptic memory cell 10 (in the direction of length a) are parallel to each other. This can reduce the overall aspect ratio of the synaptic memory cell 10 (i.e., the ratio of the vertical direction of the memory cell 11 to the orientation of the memory cell 11) relative to the aspect ratio of a single memory device 11. This increases the flexibility in the shape of the synaptic memory cell 10 and the synaptic memory 100 in a configuration in which multiple memory devices 11 are combined into one synaptic memory cell 10.

[0074] Third Exemplary Example

[0075] For reference Figure 2 As explained, the synaptic memory system 1 may include or may include an external block that may include peripheral devices connected to the synaptic memory 100. These peripheral devices include those disposed on the axonal 20 side of the synaptic memory 100 and those disposed on the fused dendrite 35 side of the synaptic memory 100.

[0076] During normal operation of the synaptic memory system 1, involving reasoning (or recognition) and training, the signal output from the preneuron body 700 is input into the synaptic memory 100 via the pre-driven axon 25, which then outputs the signal to the postneuron body 700 via the fused dendrites 35.

[0077] On the other hand, under the operation of the synaptic memory system 1 involving back propagation, the signal output from the postneuron body 700 is input to the synaptic memory 100 via the merged dendrites 35, which then outputs the signal to the preneuron body 700 via the pre-driven axon 25.

[0078] Therefore, a set of peripheral devices of nearly the same size is provided on both the axon 20 (or pre-driven axon 25) side and the dendrite 30 (or merged dendrite 35) side of the synaptic memory 100. Thus, as the aspect ratio of the synaptic memory 100 (i.e., the ratio of its length along its axon 20 to its length along its dendrite 30) becomes closer to 1:1, it becomes easier to place peripheral devices relative to the synaptic memory 100, and therefore easier to design the synaptic memory system 1.

[0079] For reference Figure 4 As explained, when the synaptic memory cell 10 consists of multiple memory devices 11, the synaptic memory cell 10 can have a large aspect ratio, depending on the number of memory devices 11 included in the synaptic memory cell 10. In this case, in order to reduce the overall aspect ratio of the synaptic memory 100, the synaptic memory cells 10 need to have blank gaps spaced apart from each other in the vertical direction according to the aspect ratio of each synaptic memory cell 10, which results in the creation of useless space.

[0080] On the other hand, such as Figure 6 As shown, arranging the analog memory 16 as a memory device 11 in each synaptic memory unit 10 can reduce the overall aspect ratio of the synaptic memory 100 while eliminating unused space.

[0081] More specifically, the plurality of memory devices 11 (analog memory 16) in each synaptic memory cell 10 are arranged such that their long sides are parallel to each other. This allows the aspect ratio of the synaptic memory cells 10 to be close to 1:1. Therefore, the synaptic memory 100 composed of such synaptic memory cells 10 can have an aspect ratio close to 1:1, and there is no useless space between the synaptic memory cells 10.

Claims

1. A synaptic memory system, comprising: Multiple synaptic memory units are disposed at the intersections of multiple axons and multiple dendritic lines. Each synaptic memory unit includes multiple analog memory devices, each analog memory device includes multiple resolution steps, and each synaptic memory unit is configured to store weight values ​​according to the output level of a write signal. The weight value to be stored in each synaptic memory unit is one of at least three different values. The multiple analog memory devices are combined to form each synaptic memory unit, and each synaptic memory unit is represented by an exponential scale of multiple resolution steps used by the analog memory devices in each synaptic memory unit. A write portion configured to write the weight value to each synaptic memory cell includes a write driver and an output controller. The write driver is configured to output the write signal to a target synaptic memory cell, which is one of the synaptic memory cells selected to store the weight value. The output controller is configured to control the output level of the write signal from the write driver. And a read driver, configured to read weight values ​​stored in the synaptic memory cell.

2. The synaptic memory system of claim 1, wherein the dynamic ranges of the plurality of analog memory devices are combined to obtain the dynamic range of each synaptic memory cell as a whole.

3. The synaptic memory system of claim 2, wherein each of the plurality of analog memory devices is assigned a different amplitude.

4. The synaptic memory system of claim 1, wherein the plurality of synaptic memory cells are arranged such that the long sides of the plurality of analog memory devices included in each synaptic memory cell are parallel to each other.

5. The synaptic memory system of claim 4, wherein the aspect ratio of each synaptic memory cell is smaller than the aspect ratio of each analog memory device.

6. The synaptic memory system of claim 4, wherein the aspect ratio of each synaptic memory cell is approximately 1:

1.

7. The synaptic memory system according to any one of claims 1-6, wherein each analog memory device comprises non-volatile random access memory (NVRAM).

8. The synaptic memory system according to any one of claims 1-6, wherein each analog memory device comprises a magnetoresistive random access memory (MRAM).

9. A method for operating a synaptic memory system, the synaptic memory system comprising: Multiple synaptic memory units are arranged at the intersection of multiple axons and multiple dendritic lines. Each synaptic memory unit includes multiple analog memory devices, each analog memory device includes multiple resolution steps, the multiple analog memory devices are combined to form each synaptic memory unit, and each synaptic memory unit is represented by an exponential scale of multiple resolution steps used by the analog memory devices in each synaptic memory unit. The writing section includes the write driver and the output controller; And a set of read drives; The method includes: The weight value is stored by the synaptic memory unit of the system according to the output level of the write signal, and the stored weight value is one of at least three different values; The weight value is written into the synaptic memory cell by the writing portion, the writing including: The write driver outputs the write signal to the synaptic memory cell selected to store the weight value, and the output controller controls the output level of the write signal of the write driver. And the weight values ​​stored in the synaptic memory cell are read by the read driver.

10. The method of claim 9, further comprising combining the dynamic ranges of the plurality of analog memory devices to obtain the dynamic range of each synaptic memory cell as a whole.

11. The method of claim 10, further comprising assigning a different amplitude to each of the plurality of analog memory devices.

12. The method of claim 9, further comprising arranging the plurality of synaptic memory cells such that the long sides of the plurality of analog memory devices included in each synaptic memory cell are parallel to each other.

13. The method of claim 12, wherein the aspect ratio of each synaptic memory cell is smaller than the aspect ratio of each analog memory device.

14. The method of claim 12, wherein the aspect ratio of each synaptic memory unit is approximately 1:

1.

15. The method according to any one of claims 9 to 14, wherein each analog memory device comprises non-volatile random access memory (NVRAM).

16. The method according to any one of claims 9 to 14, wherein each analog memory device comprises a magnetoresistive random access memory (MRAM).

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