TRACK-AND-HOLD CIRCUITS FOR FAST ADWS

Abstract

Featuring track-and-hold functionality: a sampling buffer; a sampling network for sampling a buffered input signal from the sampling buffer onto a capacitor, wherein the sampling network includes a dither capacitor for coupling an additive dither to a summing node of the sampling network; and a hold buffer for receiving a hold signal from the sampling network.

Description

PRIORITY DATA

[0001] The present patent application claims priority over and receives the benefit from the preliminary US patent application filed on December 6, 2017, with serial number 62 / 595,470 entitled “MULTI-INPUT DATA CONVERTERS USING CODE MODULATION” and the US patent application filed on November 16, 2018, with serial number 16 / 193,202 entitled “MULTI-INPUT DATA CONVERTERS USING CODE MODULATION”. TECHNICAL AREA OF REVELATION

[0002] The present disclosure relates to the field of integrated circuits, in particular multi-input data converters using code modulation. GENERAL STATE OF THE ART

[0003] In many electronics applications, an analog-to-digital converter (ADC) transforms an analog input signal into a digital output signal, for example, for further digital signal processing or storage by digital electronics. Generally, ADCs can convert analog electrical signals representing real-world phenomena, such as light, sound, temperature, electromagnetic waves, or pressure, into data processing signals. For example, in measurement systems, a sensor takes measurements and generates an analog signal. This analog signal would then be fed as input to an ADC to generate a digital output signal for further processing. In another scenario, a transmitter generates an analog signal using electromagnetic waves to carry information through the air, or a transmitter transmits an analog signal to carry information over a cable.The analog signal is then supplied as input to an ADW at a receiver to generate a digital output signal, e.g. for further processing by digital electronics.

[0004] Due to their broad applicability in many applications, ADWs are found in places such as broadband communication systems, audio systems, receiver systems, and more. Designing a circuit layout in an ADW is a non-trivial task because each application may have different requirements regarding performance, power, cost, and size. ADWs are used in a wide range of applications, including communications, power, healthcare, instrumentation and measurement, motor and power control, industrial automation, and aerospace / defense. As the number of applications requiring ADWs grows, so does the need for fast yet accurate conversion.

[0005] WO 2009 / 034543 A1 describes a signal acquisition circuit.

[0006] The claimed subject matter is defined in the independent claims. Advantageous further developments are described in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To provide a more complete understanding of the present disclosure, its features and advantages, reference is made to the following description in conjunction with the accompanying figures, where identical reference numbers represent identical parts. They show: Fig. 1 a track-and-hold circuit that controls M ADWs of a time-nested ADW, according to some embodiments of the disclosure; Fig. 2 an exemplary track-and-hold circuit with two buffers and a switching capacitor network between them according to some embodiments of the disclosure; Fig. 3 an exemplary track-and-hold circuit comprising a buffer, a switching capacitor network and an amplifier according to some embodiments of the disclosure; Fig. 4 an exemplary track-and-hold circuit representing an exemplary switching capacitor network with sampling and dither coupling, according to some embodiments of the disclosure; Fig. 5 an exemplary track-and-hold circuit, which represents a further exemplary switching capacitor network with sampling and dither coupling, according to some embodiments of the disclosure; Fig. 6 an exemplary track-and-hold circuit, which also represents a further exemplary switching capacitor network with sampling and dither coupling, according to some embodiments of the disclosure; Fig. 7 an exemplary multi-input ADW according to some embodiments of the disclosure; Fig. 8 a circuit arrangement for implementing coding using a chopper according to some embodiments of the disclosure; Fig. 9 another exemplary multi-input ADW according to some embodiments of the disclosure; Fig. 10 another exemplary multi-input ADW according to some embodiments of the disclosure; Fig. 11 another exemplary multi-input ADW according to some embodiments of the disclosure; Fig. 12 another exemplary multi-input ADW according to some embodiments of the disclosure; Fig. 13-15 nested sampling networks of the multi-input ADW in Fig. 12 according to some embodiments of the disclosure; Fig. 16 another exemplary multi-input ADW according to some embodiments of the disclosure; Fig. 17 a timing diagram showing the timing of the switches in Fig. 16 illustrated, according to some embodiments of the disclosure; Fig. 18 another exemplary multi-input ADW according to some embodiments of the disclosure; Fig. 19 another exemplary multi-input ADW according to some embodiments of the disclosure; Fig. 20 a flowchart illustrating a method for multiplexing inputs into an ADW according to some embodiments of the disclosure; Fig. 21 an exemplary track-and-hold circuit illustrating an exemplary switching capacitor network with sampling and dither coupling, according to some embodiments of the disclosure; Fig. 22 an exemplary track-and-hold circuit illustrating an exemplary switching capacitor network with sampling and dither coupling, according to some embodiments of the disclosure; Fig. 23 a track-and-hold circuit illustrating an exemplary switching capacitor network with sampling and dither coupling, according to some embodiments of the disclosure; and Fig. 24 an exemplary track-and-hold circuit illustrating an exemplary switching capacitor network with sampling and dither coupling, according to some embodiments of the disclosure. DETAILED DESCRIPTION Overview

[0008] A multi-input analog-to-digital converter (ADC) with multiple inputs, i.e., a single ADW, can receive multiple analog input signals and generate multiple digital outputs. To combine multiple analog input signals into a single multi-input ADW, the ADW would typically require multiple track-and-hold (T / H) circuits and an adder, which can consume a significant amount of power and incur substantial costs. An improved approach is to combine multiple inputs through a single T / H circuit in the ADW's front end. The multiple analog input signals can then be aggregated using code sequences, eliminating the need for a significant amount of external circuitry. Fast ADWs

[0009] Analog-to-digital converters (ADCs) are electronic devices that convert a continuous physical quantity passed through an analog signal into a digital output or number representing the amplitude of the quantity (or into a digital signal carrying the digital number). An ADC can be defined by the following application requirements: its speed (number of samples per second), its power consumption, its bandwidth (the range of frequencies of analog signals that it can accurately convert into a digital signal), and its resolution (the number of discrete levels into which the largest analog signal can be divided and represented in the digital signal).An ADW also has various specifications for quantifying its dynamic performance, including signal-to-noise-distortion ratio (SINAD), effective number of bits (ENOB), signal-to-noise ratio (SNR), total harmonic distortion (THD), total harmonic distortion plus noise (THD+N), and no-noise dynamic range (SFDR). ADWs come in many different designs that can be selected based on application requirements and specifications.

[0010] To achieve higher speeds, time-nesting is used to increase the sampling rate of analog-to-digital processors (ADWs). A time-nested ADW can use M ADWs to sample an analog input signal to generate digital outputs. The M ADWs (referred to here as the M slices or M channels) operating in a time-nested manner can increase the sampling rate many times over compared to the sampling rate of a single ADW. The M ADWs can be used in parallel, operating to sample an analog input one after the other in a time-nested manner. Using appropriate clocking to control the ADWs can greatly increase the effective combined ADW sampling rate. In some cases, the M ADWs are selected sequentially to sample the input signal. In other cases, the M ADWs can be selected pseudo-randomly.Since not all M ADWs are precisely matched or identical, discrete tones (noise) would be present if the selection were sequential, for example, if the M ADWs were used according to a fixed sequence. Pseudorandomization helps to distribute discrete mismatch error tones into the noise floor of the ADW output spectrum.

[0011] High-speed ADWs, typically operating at gigahertz sampling rates, are particularly important in fields such as communications and instrumentation. The input signal can have a frequency in the gigahertz range, and the ADW may need to sample at gigahertz sampling rates. High-frequency input signals can impose many demands on the circuitry receiving the input signal, i.e., the ADW's "front-end" circuitry. In some applications, the circuitry not only needs to be fast, but it must also meet certain performance requirements, such as signal-to-noise ratio (SNR) and solid-state rate (SFDR). Designing an ADW that meets speed, performance, area, and power requirements is not trivial, as higher speeds and performance often come at the expense of area and power. Fast track-and-hold (T / H) shifting

[0012] Track-and-hold (T / H) circuits can be an important part of the input circuitry for automatic document processors (ADWs). T / H circuits convert the continuous-time input signal into a discrete-time hold signal for the ADW(s) following the T / H circuit. The ADW(s) can then perform a conversion based on the discrete-time hold signal provided by the T / H circuit. In nested ADWs with M ADWs, separate T / H circuits can be provided for each of the M ADWs, with the individual T / H circuits running at the (lower) speed of the M ADWs. Operating at the speed of the M ADWs simplifies the design of the T / H circuits. However, distributing the T / H circuits across the M channels means that there may be a timing and / or bandwidth mismatch between the M channels, as the T / H circuits may not be exactly the same for the M channels.Timing and bandwidth mismatches can be very difficult to measure and treat, especially at high speeds.

[0013] Another approach is to use a single or dedicated T / H circuit for multiple time-nested ADWs to avoid timing and / or bandwidth mismatches between the channels. Fig. Figure 1 shows a track-and-hold circuit that controls M ADWs of a time-nested ADW, according to some embodiments of the disclosure. Fig. Figure 1 shows a T / H circuit 104 that controls M ADWs operating in a time-nested manner, shown as Slice 1021, Slice 1022, ... Slice 102 M of a time-nested ADW, according to some embodiments of the disclosure. In this example, the T / H can be operated with a sampling rate f. S (or the full speed of the time-nested ADW) while each slice can operate at a lower rate, such as fs / M. The output of the T / H circuit 104 is a hold signal, and each slice is driven by the same hold signal. Therefore, the effect of timing and bandwidth (BW) mismatches between the slices can be eliminated.

[0014] Designing a fast T / H circuit can be non-trivial. Fast T / H circuits can, in some cases, suffer from very high power consumption, significant noise, and low performance. Choosing to use a faster T / H circuit to drive multiple ADW slices is a conscious decision between what to optimize in the analog circuitry and what to fix through calibration. Since timing and / or bandwidth mismatches are difficult to address, the T / H circuit and the rest of the ADW can be designed to avoid timing and / or bandwidth mismatch problems. Gain and offset mismatches can be more compatible with calibration.Several T / H circuits described here have been designed to facilitate the digital calibration of gain and offset mismatches, while deliberately avoiding timing and bandwidth mismatch problems through analog circuit design.

[0015] This section illustrates the implementation of T / H circuits in single-ended form. In practice, T / H circuits can be implemented differentially to suppress possible even-order harmonics. Improved track-and-hold circuits that allow dither coupling

[0016] Because a full-speed transceiver circuit can be complex and power-hungry, certain design decisions have been made to ensure that the transceiver circuit can achieve target performance while not consuming excessive power. One way to improve circuit performance is to use calibration to linearize the transceiver circuit. To allow for calibration, the transceiver circuit is designed to incorporate the coupling of additive and multiplicative dither into the circuit, enabling calibration of the circuit arrangement downstream of where the dither is coupled in.

[0017] For example, circuit arrangement calibration can include extracting and calibrating for non-ideal states in the T / H circuit based on additive and / or multiplicative dither. Furthermore, calibration can include extracting and calibrating offset and gain mismatches between slices. For instance, adding a pseudorandom signal (dither) to the input signal allows for the calibration of gain mismatches in time-nested ADWs. Additionally, dither can be used to calibrate the T / H circuit nonlinearity and the ADW nonlinearity. Advantageously, additive dither in the T / H circuit can: • Enabling nonlinear calibration of the holding-phase nonlinearity of the T / H circuit; ◯ Lower power output in T / H circuit, ◯ Improved second harmonic (HD2) and third harmonic (HD3) performance and ◯ Simpler switches → lower power consumption during clocking, • Enabling nonlinear calibration of the nonlinearity of the ADW slices: ◯ Lower power in the ADW slices (e.g. reference buffer, amplifier, etc.), ◯ Lower performance during clocking and switching, and ◯ Improved HD2 and HD3 performance in ADW slices, • Enabling nested gain mismatch calibration in the ADW slices: ◯ Insensitive to the presence of an input signal, ◯ Insensitive to the input signal frequency, and ◯ More robust calibration, and • Dithering of the holding phase disturbances.

[0018] Furthermore, multiplicative dither (e.g., random chopping) can be used to calibrate offsets and offset mismatches. Advantageously, multiplicative dither can be used in the T / H circuit: • Enabling robust calibration of offset mismatch between ADW slices: ◯ Regardless of the input signal, and ◯ Insensitive to “bad” frequencies (e.g. f S / M, M is the number of ADW slices), • Protect the direct current (DC) input from being zeroed out, • Dithering of any remaining offsets, flicker noise, offset mismatch, thermal drifts, etc., and • Avoiding the need for kernel randomization for offset mismatch.

[0019] Additive dither can be coupled in to correct one or more of the following: nonlinearity calibration, memory effect calibration, chopping non-ideal states calibration, gain error calibration, gain mismatch calibration in nested ADWs, and track / sample memory calibration. Multiplicative dither can be used for one or more of the following: offset mismatch correction and even-order distortion correction.

[0020] Fig. Figure 2 shows an exemplary T / H circuit 200 with two buffers, buffer-1 202 and buffer-2 206, and a switched-capacitor network 204 between the two buffers, according to some embodiments of the disclosure. A dither can be coupled into the switched-capacitor network 204, and the dither can be used to calibrate buffer-2 206 and the ADW behind the T / H circuit 200. As mentioned above, the dither can be an additive dither or a multiplicative dither. Buffer-1 202 receives the (voltage) input V in and buffers the input. The buffered input can be sampled on the switching capacitor network 204. For example, the switching capacitor network 204 can sample the buffered input on the capacitor using suitable switches. The buffer 206 can temporarily store the sampled input and the hold signal V s-h deliver to an ADW (in Fig. 2 not shown).

[0021] The T / H circuit 200 can be considered a T / H control circuit. The switching capacitor network 204 can be a sampling network. Buffer 1 202 can be a sampling buffer, and Buffer 2 206 can be a holding buffer. The buffers are optional and can be included to provide isolation between different circuit stages. The buffers can be source followers, emitter followers, a push-pull topology, or any other suitable buffer structure. Buffer 1 202 can be optimized for sampling linearity. Buffer 2 206 can be optimized for low power consumption, small size, low input capacitance, and good isolation. The isolation provided by Buffer 2 206 can help reduce the input-related noise of the ADW following the T / H circuit 200. The linearity of buffer-2 206 is not as critical as the linearity of buffer-1 202, because buffer-2 206 processes and buffers a hold signal.Since dither is coupled into the switching capacitor network 204, the nonlinearity of buffer 2 206 can also be calibrated, which helps to further reduce the power consumption and size of buffer 2 206. Furthermore, the gain and offset mismatches between the ADW slices driven by the T / H circuit can be calibrated by coupling a dither into the switching capacitor network 204. Different gains of the ADW slices can be measured with a dither coupled into the shared T / H circuit 200 that drives the ADW slices.

[0022] One insight into the three-part circuit design of the T / H circuit comes from realizing how to reduce the power consumption of a T / H circuit that has to drive M ADW slices. In the past, an input buffer had to drive M ADW slices, and such an input buffer had to be very linear and likely consumed a lot of power. With the in Fig. In the three-part circuit design shown in Figure 2, the sampling buffer (Buffer-1 202) only needs to drive one sampling network (or, in some cases, two to four sampling networks, depending on the implementation). The (capacitive) load on the sampling buffer can be smaller, and therefore the sampling buffer can consume less current while achieving comparable or better performance, even if the sampling buffer has to sample a high-frequency or RF signal. The hold buffer (Buffer-2 206) drives a hold signal, and any problems with the hold buffer may be less severe. The primary requirement for the hold buffer is how well the hold buffer output settles. Furthermore, the hold buffer has no input frequency sensitivity. Although the hold buffer may have to drive M ADW slices, the linearity of the hold buffer is not extremely critical, since the hold buffer can be calibrated using the dither coupled into the sampling network.Therefore, further energy savings can be achieved. Track-and-hold circuit with amplification

[0023] In fast ADWs, amplification is typically not available in the input circuit arrangement because the control circuit gain can be very nonlinear. Fig. Figure 3 shows an exemplary T / H circuit 300 with a buffer 302, a switching capacitor network 204, and an amplifier 304, according to some embodiments of the disclosure. When the T / H circuit 300 is combined with the T / H circuit 200 of Fig. When comparing buffer 2, buffer 302 can be similar to buffer 1 202, but buffer 2 206 is replaced by amplifier 304. Since amplifier 304 can be a control circuit amplifier, it is likely to suffer from poor linearity. Due to dither coupling into the switching capacitor network 204, amplifier 304 can be calibrated, and any possible nonlinearities associated with it can be addressed. The ability to provide gain in the T / H circuit 300 is advantageous because it greatly relaxes the requirements for the input signal supplied to the T / H circuit 300. Furthermore, amplifier 304, like buffer 2 206, can be used in the T / H circuit 300. Fig. 2, reduce the input-related noise of the ADW following the T / H circuit 300.

[0024] In addition to providing gain, the amplifier 304 can be a VGA or provide variable gain. The gain can be varied based on one or more conditions and / or set by one or more predefined parameters. A gain control signal “GAIN” can be used to vary the gain provided by the amplifier 304. In some embodiments, a signal level detector 306 can be implemented to generate the gain control signal “GAIN” to control the amplifier 304 based on signal level conditions. For example, if the signal level detector 306 detects an overload condition (e.g., a very large input signal V), the gain control signal “GAIN” can be used to control the amplifier 304 based on signal level conditions. in ) detected, the signal level detector 306 can generate a corresponding gain control signal “GAIN” to reduce the gain of the amplifier 304.

[0025] Although not shown as an amplifier, buffer 302 can, in some cases, be implemented as one. The amplifier in place of buffer 302 can be a variable-gain amplifier (e.g., controllable by the signal-level detector 306). Depending on the implementation, the amplifier may be a control-circuit amplifier or a feedback-circuit amplifier. A feedback-circuit amplifier may be preferred because they can be more precise than a control-circuit amplifier. In some cases, buffer 302 may be preceded by a separate amplifier (control circuit or feedback loop). Gain on the sampling side can also relax the requirements for the input signal supplied to the T / H circuit 300.

[0026] It is understood that the various embodiments shown here with a holding buffer such as “Buffer-2” can be replaced with an amplifier 304, as shown by Fig. 3 illustrated.

[0027] It is possible that the various embodiments shown herein with one or more sampling buffers could be replaced by an amplifier or a variable-gain amplifier. However, linearity may be critical for such an amplifier, and the amplifier may need to be calibrated or linearized using an appropriate calibration scheme. Similarly, a signal-level detector can be used to adjust the gain of such a variable-gain amplifier. Sampling network with dither coupling

[0028] Dither can be coupled into a node of the switching capacitor network of the T / H circuit by various circuit topologies described herein. A dither is a random signal. A dither can have different levels. For example, a dither can be generated by a digital-to-analog converter that receives a digital input (the dither in digital form) and generates an analog output (the dither in analog form). The analog output from the digital-to-analog converter can be coupled into the switching capacitor network of a T / H circuit. In some cases, a dither can randomly change between positive and negative (e.g., randomly changing between +1 and -1, or +V or -V, where V is a nominal value). The type of dither coupled in can vary depending on the desired calibration to be performed or the effect to be achieved.

[0029] Fig. Figure 4 shows an exemplary T / H circuit 400, which represents an exemplary switching capacitor network with sampling and dither coupling, according to some embodiments of the disclosure. Dither is introduced at node V. R The switching capacitor network is coupled in and can be used to calibrate Buffer-2 206 and the ADW, following the T / H circuit 400. The switching capacitor network has a capacitor C 402 for sampling the input, an input switch 404 for receiving the (buffered) input from Buffer-1 202, a sampling switch 406, and a dither coupling switch 408. In the figures, different phase ϕ symbols at the switches indicate a phase or timing control that specifies when a given switch is closed. The top and bottom plates of capacitor C are labeled "t" and "b," respectively.

[0030] During the sampling phase, input switch 404 with phase ϕ1_btst and sampling switch 406 with phase ϕ1a are closed. Input switch 404 can be a bootstrapped switch (i.e., bootstrapped to the buffered input) to achieve good linearity. Sampling switch 406 with phase ϕ1a is pre-adjusted (opens before input switch 404 opens) to achieve ground-plate sampling. Dither coupling switch 408 with phase ϕ2 is opened during the sampling phase. At the end of the sampling phase, the input signal is sampled across capacitor C402.

[0031] During a hold phase, both the input switch 404 with phase ϕ1_btst and the sampling switch 406 with phase ϕ1a are open. The dither coupling switch 408 with phase ϕ2 closes to connect the upper plate of capacitor C 402 to node V. Rto connect. Accordingly, additive dither can be coupled into the switching capacitor network. The T / H circuit 400 holds the sampled voltage (the sampled input signal) plus the coupled additive dither at the output as V s-h In this embodiment, the output bias point of buffer 1 202 does not need to be compatible with the input bias point of buffer 2 206. The output V s-h in Fig. 4 is an inverted version of input V in plus the one at node V R coupled additive dither.

[0032] Fig. Figure 5 shows an exemplary T / H circuit 500, illustrating another exemplary switching capacitor network with sampling and dither coupling, according to some embodiments of the disclosure. Similar to Fig. 4. Additive dither is coupled into the switching capacitor network and can be used to calibrate Buffer-2 206 and the ADW, following the T / H circuit 500. The switching capacitor network has a capacitor C 502 for sampling the input, an input switch 504 for receiving the (buffered) input from Buffer-1 202, a sampling switch 510, a dither coupling switch 508, and an output switch 506.

[0033] During the sampling phase, input switch 504 with phase ϕ1_btst and sampling switch 510 with phase ϕ1a are closed. Input switch 504 can be a bootstrapped switch (i.e., bootstrapped to the buffered input) to achieve good linearity. Sampling switch 510 with phase ϕ1a is pre-adjusted (opens before input switch 504 opens) to achieve bottom-plate sampling. Dither coupling switch 508 with phase ϕ2 and output switch 506 with phase ϕ1_btst are open during the sampling phase. At the end of the sampling phase, the input signal is sampled across capacitor C502.

[0034] During a hold phase, both the input switch 504 with phase ϕ1_btst and the sampling switch 510 with phase ϕ1a are open. The dither coupling switch 508 with phase ϕ2 closes to connect the lower plate of capacitor C 502 to node V. Rto connect. Accordingly, additive dither can be coupled into the switching capacitor network. The output switch 506 with phase ϕ2_btst also closes to connect capacitor C 502 to buffer 206. The output switch 506 can optionally be a bootstrapped switch to achieve good linearity. The T / H circuit 500 holds the sampled voltage (the sampled input signal) plus the coupled additive dither at the output as V s-h In this embodiment, the output bias point of buffer 1 202 is preferably compatible with the input bias point of buffer 2 206. The output V s-h is a non-inverted version of input V in plus the one at node V R coupled additive dither.

[0035] Compared to the T / H circuit 400 in Fig. 4. The T / H circuit 500 can have two bootstrapped switches, which can be more complicated and expensive. However, having two bootstrapped switches can provide better isolation and can allow the use of more than one sampling network (e.g., more than one switching capacitor network sampling in a nested manner) with the same buffer-2 206, if needed to achieve higher speeds.

[0036] The output switch 506 does not need to be bootstrapped, as the coupled dither can be used to calibrate it. If the output switch 506 is indeed bootstrapped, calibration may not be necessary because it is sufficiently linear. If the output switch 506 is not bootstrapped (e.g., simply amplified), calibration can be used to address any nonlinearities in the output switch 506.

[0037] Fig. Figure 6 shows an exemplary T / H circuit 600, which represents yet another exemplary switching capacitor network with sampling and dither coupling, according to some embodiments of the disclosure. Dither is coupled into the switching capacitor network and can be used to calibrate Buffer-2 206 and the ADW, following the T / H circuit 600. The switching capacitor network has a capacitor C 602 for sampling the input, an input switch 604 for receiving the (buffered) input from Buffer-1 202, a sampling switch 606, a dither coupling switch 608, and an output switch 610. The T / H circuit 600 can be considered a combination of the T / H circuit 400 of Fig. 4 and the T / H circuit 500 from Fig. 5 can be viewed. The scanning is done in a similar way. Fig. 4, but an additional switch (i.e., the output switch 610) is in series with capacitor C 602 to connect capacitor C 602 during the holding phase and to disconnect the switching capacitor network from the buffer-2 206.

[0038] During the sampling phase, input switch 604 with phase ϕ1_btst and sampling switch 606 with phase ϕ1a are closed. Input switch 604 can be a bootstrapped switch to achieve good linearity. Sampling switch 606 with phase ϕ1a is pre-adjusted (opens before input switch 604 opens) to achieve bottom plate sampling. Dither coupling switch 608 with phase ϕ2 and output switch with phase ϕ2 are opened during the sampling phase. At the end of the sampling phase, the input signal is sampled across capacitor C602.

[0039] During a hold phase, both the input switch 604 with phase ϕ1_btst and the sampling switch 606 with phase ϕ1a are open. The dither coupling switch 608 with phase ϕ2 closes to connect the upper plate of capacitor C 602 to node V. Rto connect. Accordingly, additive dither can be coupled into the switching capacitor network. The output switch 610 with phase ϕ2 also closes to connect capacitor C 502 to buffer 2 206. In some cases, output switch 610 may be a bootstrapped switch to achieve good linearity. In other cases, the output switch is not bootstrapped. Bootstrapping output switch 610 is less critical in this case, as output switch 610 can be calibrated using the coupled additive dither. The T / H circuit 600 holds the sampled voltage (the sampled input signal) plus the coupled additive dither at the output as V s-h In this embodiment, the output bias point of buffer 1 202 does not need to be compatible with the input bias point of buffer 2 206. The output V s-h is an inverted version of input V in plus the one at node VR coupled additive dither. Multiplexing multiple inputs into the T / H circuits

[0040] As described above, a full-speed transceiver (T / H) circuit can be used to drive a fast automatic digital-to-analog converter (ADC). The fast ADC may consist of a single sampling ADC or multi-level digital-to-analog converter (MAD) slices (time-nested to achieve higher sampling rates or conversion speeds). In some applications, it may often be desirable to combine multiple input signals into a single ADC to generate multiple digital outputs while minimizing interference between them. The T / H or input circuits presented or visualized herein may be designed or configured to include a circuit arrangement that permits spread spectrum and code division multiplexing, allowing multiple inputs to be multiplexed or combined to form a single signal for a quantizer following the T / H or input circuit.In addition to spread spectrum and code division multiplexing, the T / H or input circuitry can be designed or configured to include a circuit arrangement that allows spatial multiplexing, where coding is used to spatially multiplex signals (as opposed to frequency-domain multiplexing). More generally, the circuit arrangement can allow various forms of multiplexing that involve coding. As a result, the fast ADW with the T / H or input circuitry can receive multiple inputs, making it a multi-input ADW. Appropriate coding also means that a multiplexed coded signal can be demultiplexed into multiple signals. Consequently, the fast ADW can generate multiple outputs, making it a multi-input, multi-output ADW.The resulting front end (transaction / heavy or input circuitry) of the ADW can aggregate multiple input signals, encode them, and combine them with minimal power consumption. The ADW can also demultiplex the signals with minimal power consumption.

[0041] To accommodate encoding, such as code division multiplexing or other suitable code-based multiplexing schemes, a T / H circuit or input circuit of a multi-input ADW can multiplex multiple inputs by providing multiple sampling buffers (e.g., buffer 1s) and multiple switching capacitor networks. The pairs of sampling buffers and switching capacitor networks are provided in parallel to process multiple inputs simultaneously.

[0042] Fig. Figure 7 shows an exemplary multi-input ADW 700 according to some embodiments of the disclosure. The multi-input ADW 700 has an input circuit arrangement capable of encoding and multiplexing, a quantizer 724 for generating a digital output signal based on a multiplexed encoded signal at a common node 720, and a digital circuit arrangement for demultiplexing the digital output signal from the quantizer 724 into separate digital output signals. In this example, the multi-input ADW 700 can receive and multiplex N inputs, e.g., three inputs V. in1 , V in2 and V in3 in this FIGURE. In this example, N is 3 (i.e., the multi-input ADW receives 3 inputs), but the person skilled in the art understands that the multi-input ADW 700 (or other multi-input ADWs described herein) may be configured to receive a different number of inputs (with different values ​​of N).

[0043] The entire T / H or input circuit for the multi-input ADW 700 can be viewed as a split T / H structure, where a section of the T / H circuit is divided into N parallel paths. The sampling buffer of the T / H circuit is divided / extended into N=3 parallel buffers, e.g., Buffer-1 702, Buffer-1 704, and Buffer-1 706. The T / H circuit also has N=3 parallel switching capacitor networks. Note that the sampling network of the T / H circuit is also divided / extended into N=3 parallel switching capacitor networks. The N parallel switching capacitor networks have N parallel capacitors, e.g., C 708, C 710, and C 712. In this example, the parallel switching capacitor networks utilize the capacitors in the diagram. Fig. The circuit structure shown in section 5 is not intended to be used; it is understood that other switching capacitor circuit topologies can be used for sampling the signal from the buffer 1s (e.g., one in Fig. 4 or Fig. 5 T / H circuits shown or others described herein).

[0044] The parallel sampling buffers, i.e., buffer-1702, buffer-1704, and buffer-1706, are optional. These parallel sampling buffers can buffer the respective input signals before the buffered input signals are sampled onto the respective sampling capacitors in the parallel switching capacitor networks.

[0045] The signals in the N parallel paths formed by the N parallel switching capacitor networks are combined by capacitive charge redistribution of the parallel capacitors, e.g., C708, C710, and C712. In other words, the N sampled signals in the N switching capacitor networks are summed at the common node 720 by charge redistribution (and optionally scaled down accordingly). Charge redistribution occurs when the parallel capacitors (i.e., the sampled capacitors in the parallel switching capacitor networks) are connected in parallel through the common node 720. The signal at the common node 720 would become, through charge redistribution, a signal representing a combination of charges on the parallel capacitors. Accordingly, the signals on the N parallel paths are combined at the common node 720.

[0046] Optionally, the combined signal at the common node 720 is buffered by a single holding buffer, i.e., buffer-2 722. The output of buffer-2 722, e.g., V s-h The input is sent to the quantizer 724 for conversion. The quantizer 724 generates a digital output signal based on a multiplexed coded signal at the common node 720.

[0047] To multiplex multiple signals and subsequently demultiplex the multiplexed signal, N code sequences can be used to encode the respective N inputs. For example, orthogonal pseudorandom number (PN) sequences can be particularly useful for spread spectrum and code division multiplexing, which targets multiplexed signals in the frequency domain. Accordingly, each parallel switching capacitor network has a circuit for encoding a respective input signal using a respective orthogonal pseudorandom number sequence and generating coded input signals. The parallel switching capacitor networks can then combine coded input signals at a common node by charge redistribution of sample capacitors in the parallel switching capacitor networks to generate a multiplexed coded signal. In general, different encoding schemes can be used depending on the application.Examples of suitable coding schemes include: Walsh, PN, spatial multiplexing, etc.

[0048] One way to perform encoding on the respective N inputs is to use a chopper circuit. The chopper circuit is integrated into a switching capacitor network. In the example shown, N parallel chopper circuits, e.g., chopper 714, chopper 716, and chopper 718, perform encoding during the hold phase. In this example, the chopper circuit is controlled by a respective orthogonal PN sequence, which can encode the respective input accordingly. The chopper circuit can be integrated with a switch controlled by ϕ2_bst (an output switch of the switching capacitor network) to reverse the polarity of a differential signal based on the phase ϕ2_bst and the value of the orthogonal PN sequence. The chopper circuit can be controlled by a suitable code sequence to perform code-based multiplexing.

[0049] Fig. Figure 8 shows a circuit arrangement for implementing coding using a chopper according to some embodiments of the disclosure. The chopper 802, controlled, for example, by an orthogonal PN sequence, can interchange differential signal paths of a signal based on the value of the orthogonal PN sequence. An exemplary orthogonal PN sequence may have a sequence of values ​​containing 0s and 1s. The function of a chopper is equivalent to multiplying an analog signal by -1. PN , where PN is the value of the orthogonal PN sequence. This means that the Chopper 802 multiplies the signal by 1 or -1. When integrated with a ϕ2 bst, the Chopper 802 reverses the polarity of a difference signal based on the phase ϕ2 bst and the value of the orthogonal PN sequence. When the Chopper 802 multiplies the signal by -1 0When multiplied by =1 (PN=0), the polarity of the difference signal is maintained. If the chopper 802 multiplies the signal by -1 1 Multiplying by -1 (PN=1) reverses the polarity of the difference signal. This is equivalent to a switch controlled by phase ϕ2_bst and a chopper controlled by the orthogonal PN sequence PN 802 (equivalent to multiplying a signal by -1). PN ) is on the right side of Fig. Figure 8 shows that ϕ2_bst and the PN value together control a pair of switches (controlled by ϕ2_bst·PNϕ2_bst · PN) that passes the differential signal without swapping polarity, and a pair of switches (controlled by ϕ2_bst·PN'ϕ2_bst · PNϕ2_bst · PN') that swaps the differential signal paths to reverse the polarity.

[0050] The same / corresponding code sequences, e.g., N orthogonal PN sequences, can be used to decode or demultiplex the signals at the output of the quantizer 724. The quantizer 724 converts the combined hold signal V s-h (representing a combination / sum of the N encoded input signals multiplexed together) into a digital output. The digital output can be supplied to N parallel decoders, e.g., decoder 726, decoder 728, decoder 730, so that the N inputs can be separated or demultiplexed. In the digital domain, the same N orthogonal PN sequences used to encode the signals are used to separate the N signals. A decoder can digitally change the polarity of the digital signal (e.g., by changing a sign bit) based on the value of the PN sequence. A decoder is equivalent to multiplying a digital signal by -1. PN, where PN is the value of the orthogonal PN sequence. N digital outputs, e.g., V out1 , V out2 and V out3 , can be obtained at the output of the multi-input multi-output ADW.

[0051] Depending on the multiplexing scheme, other special code sequences, such as space-time codes, can be used with the chopper to encode the analog input signals in the channels. The same special code sequences, or corresponding code sequences, can be used to demultiplex / separate the signals in the digital domain. For example, other special code sequences can be designed to implement spatial multiplexing for encoding the analog input signals in the space-time dimension.

[0052] The sampled and held voltage V s-h is given by: Vs−h=G(Vin1⋅−1PN1+Vin2⋅−1PN2+Vin3⋅−1PN3+⋯+VinN⋅−1PNN) where: G=CNC+Cp

[0053] C is the unit capacity of the parallel capacities, N is the number of inputs, and C p The parasitic capacitance at the input of the second / holding buffer is G. The gain factor or scaling factor G is a result of the charge distribution occurring in different capacitances in the input circuit arrangement.

[0054] In some cases, the chopper circuits are located at the output of the sampling buffers (e.g., buffer 1s) instead of at the input of the hold buffers. Such chopper circuits would instead perform encoding during the sampling phase. Fig. Figure 9 shows another exemplary multi-input ADW 900 according to some embodiments of the disclosure. In the example shown, N parallel chopper circuits, e.g., chopper 902, chopper 904, and chopper 906, perform encoding during the sampling phase. The chopper circuit is controlled, e.g., by a respective orthogonal PN sequence that can encode the input accordingly. Just as before in Fig. 7. The function of the chopper is equivalent to multiplying an analog signal by -1. PN , where PN is the value of the orthogonal PN sequence. The chopper circuit can be integrated with a switching capacitor circuit via ϕ1_btst (an input switch of the switching capacitor circuit) to interchange the polarity of a differential signal based on the phase ϕ1_btst and the value of the orthogonal PN sequence.

[0055] Fig. Figure 10 shows another exemplary multi-input ADW 1000 according to some embodiments of the disclosure. How Fig. 9. Chopping / coding is performed in the sampling phase, with the chopper circuits, e.g., chopper 902, chopper 904, and chopper 906, located at the output of the sampling buffers, e.g., buffer-1 702, buffer-1 704, and buffer-1 706. The chopper circuit can be integrated with a switch controlled by ϕ1_btst (an input switch of the switching capacitor circuit) to reverse the polarity of a differential signal based on the phase ϕ1_btst and the value of the orthogonal PN sequence. The in Fig. The circuit arrangement shown in 10 utilizes the T / H circuit in Fig. The circuit topology shown in Figure 4 can reduce the number of switches required to implement the switching capacitor networks (it can have fewer switches than those shown in Figure 4). Fig. 7 and Fig. 9 structures seen). In particular, the common node 720 in Fig. 10 represents a node that connects to all the lower plates of the parallel scanning capacities 708, 710, and 720. A single bottom plate switch 1002 is required (as opposed to one per channel) to perform a bottom plate scan.

[0056] Fig. Figure 11 shows another exemplary multi-input ADW 1100 according to some embodiments of the disclosure. How Fig. 7. Chopping / coding is performed in the hold phase, where the chopper circuits, e.g., chopper 714, chopper 716, and chopper 718, are located at the input of the hold buffer, e.g., buffer-2 722. The chopper circuit can be integrated with a switch controlled by ϕ2_bst (an output switch of the switching capacitor circuit) to reverse the polarity of a differential signal based on the phase ϕ_bst and the value of the orthogonal PN sequence. In the Fig. The configuration shown in Figure 11 implements inverted sampling (i.e., the sampled value is inverted) and ground-plate sampling in the switching capacitor networks. Switches labeled S2 (e.g., output switches of the switching capacitor circuits) can be used for isolation and are optional.

[0057] Depending on the application, the circuit arrangement for encoding the multiple signals can enhance one or more of the T / H circuits shown in various FIGURES herein and other variations of the T / H circuits envisaged by the disclosure. Time nesting within a parallel channel

[0058] Fig. Figure 12 shows another exemplary multi-input ADW 1200 according to some embodiments of the disclosure. Each input (e.g., V in1 , V in2 and V in3The data are sampled by parallel nested sampling networks (e.g., nested sampling network 1202, nested sampling network 1204, and nested sampling network 1206). The speed and performance of each nested sampling network can be improved by time nesting within the nested sampling network. A given nested sampling network, e.g., nested sampling network 1202, nested sampling network 1204, or nested sampling network 1206, can contain multiple time-nested sampling networks.

[0059] Fig. Figures 13-15 show nested sampling networks 1202, 1204 and 1206 of the multi-input ADW 1200 in Fig. 12 according to some embodiments of the disclosure. A nested sampling network comprises several time-nested sampling networks. For example, shows Fig. 13 three time-nested sampling networks. Fig. 14 also three time-nested sampling networks. Fig. Model 15 also has three time-nested sampling networks. In this embodiment, multiple time-nested sampling networks of a nested sampling network can sample the input to the nested sampling network in a time-nested manner (e.g., one after the other) to increase the sampling rate (compared to using only one sampling network). In some cases, with three sampling networks in a given nested sampling network, a two-way (ping-pong) time-nesting scheme can be implemented, with a third sampling network being used to enable randomization to distribute residual nesting errors in the noise floor.

[0060] In Fig. 13-15 shows that chopping / coding can be performed during the hold phase. However, it is considered that chopping / coding can be performed during the sampling phase. Furthermore, in Fig. 13-15 Sampling is performed using inverted sampling networks with ground-plate scanning. It is considered that sampling using non-inverted sampling networks with ground-plate scanning is also possible. The code sequences, e.g., orthogonal codes, used to multiplex the inputs can be unique for each sampling network within a nested sampling network and / or for each input to the multi-input ADW 1200. Fig. In 13, the three multiply time-nested sampling networks in the nested sampling network 1202 use a first code-orthogonal PN sequence PN1. Fig. In 14, the three multiply time-nested sampling networks in the nested sampling network 1204 use a second code-orthogonal PN sequence PN2. Fig. 15 the three multiply time-nested sampling networks in the nested sampling network 1206 use a second code-orthogonal PN sequence PN3. Spreading factor

[0061] To achieve the desired spreading factor, the hold / spread rate (here denoted as fs2) should typically be higher than the input sampling rate (here denoted as fs1). The ratio between the two rates represents the spreading factor F, which is typically equal to the number of multiplexed inputs in the sampling phase. If the number of inputs multiplexed in the sampling phase is N, then F equals fs2 / fs1, which is expected to be equal to N.

[0062] To implement a spreading factor, multiple capacitors are used in parallel in a given sampling network. The number of capacitors is typically equal to the number of inputs or the spreading factor. All the capacitors sample simultaneously at fs1, then halt sequentially at the faster rate of fs2.

[0063] Fig. Figure 16 shows yet another exemplary multi-input ADW 1600 according to some embodiments of the disclosure. In the case of the one in Fig. In the example shown in Figure 16, the multi-input ADW 1600 features split T / H structures using chopping / coding in the hold phase and inverted sampling networks with bottom-plate sampling. The sampling networks of the multi-input ADW 1600 are configured to support different sampling and hold rates (different fs1 and fs2). For example, to support a spread factor of 4, the sampling capacitor for each input / channel has four parallel capacitors, C <1 : 4 >, which sample the input simultaneously at a sampling rate of fs1 and hold sequentially to support a hold rate of fs2 = 4fs1 (four times the sampling rate fs1). Note that the four parallel input switches are provided for the four parallel capacitors and are controlled by phases ϕ1_btst <1 : 4 >.If dither coupling is implemented within the sampling network, there are also 4 corresponding dither coupling switches, controlled by the phases ϕ2 < 1 : 4 >, to connect the upper plate of a corresponding parallel capacitor to node V. R to connect. There are also 4 parallel output switches provided for the 4 parallel capacitors, and the 4 parallel output switches are controlled by phases ϕ2_b < 1 : 4 >.

[0064] For example, for the first input V in1The (aggregated) sampling capacitance 1602 in the sampling network consists of 4 parallel capacitances C <1 : 4 >. There are also 4 input switches corresponding to the 4 parallel capacitances, which are controlled by respective phases ϕ1_btst < 1 : 4 >, 4 dither coupling switches corresponding to the 4 parallel capacitances, which are controlled by respective phases ϕ2 < 1 : 4 >, 4 output switches corresponding to the 4 parallel capacitances, which are controlled by respective phases ϕ2_b < 1 : 4 >, and 4 base plate sampling switches corresponding to the 4 parallel capacitances, which are controlled by respective phases ϕ1a < 1 : 4 >. The same applies to the sampling capacitance 1604 and the sampling capacitance 1606.

[0065] Fig. 17 is a timing control diagram that illustrates the timing of the in Fig. Figure 16 represents switches designated with different phase / time control, according to some embodiments of the disclosure. The timing diagram shows that the multi-input ADW 1600 can perform sampling at fs1 and hold at fs2 = 4fs1. Again with reference to the sampling capacity 1602, the phases ϕ1_btst < 1 : 4 > controlling the 4 input switches are the same and operate at the sampling rate fs1. The phases ϕ1a < 1 : 4 > controlling the 4 bottom plate sampling switches are also the same and operate at a hold rate fs2 = 4fs1. The phases ϕ2 < 1 : 4 > controlling the 4 dither coupling switches are also the same and operate at a hold rate fs2 = 4fs1. The phases / clocks ϕ2_b < 1 >, ϕ2_b < 2 >, ϕ2_b < 3 >, ϕ2_b < 4 > controlling the respective output switches each have pulses (with the hold rate fs2=4fs1) that are shifted in phase relative to each other.The respective pulses of phases ϕ2_b < 1 : 4 > can intentionally overlap the pulses in phases ϕ1a < 1 : 4 >, which control the four bottom-plate scanning switches, in order to reset the charge at the input of the hold buffer (e.g., Buffer-2 722). By carefully aligning the edges of the clocks ϕ2_b < 1 : 4 > and ϕ1a < 1 : 4 >, the storage effects caused by overlapping clocks / pulses of phases ϕ2_b < 1 : 4 > and ϕ1a < 1 : 4 > and by partially (or completely) resetting the parasitic capacitances at the input of the hold buffer (Buffer-2 722) can be reduced.

[0066] Fig. Figure 18 shows another exemplary multi-input ADW 1800 according to some embodiments of the disclosure. The multi-input ADW 1800 shows a different scheme that can implement a spreading factor F. The control circuit T / H circuits 1802, 1804, and 1806 support a sampling rate fs1 that is lower than the hold rate fs2. In the example shown, instead of using sampling buffers (Buffer-1s), the inputs are sampled and held by control circuit T / H circuits 1802, 1804, and 1806 at a sampling rate fs1. The held outputs of the T / H circuits 1802, 1804, and 1806 are then oversampled and encoded at the rate of fs2 (the hold rate) by the sampling networks operating at fs2. Since the outputs of the T / H circuits 1802, 1804 and 1806 are hold signals, the sampling circuits (switching capacitor networks) following the T / H circuits can sample the hold signals at a different / higher rate.In some cases, parallel capacities can be used to perform oversampling and encoding with fs2 in . Fig. 18 to carry out, but it is not necessary to have parallel capacities, since the T / H circuits 1802, 1804 and 1806 provide stop signals. Amplitude or peak detection and automatic gain control

[0067] Amplitude (peak or signal level) detection can be used for any input signal (e.g., V). in1 , Vi n2 , V in3To measure the relative received signal strength (RSSI), peak detectors can be provided for one or more of the input signals to perform amplitude or peak detection. These detectors can separately detect one or more range-crossing conditions of a given input signal or the crossing of a certain threshold (e.g., signal level) by the given input signal. Analog peak detectors, comparators (e.g., a flash ADW), and / or a suitable combination of the above can be used to detect these conditions. Depending on the implementation, peak detectors can operate directly at the input (directly at the input to the multi-input ADW), at the sampled input (e.g., any suitable node in the sampling path), and / or at the hold input (e.g., at the output of the sampling / switching capacitor circuits).

[0068] A peak detector can operate on any channel / input or on the summed voltage (at the node where the multiple coded input signals are multiplexed and combined). Peak detectors can generate flags (or bits) to indicate a signal level. These flags can be used for AGC (Automatic Gain Control) to enable fast control loops that prevent ADW overdrive and improve its noise performance. AGC can also be achieved by feeding the bits to an amplifier driving the ADW or by feeding them to an internal variable-gain amplifier.

[0069] Fig. Figure 19 shows another exemplary multi-input ADW 1900 according to some embodiments of the disclosure. In this example, peak detectors 1904 are coupled to the inputs to the parallel channels to measure the signal levels (separately for each input). The output of the peak detectors (flags / bits) can be extracted from the ADW 1900 for AGC control, for example, to drive an amplifier outside the multi-input ADW 1900 (an amplifier or a circuit that drives the multi-input ADW 1900). The output of the peak detectors 1904 can also be used (alternatively or additionally) to control the gain of the variable-gain amplifier 1902 (serving as a stage between the sampling / switching capacitor networks and the quantizer 724, replacing a holding buffer "Buffer-2") within the multi-input ADW 1900. In this example, the second buffer of the T / H is replaced by an amplifier.

[0070] These top-of-the-line detectors may be included in various multi-input ADWs described and envisaged herein. Exemplary procedure

[0071] Fig. Figure 20 shows a flowchart illustrating a method for multiplexing inputs into an analog-to-digital converter according to some embodiments of the disclosure. In 2002, respective input signals are encoded in respective parallel signal paths using respective code sequences. In 2004, encoded input signals are multiplexed by charge redistribution of the parallel sampling capacitors in the parallel signal paths. In 2006, a quantizer can convert the multiplexed encoded input signal into a digital output signal. In 2008, the digital output signal can be demultiplexed into separate digital output signals using the respective code sequences (or equivalently, code sequences corresponding to the respective code sequences). Examples of T / H circuits

[0072] Example 1 is a track-and-hold circuit comprising a sampling buffer, a sampling network that receives a buffered input from the sampling buffer, and a hold buffer that receives a hold signal from the sampling network.

[0073] In Example 2, the track-and-hold circuit from Example 1 can further include a node for receiving an additive dither, incorporating the sampling network.

[0074] In Example 3, the track-and-hold circuit from Example 1 or 2 can further include a chopper integrated with the sampling network.

[0075] In Example 4, the track-and-hold circuit from one of Examples 1-3 can also include one or more additional sampling networks in parallel.

[0076] In Example 5, the track-and-hold circuit from Example 4 can further include the sampling networks that sample the buffered input from the sampling buffer in a time-nested manner.

[0077] In Example 6, the track-and-hold circuit of Example 4 or 5 can further include the sampling networks that sample the buffered input from the sampling buffer in a randomized time-nested manner.

[0078] In Example 7, the track-and-hold circuit from one of Examples 4-6 may further include the sampling networks, which may be configured to sample the buffered input in different modes.

[0079] In Example 8, the track-and-hold circuit from one of Examples 1-7 may also include one or more additional hold buffers.

[0080] In Example 9, the track-and-hold circuit from one of Examples 4-7 may further include one or more additional hold buffers, each assigned to each sampling network.

[0081] Example 101 is a method comprising: buffering an input signal; during a sampling phase, sampling the buffered input signal onto a capacitor; and during a holding phase, connecting a node with a dither signal to the capacitor to output a holding signal with the dither signal; buffering the holding signal.

[0082] In Example 102, the procedure from Example 101 can further include the random chopping of the stop signal before buffering the stop signal.

[0083] In Example 103, the procedure of Example 101 or 102 may further include the control of several ADWs that are operated in a time-nested manner.

[0084] As in Fig. As can be seen in 4-7, 9-11, 13-16, 18 and 19, the additive dither is coupled in using the capacitor that also samples the input signal (e.g. C 402 in Fig. 4, C 502 in Fig. 5 and C 602 in Fig. 6) Note that by using the same capacitor that samples the input signal to couple in the dither, the dither can remain on the capacitor and cause backfeed errors. This implementation can be called common-capacitor dither coupling. Alternatively, a dither capacitor, separate from the input-signal-sampling capacitor, can be used to couple the additive dither into the switching capacitor network of the T / H circuit. This implementation can be called split-capacitor dither coupling. The dither capacitor can be connected to a summing node of the switching capacitor network. Using a separate capacitor allows the dither to be isolated from the input-signal-sampling capacitor, thus avoiding backfeed errors.

[0085] Several considerations must be taken into account when using the same capacitor to sample the input signal and couple in an additive dither. Settling in during the hold phase is faster. There is better / lower loss due to fewer capacitors connected to a summing node of the switching capacitor network (i.e., the input of Buffer-2 206). There are fewer switches and clock signals required to control them, resulting in lower power consumption and reduced complexity. As mentioned earlier, the dither is not isolated from the capacitor that also performs sampling when switching from the hold to the sample phase. The dither can bump the input, and backfire calibration may be needed to remove the error caused by the backfire to achieve a certain level of performance (and reduce distortion).

[0086] There are also several considerations to keep in mind when using a dither capacitor that is separate from the capacitor performing the sampling. The transient response during the hold phase is slower because time is needed to charge the dither capacitor during the hold phase to couple in the dither. There is also more loss due to the additional capacitors connected to the summing node of the switching capacitor network (i.e., the input of Buffer-2 206). Having a separate dither capacitor also means more switches and the clock signals required to control them, resulting in higher power consumption and increased complexity. As mentioned earlier, the separate dither capacitor isolates the dither from the capacitor performing the input signal sampling, thus preventing backlash.Furthermore, separating the dither capacitor allows the dither to be reset / removed, which means there is less interaction between the dither and the input.

[0087] Fig. Figure 21 shows an exemplary T / H circuit 2100, which represents an exemplary switching capacitor network with sampling and dither coupling, according to some embodiments of the disclosure. Similar to Fig. The switching capacitor network has capacitor C 402 for sampling the input, an input switch 404 for receiving the (buffered) input from buffer 1 202, and a sampling switch 406. Fig. The difference is that a dither coupling switching capacitor network is added to the switching capacitor network. The dither coupling switching capacitor network is added to a summing node 2120 of the switching capacitor network, which is located at the input of buffer 2206. The dither coupling switching capacitor network contains a dither capacitor C d 2102, a reset switch 2104 for connecting a first plate (designated as “1”) of the dither capacitor C d 2102 with ground, and a dither coupling switch 2106 for connecting the first plate of the dither capacitor C d 2102 with node V R Furthermore, a transfer switch 2108 is added to connect the upper plate of capacitor C 402 to ground.

[0088] In the switching capacitor network, a capacitor is connected to node V. R provided dither voltage level using a dither capacitor C d2102 is coupled into the switching capacitor network at the input of buffer 2206, which is also the bottom plate of capacitor C402. A dither voltage level can be measured at node V. R The dither can be used to calibrate buffer 2 206 and the ADW, following the T / H circuit 2100. A second plate (designated as "2") of the dither capacitor C d 2102 is connected to the lower plate of capacitor C402, which is also the summing node 2120. The first plate (designated as "1") of dither capacitor C d 2102 is connected to ground during ϕ1 (sampling phase). The first plate of the dither capacitor C d 2102 is connected to node V during ϕ2 (holding phase). R tied together.

[0089] During the sampling phase, input switch 404 with phase ϕ1_btst and sampling switch 406 with phase ϕ1a are closed. Input switch 404 connects the top plate of capacitor C402 to sample the input signal (e.g., sampling the output of buffer 1 202) to capacitor C402. Sampling switch 406 connects the bottom plate of capacitor C402 to ground. Input switch 404 can be a bootstrapped switch (i.e., bootstrapped to the buffered input) to achieve good linearity. Sampling switch 406 with phase ϕ1a is pre-adjusted (opens before input switch 404 opens at the end of the sampling phase) to achieve bottom-plate sampling. Reset switch 2104 with phase ϕ1 is closed, and so is sampling switch 406 with phase ϕ1a at the beginning of the sampling phase. When the reset switch 2104 and the scanning switch 406 are closed, the first plate of the dither capacitor C is activated. d2102 connected to ground, and the second plate of the dither capacitor C d 2102 is connected to ground. Closing the reset switch 2104 and the scanning switch 406 thus clears the dither capacitor C. d 2102 or resets it. The dither coupling switch 2106 with phase ϕ2 is opened and the transfer switch 2108 with phase ϕ2 is open during the sampling phase. At the end of the sampling phase, the input signal is sampled onto capacitor C 402 and the dither capacitor C d 2102 will be deleted / reset.

[0090] During a hold phase, the input switch 404 with phase ϕ1_btst, the sampling switch 406 with phase ϕ1a, and the reset switch 2104 with phase ϕ1 are opened. The dither coupling switch 2106 with phase ϕ2 closes to activate the first plate of the dither capacitor C. d 2102 with node V RThe transfer switch 2108 with phase ϕ2 closes to connect the top plate of capacitor C402 to ground, transferring the sampled input to the summing node 2120. Additive dither can be coupled into the switching capacitor network and is added at the summing node 2120. Accordingly, the input signal and the additive dither appear at the summing node 2120 of the switching capacitor circuit (i.e., the input of buffer 2206).

[0091] The T / H circuit 2100, e.g. the switching capacitor network and buffer-2 206, holds the sampled voltage (the sampled input signal) plus the coupled additive dither at the output as V s-h In this embodiment, the output bias point of buffer 1 202 does not need to be compatible with the input bias point of buffer 2 206. The output V s-h in Fig. 21 is an inverted version of the input V in plus the one at node V Rcoupled additive dither.

[0092] Fig. Figure 22 shows an exemplary T / H circuit 2200, which illustrates yet another exemplary switching capacitor network with sampling and dither coupling, according to some embodiments of the disclosure. Fig. 22 is similar Fig. 21, whereby Fig. 22 adds an output switch 2202. The sampling and holding operations are the same as Fig. 21, but an additional switch (i.e., the output switch 2202) is provided at the summing node 2120. The output switch 2202 with phase ϕ2 disconnects the summing node 2120, i.e., the lower plate of capacitor C402 and the second plate of the (dither) capacitor C. d2102 or ϕ2, from the input of buffer-2 206 during the sampling phase. When output switch 2202 is open, output switch 2202 can disconnect the switching capacitor network from buffer-2 206 (and vice versa). Output switch 2202 with phase ϕ2 connects the summing node 2120, i.e., the bottom plate of capacitor C 402 and the second plate of (dither) capacitor C d 2102 or ϕ2, with the input of buffer-2 206 during the hold phase. Thus, output switch 2202 transfers the input signal and the additive dither appearing at summing node 2120 to buffer-2 206. Output switch 2202 does not need to be bootstrapped for linearity if additive dither is used to calibrate out the nonlinearity of output switch 2202.

[0093] Fig. Figure 23 shows an exemplary T / H circuit 2300, illustrating another exemplary switching capacitor network with sampling and dither coupling, according to some embodiments of the disclosure. Similar to Fig. 21 and Fig. 22 Additive dither is coupled into the switching capacitor network and can be used to calibrate a circuit arrangement downstream of the node where the dither is coupled in, such as buffer 2 206 and the ADW, following the T / H circuit 2300. Similar to Fig. The switching capacitor network has a capacitor C 502 for sampling the input, an input switch 504 for receiving the (buffered) input from buffer-1 202, a sampling switch 510 and an output switch 506. Fig. The difference is that a dither coupling switching capacitor network is added to the switching capacitor network. The dither coupling switching capacitor network is added to a summing node 2320 of the switching capacitor network, which is located at the input of buffer 206 and after the output switch 506. The dither coupling switching capacitor network contains the dither capacitor C d 2302, a first reset switch 2306 for connecting a first plate (designated as “1”) of the dither capacitor C d 2302 with ground, a dither coupling switch 2304 for connecting the first plate of the dither capacitor C d 2302 with node V R , a second reset switch 2308 for connecting the second plate (designated as "2") of the dither capacitor C d 2302 with ground and a dither transfer switch 2310 for connecting the second plate of the dither capacitor C d2302 with the summing node 2320. Furthermore, a transfer switch 2312 is added to connect the lower plate of capacitor C 502 to ground.

[0094] In the switching capacitor network, a capacitor is connected to node V. R provided dither voltage level using a dither capacitor C d 2302 is coupled into the switching capacitor network at the input of buffer 206. A dither voltage level can be measured at node V. R The dither can be used to calibrate buffer 2 206 and the ADW, following the T / H circuit 2300. A second plate (designated as "2") of the dither capacitor C d During ϕ1 (sampling phase), component 2302 is connected to ground. The second plate of the dither capacitor is connected to summing node 2320 during phase ϕ2 (hold phase). The first plate (designated as "1") of dither capacitor C d2302 (or 2102) is connected to ground during ϕ1 (sampling phase). The first plate of the dither capacitor C d 2302 (or 2102) is connected to node V during ϕ2 (holding phase). R tied together.

[0095] During the sampling phase, input switch 504 with phase ϕ1_btst and sampling switch 510 with phase ϕ1a are closed. Input switch 504 connects the top plate of capacitor C 502 to sample the input signal (e.g., sampling the output of buffer 1 202) to capacitor C 502. Sampling switch 510 connects the bottom plate of capacitor C 502 to ground. Input switch 504 can be a bootstrapped switch (i.e., bootstrapped to the buffered input) to achieve good linearity. Sampling switch 510 with phase ϕ1a is pre-adjusted (opens before input switch 504 opens at the end of the sampling phase) to achieve bottom-plate sampling. The second reset switch 2308 with phase ϕ1 is closed, and so is the first reset switch 2306 with phase ϕ1a at the beginning of the sampling phase.The first reset switch 2306 with phase ϕ1a is pre-adjusted (opens before the second reset switch 2308 opens at the end of the scanning phase) to achieve a base plate scan. When the first reset switch 2306 and the second reset switch 2308 are closed, the first plate of the dither capacitor C is scanned. d 2302 connected to ground, and the second plate of the dither capacitor C d 2302 is connected to ground. Closing the first reset switch 2306 and the second reset switch 2308 thus resets the dither capacitor C. d 2302 or resets it. The dither coupling switch 2304 with phase ϕ2, the dither transfer switch 2310 with phase ϕ2, the output switch 506 with phase ϕ2_btst, and the transfer switch 2312 with phase ϕ2 are open during the sampling phase. At the end of the sampling phase, the input signal is sampled onto capacitor C 502, and the dither capacitor C d2302 will be deleted / reset.

[0096] During a hold phase, the input switch 504 with phase ϕ1_btst, the sampling switch 510 with phase ϕ1a, the first reset switch 2306 with phase ϕ1a, and the second reset switch 2308 with phase ϕ1 are open. The dither coupling switch 2304 with phase ϕ2 closes to activate the first plate of the dither capacitor C. d 2302 with node V R to connect. The dither transfer switch 2310 with phase ϕ2 closes to connect the second plate of the dither capacitor C. dThe output switch 506 closes to connect the top plate of capacitor 502 to the summing node 2320. The transfer switch 2312 with phase ϕ2 closes to connect the bottom plate of capacitor 502 to ground, transferring the sampled input to the summing node 2320. Accordingly, the input signal and the additive dither appear at the summing node 2320 of the switching capacitor circuit (i.e., the input of buffer 206).

[0097] The T / H circuit 2300, e.g. the switching capacitor network and buffer-2 206, holds the sampled voltage (the sampled input signal), plus the coupled additive dither, at the output as V s-h In this embodiment, the output bias point of buffer 1 202 is preferably compatible with the input bias point of buffer 2 206. The output Vs-h is a non-inverted version of input V in plus the one at node V R coupled additive dither.

[0098] The output switch 506 can optionally be a bootstrapped switch to achieve good linearity. Compared to the T / H circuit 2100 in Fig. The T / H circuit 2300 can have two bootstrapped switches (instead of just one), which can be more complicated and expensive. However, having two bootstrapped switches can provide better isolation and can allow the use of more than one sampling network (e.g., more than one switching capacitor network sampling in a nested manner) with the same buffer 2206, if needed, to achieve higher speeds.

[0099] Fig. Figure 24 shows an exemplary T / H circuit 2400, illustrating another exemplary switching capacitor network with sampling and dither coupling, according to some embodiments of the disclosure. Similar to Fig. 23 Additive dither is coupled into the switching capacitor network and can be used to calibrate a circuit arrangement downstream of the node where the dither was coupled in, such as buffer 2 206 and the ADW following the T / H circuit 2400. Fig. 23 different things are that in Fig. 23 A dither coupling switching capacitor network is added to a summing node 2420 (which is also the top plate of capacitor C 502), located upstream of the output switch 506. The dither transfer switch 2310 with phase ϕ2 connects the second plate of dither capacitor C d2302 with summing node 2420 during the hold phase to add the dither to summing node 2420. The output switch 506 with phase ϕ2 connects the top plate of capacitor C 502 (which is also summing node 2420) to the input of buffer-2 206.

[0100] By adding the dither before the output switch 506, the dither can be used to calibrate the output switch 506, and the need for the output switch 506 to be bootstrapped can be avoided. The output switch 506 does not need to be bootstrapped because the coupled dither can be used to calibrate it. If the output switch 506 is indeed bootstrapped, then calibration may not be necessary because the output switch 506 is sufficiently linear. If the output switch 506 is not bootstrapped (e.g., simply amplified), as in Fig. If 24 can be seen, then the calibration can be used to treat nonlinearities of the output switch 506.

[0101] In some embodiments, bottom plate sampling is optional. When bottom plate sampling is implemented, sampling the input signal onto a capacitor and even clearing / resetting the dither capacitor can benefit from reduced distortion.

[0102] In some embodiments, the output switch 2202 and the output switch 506, shown in the FIGURES, can be integrated with a chopper to couple in a multiplicative dither (as e.g. in Fig. 8 shown). In some embodiments, the output switch 2202 and the output switch 506 can be located in the Fig. Figures 22-24 show that a chopper can be integrated to implement encoding during the hold phase, as described for the multi-input T / H circuits. In some embodiments, input switch 404 and input switch 504 of the Fig. 21-24 can be integrated with a chopper to implement encoding during the sampling phase, as described with respect to the multi-input input circuits.

[0103] Example 201 is a low-power track-and-hold circuit, wherein the low-power track-and-hold circuit comprises: a sampling buffer; a sampling network for sampling a buffered input signal from the sampling buffer onto a capacitor, wherein the sampling network includes a dither capacitor for coupling an additive dither to a summing node of the sampling network; and a hold buffer for receiving a hold signal from the sampling network.

[0104] In Example 202, the low-power track-and-hold circuit from Example 201 can optionally include a chopper integrated with the sampling network to couple in a multiplicative dither.

[0105] In Example 203, the low-power track-and-hold circuit of Example 201 or 202 can optionally include a chopper integrated with the sampling network to multiply the buffered input signal by a code.

[0106] In Example 204, the low-power track-and-hold circuit from one of Examples 201-203 can optionally include the sampling network having a switching capacitor network in order to sample the buffered input signal from the sampling buffer onto one or more capacitors.

[0107] In Example 205, the low-power track-and-hold circuit from one of Examples 201-204 can optionally include the sampling network comprising: an input switch for receiving the buffered input signal from the sampling buffer; and a sampling switch for sampling the buffered input signal onto a capacitor during a sampling phase.

[0108] In Example 206, the low-power track-and-hold circuit from one of Examples 201-205 can optionally include the sampling network which has a dither coupling switching capacitor network coupled to the summing node.

[0109] In Example 207, the low-power track-and-hold circuit from one of Examples 201-206 can optionally include the dither capacitor connected to a plate of a capacitor that samples the buffered input signal at the summing node.

[0110] In Example 208, the low-power track-and-hold circuit from one of Examples 201-207 can optionally include the dither capacitor connected to the summing node during a hold phase.

[0111] In Example 209, the low-power track-and-hold circuit from one of Examples 201-208 can optionally include the sampling network which has a first switch to connect a first and second plate of the dither capacitor to ground during a sampling phase.

[0112] In Example 210, the low-power track-and-hold circuit from one of Examples 201-209 can optionally include the sampling network which has a transfer switch to connect one plate of the capacitor sampling the buffered input signal to ground during a hold phase.

[0113] In Example 211, the low-power track-and-hold circuit from one of Examples 201-210 can optionally include the sampling network which has a dither transfer switch to connect a plate of the dither capacitor to a node with a dither voltage level during a hold phase.

[0114] In Example 212, the low-power track-and-hold circuit from one of Examples 201-211 can optionally include the sampling network which has a dither coupling switch to connect a plate of the dither capacitor to a node with a dither voltage level during a hold phase.

[0115] Example 213 shows the low-power track-and-hold circuit from one of Examples 201-212, wherein the sampling network has a dither transfer switch to connect one plate of the dither capacitor to the summing node during a hold phase.

[0116] In Example 214, the low-power track-and-hold circuit from one of Examples 201-213 can optionally include the summing node located on a lower plate of a capacitor that samples the buffered input signal.

[0117] In Example 215, the low-power track-and-hold circuit from one of Examples 201-214 can optionally include the summing node located behind an output switch that transfers the buffered input signal and the additive dither to the hold buffer.

[0118] In Example 216, the low-power track-and-hold circuit from one of Examples 201-213 can optionally include the summing node located before an output switch that transfers the buffered input signal and the additive dither to the hold buffer.

[0119] Example 217 is a method for sampling an input signal, wherein the method comprises: buffering an input signal; during a first phase, sampling the buffered input signal onto a capacitor in a sampling network and resetting a dither capacitor; during a second phase, transferring the buffered input signal to a summing node, coupling an additive dither signal to the summing node using a dither capacitor, and outputting a hold signal with the buffered input signal and the additive dither signal; and buffering the hold signal to generate a buffered signal for driving one or more analog-to-digital converters.

[0120] In Example 218, the method from Example 217 can optionally include random chopping of the buffered input signal in the sampling network based on multiplicative dithering.

[0121] In Example 219, the procedure from Example 217 or 218 may optionally include multiplying the buffered input signal in the sampling network based on a code sequence.

[0122] Example 220 is a low-power track-and-hold circuit, wherein the low-power track-and-hold circuit comprises: a sampling buffer; a sampling network for sampling a buffered input from the sampling buffer onto a capacitor and transferring the buffered input to a summing node, wherein the sampling network comprises a dither coupling switching capacitor network for adding a dither to the summing node; and a hold buffer for receiving a hold signal from the summing node. Examples of multi-input ADWs

[0123] Some multi-input ADWs do not use a summing converter and do not separate T / H or sample-and-hold circuits to receive and combine multiple inputs. Instead, many of the multi-input ADWs described herein use a shared T / H circuit to receive and multiplex multiple inputs, combining the signals by redistributing the charge of the sampling capacitors (without requiring a summing converter). Having separate, full T / H circuits can consume more power. A summing converter to add multiple input signals (possibly with different frequencies) could potentially produce a composite signal, which would necessitate a quantizer with a very large dynamic range. With spread-spectrum coding in a shared T / H circuit, it is possible to multiplex signals efficiently and effectively in the front-end circuitry of a multi-input ADW.

[0124] Example 301 is a multi-input analog-to-digital converter (ADC) comprising: parallel switching capacitor networks, wherein each parallel switching capacitor network has a circuit for encoding a respective input signal using a respective code sequence; and the parallel switching capacitor networks combine encoded input signals at a common node by charge redistribution of sampling capacitors in the parallel switching capacitor networks; and a quantizer for generating a digital output signal based on a multiplexed encoded signal at the common node.

[0125] In Example 302, the multi-input ADW from Example 301 can optionally include parallel sampling buffers for buffering respective input signals before the respective buffered input signals are sampled onto the respective sampling capacitors in the parallel switching capacitor networks.

[0126] In Example 303, the multi-input ADW of Example 301 or 302 may optionally include a holding buffer to buffer the multiplexed coded signal at the common node before a buffered multiplexed coded signal is digitized by the quantizer.

[0127] In Example 304, the multi-input ADW from one of Examples 301-303 may optionally include parallel decoders for demultiplexing the digital output signal from the quantizer into separate digital output signals using the respective code sequences.

[0128] In Example 305, the multi-input ADW from one of Examples 301-304 may optionally include the circuit for encoding the respective input signal using a respective code sequence, comprising a chopper circuit integrated into a given parallel switching capacitor network.

[0129] In Example 306, the multi-input ADW from one of Examples 301-305 can optionally include each of the parallel switching capacitor networks, comprising: multiple time-nested sampling networks.

[0130] In Example 307, the multi-input ADW from any of Examples 301-306 may optionally include each of the parallel switching capacitor networks, comprising: parallel sampling capacitors for implementing a spreading factor, wherein the spreading factor is a ratio between a hold rate and a sampling rate.

[0131] In Example 308, the multi-input ADW from one of Examples 301-307 may optionally include parallel control circuit track-and-hold circuits for supplying respective hold signals to the respective parallel switching capacitor networks.

[0132] In Example 309, the multi-input ADW from Example 308 can optionally include the respective parallel switching capacitor networks that oversample the respective hold signals to implement a spreading factor; and the spreading factor is a ratio between a hold rate and a sampling rate.

[0133] In Example 310, the multi-input ADW from one of Examples 301-309 may optionally include: peak detectors for detecting respective signal levels of the respective input signals.

[0134] In Example 311, the multi-input ADW from Example 310 is used, wherein the peak detectors output respective flags to an external circuit that drives the multi-input ADW to perform automatic gain control.

[0135] Example 312 of the multi-input ADW of Example 310 or 311 further comprises: a variable-gain amplifier for amplifying the multiplexed coded signal at the common node; wherein the peak detectors control an amplification of the variable-gain amplifier.

[0136] Example 313 is a method for multiplexing inputs into an analog-to-digital converter, wherein the method comprises: encoding, in respective parallel signal paths, of respective input signals using respective code sequences; multiplexing encoded input signals by charge redistribution of parallel sampling capacitors in the parallel signal paths; and converting, by means of a quantizer, a multiplexed encoded input signal into a digital output signal.

[0137] In Example 314, the procedure of Example 313 can optionally include demultiplexing the digital output signal from the quantizer into separate digital output signals using the respective code sequences.

[0138] In Example 315, the procedure of Example 313 or 314 may optionally include the encoding of a given input signal, comprising the interchanging of differential signal paths based on values ​​of a given code sequence.

[0139] In Example 316, the method from one of Examples 313-315 can optionally include sampling respective input signals onto respective sampling capacitors in respective parallel switching capacitor networks.

[0140] In Example 317, the method from one of Examples 313-316 may optionally include buffering the multiplexed coded input signal before converting the multiplexed coded input signal.

[0141] Example 318 is a multi-input, multi-output analog-to-digital converter comprising: parallel channels for sampling and encoding respective input signals; a common node for multiplexing encoded input signals by charge redistribution of sampling capacitors in the parallel channels; an analog-to-digital converter for converting a multiplexed encoded signal into a digital output signal; and parallel demultiplexers for demultiplexing the digital output signal.

[0142] In Example 319, the multi-input multi-output analog-to-digital converter of Example 318 can optionally include parallel peak detectors for detecting signal levels of the respective input signals and for adjusting the respective gains of the respective input signals.

[0143] In Example 320, the multi-input, multi-output analog-to-digital converter of Example 318 or 319 may optionally have a coding scheme such that it can be used to encode the respective input signals in the parallel channels, and which can be designed to be suitable for one or more of the following: one or more signal condition(s) and requirement(s) of the multi-input, multi-output analog-to-digital converter.

[0144] Example 1001 is a multi-input ADW comprising parallel switching capacitor networks and a quantizer for generating a digital output; wherein each switching capacitor network has a circuit for encoding a respective input signal using a respective orthogonal pseudorandom number sequence; and the parallel switching capacitor networks combine the encoded input signals at a node by charge redistribution of the sampling capacitors in the parallel switching capacitor networks.

[0145] In Example 1002, the multi-input ADW from Example 101 can further include several parallel sampling buffers for buffering the respective input signals before sampling the respective buffered input signals onto the sampling capacitors in the respective parallel switching capacitor networks.

[0146] In Example 1003, the multi-input ADW from Example 101 or 102 may further include a holding buffer for buffering a multiplexed signal at the node and delivering a buffered multiplexed signal to the quantizer for digitizing the buffered multiplexed signal.

[0147] In Example 1004, the multi-input ADW from one of Examples 10-103 may further include parallel decoders for demultiplexing the digital output into separate digital outputs using the respective orthogonal pseudorandom number sequences.

[0148] In Example 1005, the multi-input ADW from one of Examples 101-104 may further include the circuits for encoding the respective input signals, which perform the encoding during a hold phase.

[0149] In Example 1006, the multi-input ADW from one of Examples 101-104 may further include the circuits for encoding the respective input signals, which perform the encoding during a sampling phase.

[0150] In Example 1007, the multi-input ADW from one of Examples 101-106 may further include the circuits for encoding the respective input signals, which include chopper circuits.

[0151] In Example 1008, the multi-input ADW from one of Examples 101-107 may further include the parallel switching capacitor networks performing non-inverted sampling.

[0152] In Example 1009, the multi-input ADW from one of Examples 101-108 may also include the parallel switching capacitor networks performing inverted sampling.

[0153] In Example 1010, the multi-input ADW from one of Examples 101-109 may also include the parallel switching capacitor networks performing a base plate sampling.

[0154] In Example 1011, the multi-input ADW from one of Examples 101-110 can further include the parallel switching capacitor networks with multiple time-nested sampling networks.

[0155] In Example 1012, the multi-input ADW from one of Examples 101-111 may further include the parallel switching capacitor networks with parallel sampling capacitors for implementing a spreading factor, where the spreading factor is a ratio between a hold rate and a sampling rate.

[0156] In Example 1013, the multi-input ADW from one of Examples 101-112 may further include parallel control circuit track-and-hold circuits for supplying respective hold signals to the respective parallel switching capacitor networks, the parallel switching capacitor networks cross-sampling the hold signals to implement a spreading factor; and the spreading factor is a ratio between a hold rate and a sampling rate.

[0157] In Example 1014, the multi-input ADW from one of Examples 101-113 may further include peak detectors for detecting respective signal levels of the input signals.

[0158] In Example 1015, the multi-input ADW from Example 114 is used, with the respective peak detectors outputting flags / bits to an external circuit that drives the multi-input ADW to perform automatic gain control.

[0159] In Example 1016, the multi-input ADW of Example 114 or 115 is used, with the respective peak detectors outputting flags / bits to a variable-gain amplifier at the node, which amplifies a multiplexed signal.

[0160] Advantageously, various embodiments of the multi-input ADW can be used in applications with multiple inputs and outputs (MIMO) and multi-band receivers. Massive MIMO systems and multi-band requirements can present a scalability challenge. These applications can benefit from the multi-input multi-output ADW's ability to efficiently and effectively multiplex multiple inputs. The coding aspect provides spatial diversity pre-coding for 5G and massive MIMO. In the context of 5G and massive MIMO, spatial multiplexing can be used to spatially multiplex signals using specially defined codes. The circuit arrangement in the multi-input multi-output ADW can be easily adapted to use these specially defined codes for spatially multiplexing signals in the T / H circuit (i.e., in the parallel switching capacitor networks) and demultiplexing the signals in the digital domain.Furthermore, the multi-input ADW provides flexibility in allocating ADW capacity and can make the use of channel capacity more efficient.

[0161] Code modulation can be used when multiplexing more than one input in the same ADW during oversampling of the input. It decouples the sampling rate f. s1 of the quantization rate f s2 Advantages associated with code modulation and spread spectrum coding may include one or more of the following: • The dynamic range requirement of the ADW increases with the square root of N (where N is the spreading factor). • With spread spectrum coding, the overall system dynamic range and noise spectral density improve by 10 logN (where N is the spreading factor). • The distortion of even order improves. • Oversampling of the input signal is possible (fs2 > fs1). • If N=4, the collective dynamic range / noise spectral density for the entire ADW is 6 dB better. Accordingly, there is a range of flexibility / reconfigurability of 6 dB. In other words, there can be flexibility in assigning a dynamic range (around 10 log N). • The multi-input ADW can be reconfigured from a single ADW to an N-channel ADW (number of channels can be configured). • The coding scheme can be used for other types of coding, such as spatial multiplexing precoding in massive MIMO. • The multi-input ADW architecture can mitigate some of the obstacles to using multi-band receivers: efficient aggregation, ADW dynamic range, AGC, and band-to-band interference due to harmonics. • The gain of each input can be dynamically assigned to better utilize the ADW and channel capacity. When spread spectrum coding is used to multiplex multiple inputs, it is possible to dynamically adjust the gain of individual inputs based on signal conditions and / or application requirements. Adjusting individual input gains can be done to more efficiently utilize the channel capacity and / or dynamic range of the ADW. Using peak detectors (e.g., in Fig. (as shown in 19) the gain of individual inputs can be adjusted and / or the gain of the multiplexed signal can be adjusted. • Inputs to the multi-input ADW can be disabled programmatically or via software. For example, a subset of channels in the T / H circuit can be used while the remaining channels are programmatically disabled. In a special case, the multi-input ADW can receive a single analog input signal. The encoding can be disabled, and other unused channels in the T / H circuit can be switched off. • The coding scheme used can be selected from several coding schemes or changed according to signal conditions and / or application requirements. Variations and implementations

[0162] Example A is a device comprising means for implementing / executing one of the methods described herein.

[0163] The in Fig. The alternative implementations for coupling in additive dither shown in Figures 21-24 and illustrated by Examples 201-220 and C are complementary to, and can be appropriately combined with, the features described with respect to various examples of T / H circuits, including one or more of the features shown in Examples 1-9 and Examples 101-103. Fig. The alternative implementations for coupling in additive dither shown in 21-24 and illustrated by Examples 201-220 and C are complementary to and can be appropriately combined with the features described with respect to various examples of T / H circuits of the exemplary multi-input ADWs, including one or more features illustrated in Examples 301-320 and 1001-1016.

[0164] Other structures used in SHA-less ADWs (ADWs without sample-and-hold amplifiers), which reinforce the teachings herein, are also considered by the disclosure. However, they may be less efficient than the embodiments described herein.

[0165] Here, switches (e.g., those seen in the FIGURES) represent an electronic circuit arrangement that can be controlled to conduct or prevent current from conducting. In practice, switches can be implemented using transistors. By appropriately biasing the transistors, the transistor can conduct current or not (be "on" or "off"). When the switch is closed or "on," current flows to close the circuit path. When a switch is open or "off," current does not flow, and the circuit path is open. Switches can effectively connect one part of a circuit to another part of a circuit or disconnect one part of a circuit from another part of a circuit.

[0166] Note that the activities discussed above with reference to the FIGURES are applicable to any integrated circuits that involve processing analog signals and converting those signals into digital data using one or more ADWs. In certain contexts, the features discussed here applied to ADWs in general, including, for example, ADWs of various types such as pipeline ADWs, delta-sigma ADWs, successive approximation register (SAR) ADWs, multi-stage ADWs, time-nested ADWs, randomized time-nested ADWs, and so on. In other words, the quantizer can be implemented based on various ADW architectures.

[0167] These features can be particularly advantageous for fast ADWs, where input frequencies are relatively high in the gigahertz range. The ADW can be applied to medical systems, scientific instrumentation, wireless and wired communication systems (especially systems requiring a high sampling rate), radar, industrial process control, audio and video equipment, instrumentation, and other systems that utilize ADWs. The level of performance offered by fast ADWs can be especially beneficial for products and systems in demanding markets such as high-speed communications, medical imaging, synthetic aperture radar, digital beamforming communication systems, broadband communication systems, high-performance imaging, and advanced test / measurement systems (oscilloscopes).

[0168] The present disclosure includes devices capable of performing the various methods described herein. Such devices may comprise a circuit arrangement illustrated by the figures and described herein. Parts of various devices may include an electronic circuit arrangement for performing the functions described herein. The circuit arrangement may operate in the analog domain, the digital domain, or a mixed-signal domain. In some cases, one or more parts of the device may be provided by a processor specifically configured to perform the functions described herein (e.g., control-related functions, timing-related functions). In some cases, this processor may be an on-chip processor with the ADW.The processor may include one or more application-specific components or may include programmable logic gates configured to perform the functions described herein. In some cases, the processor may be configured to perform the functions described herein by executing one or more instructions stored on a non-volatile computer medium.

[0169] In one embodiment, any number of components of the FIGURES can be implemented on a circuit board of an associated electronic device. The circuit board can be a general-purpose circuit board that can hold various components of the electronic device's internal electronic system and can also provide connectors for other peripherals. In particular, the circuit board can provide the electrical connections through which the other components of the system can communicate electrically. Any suitable processors (including digital signal processors, microprocessors, supporting chipsets, etc.), computer-readable non-volatile memory elements, etc., can be suitably coupled to the circuit board based on specific training requirements, processing needs, computer designs, etc.Other components, such as external storage, additional sensors, audio / video display controllers, and peripherals, can be attached to the board as plug-in cards and via cables, or integrated into the board itself. In various embodiments, the functionalities described herein can be implemented in emulated form as software or firmware running within one or more configurable (e.g., programmable) elements arranged in a structure that supports these functions. The software or firmware providing the emulation can be provided on a non-volatile, computer-readable storage medium containing instructions that allow a processor to execute these functionalities.

[0170] In another embodiment, the components of the FIGURES can be implemented as independent modules (e.g., a device with associated components and circuit arrangement configured to perform a specific application or function) or can be implemented as plug-in modules in application-specific hardware of electronic devices. Note that certain embodiments of the present disclosure can readily be contained, either wholly or partially, in a system-on-chip (SOC) package. An SOC is an integrated circuit that integrates components of a computer or other electronic system onto a single chip. It can include digital, analog, mixed-signal, and often high-frequency functions; all of these can be provided on a single chip substrate.Other embodiments may include a multi-chip module (MCM), wherein several separate ICs are located within a single electronics package and are configured to interact closely with each other through the electronics package. In various embodiments, the calibration functionalities may be implemented in one or more silicon cores in application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and other semiconductor chips.

[0171] It is also essential to note that all specifications, dimensions, and relationships outlined herein (e.g., the number of processors, logic operations, etc.) are provided for illustrative and teaching purposes only. Such information may be varied considerably without deviating from the intent of the present disclosure or the scope of protection of any (possibly) appended claims or examples described herein. The specifications apply only to a non-limiting example and should be interpreted accordingly. The above description presents exemplary embodiments with reference to specific processor and / or component arrangements. Various modifications and changes may be made to such embodiments without deviating from the scope of protection of any (possibly) appended claims or examples described herein.The description and drawings should therefore be viewed in an illustrative rather than a restrictive sense.

[0172] Note that the numerous examples provided herein can describe an interaction involving two, three, four, or more electrical components or parts. However, this is done for clarity and illustrative purposes only. It is understood that the system can be consolidated in any suitable manner. Along with similar design alternatives, any of the components, modules, blocks, and elements of the FIGURES shown can be combined in various possible configurations, all of which are clearly within the broad scope of protection of this patent. In certain cases, it may be easier to describe one or more of the functionalities of a given set of flows only by referring to a specific number of electrical elements.It is understood that the electrical circuits of the FIGURES and their teachings can easily be scaled and can accommodate a large number of components as well as more complex / sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope of protection or preclude the comprehensive application of the electrical circuit teachings to a multitude of other architectures.

[0173] It should be noted that in this patent specification, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) contained in "one embodiment," "an exemplary embodiment," "another embodiment," "some embodiments," "different embodiments," "other embodiments," "alternative embodiment," and the like are intended to mean that all such features are contained in one or more embodiments of the present disclosure, but may be combined in the same embodiments or may not necessarily be combined. It is also important to note that the functions described herein illustrate only some of the possible functions that can be performed by or within systems / circuits depicted in the figures.Some of these operations may be deleted or eliminated where appropriate, or these operations may be modified or substantially altered without departing from the scope of protection of this disclosure. Furthermore, the timing of these operations may be substantially modified. The preceding workflows have been offered for illustrative and discussion purposes. Considerable flexibility is provided by embodiments described herein insofar as any suitable arrangements, chronologies, configurations, and timing mechanisms may be provided without departing from the teachings of this disclosure.Numerous other changes, substitutions, variations, alterations, and modifications can be identified by a person skilled in the art, and the present disclosure is intended to include all such changes, substitutions, variations, alterations, and modifications as fall within the scope of the appended claims or examples described herein. It should be noted that all optional features of the device described above can also be implemented with respect to the method or process described herein, and specific details in the examples can be used in one or more embodiments.

[0174] From one perspective, a multi-input analog-to-digital converter (ADC), i.e., a single ADC, can receive multiple analog input signals and generate multiple digital outputs. Combining multiple analog input signals into a single multi-input ADC would typically require multiple track-and-hold (T / H) circuits and an adder, which can consume a significant amount of power and result in high overall costs. An improved approach is to combine multiple inputs through a single T / H circuit in the ADC's front end. The multiple analog input signals can then be aggregated using code sequences, eliminating the need for a significant amount of external circuitry.

Claims

[1] Featuring track-and-hold functionality: a sampling buffer; a sampling network for sampling a buffered input signal from the sampling buffer onto a capacitor, wherein the sampling network includes a dither capacitor for coupling an additive dither to a summing node of the sampling network; and a hold buffer for receiving a hold signal from the sampling network. [2] Track-and-hold circuit according to claim 1, further comprising: a chopper integrated with the sampling network to couple in a multiplicative dither. [3] Track-and-hold circuit according to one of the preceding claims, further comprising: a chopper integrated with the sampling network to multiply the buffered input signal by a code. [4] Track-and-hold circuit according to one of the preceding claims, wherein the sampling network comprises a switching capacitor network to sample the buffered input signal from the sampling buffer onto one or more capacitors. [5] Track-and-hold circuit according to any of the preceding claims, wherein the sampling network comprises: an input switch for receiving the buffered input signal from the sampling buffer; and a sampling switch for sampling the buffered input signal onto a capacitor during a sampling phase. [6] Track-and-hold circuit according to one of the preceding claims, wherein the dither capacitor is part of a dither coupling switching capacitor network coupled to the summing node. [7] Track-and-hold circuit according to one of the preceding claims, wherein the dither capacitor is connected at the summing node to a plate of a capacitor that samples the buffered input signal. [8] Track-and-hold circuit according to one of the preceding claims, wherein the dither capacitor is connected to the summing node during a hold phase. [9] Track-and-hold circuit according to any of the preceding claims, wherein the sampling network has reset switches to connect a first and second plate of the dither capacitor to ground during a sampling phase. [10] Track-and-hold circuit according to any of the preceding claims, wherein the sampling network has a transfer switch to connect one plate of the capacitor sampling the buffered input signal to ground during a hold phase. [11] Track-and-hold circuit according to one of the preceding claims, wherein the sampling network has an output switch to connect one plate of the capacitor to the summing node during a hold phase. [12] Track-and-hold circuit according to one of the preceding claims, wherein the sampling network has a dither transfer switch to connect a plate of the dither capacitor to the summing node during a hold phase. [13] Track-and-hold circuit according to one of the preceding claims, wherein the sampling network has a dither coupling switch to connect a plate of the dither capacitor to a node with a dither voltage level during a hold phase. [14] Track-and-hold circuit according to one of the preceding claims, wherein the summing node is located on a lower plate of the capacitor that samples the buffered input signal. [15] Track-and-hold circuit according to one of the preceding claims, wherein the summing node is located downstream of an output switch which transfers the buffered input signal and the additive dither to the hold buffer. [16] Track-and-hold circuit according to any one of claims 1 to 13, wherein the summing node is located upstream of an output switch which transfers the buffered input signal and the additive dither to the hold buffer. [17] Method for sampling an input signal, wherein the method comprises: Buffering an input signal; during a first phase, sampling the buffered input signal onto a capacitor in a sampling network and resetting a dither capacitor; during a second phase, transferring the buffered input signal to a summing node, coupling an additive dither signal to the summing node using a dither capacitor, and outputting a hold signal with the buffered input signal and the additive dither signal; and Buffering the hold signal to generate a buffered signal for driving one or more analog-to-digital converters. [18] Method according to claim 17, further comprising: Random chopping of the buffered input signal in the sampling network based on multiplicative dithering. [19] Method according to claim 17 or 18, further comprising: Multiplying the buffered input signal in the sampling network based on a code sequence. [20] Featuring track-and-hold functionality: a sampling buffer; a sampling network for sampling a buffered input from the sampling buffer to a capacitor and transferring the buffered input to a summing node; a dither coupling switching capacitor network for adding a dither to the summing node; and a holding buffer to receive a hold signal from the summing node.

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