calculus circuit

Abstract

We provide electronic devices for use in artificial neuronal networks. [Solution] The electronic device 100, which is an artificial neural network, has an artificial neural array (ANA) 111, a row decoder 112, a column decoder 113, an input circuit 114, an output circuit 115, an analog signal processing circuit 116, and a memory 130. The ANA 111 has multiple circuits 10, 11, multiple wires WW, WB, DL, RB, and one wire RD. The circuits 10 are arranged in an n-row m-column array, and the circuits 11 are arranged in an n-row 1-column array. The wires WW are electrically connected to the row decoder, and the wires WB are electrically connected to the column decoder. The row decoder and column decoder are peripheral circuits for writing weights or thresholds to the circuit 10. The input circuit writes data DIN to the ANA 111, and the output circuit processes the analog signal input via wires RB and RD to generate data DOUT.

Description

[Technical Field] 【0001】 This application discloses, for example, an electronic device capable of storing analog potentials. [Background technology] 【0002】 One type of machine learning is the neural network (also called an artificial neural network). .) are examples. When constructing a neural network, for example, analog circuits are used. Such circuit configurations have been proposed (for example, Patent Documents 1 and 2). [Prior art documents] [Patent Documents] 【0003】 [Patent Document 1] Japanese Patent Application Publication No. 5-12466 [Patent Document 2] Japanese Patent Application Publication No. 6-187472 [Overview of the Initiative] [Problems that the invention aims to solve] 【0004】 The challenge is, for example, to provide a novel electronic device and a method for operating it. [Means for solving the problem] 【0005】 One embodiment of the present invention has a first circuit, a second circuit, and first to sixth wirings, wherein the first circuit is It has a first transistor, a second transistor, and a capacitive element, and the second circuit has a third transistor The first transistor has a gate, and the gate of the first transistor is electrically connected to the first wiring, and the first transistor The first terminal of the first transistor is electrically connected to the second wiring, and the second terminal of the first transistor is connected to the second transistor The gate of the sta is electrically connected, and the first terminal of the capacitive element is electrically connected to the third wiring. The second terminal of the capacitive element is electrically connected to the gate of the second transistor, and the second transistor The first terminal is electrically connected to the fourth wire, and the gate of the third transistor is electrically connected to the third wire. They are connected, and the first terminal of the third transistor is electrically connected to the fifth wire, and the second transistor The second terminal of the transistor is electrically connected to the sixth wire, and the second terminal of the third transistor is connected to the It is an electronic device electrically connected to 6 wires. 【0006】 In the electronic device of the above form, the current flowing through the fourth wire and the current flowing through the fifth wire are at least Even if it has a function to calculate the correction amount for the gate potential of the second transistor using the same method Good. Also, in the above configuration, the channel formation region of the first transistor is an oxide semiconductor It can be formed from the body. 【0007】 Where it is stated in this specification, etc., that X and Y are connected, X and Y are electrically connected. When they are connected aerodynamically, when X and Y are functionally connected, and when X and Y are directly connected The case in which the connections are made shall be disclosed in this specification, etc. Therefore, The connection relationships, for example, are not limited to the connection relationships shown in the diagram or text, but are shown in the diagram or text. Other connections besides those shown shall also be described in the diagram or text. X and Y are the object( For example, consider it to be a device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc. 【0008】 A transistor has three terminals called the gate, source, and drain. This node functions as a control node that controls the conduction state of the transistor. Alternatively, two input / output nodes that function as drains are used to provide the transistor type and each terminal. Depending on the potential difference, one becomes the source and the other the drain. In detailed documents, the terms "source" and "drain" may be used interchangeably. Furthermore, in this specification, the two terminals other than the gate may be referred to as the first terminal and the second terminal. be. 【0009】 Depending on the circuit configuration and device structure, the node may consist of terminals, wiring, electrodes, conductive layers, conductors, and other components. It can be rephrased as "pure matter region," etc. Also, terminals, wiring, etc. can be rephrased as "nodes." This is possible. 【0010】 Voltage is the difference between a certain potential and a reference potential (e.g., ground potential (GND) or source potential). It often refers to a difference. Therefore, it is possible to rephrase voltage as electric potential. Electric potential is relative. Therefore, even if it is labeled GND, it does not necessarily mean 0V. Sometimes it doesn't happen. 【0011】 In this specification, ordinal numbers such as "1st," "2nd," and "3rd" are used to indicate order. It may be used. Or, it may be used to avoid confusion of components, this In this case, the use of ordinal numbers does not limit the number of constituent elements, nor does it limit their order. No. Also, for example, one form of the invention can be described by replacing "first" with "second" or "third". It can be revealed. 【0012】 Other matters relating to the description in this specification are appended to Embodiment 5. [Effects of the Invention] 【0013】 One embodiment of the present invention provides a novel electronic device, or a method for operating a novel electronic device. It is possible to provide the following. Alternatively, according to one embodiment of the present invention, miniaturization of electronic devices is possible, or electronic This enables the device to consume less power. For example, one embodiment of the present invention is a computer for machine learning. It can be applied to a cutting system. One embodiment of the present invention typically involves weights This is an electronic device that takes analog values ​​as input and stores those analog values. 【0014】 The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention is: It is not necessarily required to have all of the effects exemplified. Furthermore, with respect to one embodiment of the present invention, Any issues, effects, and novel structures other than those described herein will be clearly indicated by the description and drawings of this specification. It will soften. [Brief explanation of the drawing] 【0015】 [Figure 1] A block diagram showing an example of the configuration of an electronic device. [Figure 2] A block diagram showing an example of the configuration of an electronic device. [Figure 3] A: Circuit diagram showing an example configuration of an artificial neural array (ANA). B: Circuit diagram showing an example configuration of the circuits used by the ANA. [Figure 4] A circuit diagram showing an example of a memory cell configuration. [Figure 5] A: Block diagram showing an example of the configuration of an electronic device. B: Circuit diagram showing an example of the configuration of a wiring switch. [Figure 6] A: A flowchart showing an example of an electronic component manufacturing method. B: A schematic perspective diagram showing an example of an electronic component configuration. [Figure 7] AH: A diagram showing an example of the configuration of electronic equipment. [Figure 8] A: Top view showing an example of transistor configuration. B: Cross-sectional view along line A1-A2 in Figure 8A. C: Cross-sectional view along line A3-A4 in Figure 8A. [Figure 9] A: Enlarged view of a portion of Figure 8B. B: Energy band diagram of a transistor. [Figure 10]A: Top view showing an example of transistor configuration. B: Cross-sectional view along line A1-A2 in Figure 10A. C: Cross-sectional view along line A3-A4 in Figure 10A. [Figure 11] A: Top view showing an example of transistor configuration. B: Cross-sectional view along line A1-A2 in Figure 11A. C: Cross-sectional view along line A3-A4 in Figure 11A. [Figure 12] A: Top view showing an example of transistor configuration. B: Cross-sectional view along line A1-A2 in Figure 12A. C: Cross-sectional view along line A3-A4 in Figure 12A. D: Enlarged view of a portion of Figure 12B. [Figure 13] A: Top view showing an example of transistor configuration. B: Cross-sectional view along the line y1-y2 in Figure 13A. C: Cross-sectional view along the line x1-x2 in Figure 13A. D: Cross-sectional view along the line x3-x4 in Figure 13A. [Figure 14] A, B: Cross-sectional views showing examples of electronic device configurations. [Figure 15] AD: Cross-sectional view showing an example of transistor configuration. [Modes for carrying out the invention] 【0016】 Embodiments of the present invention are described below. However, one embodiment of the present invention is not limited to the following description. The present invention may be modified in various ways in terms of its form and details without departing from the spirit and scope of the present invention. This will be easily understood by those skilled in the art. Therefore, one embodiment of the present invention is shown below. This should not be interpreted as being limited to the contents described in the embodiment. 【0017】 The multiple embodiments shown below can be combined as appropriate. If multiple configuration examples (including examples of manufacturing methods, operating methods, etc.) are shown within the form, they should be considered in relation to each other. The configuration examples can be combined as appropriate, and one or more configuration examples described in other embodiments can be combined with It is also possible to combine them as needed. 【0018】 In the drawing, identical elements or elements with similar functions, elements of the same material, or the same Sometimes, the same symbols are assigned to elements that are formed, and the explanation of this repetition is omitted. There are cases where this is the case. 【0019】 Furthermore, when there are multiple elements with the same sign, and it is necessary to distinguish between them, The symbols are denoted with identifying codes such as "[1]", "_1", "_2", and "[i, j]". In some cases, this may be done. For example, when distinguishing between multiple wiring WLs individually, the address number (line number) may be used. In some cases, the wiring WL on the second line may be written as wiring WL[2] using the (number) symbol. If you are not targeting specific rows or columns, simply write "Wiring WL only". 【0020】 In this specification, for example, the high power supply potential VDD is abbreviated as potential VDD, VDD, etc. This can happen. This is due to other components (e.g., signals, voltages, circuits, elements, electrodes, wiring). The same applies to (etc.). 【0021】 [Embodiment 1] A neural network is an information processing system modeled after a neural network. One model of a multi-network is, for example, a hierarchical network in which artificial neurons are arranged in a hierarchical structure. One example is a network structure. Artificial neurons receive multiple inputs, and one or more It generates an output. The artificial neuron considers the synaptic signal transmission efficiency for each input node. A corresponding weight and a threshold corresponding to the membrane potential of a nerve cell are set. This calculates an output value of 1 from multiple input signals. Typically, in artificial neurons, The sum of the products of all input values ​​and their weights (weighted sum, or sum of products) is calculated, and the threshold value is calculated from the weighted sum. The value obtained by subtracting this value is calculated, and a transfer function (for example, a step function or a sigmo) that takes this value as input is generated. The output value is determined by the (D function). This output value is the input value of the next level artificial neuron. Yes. In supervised learning, the output value is compared with the target signal, and the amount of weight correction is calculated from the error. Calculations are performed, and weights are adjusted. In some cases, both weights and thresholds are adjusted. 【0022】 The input signal value of an artificial neuron is not a discrete value (digital value) of "0" or "1", It is desirable that the input signal of the artificial neuron be a continuous value (analog value). In artificial neurons, input signals are processed as analog signals. It is efficient. For example, when using artificial neurons as digital processing circuits, if a specific weight is small... To weaken (equivalent to weakening the synaptic connections between other nerve cells), or the calculation result is To exit a local optimum and converge to the correct solution, multiple steps are required. This requires complex circuitry, which increases the size of electronic devices and also increases power consumption. This also leads to... 【0023】 Furthermore, SRAM (Static Memory) is used as a storage means for holding analog values ​​(weights, thresholds). Dynamic Random Access Memory (DRAM) While it is possible to use memory such as memory, flash memory, etc., the following problems arise. Yes. When using SRAM, an analog-to-digital converter is used to convert analog values ​​to digital values. A tether converter is required. Flash memory is difficult to control when writing analog values. Furthermore, there is an upper limit to the number of rewrites. While DRAM, by its operating principle, has no limit on the number of rewrites, Maintaining analog values ​​requires frequent refreshing, which increases power consumption. Furthermore, increasing the holding capacity reduces the effect of charge leakage from the holding capacity, The power consumption of the integrated circuit will increase. 【0024】 In this embodiment, an electronic device applicable to a computing system for machine learning. This will be explained. Typically, it is possible to store weights and thresholds as analog values. A sub-device is disclosed. Figure 1 is a block diagram showing an example configuration of an electronic device. 【0025】 <<Electronic equipment>> The electronic device 100 shown in Figure 1 includes an artificial neural array (ANA) 111 and a row decoder 11 2. Column decoder 113, input circuit 114, output circuit 115, analog signal processing circuit 116 , and has memory 130. The electronic device 100 is an artificial neural network device, artificial It could also be called a neural network. 【0026】 ANA111 has multiple circuits 10, 11, multiple wirings WW, WB, DL, RB, and one wire Circuit 10 has wiring RD. Circuit 10 is arranged in an n x m array. Circuit 11 has n It is arranged in a 1x1 array. Here, n is an integer greater than 1, and m is 0. It is a larger integer. In accordance with the arrangement of circuit 10, n wires WW, DL, and m wires Wirings WB and RB are provided. Circuit 10[i,j] (where i is greater than 1 and less than or equal to n) It is an integer, and j is an integer greater than 0 and less than or equal to m. ) is the wiring WW[i], WB[ It is electrically connected to [j], DL[i], and RB[j]. Circuit 11[j] is wired to DL[j]. It is electrically connected to RD. Circuit 10 is the basic unit of an artificial neural network. This is an artificial neuron. 【0027】 The row decoder 112 has n wires WW electrically connected to it, and the column decoder 113 has m wires The wiring WB is electrically connected. Row decoder 112 and column decoder 113 are connected to circuit 10 This is a peripheral circuit for writing weights or threshold values ​​to it. 【0028】 Data DIN is the input data that ANA111 processes. Here, Data DIN is This is an analog voltage signal, and the voltage value of the data DIN corresponds to the input value to ANA111. The data DIN is written to ANA111 by input circuit 114. Input circuit 1 At point 14, n wires DL are electrically connected. 【0029】 Furthermore, the electronic device 100 is, for example, connected to each of the wirings DL[1] to DL[n-1]. Input the data, and input analog data corresponding to the threshold value to wiring DL[n]. Alternatively, the system may be configured to perform a calculation by subtracting a threshold from the weighted sum. In this case, the implementation of this configuration is... To do this, circuits 10[n,1] to 10[n,m] that hold a threshold are, in the first row The circuit configuration may be different from the circuit in row (n-1). Also, for example, the wiring DL[1 Data is input to each of the wirings DL[n], and the output circuit 115 holds a threshold value. Alternatively, the output circuit 115 may be configured to perform a calculation by subtracting a threshold value from the weighted sum. . 【0030】 Output circuit 115 is a circuit for reading data from ANA111. Output circuit 11 5 processes the analog signal input via m wires RB and RD, and then performs calculations on the data. Generates data DOUT. Data DOUT is the analog output signal of electronic device 100. In other words, output circuit 115 is an analog signal processing circuit. 【0031】 The analog signal processing circuit 116 is a circuit for generating a learning signal from a teacher signal. The signal TC is the teacher signal. The learning signal is the output signal of the electronic device 100 and the teacher signal. This is a signal whose value is obtained by comparison. Here, analog signal processing circuit 1 The learning signal generated by 16 has a value calculated using the data DOUT and the signal TC. This is the number. In addition, the analog signal processing circuit 116 adjusts the weight correction amount based on the learned signal. The calculation is performed. The calculated correction amount is stored in memory 130 as an analog value. Memory 13 The correction amount stored as 0 will be used to calculate the correction amount during the next learning process. 【0032】 In other words, with each learning session, the analog signal processing circuit 116 processes the learning signal and the information obtained from the previous learning session. The correction amount is obtained by performing analog calculations on the obtained correction amount. Based on the obtained correction amount, the circuit 10 is used to record The stored weights are updated. The weight update first involves row decoder 112 and column decoder 113. The circuit operates and stores the weight (weight W) in circuit 10. pv ) then, via wiring RB, to output circuit 11 Write to 5. In output circuit 115, read weight W pv A new weight with the correction amount added. (weight W) nw Calculate the weight W. nw This is sent to the column decoder 113. Row decoder 1 12. The column decoder 113 assigns weight W to the target circuit 10. nw This will be written. 【0033】 The correction amount obtained in the previous learning was the weight W. nw It is not essential for the calculation, but using it will lead to convergence. It will be accelerated. Weight W nw If the correction amount obtained from the previous learning is not used in the calculation, then memory 1 Even if an artificial neural network device is configured with an electronic device 101 (Figure 2) that does not have 30, good. 【0034】 Furthermore, in electronic devices 100 and 101, the wiring DL can also be controlled by the row decoder 112. Yes, it is possible. In this case, the wiring DL should be electrically connected to the row decoder 112. 【0035】 The memory 130 includes a memory cell array 131, a row decoder 132, and a column decoder 133. The memory cell array 131 has multiple memory cells 30 and multiple wirings WL and BL. ru. 【0036】 The memory cells 30 are arranged in a p-row, q-column array, where p and q are integers greater than or equal to 1. p wirings WL and q wirings BL are provided to match the arrangement of the memory cells 30. The memory cell 30 is electrically connected to wiring WL, BL. Wiring WL is a word It is a line and is electrically connected to the row decoder 132. Wiring BL is a bit line, row It is electrically connected to decoder 133. Row decoder 132, column decoder 133 Then, data is written to and read from the memory cell array 131. 【0037】 <ana> Figure 3A shows an example of the circuit configuration of ANA111. Circuit 10 consists of node SN1 and transistor It has M1, M2, and a capacitive element C1. Circuit 11 has a transistor M3. 【0038】 (Circuit 10) Node SN1 is a holding node. The potential of node SN1 is the weight stored in circuit 10. This corresponds to [this]. Capacitor element C1 is a holding capacitance for maintaining the potential of node SN1. Capacitor The first terminal of element C1 is electrically connected to wiring DL, and the second terminal is electrically connected to node SN1. The gate of transistor M1 is connected to wiring WW, the first terminal to wiring WB, and the second terminal to node SN. It is electrically connected to 1. The on / off state of transistor M1 is controlled by wiring WW. Transistor M1 controls the electrical connection or disconnection between node SN1 and wiring WW. The gate of transistor M2 is connected to node SN1, the first terminal to wiring RB, and the second terminal to potential V. It is electrically connected to the power line (VNN line) that supplies NN. 【0039】 When writing the weights to circuit 10, first the column decoder 113 calculates the values ​​corresponding to the weights. Analog data (weight data) with voltage values ​​is written to the wiring WB. Then, the row is decoded. By turning on transistor M1 with DA112, the weights written to wiring WB are The data is written to node SN1. 【0040】 When reading the weights from circuit 10, the potential of the wiring DL is increased by input circuit 114. As the potential of wiring DL rises, the potential of node SN1 also rises. Transistor M2 An on-current (source-drain current) flows, and the potential of wiring RB changes. Output circuit 115 By detecting the potential of the wiring RB, the value of the weight can be obtained. 【0041】 (Circuit 11) Circuit 11 has a circuit configuration obtained by removing the transistor M1 and the capacitor element C1 from circuit 10. The transistor M3 may be a transistor having the same device structure as the transistor M2. The gate of the transistor M3 is connected to the wiring DL, the first terminal is connected to the wiring RD, and the second terminal is electrically connected to the VNN line. 【0042】 <<Operation example of the electronic device>> Using FIGS. 1 and 3A, an example of the operation method of the electronic device 100 will be described. 【0043】 Before performing learning (inputting data DIN), the current I flowing through the wiring RB from ANA111 RB0 =βW 2 is read out and held in the output circuit 115. β is a coefficient, and W is an analog voltage depending on the potential V of the node SN1. Note that the initial value of the weight of each circuit 10 may be a random number, so before reading the current I w RB0 it is not necessary to write the initial value of the weight, RB0 or before reading the current I RB0 it is also possible to write the initial value of the weight to each circuit 10 in advance 【0044】 Next, to perform learning, data DIN is input to the input circuit 114. The input circuit 114 writes an analog potential V corresponding to the input value to the wiring DL of each row. A current I [[ID=​​​​​​​​​​​​ x This is an analog voltage that depends on [something]. 【0045】 In output circuit 115, the difference in current ΔI flowing through wiring RB[i] RB1 [i]=I RB1 [i]―I RD1 ―I RB0 [i] is calculated, and the ΔI of m wirings RB RB1 Take the sum This yields a value equivalent to the current of 2βΣWX. In the output circuit 115, Circuits that calculate the difference in current can use common components such as operational amplifiers. Circuits corresponding to transfer functions such as step functions and sigmoid functions include, for example, inverter circuits. A circuit or comparator circuit can be used. When using an inverter circuit, the transfer function is differential The calculation of minutes can be performed using the current flowing through the inverter circuit. 【0046】 Next, as described above, the amount of weight correction is calculated and the corrected weights are written to circuit 10. 【0047】 In circuit 10, the leakage current from node SN1 (typically, the capacitive element C1, transistor) If the leakage current from zistas M1 and M2 can be sufficiently reduced, then circuit 10 will be in a non-learning state (learning state). After completion, fluctuations in the potential of node SN1 can be suppressed. Therefore, during this period, The row decoder 112, column decoder 113, input circuit 114, and output circuit 115 are stopped from operating. This allows for a reduction in the power consumption of the electronic device 100. 【0048】 One factor contributing to the potential fluctuation leakage current at node SN1 is the off state of transistor M1. This is the leakage current (off-current) between drains. Transistors using metal oxides as semiconductors OS transistors (oxide semiconductor transistors) have the characteristic of having extremely low off-currents. Because it possesses this property, it is suitable for transistor M1. 【0049】 Since the band gap of oxide semiconductors is 3.0 eV or higher, OS transistors are thermally excited. The resulting leakage current is small, and as shown above, the off-current is extremely small. OS Transistors The channel-forming region of the material contains at least one of indium (In) and zinc (Zn). It is preferable that the material be an oxide semiconductor. Such an oxide semiconductor is In-M-Zn. Oxides (where element M is, for example, Al, Ga, Y, or Sn) are typical examples. Electron donors (donors) By reducing impurities such as water or hydrogen, and also by reducing oxygen deficiency, oxide semi-oxides are reduced. The conductor can be made i-type (intrinsic semiconductor), or made to be as close to i-type as possible. Therefore, such oxide semiconductors can be called high-purity oxide semiconductors. By applying a normalized oxide semiconductor, an OS transistor normalized by channel width can be created. The off-current can be reduced to approximately a few yA / μm to a few zA / μm. The radiators and oxide semiconductors will be described in Embodiments 3 and 5. 【0050】 During the learning process of the electronic device 100, the analog potential held at node SN1 is frequently updated. A transistor using silicon as the semiconductor (Si transistor) is used in transistor M1. If this occurs, circuit 10 will need to be refreshed even during learning. In contrast, When an OS transistor is used for node M1, the potential fluctuation of node SN1 is suppressed. Therefore, there is no need to refresh circuit 10. 【0051】 OS transistors, compared to Si transistors, have a voltage range that can be applied between the source and drain. The upper limit of the voltage that can be applied between the source and gate is high (excellent voltage resistance). Therefore, the transient By using OS transistors for nodes M1 and M2, a higher voltage can be maintained at node SN1. Because this allows for higher voltages to be applied to wiring such as WW and DL. 【0052】 A modified version of circuit 10 is shown in Figure 3B. In circuit 13 of Figure 3B, the transistor M1 is replaced with a battery A transistor M4 having a gate is provided. Transistor M4 is also a transistor Similar to M1, it is preferable that it be an OS transistor. Backgain of transistor M4 By controlling the potential of the transistor, the threshold voltage of transistor M4 can be changed. Therefore, for example, the leakage current of transistor M4 can be changed. The potential of the back gate of the ZISTA M4 can be controlled for each circuit 13, or ANA111 You can also divide it into multiple blocks and perform the process block by block. 【0053】 When the leakage current of transistor M4 increases during non-learning, the potential of node SN1 decreases. This corresponds to a weakening of synaptic connections. 【0054】 During learning, if the leakage current of transistor M4 increases, the correct weights are written to circuit 13. It's not possible. In particular, supervised learning of neural networks (backpropagation) In some cases, the calculation result tends to be a local optimum, so the leakage of transistor M4 should be adjusted as appropriate. In some cases, increasing the current can allow us to escape the local minima and converge to the correct solution. In other words, the electronic device 100 has a large-scale mechanism to escape local minima and converge to the correct solution. Since there is no need to install a circuit, the electronic device 100 can be miniaturized. Alternatively, the electronic device 100 This allows for lower power consumption. 【0055】 The method for changing the leakage current of transistor M4 is not limited to controlling the back gate potential. For example, the leakage current of transistor M4 can be increased by irradiating it with ultraviolet light. The same applies to transistor M1. 【0056】 Figure 4 shows an example of a suitable memory cell circuit configuration for memory cell 30. The memory cell shown in Figure 4A Element 31 has transistors M31 and M35, a capacitive element C2, and node SN2. Memory Cell 31 is a gain-type cell having two transistors. In principle, This memory circuit has no limitations on the number of rewrite cycles and is capable of storing analog electrical potentials. . 【0057】 Node SN2 is a node that holds the potential corresponding to the data, and the capacitive element C2 is node S This is a holding capacitance for maintaining the potential of N2. Transistor M31 is a writing transistor. This is the case. By turning on transistor M31, data is written to node SN2. Transistor M35 is a readout transistor, and its gate is electrically connected to node SN2. Connected. 【0058】 The memory cell 32 shown in Figure 4B is a modified version of the memory cell 31. Transistor M31 A transistor M32 with a back gate is provided instead. (See Figure 4C for memory) Cell 33 is a modified version of memory cell 31, and replaces transistor M31 with a back gate. A transistor M33 is provided. The back gate of transistor M33 is It is electrically connected to the source, but the back gate is electrically connected to the source or drain. That's good too. 【0059】 Transistors M31 through M33 are OS transistors with extremely low off-current. It is preferable that it is a type. This increases the retention time of memory cells 31 to 33. It can be made longer. In memory cells 31 to 33, transistor M3 5 is a p-channel transistor, but it can also be an n-channel transistor. In the case of a channel-type transistor, transistor M35 may also be an OS transistor. A Si transistor would also be acceptable. 【0060】 The memory cell 34 shown in Figure 4D is a gain-type cell with three transistors. (Note) Like the memory cell 31, the recell 34 also has no limit on the number of rewrites in principle, and is analog This is a memory circuit capable of maintaining a certain electrical potential. 【0061】 Memory cell 34 consists of transistors M31, M36, M37, capacitive element C2, and node SN2. It has. Instead of transistor M31, transistor M32 or transistor M33 It may be provided. Also, transistors M36 and M37 may be OS transistors. Si transistors are also acceptable. Furthermore, transistors M36 and M37 are p-channel type transistors. Zista is also fine. 【0062】 The memory cell 35 shown in Figure 4E has a circuit configuration similar to that of a DRAM memory cell. Cell 35, like memory cell 31, has no limit on the number of rewrites in principle, and is analog. This is a memory circuit capable of maintaining electrical potential. The memory cell 35 is connected to transistor M31 It has a capacitive element C2 and a node SN2. Transistor M31 is replaced with transistor M 32 or transistor M33 may be provided. 【0063】 An artificial neural network device with complex functions created by connecting multiple ANA111s It can be constructed. Furthermore, multiple ANA111s can be used to create an FPGA-like configuration. In this case, an artificial neural network device can be constructed. Treating them as logic elements, ANA111 and ANA111 are programmed as a switch A simple electrical connection can be made using a switch. Figure 5A shows an example of an electronic device with such a configuration. 【0064】 The electronic device 102 shown in Figure 5A consists of multiple ANA111 and a wiring switch array 140. The wiring switch array 140 has a plurality of wiring switches. Figure 5B shows the wiring. An example of a switch configuration is shown. 【0065】 The wiring switch 141 shown in Figure 5B is a programmable wiring switch. Node IN The output node of the ANA111 is electrically connected to it, and another ANA11 is connected to node OUT. One input node is electrically connected. Wiring switch 141 is connected to transistor M41 or It has a transistor M43, a capacitive element C4, a node SN4, and wirings 144 to 146. The potential of node SN4 determines the conduction state between node IN and node OUT. Capacitor element C4 is the holding capacitance of node SN4. Transistor M41 is a memory cell. Similar to transistor M31 of 31, it is preferable that it be an OS transistor. This allows the state of the wiring switch 141 to be maintained for a long time. Transistor M41 has , transistors with back gates such as transistor M32 or transistor M33 You may apply the ta. 【0066】 The electronic device of this embodiment can be used to construct an artificial neural network. The electronic device of this embodiment can be used to perform, for example, speech recognition or image recognition. For example, by having the electronic device of this embodiment perform voice recognition, electronic devices can be controlled by voice. It is possible to input and operate the electronic device of this embodiment. By doing so, electronic devices incorporating electronic equipment can be used to match faces and fingerprints, and input handwritten characters. This enables force and optical character recognition. 【0067】 [Embodiment 2] This embodiment describes a method for manufacturing an electronic device and an example of its configuration. Furthermore, it describes an electronic device comprising... This section will explain electronic devices and the like. 【0068】 <<Examples of methods for manufacturing electronic components>> Figure 6A is a flowchart showing an example of a method for manufacturing electronic components. The electronic component is a transistor. The printed circuit board goes through the manufacturing process (front-end process) and assembly process (back-end process) of such devices. It is completed by combining several detachable parts. Figure 6A shows an example of a subsequent process. Figure 6A The electronic components completed through subsequent processes are semiconductor packages, IC packages, or packages. Also called a connector. Electronic components have multiple connectors depending on the direction of terminal extraction, the shape of the terminals, etc. There are ranks and names associated with them. Therefore, we will explain one example here. 【0069】 First, the preprocessing is carried out to complete the element substrate (Step S1). Next, the substrate is assembled into multiple chips. A dicing process is performed to separate the substrate into multiple parts (step S2). Before dividing the substrate into multiple parts, the substrate is By thinning the film, we reduce warping of the substrate during the front-end process and aim to miniaturize the components. The chip is picked up The die bonding process is performed (step S) to mount the lead frame and join the components. 3) The bonding between the chip and the lead frame in the die bonding process is done with resin or tape. Therefore, it should be done as is. The bonding method should be selected to suit the product. Die bonding work Alternatively, the chip may be mounted on the interposer and joined. In the wire bonding process... The leads of the lead frame and the electrodes on the chip are electrically connected with thin metal wires. (Step S4). For the thin metal wire, silver or gold wire can be used. The bonding can be either ball bonding or wedge bonding. 【0070】 The wire-bonded chips are then sealed with epoxy resin or the like in a molding process. (Step S5). The leads of the lead frame are plated. Then the leads are cut. Cutting and shaping are performed (step S6). Plating is performed to prevent rusting of the lead, and then pre- This allows for more reliable soldering when mounting to a circuit board. The printing process (marking) is performed (step S7). After the inspection process (step S8), the electric The sub-component is completed (Step S9). 【0071】 <<Example of electronic component configuration>> Figure 6B is a schematic perspective view of an electronic component. As an example, Figure 6B is a QFP (Quad Flare). The package is shown. The electronic component 7000 shown in Figure 6B has lead 7001 The diagram also shows the circuit section 7003. The circuit section 7003 includes, for example, the electronic components of Embodiment 1. The circuits that make up the arrangement are fabricated. The electronic component 7000 is, for example, a printed circuit board 7002 It is implemented in. Multiple such electronic components 7000 are combined, and each one is printed Electrically connected on board 7002. The completed circuit board 7004 is mounted on an electronic device. It can be done. 【0072】 Electronic component 7000 can be used in various processors. For example, electronic component 700 0 is digital signal processing, software-defined radio, avionics (communication equipment, navigation systems, Aerospace electronic equipment such as autopilot systems and flight management systems, ASIC prototyping Image processing, medical image processing, speech recognition, cryptography, bioinformatics (biological information science), Examples include emulators for mechanical devices, radio telescopes in radio astronomy, and in-vehicle electronic equipment. It can be applied to electronic components (IC chips) in a wide range of electronic devices. 【0073】 Other electronic devices that can use the Electronic Component 7000 include smartphones and mobile phones. Telephones, game consoles including portable devices, e-readers, cameras (video cameras, digital still cameras) Cameras, etc., wearable information terminals (head-mounted, goggles, glasses, armbands, etc.) Bracelet type, wristwatch type, necklace type, etc.), navigation system, sound playback device ( Car audio systems, digital audio players, etc., television tuners for receiving television broadcasts. , photocopiers, fax machines, printers, multifunction printers, automated teller machines (ATMs) Examples include vending machines, etc. 【0074】 By incorporating electronic component 7000, the electronic device will have the functions of the electronic device of Embodiment 1. This becomes possible. For example, by giving electronic devices voice recognition capabilities, electronic devices can be controlled by voice. It becomes possible to operate equipment or input information into electronic devices. By equipping the device with image recognition capabilities, it can perform matching using fingerprints, veins, faces, etc., as well as handwritten character input. These and other possibilities become possible. A specific example of such an electronic device is shown in Figure 7. 【0075】 The portable game console 2900 shown in Figure 7A consists of a casing 2901, a casing 2902, and a display unit 2903. , display unit 2904, microphone 2905, speaker 2906, operation keys 2907, etc. It has. The display unit 2903 is equipped with a touchscreen as an input device, style It can be operated using LASS 2908, etc. 【0076】 The information terminal 2910 shown in Figure 7B has a housing 2911, a display unit 2912, a microphone 2917, Speaker unit 2914, camera 2913, external connection unit 2916, and operation button 29 It has 15 etc. The display unit 2912 has a display panel and touch screen made of a flexible substrate. It is equipped with cleanliness. The information terminal 2910 is, for example, a smartphone, mobile phone, tablet. It can be used as a type-type information terminal, tablet PC, e-book reader, etc. 【0077】 The notebook PC 2920 shown in Figure 7C consists of a casing 2921, a display unit 2922, and a keyboard 29 It has 23, and a pointing device 2924, etc. 【0078】 The video camera 2940 shown in Figure 7D consists of a housing 2941, a housing 2942, a display unit 2943, It has an operation key 2944, a lens 2945, and a connecting part 2946, etc. Operation key 2944 The lens 2945 is provided in the housing 2941, and the display unit 2943 is provided in the housing 2942. It is provided. And housing 2941 and housing 2942 are connected by connection part 2946. The angle between housing 2941 and housing 2942 is changed by the connecting part 2946. The structure allows for this. Depending on the angle of housing 2942 relative to housing 2941, the display section You can change the orientation of the image displayed in 2943, and toggle the display / hide of the image. can. 【0079】 Figure 7E shows an example of a bangle-type information terminal. The information terminal 2950 consists of a housing 2951 and It has a display unit 2952, etc. The display unit 2952 is supported by a curved housing 2951. The display unit 2952 is equipped with a display panel using a flexible substrate, so We can provide the 2950, ​​a flexible, lightweight, and user-friendly information terminal. 【0080】 Figure 7F shows an example of a wristwatch-type information terminal. The information terminal 2960 consists of a housing 2961 and a display unit. 2962, Band 2963, Buckle 2964, Operation Button 2965, Input / Output Terminal 296 It is equipped with 6, etc. The information terminal 2960 is a mobile phone, email, document viewing and creation, music It runs various applications such as playback, internet communication, and computer games. It is possible. 【0081】 The display surface of the display unit 2962 is curved, and the display can be displayed along the curved surface. Furthermore, the display unit 2962 is equipped with a touch sensor, allowing the user to touch the screen with their finger or stylus. It can be operated by touching the icon 2967 displayed on the display unit 2962. This allows you to launch the application. Operation button 2965 is for setting the time. In addition to the above, it also controls power on / off, wireless communication on / off, silent mode, and It can be equipped with various functions, such as disabling, activating and disabling power saving mode, etc. For example, The operating system built into the information terminal 2960 controls the operation buttons 2965 You can also configure the functions. 【0082】 Furthermore, the information terminal 2960 is capable of performing short-range wireless communication compliant with communication standards. Yes, for example, by communicating with a wireless headset, hands-free operation is possible. It can also make phone calls. Furthermore, the information terminal 2960 is equipped with input / output terminals 2966, which can also be used for other information. Data can be exchanged directly between the terminal and the connector. Also, input / output terminal 29 Charging can also be performed via 66. Note that the charging operation does not use input / output terminal 2966. This may also be done by wireless power transfer. 【0083】 Figure 7G shows an electric refrigerator as an example of a household electrical appliance. Electric refrigerator 2970 is It includes a housing 2971, a door for the refrigerator compartment 2972, and a door for the freezer compartment 2973, etc. 【0084】 Figure 7H is an external view showing an example of the configuration of an automobile. Automobile 2980 is a vehicle body 2981, It has wheels 2982, a dashboard 2983, and lights 2984, etc. Automobile 298 Not limited to 0, the electronic components of this embodiment can also be incorporated into ships, aircraft, and motorcycles. can. 【0085】 [Embodiment 3] This embodiment describes the device structure of the OS transistor, etc. 【0086】 <<Transistor Configuration Example 1>> Figure 8A is a top view of transistor 400a. Figure 8B shows the same configuration as in Figure 8A, but with lines A1-A2. This is a cross-sectional view, and Figure 8C is a cross-sectional view of Figure 8A along the line A3-A4. Note that A1-A2 The direction of the line is called the channel length direction of transistor 400a, and the direction of the A3-A4 line is called the channel length direction of transistor 400a. This is sometimes referred to as the channel width direction of the ZISTA 400a. Note that in Figure 8A, for clarity of the figure... Some elements have been omitted from the illustration for clarity. The top view in Figure 9A, etc., is similar to that of Figure 8A. 【0087】 Transistor 400a is formed on substrate 450. Transistor 400a is insulating Films 401 to insulating film 408, conductive films 411 to conductive films 414, conductive films 421 to conductive films 4 24. It has metal oxides 431 to 433. Here, metal oxide 431 is The metal oxides 433 are sometimes collectively referred to as metal oxide 430. 【0088】 Metal oxide 432 is a semiconductor and has a channel-forming region. A layer of metal oxide is formed between 1 and metal oxide 432. The layer is in regions 441 and 442. Region 441 is formed in the region where the conductive film 421 and the laminate are in contact, and region 442 is , formed in the region where the conductive film 423 and the laminate are in contact. In the laminate, regions 441, 4 Region 42 is a low-resistance region with lower resistivity than other regions. The stacking has region 441. This makes it possible to reduce the contact resistance between the conductive film 421 and the laminate. Similarly, the laminate Having region 442 reduces the contact resistance between it and the conductive film 423. It becomes Noh. 【0089】 The lamination of conductive films 421 and 422, and the lamination of conductive films 423 and 424, respectively, are based on the source power It constitutes an electrode or drain electrode. The conductive film 422 is less permeable to oxygen than the conductive film 421. It has a function that prevents a decrease in the conductivity of the conductive film 421 due to oxidation. Similarly, conductive film 424 has the property of being less permeable to oxygen than conductive film 423. Therefore, it becomes possible to prevent a decrease in the conductivity of the conductive film 423 due to oxidation. 【0090】 Conductive films 411 to 413 are the gate electrodes (front gate) of transistor 400a. The electrode is formed by the conductive film 411 to the conductive film 413, which constitutes the gate electrode. It is formed self-aligningly to fill the opening 415 formed in the insulating film 405, etc. It is preferable that the electrical films 411 and 413 are less permeable to oxygen than the conductive film 412. This makes it possible to prevent a decrease in the conductivity of the conductive film 412 due to oxidation. The conductive film 414 is It constitutes the back gate electrode. The conductive film 414 may be omitted in some cases. 【0091】 Insulating films 405 to 408 are protective insulating films or interlayer insulating films of transistor 400a. They constitute. In particular, insulating film 406 constitutes the gate insulating film. insulating films 401 to insulating films 40 4 has the function of an underlayer insulating film for transistor 400a. In particular, insulating film 402 to insulating film Film 404 also functions as a gate insulating film on the back gate side. 【0092】 As shown in Figure 8C, the side surface of the metal oxide 432 is surrounded by the conductive film 411. By adopting this device structure, the electric field of the gate electrode (conductive film 411 to conductive film 413) Therefore, the metal oxide 432 can be electrically surrounded by the electric field of the gate electrode. The structure of a transistor, which electrically surrounds a semiconductor, is called a surrounded channel. This is called an el(s-channel) structure. Therefore, the entire (bulk) metal oxide 432 A channel is formed. The s-channel structure is the source-drain of the transistor. A large current can be passed through it, allowing the transistor's on-current to be increased. The hannel structure allows for high on-current, making it suitable for use in processors, memory devices, and other micro-devices. This structure is suitable for semiconductor devices that require a small transistor. Because it can be miniaturized, the semiconductor device having the transistor has a high degree of integration and high density. It can be used as a semiconductor device. 【0093】 As shown in Figure 8B, the layering of conductive films 411 to 413 and conductive film 422 are insulating films. 405 and 406 have overlapping regions with each other in between. Similarly, conductive films 411 to The laminated film 413 and the conductive film 424 are separated by insulating films 405 and 406, and overlap each other. These regions have a region between the gate electrode and the source electrode or drain electrode. This acts as a parasitic capacitance, causing a decrease in the operating speed of transistor 400a. To obtain the above-mentioned parasitic capacity, transistor 400a is provided with a relatively thick insulating film 405. It becomes possible to reduce the amount. The insulating film 405 is made of a material with a low relative permittivity. preferable. 【0094】 Figure 9A is an enlarged view of the channel formation region of transistor 400a. In Figure 9A, The bottom surface of the conductive film 411 is connected to the metal oxide 432 via the insulating film 406 and the metal oxide 433. The length of the area parallel to the top surface is the width L. G Let's assume the width L G This is the transistor 400a This represents the line width of the gate electrode. Also, in Figure 9A, the length between conductive film 421 and conductive film 423. Width L SD Let's assume the width L SD The source electrode and drain electrode of transistor 400a It represents the length of time between two points. 【0095】 Width L SD The width L is often determined by the minimum machining dimension, as shown in Figure 9A. G is width L SD It is smaller than the minimum processing dimensions of the gate electrode of transistor 400a. This shows that it is possible to make it even smaller. For example, width L G 5nm or more 60 It becomes possible to set the wavelength to less than nm, preferably between 5 nm and 30 nm. 【0096】 In Figure 9A, the sum of the thicknesses of conductive film 421 and conductive film 422, or conductive film 423 and The total thickness of the conductive film 424 is the height H SD This is expressed as follows: The thickness of the insulating film 406 is the height H. SD Same Alternatively, by making it even smaller, the electric field of the gate electrode is applied to the entire channel formation region. This becomes possible and preferable. For example, the thickness of the insulating film 406 is 30 nm or less, preferably 1 The nm size should be 0 nm or less. 【0097】 Furthermore, the parasitic capacitance formed between the conductive film 422 and the conductive film 411, and the conductive film 424 and the conductive The magnitude of the parasitic capacitance formed between the film 411 is inversely proportional to the thickness of the insulating film 405. For example, the thickness of insulating film 405 is three times or more the thickness of insulating film 406, preferably five times or more. By doing so, these parasitic capacitances become negligibly small, and the transistor 400a This is preferable because it improves high-frequency characteristics. The following describes the components of transistor 400a. An explanation will be given. 【0098】 <Metal oxide> The metal oxide 432 is, for example, an oxide semiconductor containing indium (In). The metal oxide 432 has, for example, a higher carrier mobility (electron mobility) when it contains indium. Also, it is preferable that the metal oxide 432 contains an element M. The element M is preferably aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), or the like. Other elements applicable to element M include boron (B), silicon (Si), titanium ( Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr) , molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), haf nium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), and the like. However, a plurality of the aforementioned elements may be combined as the element M. The element M is, for example , an element having a high binding energy with oxygen. For example, an element having a higher binding energy with oxygen than indium . Or, the element M is, for example, an element having a function of increasing the energy gap of the metal oxide. Also, it is preferable that the metal oxide 432 contains zinc (Zn). The metal oxide may be likely to crystallize when it contains zinc. 【0099】 However, the metal oxide 432 is not limited to an oxide semiconductor containing indium. The metal oxide 432 may be, for example, an oxide semiconductor that does not contain indium, such as zinc tin oxide or gallium tin oxide, an oxide semiconductor containing zinc, an oxide semiconductor containing gallium, an oxide semiconductor containing tin, or the like . 【0100】 The metal oxide 432 uses, for example, an oxide semiconductor having a large energy gap. Metal The energy gap of the oxide 432 is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less. It is preferable to use CAAC-OS described later for the metal oxide 432. 【0101】 For example, it is preferable that the metal oxides 431 and 433 contain at least one kind of the metal element constituting the metal oxide 432. Thereby, at the interface between the metal oxide 431 and the metal oxide 432, and at the interface between the metal oxide 432 and the metal oxide 433, interface levels are less likely to be formed. 【0102】 When the metal oxide 431 is an In-M-Zn oxide, when the sum of In and M is 100 atomic% preferably In is less than 50 atomic% and M is higher than 50 atomic %, and more preferably In is less than 25 atomic% and M is higher than 75 atomic% When forming the metal oxide 431 by sputtering method, it is preferable to use a sputtering target satisfying the above composition. For example, In:M:Zn = 1: 3:2, In:M:Zn = 1:3:4, etc. are preferable. 【0103】 When the metal oxide 432 is an In-M-Zn oxide, when the sum of In and M is 100 atomic% preferably In is higher than 25 atomic% and M is less than 75 ato mic%, and more preferably In is higher than 34 atomic% and M is less than 66 ato mic%. When forming the metal oxide 432 by sputtering method, the above composition It is preferable to use a sputtering target that satisfies the following conditions. For example, In:M:Zn= 1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M Zn=3:1:2 and In:M:Zn=4:2:4.1 are preferred. In particular, sputtering When using an atomic ratio of In:Ga:Zn=4:2:4.1 as the target material, The atomic ratio of the metal oxide 432 is approximately In:Ga:Zn = 4:2:3. be. 【0104】 Furthermore, when metal oxide 433 is In-M-Zn oxide, the sum of In and M is 100ato When expressed as mic%, preferably In is less than 50 atomic%, and M is 50 atomic%. Higher than %, and more preferably In is less than 25 atomic%, and M is 75 atomic% Make it higher than %. For example, In:M:Zn=1:3:2, In:M:Zn=1:3:4 These are preferable. Also, metal oxide 433 may be the same type of metal oxide as metal oxide 431. It's okay to be there. 【0105】 Furthermore, there are cases where metal oxide 431 or metal oxide 433 does not need to contain indium. For example, metal oxide 431 or metal oxide 433 may be gallium oxide. 【0106】 <Energy band structure> Using the energy band structure diagram shown in Figure 9B, metal oxides 431 to 433 The function and effects of the metal oxide 430, which is formed by the layering of these materials, will be explained. (Figure 9B) This shows the energy band structure of the region indicated by the Y1-Y2 line in Figure 9A. Ec40 4. Ec431, Ec432, Ec433, and Ec406 are, respectively, insulating film 404 and gold. The energies of the lower ends of the conduction bands of the oxide 431, metal oxides 432, 433, and the insulating film 406 are shown. is shown. 【0107】 Here, the difference between the vacuum level and the energy of the lower end of the conduction band (also referred to as "electron affinity") is the value obtained by subtracting the energy gap from the difference between the vacuum level and the energy of the upper end of the valence band (also referred to as ionization potential). The energy gap can be measured using a spectroscopic ellipsometer. Also, the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS) apparatus. from the difference between the vacuum level and the energy of the upper end of the valence band (also referred to as ionization potential) by subtracting the energy gap. The energy gap can be measured using a spectroscopic ellipsometer. Also, the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS) apparatus. Since the insulating films 404 and 406 are insulators, Ec406 and Ec404 are closer to the vacuum level (have a smaller electron affinity) than Ec431, Ec432, and Ec433. Analysis (UPS: Ultraviolet Photoelectron Spectro scopy) apparatus. 【0108】 Ec432, and Ec433. Ec432, and Ec433. 【0109】 It is preferable to use a metal oxide for the metal oxide 432 that has a larger electron affinity than the metal oxides 431 and 433. For example, as the metal oxide 432, a metal oxide having an electron affinity 0.07 eV or more and 1.3 eV or less, preferably [[ID= 28]]0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less larger than that of the metal oxides 431 and 433 is used. The electron affinity is the difference between the vacuum level and the energy of the lower end of the conduction band. 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less is used. The electron affinity is the difference between the vacuum level and the energy of the lower end of the conduction band. is the difference. 【0110】 Note that indium gallium oxide has a small electron affinity and high oxygen blocking properties. Therefore, it is preferable that the metal oxide 433 contains indium gallium oxide. Therefore, it is preferable that the metal oxide 433 contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more. More preferably, it should be 90% or more. 【0111】 When a gate voltage is applied to transistor 400a, electron affinity occurs in metal oxide 430. A channel is formed in the metal oxide 432, which has a high force. At this time, electrons are in the metal oxide 4 It primarily moves within the metal oxide 432, rather than within 31 and 433. Therefore, metal The interface between oxide 431 and insulating film 404, or between metal oxide 433 and insulating film 406 Even if there are many interface levels at the interface that inhibit the flow of electrons, transistor 400a It has almost no effect on the on current. Metal oxides 431 and 433 act like insulating films. To be able to. 【0112】 Between metal oxide 431 and metal oxide 432, A mixed region may exist. Also, between metal oxide 432 and metal oxide 433 A mixed region of metal oxide 432 and metal oxide 433 may exist. This results in a lower interfacial state density. Therefore, the stacking of metal oxides 431-433 is as follows: A band structure in which the energy changes continuously near the interface (also called a continuous junction). This is the result. 【0113】 The interface between metal oxide 431 and metal oxide 432, or between metal oxide 432 and metal oxide As mentioned above, the interface with material 433 has a low interface state density, therefore in the metal oxide 432 Since electron movement is less hindered, the on-current of transistor 400a is increased. This becomes possible. 【0114】 For example, electron movement in transistor 400a is affected by large physical irregularities in the channel formation region. It is inhibited in certain cases. In order to increase the on-current of transistor 400a, for example, The upper or lower surface of the metal oxide 432 (the surface to be formed, in this case the upper surface of the metal oxide 431), The root mean square (RMS) roughness in the μm × 1 μm range is less than 1 nm, preferably 0 If the wavelength is less than 0.6 nm, more preferably less than 0.5 nm, and more preferably less than 0.4 nm If so, then. Also, the average surface roughness (also called Ra) in a 1 μm × 1 μm area is less than 1 nm. Less than 0.6 nm, more preferably less than 0.5 nm, and more preferably 0. It should be less than 4 nm. Also, the maximum height difference (PV) within a 1 μm × 1 μm area (also known as PV) (It is said that) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and more preferably The minimum wavelength should be less than 7nm. 【0115】 Electron movement is also inhibited when the defect level density in the channel formation region is high. For example, metal oxide 432 is oxygen-deficient (V O Also written as: ) If it has oxygen deficiency Hydrogen can enter the site, forming a donor level. Below is information on oxygen-deficient sites. V is the state in which hydrogen is incorporated. O It is sometimes written as H. O Because H scatters electrons, This is a factor that reduces the on-current of the transistor. Furthermore, oxygen-deficient sites are filled with hydrogen. It is more stable when oxygen is present than when it is absent. Therefore, reducing the oxygen deficiency in metal oxide 432 This can sometimes increase the on-current of the transistor. 【0116】 For example, at a certain depth of the metal oxide 432, or in a certain region of the metal oxide 432 Furthermore, the hydrogen concentration measured by secondary ion mass spectrometry (SIMS) is 1 × 10⁻⁶. 16 ato ms / cm 3 The above is 2 x 10 20 atoms / cm 3 The following is preferably 1 × 10 16 at oms / cm 3 The above 5 x 10 19 atoms / cm 3 More preferably 1 × 10 1 6 atoms / cm 3 The above is 1 x 10 19 atoms / cm 3 More preferably, 1 ×10 16 atoms / cm 3 The above 5 x 10 18 atoms / cm 3 The following applies: 【0117】 To reduce oxygen deficiency in the metal oxide 432, for example, excess acid contained in the insulating film 404 One method involves moving the element to metal oxide 432 via metal oxide 431. In this case, the metal oxide 431 is an oxygen-permeable layer (a layer that allows oxygen to pass through or permeate). It is preferable to do so. 【0118】 The thickness of metal oxide 432 can be between 1 nm and 20 nm. The thickness of 2 depends on the channel length; the shorter the channel length, the thinner it can be, for example, 1 nm or more. It can be less than or equal to nm, or between 1 nm and 10 nm. 【0119】 The thickness of metal oxide 431 can be between 5 nm and 200 nm, or 10 nm. 120nm or more, or 20nm or more and 120nm or more, or 40nm or more and 80nm or more It can be as follows. It is preferable that the metal oxide 431 is thicker than the metal oxide 432. By increasing the thickness of the metal oxide 431, from the interface between the adjacent insulator and the metal oxide 431 This allows us to increase the distance to the channel formation region. 【0120】 The thickness of metal oxide 433 can be 1 nm or more and 100 nm or less, or 1 nm or less The wavelength can be 50nm or less, or 1nm to 10nm. Also, transistors To increase the on-current of 400A, metal oxide 433 is thinner than metal oxide 431. It is preferable to do so. 【0121】 For example, between metal oxide 432 and metal oxide 431, for example, silico by SIMS The concentration is 1 × 10 16 atoms / cm 3 The above is 1 x 10 19 atoms / cm 3 less than Preferably 1 × 10 16 atoms / cm 3 The above 5 x 10 18 atoms / cm 3 Not yet Full, more preferably 1 × 10 16 atoms / cm 3 The above 2 x 10 18 ate / c m 3 It has a region that is less than . Also, between metal oxide 432 and metal oxide 433, S The silicon concentration measured by IMS is 1 × 10 16 atoms / cm 3 The above 1 x 10 19 ato ms / cm 3 Less than 1 × 10 16 atoms / cm 3 The above 5 x 10 18 ato ms / cm 3 Less than 1 × 10 16 atoms / cm 3 above 2×10 18 atoms / cm 3 has a region that is less than. 【0122】 Also, in order to reduce the hydrogen concentration of the metal oxide 432, it is preferable to reduce the hydrogen concentration of the metal oxide 431 and the metal oxide 433. The metal oxides 431 and 433 are S In IMS, 1×10 16 atoms / cm 3 or more and 2×10 20 atoms / cm 3 or less, preferably 1×10 16 atoms / cm 3 or more and 5×10 19 atoms / c m 3 or less, more preferably 1×10 16 atoms / cm 3 or more and 1×10 19 atom s / cm 3 or less, even more preferably 1×10 16 atoms / cm 3 or more and 5×10 18 atoms / cm 3 or less, and has a region with a hydrogen concentration as described above. Also, in order to reduce the nitrogen concentration of the metal oxide 432, it is preferable to reduce the nitrogen concentration of the metal oxides 431 and 433. The metal oxides 431 and 433 are, in SIMS, 1×10 16 atoms / cm 3 or more and 5×10 19 atoms / cm 3 or less, preferably 1×10 16 atoms / cm 3 or more and 5×10 18 atoms / cm 3 or less, more preferably 1×10 16 atoms / cm 3 The above is 1 x 10 18 atoms / cm 3 More preferably, 1 x 10 16 atoms / cm 3 The above 5 x 10 17 atoms / cm 3 The following nitrogen concentrations and It has a domain. 【0123】 The metal oxides 431 to 433 are deposited by sputtering, CVD (Chemical Vapor Deposition). ical vapor deposition) method, MBE (Molecular Be am Epitaxy) method or PLD (Pulsed Laser Depositio) n) Using methods such as ALD (Atomic Layer Deposition) Just say it. 【0124】 It is preferable to perform the first heat treatment after forming the metal oxides 431 and 432. The heat treatment is performed at a temperature of 250°C to 650°C, preferably 450°C to 600°C, and more preferably The first heat treatment should be carried out at a temperature between 520°C and 570°C. The first heat treatment is performed in an inert gas atmosphere. Alternatively, the procedure shall be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The first heat treatment may be carried out under reduced pressure. Alternatively, the first heat treatment may be carried out in an inert gas atmosphere. After heat treatment, an oxidizing gas is added at a concentration of 10 ppm or more, or at a concentration of 1% or more, to replenish the oxygen that has been removed. The heat treatment may be carried out in an atmosphere containing 10% or more of the substance. The first heat treatment causes metal oxidation It is possible to enhance the crystallinity of substances 431 and 432, and to remove impurities such as hydrogen and water. It will become. 【0125】 FIG. 9 shows an example of a three-layer structure of the metal oxide 430, but is not limited thereto. For example, the metal oxide 430 can have a two-layer structure without the metal oxide 431 or the metal oxide 433. Alternatively, a single layer or a stack of the metal oxides exemplified as the metal oxide 4 31 to the metal oxide 433 may be provided at least at one position above, below, or in the layer of the metal oxide 430 to form an n-layer structure (n is an integer greater than 3). 【0126】 <Substrate> As the substrate 450, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), a resin substrate, etc. Further, examples of the semiconductor substrate include a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. Furthermore, there is a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, such as a SOI (Silicon On Insulator) substrate, etc. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. Or, there is a substrate having a metal nitride, a substrate having a metal oxide, etc. Furthermore, there is a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, etc. Or, a substrate provided with an element on these substrates may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a rectifier element, a switch element, a light-emitting element, a memory element, etc. 【0127】 ​​Furthermore, a flexible substrate may be used as the substrate 450. One method for creating a transistor is to fabricate a transistor on a non-flexible substrate, and then... Another method involves peeling it off and transferring it to a flexible substrate, substrate 450. In that case, the non-flexible It is preferable to provide a release layer between the substrate and the transistor. Furthermore, the substrate 450 may be made of woven fibers. A sheet, film, or foil containing the material may also be used. Furthermore, the substrate 450 has elasticity. It is also acceptable for the substrate 450 to return to its original shape when bending or pulling is stopped. It may have the property of not returning to its original shape, or it may have the property of not returning to its original shape. The thickness of the substrate 450 is, for example However, it is sufficient if it is between 5 μm and 700 μm, preferably between 10 μm and 500 μm. More preferably, the thickness is 15 μm or more and 300 μm or less. When the substrate 450 is thinned, the semiconductor The device can be made lighter. Also, by making the substrate 450 thinner, glass and other materials can be used. Even when bent or pulled, it may still have elasticity, or it may return to its original shape when the bending or pulling is stopped. It may have a quality. Therefore, when the semiconductor device on the substrate 450 is subjected to a fall or the like, It can mitigate shocks and other impacts. In other words, it can provide a robust semiconductor device. 【0128】 Flexible substrates applicable to substrate 450 include, for example, metal, alloy, resin, or glass, These are substrates made of fibers, etc. The lower the coefficient of thermal expansion of a flexible substrate, the less it is affected by environmental deformation. This is preferable as it is suppressed. The flexible substrate has, for example, a coefficient of thermal expansion of 1 × 10 -3 / K or less, 5 ×10 -5 / K or less, or 1 × 10 -5 A material with a temperature of / K or less should be used. Examples include polyester, polyolefin, polyamide (nylon, aramid, etc.), Polyimide, polycarbonate, acrylic, polytetrafluoroethylene (PTFE) There are such things. In particular, aramid has a low coefficient of thermal expansion, so it is used as a flexible substrate, substrate 450. It is suitable. 【0129】 <Undercoat insulating film> The insulating film 401 has the function of electrically separating the substrate 450 and the conductive film 414. 401 or the insulating film 402 is formed of an insulating film with a single-layer or multi-layer structure. Examples of materials used include aluminum oxide, magnesium oxide, silicon oxide, and nitridation. Silicon, silicon nitride, silicon nitride, gallium oxide, germanium oxide, gallium oxide Zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tarnish oxide Examples include tar. Also, as the insulating film 402, TEOS (Tetra-Ethyl-O (Urtho-Silicate), or silane, etc., are reacted with oxygen or nitrous oxide, etc. A silicon oxide with good step coverage properties formed in response may also be used. To improve the flatness of the upper surface, a planarization treatment using CMP or the like is performed after the deposition of the insulating film 402. You may go. 【0130】 In this specification, the term "oxidized nitride" refers to a compound in which the oxygen content is greater than the nitrogen content. Nitride oxides are compounds that contain more nitrogen than oxygen. 【0131】 The insulating film 404 preferably contains an oxide. In particular, an acid from which some oxygen is removed upon heating. It is preferable that the acid contains an ionized material. It is preferable to use an oxide. An oxide containing more oxygen than satisfactorily satisfying the stoichiometric composition. When heated, some of the oxygen in the film is removed. The oxygen removed from the insulating film 404 is a metal oxide. This is supplied to 430, making it possible to reduce oxygen deficiency in the metal oxide 430. This can suppress fluctuations in the electrical characteristics of transistors and improve their reliability. 【0132】 Oxide films containing more oxygen than satisfying the stoichiometric composition are, for example, TDS(Th In urinary desorption spectroscopy analysis, oxygen atoms were found to The amount of oxygen removed after conversion is 1.0 × 10⁻⁶ 18 atoms / cm 3 Preferably 3.0 ×10 20 atoms / cm 3 The above describes the oxide film. Note that during the above TDS analysis... The surface temperature of the film is between 100°C and 700°C, or between 100°C and 500°C. This is preferable. 【0133】 The insulating film 404 preferably contains an oxide that can supply oxygen to the metal oxide 430. It is preferable to use a material containing silicon oxide or silicon oxide nitride, for example. Alternatively, as insulating film 404, aluminum oxide, aluminum oxide nitride, gallium oxide Gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, oxide Metal oxides such as hafnium nitride may be used. The insulating film 404 contains an excess of oxygen. To achieve this, for example, the insulating film 404 can be deposited under an oxygen atmosphere. Alternatively, the insulating film can be deposited in an oxygen atmosphere. Oxygen may be introduced into the border film 404 to form a region containing an excess of oxygen, and both methods are possible. They can be combined. 【0134】 For example, the insulating film 404 after film formation contains oxygen (at least oxygen radicals, oxygen atoms, oxygen ions). A region containing an excess of oxygen is formed by introducing (containing any of the following). Method of introducing oxygen These include ion implantation, ion doping, plasma immersion ion implantation, and A rasma treatment or similar method can be used. For oxygen introduction treatment, an oxygen-containing gas can be used. This is possible. Examples of oxygen-containing gases include oxygen, nitrous oxide, nitrogen dioxide, and carbon dioxide. Carbon monoxide and the like can be used. In addition, in the oxygen introduction treatment, an oxygen-containing gas can be used. It may contain noble gases, or hydrogen, for example, carbon dioxide, hydrogen. It is also preferable to use a mixed gas of argon. Furthermore, to improve the flatness of the upper surface of the insulating film 404 Therefore, after depositing the insulating film 404, a planarization treatment using CMP or the like may be performed. 【0135】 The insulating film 403 is a passivation device that prevents the oxygen contained in the insulating film 404 from decreasing. It has the ability to conduct electricity. Specifically, the insulating film 403 allows oxygen contained in the insulating film 404 to conduct electricity. It prevents bonding with the metal contained in 414. The insulating film 403 is protected from oxygen, hydrogen, water, It has the function of blocking alkali metals, alkaline earth metals, etc. An insulating film 403 is provided. This allows for the diffusion of oxygen from the metal oxide 430 to the outside, and from the outside the metal oxide 430. It can prevent hydrogen, water, etc. from entering. The insulating film 403 is, for example, a nitride, nitride It can be formed from an insulator containing an oxide, oxide, or oxidnitride. This includes silicon nitride, silicon oxide nitride, aluminum nitride, aluminum oxide nitride, and oxide Aluminum, aluminum oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide Examples include yttrium oxide nitride, hafnium oxide, and hafnium oxide nitride. 【0136】 Transistor 400a controls the threshold voltage by injecting electrons into the charge trapping layer. This becomes possible. The charge trapping layer is preferably provided in the insulating film 402 or insulating film 403. For example, insulating film 403 can be made from hafnium oxide, aluminum oxide, tantalum oxide, and aluminum. By forming it with nium silicate or similar materials, it can function as a charge trapping layer. 【0137】 <Back gate electrode, gate electrode, source electrode, and drain electrode> Conductive films 411 to 414 and 421 to 424 are made of copper (Cu), tungsten, and Stainless steel (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (M) n), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (P) b) Tin (Sn), Iron (Fe), Cobalt (Co), Ruthenium (Ru), Platinum (Pt) iridium (Ir), strontium (Sr), and other low-resistance materials, either as elements, alloys, or It is preferable to have a single layer or a multilayer conductive film containing compounds that are the main components of these compounds. In particular, It is preferable to use high-melting-point materials such as tungsten or molybdenum that offer both heat resistance and conductivity. It is preferable to form it with a low-resistance conductive material such as aluminum or copper. Furthermore, when a Cu-Mn alloy is used, manganese oxide is formed at the interface with the oxygen-containing insulator. Manganese oxide is preferable because it has the function of suppressing the diffusion of Cu. 【0138】 Furthermore, conductive films 421 to 424 contain iridium oxide, ruthenium oxide, and strontium oxide. It is preferable to use conductive oxides containing noble metals, such as thiumrutenite. Electrolytic oxides do not remove oxygen from oxide semiconductors even when in contact with them, thus oxidizing... It is difficult to create oxygen vacancies in material semiconductors. 【0139】 <Low resistance area> Regions 441 and 442 are, for example, conductive films 421 and 423, and metal oxides 431 and 432. It is formed by the extraction of oxygen. The extraction of oxygen occurs more readily at higher temperatures. Yes. The manufacturing process for transistor 400a involves several heating steps, so the region Oxygen vacancies are formed at 441 and 442. Furthermore, heating causes hydrogen to form at the sites of these oxygen vacancies. As a result, the carrier concentration in regions 441 and 442 increases. 41 and 442 will have lower resistance. 【0140】 <Gate insulating film> The insulating film 406 preferably has an insulator with a high relative permittivity. For example, insulating film 406 This includes gallium oxide, hafnium oxide, aluminum, and oxides containing hafnium, Oxiditrides having silicon and hafnium, oxides having silicon and hafnium, Alternatively, it is preferable to form it with an oxidized nitride having silicon and hafnium. 【0141】 The insulating film 406 is the product of silicon oxide or silicon oxide nitride and an insulator with a high dielectric constant. It is preferable to have a layered structure. Silicon oxide and silicon oxide-nitride are thermally stable. Therefore, by combining it with an insulator with a high dielectric constant, a thermally stable and high dielectric constant multiplier can be achieved. It can be a layered structure. For example, aluminum oxide, gallium oxide, or hafnius oxide. By having the metal oxide 433 side, the components contained in silicon oxide or silicon oxide nitride are This can suppress the mixing of silicon with the metal oxide 432. 【0142】 For example, by having silicon oxide or silicon oxidiznitride on the metal oxide 433 side, oxidation Aluminum, gallium oxide, or hafnium oxide, and silicon oxide or silicon nitride. A trap center may form at the interface between the two. This trap center traps electrons If capturing the transistor can cause the threshold voltage to change in the positive direction There is. 【0143】 <Interlayer insulating film, protective insulating film> The insulating film 405 preferably has an insulator with a low relative permittivity. For example, insulating film 405 This includes silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, or resins. It is preferable to have. Alternatively, the insulating film 405 is silicon oxide or silicon oxide nitride, It is preferable to have a laminated structure of resin and silicon oxide. Because it is thermally stable, when combined with resin, it creates a thermally stable laminated structure with a low dielectric constant. It can be made into a structure. Examples of resins include polyester, polyolefin, and polyamide. Materials include mids (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic. ru. 【0144】 The insulating film 407 blocks oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. It has the function of preventing oxygen from the metal oxide 430 from being released to the outside. It prevents diffusion and the intrusion of hydrogen, water, etc., into the metal oxide 430 from the outside. The film 407 is formed of, for example, an insulator having a nitride, nitride oxide, oxide, or oxidized nitride. This is possible. The insulating material can be silicon nitride, silicon nitride oxide, aluminum nitride. Aluminum oxide, aluminum nitride, aluminum oxide, aluminum oxide nitride, gallium oxide Gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, oxide Examples include hafnium nitride. Aluminum oxide films contain impurities such as hydrogen, water, and oxygen. Because it has a high barrier effect that prevents the film from passing through to both, it is preferable to apply it to insulating film 407. . 【0145】 The insulating film 407 is deposited using an oxygen-containing plasma, such as by sputtering or CVD. This makes it possible to add oxygen to the sides and surfaces of the insulating films 405 and 406. Furthermore, after forming the insulating film 407, a second heat treatment is performed at some point. This is preferable. The second heat treatment causes the oxygen added to the insulating films 405 and 406 to be absorbed. It diffuses through the edge film, reaches the metal oxide 430, and reduces the oxygen deficiency of the metal oxide 430. This becomes possible. 【0146】 The insulating film 407 has the function of blocking oxygen, and oxygen does not diffuse upward from the insulating film 407. Similarly, insulating film 403 has the function of blocking oxygen, preventing oxygen from entering the insulating film. Prevents diffusion below 403. 【0147】 Furthermore, in the second heat treatment, the oxygen added to the insulating films 405 and 406 reaches the metal oxide 430. The process should be carried out at a temperature at which diffusion occurs. For example, refer to the description of the first heat treatment. Yes, it is possible. Alternatively, the second heat treatment is preferably performed at a lower temperature than the first heat treatment. The temperature difference between the heat treatment and the second heat treatment should be between 20°C and 150°C, preferably. The temperature is between 40°C and 100°C. This prevents excess oxygen from being released from the insulating film 404. This can suppress the effects of the second heat treatment, which is equivalent to the heat treatment applied during film formation of each layer. In cases where the process can be combined with heat, it may not be necessary. The compound 430 is supplied with oxygen from above and below by the deposition of the insulating film 407 and the second heat treatment. It becomes possible to supply it. Also, films containing indium oxide, such as In-M-Zn oxide. Oxygen may be added to insulating films 405 and 406 by forming an insulating film 407. 【0148】 Insulating film 408 contains aluminum oxide, aluminum nitride oxide, magnesium oxide, and oxide Silicon, silicon oxide nitride, silicon nitride, silicon nitride, gallium oxide, gallium oxide Lumanium, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, oxide An insulator containing one or more elements selected from hafnium, tantalum oxide, etc., can be used. Furthermore, the insulating film 408 may contain a resin that can be used in the insulating film 405, such as a polyimide resin. It can also be used. Furthermore, the insulating film 408 may be a laminate of the above materials. 【0149】 <<Example of transistor configuration 2>> The transistor 400a shown in Figure 8 omits the conductive film 414 and insulating films 402 and 403. This is also acceptable. An example of this case is shown in Figure 10. Figure 10A is a top view of transistor 400b. Figure 10B is a cross-sectional view of line A1-A2 in Figure 10A, and Figure 10C is a cross-sectional view of line A3-A4 in Figure 10A. This is a cross-section. 【0150】 <<Transistor Configuration Example 3>> In the transistor 400a shown in Figure 8, conductive films 421 and 423 are gate electrodes (conductive The film thickness in the portion overlapping with films 411 to 413 may be reduced. An example of this is shown in Figure 11. Figure 11A is a top view of transistor 400c. Figure 11B is a top view of A1-A2 of Figure 11A. These are cross-sectional views, and Figure 11C is a cross-sectional view taken along line A3-A4. 【0151】 As shown in Figure 11B, in transistor 400c, the conductive film 4 overlaps with the gate electrode. 21 is made into a thin film, and the conductive film 422 covers it. Similarly, the part that overlaps with the gate electrode A conductive film 423 is thinned, and a conductive film 424 covers it. By doing so, the distance between the gate electrode and the source electrode, or between the gate electrode and the drain electrode, This makes it possible to increase the distance between the gate electrode and the source and drain electrodes. This makes it possible to reduce the parasitic capacity that forms in between. As a result, high-speed operation is possible. It becomes possible to obtain a generator. 【0152】 <<Transistor Configuration Example 4>> Figure 12A is a top view of transistor 400d. Figure 12B is an open section of the A1-A2 line in Figure 12A. This is a top view, and Figure 12C is a cross-sectional view along line A3-A4. Transistor 400d is also a transistor Similar to the Ta400a, it is an s-channel transistor. Transistor 4 In 00d, an insulating film 409 is provided in contact with the side surface of the conductive film 412 that constitutes the gate electrode. The insulating film 409 and the conductive film 412 are covered by insulating film 407 and insulating film 408. The insulating film 409 functions as the sidewall insulating film of transistor 400d. Similar to transistor 400a, transistor 400d also has a gate electrode made of conductive film 411 or conductive film. The film 413 may be stacked. 【0153】 The insulating film 406 and the conductive film 412 are at least partially made of conductive film 414 and metal oxide 432 This overlaps with the side edge of the conductive film 412 in the channel length direction and the insulating film 406 in the channel length direction. The side edges are preferably roughly aligned. Here, the insulating film 406 is transistor 40 It functions as the gate insulating film of transistor 400d, and the conductive film 412 is connected to the gate electrode of transistor 400d. It functions in this way. 【0154】 The metal oxide 432 overlaps with the conductive film 412 via the metal oxide 433 and the insulating film 406. It has a region. The outer circumference of metal oxide 431 roughly coincides with the outer circumference of metal oxide 432, and the metal acid The outer circumference of oxide 433 is located outside the outer circumferences of metal oxides 431 and 432. Preferably, the outer circumference of metal oxide 433 is wider than the outer circumference of metal oxide 431. Although the shape is positioned on the side, the transistor shown in this embodiment is not limited to this. For example, the outer circumference of metal oxide 431 may be located outside the outer circumference of metal oxide 433. Furthermore, the side edges of metal oxide 431 and metal oxide 433 are roughly aligned. It can also be written as "form". 【0155】 Figure 12D shows a magnified view of a portion of Figure 12B. As shown in Figure 12D, the metal oxide 430 contains Regions 461a, 461b, 461c, 461d and 461e are formed. Region 4 Regions 61b to 461e have a higher dopant concentration and lower resistance compared to region 461a. Furthermore, regions 461b and 461c are located in regions 461d and 461e. Compared to that, the hydrogen concentration is higher and the resistance is lower. For example, region 461a is region A region with a concentration of 5% or less relative to the maximum concentration of the dopant in region 461b or region 461c, 2 The concentration range should be less than % or less than 1%. These terms can also be rephrased as 'ener,' 'acceptor,' 'impurity,' or 'element.' 【0156】 As shown in Figure 12D, in the metal oxide 430, region 461a is roughly the same as the conductive film 412. These are overlapping regions, and regions 461b, 461c, 461d, and 461e are, This region excludes region 461a. In regions 461b and 461c, metal oxides are present. The upper surface of 433 is in contact with the insulating film 407. In regions 461d and 461e, the metal The upper surface of the oxide 433 is in contact with the insulating film 409 or the insulating film 406. That is, as shown in Figure 12D. As shown, the boundary between region 461b and region 461d is the side edge of insulating film 407 and insulating film 409. This is the part that overlaps with the boundary. The same applies to the boundary between region 461c and region 461e. Here, parts of regions 461d and 461e overlap with the conductive film 412 of the metal oxide 432. It is preferable that it overlaps with a part of the region (channel formation region). For example, region 461d and The side edge of region 461e in the channel length direction is a distance d from the side edge of the conductive film 412. It is preferable that it be located inside the conductive film 412. In this case, the film thickness H of the insulating film 406 406 And distance d is 0.25H 406 <d<H 406 It is preferable that the following conditions be met. 【0157】 Thus, in a portion of the region overlapping with the conductive film 412 of the metal oxide 430, region 461d and region Region 461e is formed. This creates a channel formation region and a resistor for transistor 400d. Regions 461d and 461e are adjacent, and regions 461d and 461e are adjacent to each other. Since a high-resistance offset region is not formed between transistor 461a and transistor 400d, The on current of region 461d and region 461e can be increased. The lateral end in the longitudinal direction is formed to satisfy the above range, so that region 461d and region 4 The 61e is formed too deeply within the channel formation region, resulting in a constant conductive state. This can also be prevented. 【0158】 Regions 461b, 461c, 461d, and 461e are areas where ion implantation and other methods are used. It is formed by on-doping. Therefore, as shown in Figure 12D, region 461d The boundary between region 461a is deep from the upper surface of metal oxide 433 towards the lower surface of metal oxide 431. As it gets closer, it may approach the boundary between region 461d and region 461b. The distance d is the region 46 closest to the innermost part of the conductive film 412 in the direction of the dashed line A1-A2. The boundary between 1d and region 461a, and the A1 side of the conductive film 412 in the direction of the dashed line A1-A2. This is the distance from the side edge. Similarly, the boundary between region 461e and region 461a is the metal oxide 4 As the depth increases from the upper surface of 33 toward the lower surface of the metal oxide 431, region 461e and region It may approach the boundary of 461c. The distance d at this time is in the direction of the dashed line A1-A2. And the boundary between region 461e and region 461a, which is closest to the innermost part of the conductive film 412, and the conductive film 41 This is the distance from the side edge on the A2 side in the direction of the dashed line A1-A2 in 2. 【0159】 In this case, for example, regions 461d and 461e formed in the metal oxide 431 are derived In some cases, the film may not be formed in the region overlapping with the film 412. In this case, the metal oxide 431 or gold At least a portion of the regions 461d and 461e formed in the group oxide 432 is a conductive film 4 It is preferable that it be formed in the region that overlaps with 12. 【0160】 Furthermore, the boundaries between metal oxide 431, metal oxide 432, and metal oxide 433 and the insulating film 407 It is preferable that low-resistance regions 451 and 452 are formed near the surface. Region 451 and the low-resistance region 452 contain at least one of the elements included in the insulating film 407. Parts of the low-resistance region 451 and the low-resistance region 452 are made of the conductive film 412 of the metal oxide 432. It is preferable that the region overlapping with the channel-forming region is roughly adjacent to it, or that it overlaps with a part of that region. It's nice. 【0161】 Furthermore, because the metal oxide 433 has a large area in contact with the insulating film 407, the low-resistance region 451 and The low resistance region 452 is easily formed in the metal oxide 433. The resistance region 451 and the low resistance region 452 are the low resistance region 451 and low resistance of the metal oxide 433. From regions other than region 452 (for example, regions overlapping with the conductive film 412 of metal oxide 433) Furthermore, the concentration of elements contained in the insulating film 407 is high. 【0162】 A low-resistance region 451 is formed in region 461b, and a low-resistance region 452 is formed in region 461c. The ideal structure of metal oxide 430 is, for example, the region where the concentration of the additive element is highest. The low-resistance regions are 451 and 452, and the next highest concentration regions are region 461b and region 461. This region does not include the low-resistance regions 451 and 452 of c, and region 461 is the region with the lowest concentration. The condition is a. The added element is dopant to form regions 461b and 461c. This includes elements added from the insulating film 407 to the low-resistance regions 451 and 452. 【0163】 In addition, transistor 400d is configured to form low-resistance regions 451 and 452. The transistors shown in this embodiment are not limited to those shown. For example, region 461b and If the resistance of region 461c is sufficiently low, low-resistance regions 451 and 452 are formed. It's not necessary. 【0164】 <<Transistor Configuration Example 5>> Figure 13 shows an example of a transistor configuration. Figure 13A shows the top view of transistor 400e. This is a diagram. Figure 13B is a cross-sectional view of Figure 13A along the line y1-y2, and Figure 13C is a cross-sectional view of Figure 13A along the line x1-x2. This is a cross-sectional view, and Figure 13D is a cross-sectional view taken along the line x3-x4. 【0165】 Like the transistor 400a, the transistor 400e is a transistor with an s-channel structure. It is a transistor. The transistor 400e is provided with conductive films 471 and 472. The conductive films 471 and 472 function as either a source electrode or a drain electrode, respectively. Similar to transistor 400a, the gate electrode is made of a stack of conductive films 411 to 413. That's fine. 【0166】 Metal oxide 430 is compounded in the order of metal oxide 431, metal oxide 432, and metal oxide 433. It has a layered portion. The conductive films 471 and 472 are metal oxide 431 and metal oxide 4 It is provided on a laminate consisting of 32. Metal oxide 433 is metal oxide 431, 432 , and are formed to cover conductive films 471, 472. The insulating film 406 is a metal oxide 4 33 is covered. Here, the metal oxide 433 and the insulating film 406 use the same mask. It is being checked. 【0167】 The conductive films 471 and 472 form a laminate of metal oxide 431 and metal oxide 432. It is made from a hard mask used in [the process]. Therefore, conductive films 471 and 472 are made of gold It does not have a region in contact with the side surfaces of the genus oxide 431 and the metal oxide 432. For example, the following Through such a process, metal oxides 431 and 432 and conductive films 471 and 472 can be produced. Yes, it is possible. It forms a two-layer oxide semiconductor film that constitutes metal oxides 431 and 432. A single-layer or multi-layer conductive film is formed on a semiconductor film. This conductive film is etched to harden A hard mask is formed. Using this hard mask, the two layers of oxide semiconductor film are etched. A layer of metal oxide 431 and metal oxide 432 is formed. Next, the hard mask is etched. Then, conductive films 471 and 472 are formed. 【0168】 [Embodiment 4] In this embodiment, the device structure is characterized by stacking Si transistors and OS transistors. Next, we will describe the electronic device. Here, as an example, we will describe the device of the electronic device of Embodiment 1. An example of a S structure is shown. 【0169】 Figures 14A and 14B are cross-sectional views showing the device structure of an electronic device, and typically represent circuit 13 (Transistors M2, M4, and capacitance element C1 are shown.) Figure 14A shows the electronic device 100 Figure 14B is a cross-sectional view of the transistor in the channel length direction, and Figure 14B shows the transistor This is a cross-sectional view in the channel width direction. Figures 14A and 14B show the devices of the electronic device 100. This shows the structure, and the orientation of the transistors constituting the electronic device 100 is as shown in the figure. There may be cases where this is not the case. 【0170】 The electronic device 100 has layers 781 to 789 in order from bottom to top. Layer 781 is a substrate 700 And, a transistor M2 formed on the substrate 700, an element isolation layer 701, and a plug 710, It has multiple plugs such as 711. Layer 781 is a Si transistor such as transistor M2. This is the element layer on which the element layer is formed. 【0171】 The substrate 700 can be a single-crystal semiconductor substrate made of silicon or silicon carbide, or a polycrystalline semiconductor substrate. The substrate can be a compound semiconductor substrate made of silicon germanium, or an SOI substrate. This can be done. Also, the substrate 700 can be, for example, a glass substrate, a quartz substrate, or a plastic substrate. Metal substrates, flexible substrates, laminated films, paper containing fibrous materials, or base material films You may also use materials such as M. Alternatively, you can form a semiconductor element using one substrate, and then use another substrate. A semiconductor element may be placed on the substrate 700. Here, as an example, a single crystal silicon wafer is placed on the substrate 700. An example using EHA is shown. 【0172】 Figure 15 shows an example of the configuration of transistor M2. Figure 15A shows the channel length of transistor M2. Figure 15B shows a cross-sectional view in the direction of the channel width of transistor M2. Transistor M2 has a channel formation region 1793 provided in well 1792 and low The high-concentration impurity region 1794 and the high-concentration impurity region 1795 (these together are simply called the impurity region) (also called the impurity region), a conductive region 1796 provided in contact with the impurity region, and channel formation A gate insulating film 1797 provided on region 1793, and provided on gate insulating film 1797 A gate electrode 1790 and a side wall insulating layer 1798 provided on the side of the gate electrode 1790. It has a side wall insulating layer 1799. The conductive region 1796 is made of metal silicide, etc. You may use it. 【0173】 The channel formation region 1793 of transistor M2 has a convex shape, and along its side and top surface... A gate insulating film 1797 and a gate electrode 1790 are provided. Transistors with this structure are called FIN type transistors. Here, substrate 700 The example shows how to process a part of the substrate to form a convex portion, but it also shows how to process an SOI substrate to create a convex shape. A semiconductor layer may be formed. 【0174】 Note that transistor M2 is not limited to a FIN-type transistor. For example, Figure 15C, A planar transistor like the one shown in Figure 15D may also be used. Figure 15C shows transistor M. Figure 15D is a cross-sectional view of transistor M2 in the channel length direction, and Figure 15D is a cross-sectional view of transistor M2 in the channel width direction. This is a view drawing. 【0175】 Layer 782 has multiple wirings such as wiring 730, 731, etc. Layer 783 has plug 712 It has multiple plugs such as 713 and multiple wires (not shown). 【0176】 Layer 784 consists of insulating film 702 to insulating film 705, transistor M4, and plugs 714 and 7 It has multiple plugs such as 15. Layer 784 has OS transistors such as transistor M4. This is the element layer where the transistor is formed. Here, transistor M4 is transistor 400c It has a device structure similar to (Figure 11). 【0177】 Layer 785 has multiple wires such as wires 732, 733, etc. Layer 786 has plug 716 It has multiple plugs and multiple wires (not shown). Layer 787 has wiring 734 It has multiple wirings. Layer 788 has multiple capacitive elements C1 and plugs such as plug 717. It has a lag. Layer 788 is the element layer on which the capacitive element C1 of circuit 13 is formed. Capacitive element C1 has electrodes 751, 752 and an insulating film 753. Layer 789 has wiring 735, etc. It has multiple wires. 【0178】 Preferably, the insulating films 704 and 705 have a blocking effect against hydrogen, water, etc. Water, hydrogen, etc. are one of the factors that generate carriers in oxide semiconductors, therefore hydrogen, water, etc. By providing a blocking layer, the reliability of transistor M4 is improved. This becomes possible. Insulators that have a blocking effect against hydrogen, water, etc. include, for example, acid Aluminum oxide, aluminum nitride oxide, gallium oxide, gallium nitride oxide, yt oxide Yttrium oxide, yttrium nitride, hafnium oxide, hafnium nitride, yttria stable Examples include zirconia (YSZ). 【0179】 Wiring 730 to 735 and plugs 710 to 717 are made of copper (Cu), Sten (W), Molybdenum (Mo), Gold (Au), Aluminum (Al), Manganese (Mn), Titanium (Ti), Tantalum (Ta), Nickel (Ni), Chromium (Cr), Lead A single element consisting of low-resistance materials (Pb), tin (Sn), iron (Fe), and cobalt (Co), if It is preferable to have a single layer or a multilayer of conductive film containing an alloy or a compound mainly composed of these. In particular, high-melting-point materials such as tungsten and molybdenum that offer both heat resistance and conductivity. It is preferable to use it. Furthermore, it is preferable to form it with a low-resistance conductive material such as aluminum or copper. This is preferable. Furthermore, when a Cu-Mn alloy is used, mann oxide forms at the interface with the oxygen-containing insulator. It is preferable because it forms cancer cells, and manganese oxide has the function of suppressing the diffusion of Cu. 【0180】 In Figure 14, the areas where no symbols or hatching patterns are provided are composed of an insulator. The above insulators include aluminum oxide, aluminum nitride, and magnesium oxide. Um, silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide, galvanic oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neophosphate An insulator containing one or more materials selected from dymium, hafnium oxide, tantalum oxide, etc. is used. It can be present in this region. In addition, polyimide resin, polyamide resin, acrylic resin Resins such as fats, siloxane resins, epoxy resins, and phenolic resins can also be used. 【0181】 [Embodiment 5] This embodiment describes the structure of an oxide semiconductor. The oxide semiconductor is a single-crystal oxide They can be divided into semiconductors and other non-single-crystal oxide semiconductors. Non-single-crystal oxide semiconductors include , CAAC-OS(c-axis-aligned crystalline oxide e semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocry stalline oxide semiconductor, pseudo-amorphous oxide semiconductor body(a-like OS:amorphous-like oxide semicon Examples include ductors and amorphous oxide semiconductors. From another perspective, oxide semiconductors are amorphous. They can be divided into crystalline oxide semiconductors and other crystalline oxide semiconductors. These include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS. ru. 【0182】 Generally, amorphous structures are isotropic and do not have heterogeneous structures; they are metastable states with a specific arrangement of atoms. The position is not fixed, the connection angle is flexible, and it has short-range order but not long-range order. It is said that there are none. In other words, stable oxide semiconductors are completely amorphous (complete (For example) It cannot be called an oxide semiconductor. Also, it is not isotropic (for example) Oxide semiconductors (which have a periodic structure in a minute region) are different from perfectly amorphous oxide semiconductors. It cannot be called. On the other hand, a-like OS is not isotropic but has porosity (also called voids). It has an unstable structure. In terms of instability, a-like OS is amorphous in terms of physical properties. It is similar to a phosphate oxide semiconductor. 【0183】 <caac-os> CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline portions (also called pellets). It is a type of conductor. 【0184】 (XRD) CAAC-OS can be analyzed by X-ray diffraction (XRD). Let's explain the case of analysis. For example, InGaZnO4, which is classified as space group R-3m Structural analysis of crystalline CAAC-OS is performed using the out-of-plane method. Then, a peak appears near the diffraction angle (2θ) of 31°. This peak is the result of InGaZnO4 Since it is attributed to the (009) plane of the crystal, CAAC-OS has c-axis orientation. The c-axis is approximately perpendicular to the surface (also called the surface to which the CAAC-OS film is formed) or the upper surface. It can be confirmed that it is facing in that direction. In addition to the peak where 2θ is near 31°, there is also a peak where 2θ is 3 Peaks may also appear near 6°. Peaks near 36° of 2θ are associated with the space group Fd-3. This is due to the crystal structure classified as m. Therefore, CAAC-OS does not exhibit this peak. It is preferable. 【0185】 On the other hand, in CAAC-OS, X-rays are incident from a direction parallel to the surface being formed. Structural analysis using the ne method reveals a peak near 2θ = 56°. This peak corresponds to I It is attributed to the (110) plane of the nGaZnO4 crystal. Then, 2θ is fixed near 56°. The analysis (φ-scan) is performed while rotating the sample around the normal vector of the sample surface as the axis (φ-axis). Even when performed, no clear peak is observed. For single crystal InGaZnO4, 2θ is set to approximately 56°. When fixed nearby and scanned with φ, six P-shaped lines are attributed to the crystal plane equivalent to the (110) plane. A 'ku' is observed. Therefore, structural analysis using XRD shows that CAAC-OS has an a-axis and It can be confirmed that the orientation of the b-axis is irregular. 【0186】 (Electron diffraction) For example, in the case of CAAC-OS having an InGaZnO4 crystal, the shape of CAAC-OS When an electron beam with a probe diameter of 300 nm is incident parallel to the surface, the diffraction pattern (limited field of view) is observed. Also called an electron diffraction pattern.) This diffraction pattern may appear. The nO4 crystal contains spots originating from the (009) plane. Therefore, electron diffraction However, the pellets contained in CAAC-OS have c-axis orientation, and the c-axis is on the surface to be formed or above It can be seen that it is oriented in a direction approximately perpendicular to the surface. A probe with a diameter of 300 nm is perpendicular to the sample surface. When an electron beam is incident, a ring-shaped diffraction pattern appears. Therefore, the probe diameter is 3 Electron diffraction using an electron beam of 00 nm also reveals the a-axis of the crystalline portion contained in CAAC-OS. Furthermore, it can be confirmed that the b-axis does not have orientation. 【0187】 (High resolution TEM image) Transmission Electron Microscope (TEM) A composite analysis image (TE) of the bright-field image and diffraction pattern of CAAC-OS is obtained using the scope. Also called the M image.) When observed, multiple crystalline regions can be identified. On the other hand, high resolution Even in TEM images, the boundaries between crystalline parts, i.e., grain boundaries (also called grain boundaries), are visible. ) may not be clearly identifiable. Therefore, CAAC-OS is used to identify grain boundaries. It can be said that a decrease in electron mobility caused by this is less likely to occur. For observation of high-resolution TEM images, sphere Spherical Aberration Corrector function It is preferable to use this. Here, a high-resolution TEM image using spherical aberration correction function is obtained from Cs This is called a corrected high-resolution TEM image. 【0188】 High-resolution TEM images of the cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface revealed that The crystalline region, where metal atoms are arranged in layers, can be observed. Its size is 1n. It has been confirmed that there are crystalline regions larger than m and crystalline regions larger than 3 nm. Therefore, crystal The part can also be called a nanocrystal (nc). Also, CAAC -OS has CANC (C-Axis Aligned nanocrystals) It can also be called an oxide semiconductor. The crystalline part is the surface or top surface of CAAC-OS. It reflects the uneven surface and is parallel to the surface or top surface of the CAAC-OS that is being formed. 【0189】 A Cs-corrected high-resolution TEM image of the CAAC-OS plane observed from a direction approximately perpendicular to the sample surface. Image processing confirms that the crystal portion has a hexagonal shape. The shape is not necessarily a regular hexagon, and is often a non-regular hexagon. The image processing method is as follows: It is as follows: 【0190】 An FFT image is obtained by performing a Fast Fourier (FFT) transform on a Cs-corrected high-resolution TEM image. In the acquired FFT image, the origin is referenced to 2.8 nm. -1 from 5.0nm -1 During A mask is applied to leave a certain range. The masked FFT image is then subjected to an inverse fast Fourier transform (IFF). T) Process the image (FFT filtered image) to obtain the image. The FFT filtered image is Since this image is an image obtained by extracting the periodic component from a Cs-corrected high-resolution TEM image, it does not show the grid arrangement. ru. 【0191】 The acquired FFT filtered image does not show any clear grain boundaries. The presence of angular crystal regions is due to the suppression of grain boundary formation by distorting the lattice arrangement. This is because the atomic arrangement is not dense in the ab-plane direction. For example, the substitution of metal elements changes the bond distance between atoms, resulting in CAAC. -This is thought to be because the OS can tolerate distortion. 【0192】 As described above, CAAC-OS has c-axis orientation and multiple properties in the ab-plane direction. A number of crystalline parts (nanocrystals) are linked together, resulting in a distorted crystalline structure. Therefore, CAA C-OS, CAA crystal(c-axis-aligned ab-pla It can also be called an oxide semiconductor having an ne-anchored crystal. . 【0193】 CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors depends on the presence of impurities. CAAC-OS may decrease in quality due to impurities and defects (acids). It can be described as an oxide semiconductor with few elementary defects (such as elementary defects). 【0194】 Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. There are elements, etc. For example, silicon and other metal elements that make up oxide semiconductors have more oxygen than metal elements. Elements with strong bonding forces disrupt the atomic arrangement of oxide semiconductors by removing oxygen from them. This can be a factor that reduces crystallinity. Also, heavy metals such as iron and nickel, argon, and carbon dioxide can cause this. Because elements have a large atomic radius (or molecular radius), they disrupt the atomic arrangement of oxide semiconductors, causing crystallization. This can be a factor that reduces sexual performance. 【0195】 If oxide semiconductors contain impurities or defects, their properties may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps, or carriers It can be a source of generation. For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, it may act as a carrier source by capturing hydrogen. 【0196】 CAAC-OS, with its low impurity and oxygen vacancy rate, is an oxide semiconductor with a low carrier density. Specifically, 8 x 10 11 pieces / cm 3 Less than 1 × 10 11 / cm 3 Less than, More preferably 1 × 10 10 pieces / cm 3 It is less than 1 × 10 -9 pieces / cm 3 The above It can be made into a rear-density oxide semiconductor. Such an oxide semiconductor can be made into a high-purity intrinsic or This is essentially a high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and is defective. It has a low depression density. In other words, it can be said to be an oxide semiconductor with stable properties. 【0197】 <nc-os> (XRD) For example, when structural analysis is performed on nc-OS using the out-of-plane method, the orientation is No peaks indicating orientation appear. That is, nc-OS crystals do not have orientation. For example, In A thin layer of nc-OS containing GaZnO4 crystals was prepared, and a region with a thickness of 34 nm was subjected to a shaping process. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface, a ring-shaped diffraction pattern is observed. It is observed. Also, when an electron beam with a probe diameter of 1 nm is incident on the same sample, a ring shape is observed. Multiple spots are observed within the region. Therefore, nc-OS has a probe diameter of 50n Order is not observed when an electron beam of m is incident, but when an electron beam with a probe diameter of 1 nm is incident... Order can be confirmed by injecting it. 【0198】 Furthermore, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, In some cases, an electron diffraction pattern may be observed in which the spots are arranged in a roughly regular hexagonal shape. In the range of less than 10 nm in thickness, nc-OS has a highly ordered region, i.e., a crystalline structure. It can be seen that the crystals are oriented in various directions, so a regular electron diffraction pattern is observed. There are also regions where the phenomenon is not observed. 【0199】 (High resolution TEM image) In the Cs-corrected high-resolution TEM image of the cross-section of nc-OS, the crystalline region can be observed. This allows us to identify regions where a clear crystalline structure cannot be observed. nc-OS The crystalline parts contained within are between 1 nm and 10 nm in size, and especially between 1 nm and 3 nm. The size is often as shown below. Note that the size of the crystal portion is greater than 10 nm and less than 100 nm. The oxide semiconductor shown below is a microcrystalline oxide semiconductor. It is sometimes called ide semiconductor. In high-resolution TEM images, nc -In some cases, the grain boundaries of the OS crystal may not be clearly visible. Note that the nanocrystals are CAAC-OS. It is possible that the crystalline part of nc-OS has the same origin as the crystalline part of nc-OS. It is sometimes called a "tt." 【0200】 Thus, nc-OS is suitable for minute regions (for example, regions between 1 nm and 10 nm, particularly The atomic arrangement has periodicity in the region between 1 nm and 3 nm. Furthermore, nc-OS is Furthermore, no regularity is observed in the crystal orientation between different crystalline regions. Therefore, orientation is observed throughout the entire film. No. Therefore, depending on the analytical method, nc-OS may be a-like OS or amorphous acid. It can sometimes be indistinguishable from ionized semiconductors. The crystal orientation is regular between the crystalline parts (nanocrystals). Therefore, nc-OS is RANC (Random Aligned nanoc Oxide semiconductor having rystals, or NANC (Non-Aligned Na It can also be called an oxide semiconductor that contains nocrystals. 【0201】 The structure of nc-OS is more regular than that of amorphous oxide semiconductors. Therefore, nc-OS is It has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc- Since OS does not show any regularity in crystal orientation between different crystal regions, nc-OS is CAAC-O Compared to S, it has a higher defect level density. 【0202】 <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. It is a conductor. For example, the structural regularity of a-like OS is lower than that of nc-OS, Higher than amorphous oxide semiconductors. a-like OSs include nc-OS and CAAC-OS. In comparison, it has an unstable structure. Furthermore, a-like OS is different from nc-OS and CAAC. -It has a lower density compared to an OS. This is because a-like OSs have porous (low-density regions). This is the case. The porosity can be confirmed by high-resolution cross-sectional TEM images. 【0203】 The density of a-like OS is between 78.6% and 92.3% of the density of a single crystal of the same composition. The density of nc-OS and CAAC-OS is 92 times that of a single crystal of the same composition. It is between 0.3% and less than 100%. Oxide semiconductors whose density is less than 78% of the density of a single crystal are Furthermore, forming the film itself is difficult. 【0204】 For example, the density of a single crystal InGaZnO4 with a rhombohedral structure is 6.357 g / cm³. 3 in Yes, it exists. Therefore, in the case of an oxide semiconductor that satisfies In:Ga:Zn=1:1:1 [atomic ratio] The density of a-like OS is 5.0 g / cm³. 3 More than 5.9g / cm 3 Less than nc -The density of OS and CAAC-OS is 5.9 g / cm³ 3 More than 6.3g / cm 3 Less than be. 【0205】 If single crystals with the same composition do not exist, single crystals with different compositions can be combined in any proportion. By doing so, the density equivalent to a single crystal at the desired composition can be estimated. Example For example, taking into account the ratio of single crystals with different compositions, the weighted average density of these single crystals The average should be calculated. Furthermore, the density should be estimated by combining as few types of single crystals as possible. It is preferable to do so. 【0206】 As described above, oxide semiconductors can take on various structures, each possessing various properties. For example... For example, oxide semiconductor films used in semiconductor devices such as OS transistors are, A single layer film made of AC-OS, nc-OS, a-like OS, or amorphous oxide semiconductor Alternatively, it may be a multilayer film composed of oxide semiconductors with different structures. 【0207】 The following are matters relating to this specification, etc. In this specification, etc., "Part 1", "Part 2", Ordinal numbers such as "the third" are sometimes used to indicate order. Or, confusion of constituent elements. It may be used to avoid this, in which case the use of ordinal numbers limits the number of constituent elements. It does not mean that it is a fixed order, nor does it limit the order. Also, for example, "1st" can be changed to "2nd" or By substituting "third," one embodiment of the present invention can be described. 【0208】 In this specification, terms indicating placement, such as "above" and "below," refer to the positional relationship between components. In some cases, diagrams are used for convenience when explaining things. Also, the position of the components. The relationships change as appropriate depending on the direction in which each component is described. Therefore, they are explained in the specification. The words used are not limited to those already mentioned, and can be appropriately rephrased depending on the situation. 【0209】 In this specification, the terms "membrane" and "layer" may be used interchangeably, or Depending on the situation, they can be interchanged. For example, the term "conductive layer" In some cases, the term "conductive film" can be changed. In some cases, it may be possible to change the term to "insulating layer." 【0210】 Voltage is the potential difference between a given potential and a reference potential (for example, ground potential or source potential). It is often shown. Therefore, it is possible to rephrase voltage as electric potential. Note that electric potential is phase They are opposites. Therefore, even if it is written as ground potential (GND), it does not necessarily mean 0V. Sometimes it has no taste. 【0211】 In drawings, size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Note that the drawing schematically represents an ideal example. This is an example, and is not limited to the shapes or values ​​shown in the drawings. For example, noise-induced signals Variations in the number, voltage, or current, or timing differences in the signal, voltage, or This can include variations in current, etc. 【0212】 In this specification, "parallel" means that two straight lines are positioned at an angle of -10° or more and 10° or less. This refers to a state in which it is in a certain condition. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "abbreviated "Parallel" refers to a state where two straight lines are positioned at an angle between -30° and 30°. Furthermore, "perpendicular" refers to a state where two straight lines are positioned at an angle between 80° and 100°. This refers to the case where the angle is between 85° and 95°. Furthermore, "approximately perpendicular" means This refers to a state where two straight lines are positioned at an angle between 60° and 120°. 【0213】 Furthermore, in this specification and other documents, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal crystal system. . [Explanation of symbols] 【0214】 Circuits 10, 11, and 13 30-35 memory cells 100―102 Electronic equipment 111 Artificial Neural Arrays (ANA) 112-line decoder 113-row decoder 114 Input Circuit 115 Output Circuit 116 Analog signal processing circuit 130 memory 131 memory cell array 132-line decoder 133-row decoder 140 Wiring Switch Array 141 Wiring switch 144-146 Wiring < / ana>

Claims

[Claim 1] A capacitive element in which one electrode is electrically connected to a node and the other electrode is electrically connected to a wire, The system comprises a plurality of circuits, each having a transistor to which a signal corresponding to a weight value is input, either to the source or the drain, and the other to which the source or drain is electrically connected to the node. The transistor has a channel formation region in the oxide semiconductor layer, An arithmetic circuit receives an input value, which is an analog voltage signal, from the wiring, and outputs a calculation result based on the input value received from the wiring and the potential held at the node, It has a first insulating layer, a second insulating layer, and a conductive layer. The first insulating layer has a region located above the oxide semiconductor layer and is provided with an opening that overlaps with the oxide semiconductor layer. The second insulating layer has a region located inside the opening and overlaps with the oxide semiconductor layer. The conductive layer has a region located inside the opening and overlaps with the oxide semiconductor layer via the second insulating layer. The conductive layer functions as the gate electrode of the transistor in the arithmetic circuit. [Claim 2] A capacitive element in which one electrode is electrically connected to a node and the other electrode is electrically connected to a wire, A signal corresponding to a weight value is input to either the source or the drain of a first transistor, and the other source or drain is electrically connected to the node. The circuit comprises a second transistor whose gate is electrically connected to the node, and a plurality of other circuits. The first transistor has a channel formation region in the oxide semiconductor layer, The second transistor has silicon in the channel formation region, An arithmetic circuit receives an input value, which is an analog voltage signal, from the wiring, and outputs a calculation result based on the input value received from the wiring and the potential held at the node from the source or drain of the second transistor, It has a first insulating layer, a second insulating layer, and a conductive layer. The first insulating layer has a region located above the oxide semiconductor layer and is provided with an opening that overlaps with the oxide semiconductor layer. The second insulating layer has a region located inside the opening and overlaps with the oxide semiconductor layer. The conductive layer has a region located inside the opening and overlaps with the oxide semiconductor layer via the second insulating layer. The conductive layer functions as the gate electrode of the first transistor in the arithmetic circuit. [Claim 3] In claim 1 or claim 2, The aforementioned oxide semiconductor layer contains indium, and is part of an arithmetic circuit.

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