Memory power consumption determination method and apparatus, storage medium, and electronic device

Abstract

This disclosure relates to a method, apparatus, computer-readable storage medium, and electronic device for determining memory power consumption, and pertains to the field of integrated circuit technology. The method for determining memory power consumption includes: receiving a memory control command; controlling an analog memory to enter different operating stages according to the memory control command; acquiring the original current variation curves of the analog memory in different operating stages; determining a target time period corresponding to a target operating stage according to the timing of the memory control command; extracting a stage current variation curve corresponding to the target operating stage from the original current variation curves according to the target time period to obtain a target current variation curve; selecting target performance parameters from a memory performance parameter table according to the target operating stage; and determining the memory power consumption based on the target performance parameters and the target current variation curve. This disclosure provides a method for determining memory power consumption.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a method for determining memory power consumption, a device for determining memory power consumption, a computer-readable storage medium, and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers. Due to its advantages such as simple structure, high density, low power consumption, and low price, it has been widely used in the computer field and the electronics industry.

[0003] Memory power consumption plays a crucial role in system performance. Excessive memory power consumption may lead to system failure. Therefore, determining memory power consumption for system failure analysis is a necessary means to ensure the normal operation of the system.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a method, apparatus, computer-readable storage medium, and electronic device for determining memory power consumption.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0007] According to a first aspect of this disclosure, a method for determining memory power consumption is provided. The method includes: receiving a memory control command; controlling an analog memory to enter different operating stages according to the memory control command; acquiring original current variation curves of the analog memory in different operating stages; determining a target time period corresponding to a target operating stage according to the timing of the memory control command; extracting a stage current variation curve corresponding to the target operating stage from the original current variation curves according to the target time period to obtain a target current variation curve; selecting a target performance parameter from a memory performance parameter table according to the target operating stage; and determining the memory power consumption according to the target performance parameter and the target current variation curve.

[0008] According to a second aspect of this disclosure, a memory power consumption determination apparatus is provided. In an exemplary embodiment of this disclosure, the apparatus includes: a memory simulation module, configured to receive a memory control command and control a simulated memory to enter different operating stages according to the memory control command; a raw current acquisition module, configured to acquire raw current variation curves of the simulated memory in different operating stages; a target time period determination module, configured to determine a target time period corresponding to a target operating stage according to the timing of the memory control command; a target current determination module, configured to extract a stage current variation curve corresponding to the target operating stage from the raw current variation curves according to the target time period to obtain a target current variation curve; a target parameter determination module, configured to select a target performance parameter from a memory performance parameter table according to the target operating stage; and a power consumption determination module, configured to determine the memory power consumption according to the target performance parameter and the target current variation curve.

[0009] According to a third aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the memory power consumption determination method described above.

[0010] According to a fourth aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the memory power consumption determination method described above by executing the executable instructions.

[0011] The technical solution provided in this disclosure may include the following beneficial effects:

[0012] In the exemplary embodiments of this disclosure, on the one hand, by controlling the analog memory to enter different working stages, the original current change curves of the analog memory in different working stages can be easily obtained as the original current change curves of the memory for subsequent power consumption determination; on the other hand, after determining the target working stage, the stage current change curve corresponding to the target working stage can be extracted according to the corresponding target time period. Based on the stage current change curve, the target current change curve can be obtained. Finally, by combining the target current change curve and the target performance parameters, the power consumption of the memory can be determined. The determined power consumption of the memory can be used as the actual power consumption of the memory for memory performance analysis, and can also provide a basis for system failure analysis.

[0013] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0015] Figure 1 The illustration schematically shows a structural diagram of a storage cell according to an exemplary embodiment of the present disclosure;

[0016] Figure 2 The schematic diagram illustrates a structural schematic of a memory peripheral circuit according to an exemplary embodiment of the present disclosure;

[0017] Figure 3 The illustration schematically shows a memory block in a memory according to an exemplary embodiment of the present disclosure;

[0018] Figure 4 A flowchart illustrating a method for determining memory power consumption according to an exemplary embodiment of the present disclosure is shown schematically.

[0019] Figure 5 The illustration schematically shows a stage current variation curve data processing diagram according to an exemplary embodiment of the present disclosure;

[0020] Figure 6 A block diagram schematically illustrates a memory power consumption determination apparatus according to an exemplary embodiment of the present disclosure;

[0021] Figure 7 The illustration schematically shows a module diagram of an electronic device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0022] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0023] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0024] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0025] Semiconductor memories are used in computers, servers, handheld devices such as mobile phones, printers, and many other electronic devices and applications. A semiconductor memory comprises multiple memory cells in a memory array, each memory cell storing at least one bit of information. DRAM is an example of such a semiconductor memory. This solution is preferably used in DRAM. Therefore, the following description of embodiments is made with reference to DRAM as a non-limiting example.

[0026] In DRAM integrated circuit devices, memory cell arrays are typically arranged in rows and columns, allowing specific memory cells to be addressed by specifying their row and column in the array. Word lines connect rows to bit-line sense amplifiers (SAs) that detect data in a set of probe cells. Then, during a read operation, a subset of data in the sense amplifiers is selected, either by choice or column selection, for output.

[0027] Reference Figure 1 Each memory cell 100 in a DRAM typically includes a capacitor 110, a transistor 120, a word line (WL) 130, and a bit line (BL) 140. The gate of transistor 120 is connected to word line 130, the drain of transistor 120 is connected to bit line 140, and the source of transistor 120 is connected to capacitor 110. The voltage signal on word line 130 can control transistor 120 to turn on or off, thereby reading data information stored in capacitor 110 through bit line 140, or writing data information into capacitor 110 for storage through bit line 140.

[0028] A memory block is composed of multiple memory cells as described above. A memory block typically occupies 50-65% of the total area of ​​a DRAM device, with the remaining area primarily consisting of peripheral circuitry. (See reference...) Figure 2 The diagram shows a schematic of a peripheral circuit. Figure 2 The peripheral circuitry of the DRAM device includes a Command Decoder 210, an Address Latch 220, a Refresh Address Counter (RAC) 230, an Address Mux (AM) 240, and a Pre-Decoder (Pre-D) 250. The Command Decoder 210 decodes system-issued commands (CMD) such as RESET_n, CKE, CK_t / CK_c, PAR, TEN, CS_n, and ACT_n. The Address Latch 220 temporarily stores address codes such as A<16:0>.

[0029] In addition, the peripheral circuitry of the DRAM device includes: an activation window signal generation module 260, a refresh window signal generation module 270, and a control signal generation module 280; the activation window signal generation module 260 is used to generate a memory block activation window signal BANK ACT Window Signal, and the refresh window signal generation module 270 is used to generate a refresh window signal RefreshWindow Signal.

[0030] Reference Figure 3 The diagram illustrates the structure of a memory block 300. The memory block 300 includes a bit line BL, a complementary bit line BL_B, several word lines WL, and several memory cells 100, which share either the bit line BL or the complementary bit line BL_B. Furthermore, the bit line BL and the complementary bit line BL_B are also used to connect to write input drivers INPUT Write Driver and INPUT_BWrite Driver, and to output output signals OUTPUT and OUTPUT_B.

[0031] In an exemplary embodiment of this disclosure, the storage block 300 further includes a sensing module 310 and a bit line balancing module 320, wherein the bit line balancing module 320 is used to pinch bit line BL and complementary bit line BL_B under the action of bit line balancing control signal BLEQ, so as to disable read and write operations on the storage unit 100.

[0032] Reference Figure 3The sensing module 310 mainly includes a sense amplifier (SA), which can address multiple memory cells 100 via bit lines BL or BL_B. More specifically, a conventional sense amplifier is a differential amplifier that operates using bit line BL and a complementary bit line BL_B (as a reference line) to detect and amplify the voltage difference across a pair of bit lines BL and BL_B.

[0033] A memory typically has multiple distinct operating phases, such as read, write, and refresh phases. A complete read operation phase includes four sub-phases: Precharge, Access, Sense, and Restore. A write operation phase includes five sub-phases: Precharge, Access, Sense, Restore, and Write Recovery. This disclosure does not describe the specific operating phases of the memory in detail; reference to existing memory models is sufficient.

[0034] The memory power consumption determination method provided in the exemplary embodiments of this disclosure is referred to... Figure 4 This may include the following steps:

[0035] Step S410: Receive memory control commands and control the analog memory to enter different working stages according to the memory control commands;

[0036] Step S420: Obtain the original current variation curves of the analog memory in different operating stages;

[0037] Step S430: Determine the target time period corresponding to the target working stage according to the timing of the memory control commands;

[0038] Step S440: Based on the target time period, extract the stage current change curve corresponding to the target working stage from the original current change curve to obtain the target current change curve;

[0039] Step S450: Select the target performance parameters from the memory performance parameter table according to the target operating stage;

[0040] Step S460: Determine the memory power consumption based on the target performance parameters and the target current change curve.

[0041] In the memory power consumption determination method provided by the exemplary embodiments of this disclosure, on the one hand, by controlling the analog memory to enter different working stages, the original current change curves of the analog memory in different working stages can be easily obtained as the original current change curves of the memory for subsequent power consumption determination; on the other hand, after determining the target working stage, the stage current change curve corresponding to the target working stage can be extracted according to the corresponding target time period. Based on the stage current change curve, the target current change curve can be obtained. Finally, by combining the target current change curve and the target performance parameters, the memory power consumption can be determined. The determined memory power consumption can be used as the actual power consumption of the memory for memory performance analysis, and can also provide a basis for system failure analysis.

[0042] In step S410, a memory control command is received, and the analog memory is controlled to enter different working stages according to the memory control command.

[0043] In the exemplary embodiments of this disclosure, the simulated memory is a memory model simulated based on the components of the memory and their corresponding connections. For example, the memory structure can be built on simulation software based on the actual memory used. Furthermore, various operations of the memory during actual operation can be executed according to memory control commands. In other words, the aforementioned simulated memory can simulate the different working stages of a real memory to facilitate the acquisition of various required data, such as current data and voltage data.

[0044] In practical applications, memory has multiple control commands, such as read operation commands, write operation commands, refresh operation commands, etc. According to different control commands, memory will enter different working stages to complete the corresponding operations.

[0045] In the exemplary embodiments of this disclosure, by simulating a real memory to enter different working stages, the problem that it is difficult to record and obtain current data or voltage data of a real memory during its operation can be solved.

[0046] In step S420, the original current variation curves of the analog memory in different operating stages are obtained.

[0047] The analog memory is controlled to enter different operating stages according to memory control commands, such as read operation stage, write operation stage, and refresh operation stage. Typically, these different operating stages are executed intermittently; therefore, it is necessary to mark the time when the analog memory enters each operating stage. Simultaneously, during the marking process, the time lag between the issuance of the memory control command and the actual start of execution must be considered. The actual start time of execution is used as the mark point to mark the collected data, for example, to obtain the original current change curve.

[0048] The aforementioned original current change curve contains current change data over time corresponding to multiple different operating stages, including the read operation stage, the write operation stage, and the refresh operation stage. Based on this data, subsequent memory power consumption can be determined.

[0049] In step S430, the target time period corresponding to the target working stage is determined according to the timing of the memory control commands.

[0050] In practical applications, memory control commands are usually issued according to the timing of memory control commands. Based on the specific issuance time of the control command and the delay from issuance to execution, the start time of the target working stage can be determined. Then, based on the execution duration of the target working stage, the target time period of the target working stage can be determined.

[0051] In the exemplary embodiments of this disclosure, the target working stage can be at least one of different working stages, that is, the target working stage can be just a read operation stage, a write operation stage, or a refresh operation stage; it can also be a read and write operation stage, or a complete operation stage including read, write, and refresh; or, the target working stage can also be at least one of the four different sub-stages of the read operation stage: Precharge, Access, Sense, and Restore. The exemplary embodiments of this disclosure do not impose special limitations on the specific target working stage, and can be flexibly determined according to actual needs.

[0052] In step S440, based on the target time period, the stage current change curve corresponding to the target working stage is extracted from the original current change curve to obtain the target current change curve.

[0053] After determining the target time period according to step S430, the stage current change curve corresponding to the target time period can be extracted from the original current change curve, that is, the stage current change curve corresponding to the target operating stage. For example, the stage current change curve corresponding to the target read operation stage, the stage current change curve corresponding to the target write operation stage, etc.

[0054] In the exemplary embodiments of this disclosure, after capturing the stage current change curve corresponding to the target working stage, it is necessary to process the stage current change curve to obtain the target current change curve.

[0055] The specific current change curve for each processing stage can be determined based on the required memory power consumption. If the required memory power consumption is the total power consumption, the total power consumption can be determined directly based on the current change curve and memory performance parameters.

[0056] In this exemplary embodiment of the disclosure, taking the average over-limit power consumption of the memory as an example, the processing procedure of the extracted stage current change curve is described in detail:

[0057] Reference Figure 5 After capturing the current variation curve corresponding to the target operating stage, the captured current variation curve can be discretized according to a preset step size to obtain discrete data. Then, the stage peak and valley values ​​are determined from the discrete data. Linear interpolation is then performed on the aforementioned stage peak and valley values ​​to obtain an interpolation line. Next, a preset error range can be determined based on the interpolation line, for example... Figure 5 Two preset error range boundary lines are used. Part of the current change curve falls within the preset error range, while the other part falls outside the preset error range.

[0058] In practical applications, the aforementioned preset error range can be determined based on the actual situation. For example, the preset error range can be any value between 5% and 15%. If the preset error range is 5%, then... Figure 5 As shown, the preset error range boundary lines can be determined at a distance of ±5% from the interpolation line on both sides of the interpolation line, using the interpolation line as a reference.

[0059] It should be noted that the process of determining the peak and trough values ​​of each stage can also be performed before discretizing the stage current variation curve. That is, the highest point can be directly determined from the stage current variation curve as the stage peak value, and the lowest point can be determined as the stage trough value. This improves the accuracy of determining the stage peak and trough values ​​and avoids their loss during the discretization process.

[0060] In an exemplary embodiment of this disclosure, discrete data falling outside a preset error range can be acquired and denoted as out-of-limit data. This out-of-limit data, along with stage peaks and stage valleys, is fitted to obtain a target current variation curve. The obtained target current variation curve is primarily composed of data exceeding the preset error range. Therefore, based on this target current variation curve, the average out-of-limit power consumption of the memory can be calculated. This average out-of-limit power consumption can then be used for memory performance analysis, failure analysis, and other purposes.

[0061] It should be noted that, in the process of determining the average over-limit power consumption, the valley value of the stage can be omitted, and the over-limit data and the peak value of the stage can be directly used for fitting to obtain the target current change curve. The exemplary embodiments of this disclosure do not impose any special limitations on the method of determining the target current change curve.

[0062] In practical applications, the preset step size can be determined according to the actual situation. For example, the preset step size can be any value between 8ps and 12ps, such as 10ps. It is understood that the smaller the step size, the higher the accuracy and the longer the simulation time. That is to say, the preset step size can be adjusted according to the required accuracy and time cost. The exemplary embodiments of this disclosure do not impose any special limitation on the specific value of the preset step size.

[0063] In some embodiments, preliminary data discretization can be performed first with a larger preset step size. For example, the intercepted stage current change curve can be discretized with a first preset step size to obtain first discrete data. The first discrete data outside the preset error range is recorded as the first out-of-limit data. Then, the stage current change curve corresponding to the time period of the first out-of-limit data is further discretized with a smaller second preset step size to obtain second discrete data. The second discrete data outside the preset error range is recorded as the second out-of-limit data. Subsequently, the second out-of-limit data, stage peak value, and stage valley value are fitted to obtain the target current change curve. In this way, it is beneficial to dynamically balance the simulation time and simulation accuracy according to the actual waveform of the stage current change curve, and it is beneficial to simultaneously shorten the simulation time and improve the simulation accuracy.

[0064] In practical applications, the first preset step size is greater than the second preset step size. The values ​​of the first and second preset step sizes can be determined according to the actual situation. For example, the first preset step size can be greater than 12 ps, and the second preset step size can be less than or equal to 12 ps. The exemplary embodiments of this disclosure do not impose special limitations on the specific values ​​of the first and second preset step sizes.

[0065] In steps S450 and S460, target performance parameters are selected from the memory performance parameter table according to the target operating stage; and the memory power consumption is determined according to the target performance parameters and the target current change curve.

[0066] In the exemplary embodiments of this disclosure, after determining the target current change curve, it is also necessary to select target performance parameters from the memory performance parameter table according to the target operating stage. If the target operating stage is the read operation stage, it is necessary to obtain the constituent elements in the memory involved in the read operation stage, and the target performance parameters can be determined from the performance parameters of these constituent elements.

[0067] In practical applications, based on the actual memory being simulated, the target performance parameters for different operating stages are usually determined in advance and stored in a memory performance parameter table for easy retrieval later. These target performance parameters may include resistance, capacitance, and inductance values ​​corresponding to the target operating stage.

[0068] After selecting the target performance parameters, the memory power consumption can be determined based on these parameters and the target current variation curve. Specifically, the determined memory power consumption will vary depending on the specific target current variation curve.

[0069] If the target current change curve is the same as the initial stage current change curve, then the total power consumption of the memory during the target operating stage can be calculated. If the target current change curve is composed of the above-mentioned over-limit data, stage peak value, and stage valley value, then the determined memory power consumption is the memory over-limit power consumption and average over-limit power consumption.

[0070] Taking the determination of the average over-limit power consumption of the memory as an example, the average over-limit current during the target operating stage can be determined based on the target current change curve determined in step S440 above. Specifically, the average over-limit current can be obtained by dividing the area covered by the target current change curve by the length of the covered time. Finally, the average over-limit power consumption of the memory can be determined based on the average over-limit current, the resistance value, capacitance value, and inductance value corresponding to the target operating stage. The specific determination process will not be elaborated here.

[0071] In the exemplary embodiments of this disclosure, after determining the average over-limit power consumption of the memory, the memory can be adjusted accordingly based on its magnitude. For example, when the average over-limit power consumption is greater than or equal to a preset power consumption, power consumption analysis is performed on the memory to adjust target performance parameters. This can be done by reducing resistance, capacitance, or inductance values. Specifically, reducing resistance can involve selecting components with lower resistance values ​​or reducing the memory's operating frequency to ensure it operates within a safe range. When the average over-limit power consumption is less than the preset power consumption, the operating parameters of the target operating stage in the memory can be adjusted, for example, by increasing the memory's operating frequency, thereby improving the memory's performance while ensuring normal operation.

[0072] In practical applications, the aforementioned preset power consumption can be the maximum power consumption of the memory during the target working stage as specified by memory-related standards, or it can be set manually according to actual conditions, or determined by the peak and valley values ​​of the stage. The exemplary embodiments disclosed herein do not impose any special limitations on this.

[0073] It should be noted that, in addition to the method of directly determining memory power consumption described above, after determining the target current change curve, the data corresponding to the target current change curve can also be processed into a data format recognizable by the analysis model. The processed data can then be input into the analysis model for system power consumption analysis to identify potential power consumption problems in the memory, such as whether the power consumption is caused by the memory itself or by noise. This exemplary embodiment will not elaborate on this data analysis method.

[0074] In summary, the memory power consumption determination method provided by the exemplary embodiments of this disclosure can select a target current variation curve corresponding to a target operating stage according to different operating stages, and then determine the average over-limit power consumption that the memory may have based on the target current variation curve. Based on the average over-limit power consumption, the target performance parameters or operating parameters of the memory can be adjusted, thereby adjusting the memory to the best operating state and improving the utilization rate of the memory while meeting actual needs.

[0075] It should be noted that although the steps of the method in this invention are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0076] Furthermore, in this example embodiment, a memory power consumption determination apparatus is also provided. (Refer to...) Figure 6 The memory power consumption determination device 600 may include: a memory simulation module 610, a raw current acquisition module 620, a target time period determination module 630, a target current determination module 640, a target parameter determination module 650, a power consumption determination module 660, and a memory adjustment module 670, wherein:

[0077] The memory simulation module 610 can be used to receive memory control commands and control the simulated memory to enter different working stages according to the memory control commands;

[0078] The raw current acquisition module 620 can be used to acquire the raw current change curves of the analog memory at different operating stages.

[0079] The target time period determination module 630 can be used to determine the target time period corresponding to the target working stage based on the timing of the memory control commands.

[0080] The target current determination module 640 can be used to extract the stage current change curve corresponding to the target working stage from the original current change curve according to the target time period, so as to obtain the target current change curve.

[0081] The target parameter determination module 650 can be used to select target performance parameters from the memory performance parameter table according to the target working stage;

[0082] The power consumption determination module 660 can be used to determine the power consumption of the memory based on the target performance parameters and the target current change curve.

[0083] In one exemplary embodiment of this disclosure, the target current determination module 640 can be used to discretize the stage current change curve according to a preset step size to obtain discrete data; determine the stage peak value and stage valley value from the discrete data; perform linear interpolation on the stage peak value and stage valley value to obtain an interpolation line; use the interpolation line as a reference to obtain discrete data outside the preset error range, which is recorded as out-of-limit data; and fit the out-of-limit data, stage peak value and stage valley value to obtain the target current change curve.

[0084] In one exemplary embodiment of this disclosure, the target current determination module 640 can also be used to discretize the intercepted stage current change curve according to a first preset step size to obtain first discrete data; obtain the first discrete data outside the preset error range and record it as the first out-of-limit data; discretize the stage current change curve corresponding to the time period where the first out-of-limit data is located with a second preset step size to obtain second discrete data; obtain the second discrete data outside the preset error range and record it as the second out-of-limit data; and fit the second out-of-limit data, the stage peak value, and the stage valley value to obtain the target current change curve.

[0085] In one exemplary embodiment of this disclosure, the first preset step size is larger than the second preset step size.

[0086] In one exemplary embodiment of this disclosure, the power consumption determination module 660 can be used to determine the average overcurrent of the target operating stage based on the target current change curve; the target performance parameters include the resistance value, capacitance value and inductance value corresponding to the target operating stage; and the average overcurrent of the memory is determined based on the average overcurrent, resistance value, capacitance value and inductance value.

[0087] In one exemplary embodiment of this disclosure, the memory power consumption determination device further includes:

[0088] The memory adjustment module 670 can be used to perform power consumption analysis on the memory when the average over-limit power consumption of the memory is greater than or equal to the preset power consumption, so as to adjust the target performance parameters.

[0089] In one exemplary embodiment of this disclosure, the memory adjustment module 670 can also be used to adjust the operating parameters of the target working stage in the memory when the average over-limit power consumption of the memory is less than the preset power consumption.

[0090] In one exemplary embodiment of this disclosure, the different working phases include: a read operation phase, a write operation phase, and a refresh operation phase.

[0091] In one exemplary embodiment of this disclosure, the target working stage is at least one of different working stages.

[0092] In one exemplary embodiment of this disclosure, the preset error range is any value between 5% and 15%.

[0093] In one exemplary embodiment of this disclosure, the simulated memory is a memory model simulated based on the constituent elements of the memory and their corresponding connection relationships.

[0094] The specific details of the virtual modules of each memory power consumption determination device mentioned above have been described in detail in the corresponding memory power consumption determination methods, so they will not be repeated here.

[0095] It should be noted that although several modules or units of the memory power consumption determination device have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0096] In an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0097] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”

[0098] The following reference Figure 7 To describe an electronic device 700 according to this embodiment of the present invention. Figure 7 The electronic device 700 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0099] like Figure 7As shown, the electronic device 700 is presented in the form of a general-purpose computing device. The components of the electronic device 700 may include, but are not limited to: at least one processing unit 710, at least one storage unit 720, a bus 730 connecting different system components (including storage unit 720 and processing unit 710), and a display unit 740.

[0100] The storage unit 720 stores program code that can be executed by the processing unit 710, causing the processing unit 710 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 710 can perform actions such as... Figure 4 The steps shown are as follows: S410: Receive memory control commands and control the analog memory to enter different working stages according to the memory control commands; S420: Obtain the original current change curves of the analog memory in different working stages; S430: Determine the target time period corresponding to the target working stage according to the timing of the memory control commands; S440: Extract the stage current change curve corresponding to the target working stage from the original current change curves according to the target time period to obtain the target current change curve; S450: Select target performance parameters from the memory performance parameter table according to the target working stage; S460: Determine the memory power consumption according to the target performance parameters and the target current change curve.

[0101] Storage unit 720 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 7201 and / or cache memory 7202, and may further include a read-only memory (ROM) 7203.

[0102] The storage unit 720 may also include a program / utility 7204 having a set (at least one) program module 7205, such program module 7205 including but not limited to: an operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0103] Bus 730 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0104] Electronic device 700 can also communicate with one or more external devices 770 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 700, and / or with any device that enables electronic device 700 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 750. Furthermore, electronic device 700 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 760. As shown, network adapter 760 communicates with other modules of electronic device 700 via bus 730. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 700, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0105] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0106] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the invention described in the "Exemplary Methods" section of this specification.

[0107] According to embodiments of the present invention, a program product for implementing the above-described method may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0108] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0109] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0110] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0111] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0112] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0113] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0114] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A method for determining the power consumption of a memory, characterized in that, The method includes: Receive memory control commands and control the analog memory to enter different working stages according to the memory control commands; Obtain the original current variation curves of the analog memory during different operating stages; Based on the timing of the memory control commands, determine the target time period corresponding to the target working stage; Based on the target time period, the stage current change curve corresponding to the target working stage is extracted from the original current change curve to obtain the target current change curve; Based on the target operating stage, select the target performance parameters from the memory performance parameter table; The power consumption of the memory is determined based on the target performance parameters and the target current variation curve.

2. The method according to claim 1, characterized in that, The step of extracting the stage current change curve corresponding to the target operating stage from the original current change curve to obtain the target current change curve includes: According to a preset step size, the current change curve of the segment is discretized to obtain discrete data; The stage peak and stage trough values ​​are determined from the discrete data; Linear interpolation is performed on the peak value and the valley value of the stage to obtain an interpolation line; Using the interpolation line as a reference, the discrete data outside the preset error range is obtained and recorded as out-of-limit data; The target current variation curve is obtained by fitting the out-of-limit data, the peak value of the stage, and the valley value of the stage.

3. The method according to claim 2, characterized in that, The step of extracting the stage current change curve corresponding to the target operating stage from the original current change curve to obtain the target current change curve includes: According to the first preset step size, the current change curve of the segment is discretized to obtain the first discrete data; The first discrete data outside the preset error range is obtained and recorded as the first out-of-limit data; The current change curve of the stage corresponding to the time period where the first over-limit data is located is discretized with a second preset step size to obtain the second discrete data. Obtain the second discrete data outside the preset error range, and record it as the second out-of-limit data; The target current variation curve is obtained by fitting the second over-limit data, the stage peak value, and the stage valley value.

4. The method according to claim 3, characterized in that, The first preset step size is greater than the second preset step size.

5. The method according to any one of claims 2-4, characterized in that, Determining the memory power consumption based on the target performance parameters and the target current variation curve includes: Based on the target current variation curve, the average overcurrent during the target operating phase is determined; The target performance parameters include the resistance, capacitance, and inductance values ​​corresponding to the target operating stage; The average overcurrent of the memory is determined based on the average overcurrent, the resistance value, the capacitance value, and the inductance value.

6. The method according to claim 5, characterized in that, The method further includes: When the average over-limit power consumption of the memory is greater than or equal to the preset power consumption, power consumption analysis is performed on the memory in order to adjust the target performance parameters.

7. The method according to claim 6, characterized in that, The method further includes: When the average over-limit power consumption of the memory is less than the preset power consumption, the operating parameters of the target working stage in the memory are adjusted.

8. The method according to claim 1, characterized in that, The different working phases include: read operation phase, write operation phase, and refresh operation phase.

9. The method according to claim 8, characterized in that, The target working stage is at least one of the different working stages.

10. The method according to any one of claims 2-4, characterized in that, The preset error range is any value between 5% and 15%.

11. The method according to claim 1, characterized in that, The simulated memory is a memory model simulated based on the components of the memory and their corresponding connections.

12. A memory power consumption determination device, characterized in that, The device includes: The memory simulation module is used to receive memory control commands and control the simulated memory to enter different working stages according to the memory control commands; The raw current acquisition module is used to acquire the raw current variation curves of the analog memory in different operating stages. The target time period determination module is used to determine the target time period corresponding to the target working stage based on the timing of the memory control commands. The target current determination module is used to extract the stage current change curve corresponding to the target working stage from the original current change curve according to the target time period, so as to obtain the target current change curve; The target parameter determination module is used to select target performance parameters from the memory performance parameter table according to the target working stage; The power consumption determination module is used to determine the power consumption of the memory based on the target performance parameters and the target current change curve.

13. The apparatus according to claim 12, characterized in that, The target current determination module is used to discretize the stage current change curve according to a preset step size to obtain discrete data; perform linear interpolation on the stage peak and stage valley to obtain an interpolation line; use the interpolation line as a reference to obtain the discrete data outside the preset error range, which is recorded as out-of-limit data; and fit the out-of-limit data, the stage peak, and the stage valley to obtain the target current change curve.

14. The apparatus according to claim 13, characterized in that, The step of extracting the stage current change curve corresponding to the target operating stage from the original current change curve to obtain the target current change curve includes: According to the first preset step size, the current change curve of the segment is discretized to obtain the first discrete data; The first discrete data outside the preset error range is obtained and recorded as the first out-of-limit data; The current change curve of the stage corresponding to the time period where the first over-limit data is located is discretized with a second preset step size to obtain the second discrete data. Obtain the second discrete data outside the preset error range, and record it as the second out-of-limit data; The target current variation curve is obtained by fitting the second over-limit data, the stage peak value, and the stage valley value.

15. The apparatus according to claim 14, characterized in that, The first preset step size is greater than the second preset step size.

16. The apparatus according to any one of claims 13-15, characterized in that, The power consumption determination module is used to determine the average overcurrent of the target operating stage based on the target current change curve; the target performance parameters include the resistance value, capacitance value and inductance value corresponding to the target operating stage. The average overcurrent of the memory is determined based on the average overcurrent, the resistance value, the capacitance value, and the inductance value.

17. The apparatus according to claim 16, characterized in that, The device further includes: The memory adjustment module is used to perform power consumption analysis on the memory when the average over-limit power consumption of the memory is greater than or equal to the preset power consumption, so as to adjust the target performance parameters.

18. The apparatus according to claim 17, characterized in that, The memory adjustment module is further configured to adjust the operating parameters of the target working stage in the memory when the average over-limit power consumption of the memory is less than the preset power consumption.

19. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the memory power consumption determination method according to any one of claims 1-11.

20. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the memory power consumption determination method according to any one of claims 1-11 by executing the executable instructions.

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