New Method for Gate Interface Engineering

Abstract

A processing method can be performed to produce a semiconductor structure that can include a high-k dielectric material. The method can include removing a native oxide from a surface of a substrate. The method can include delivering dinitrogen monoxide to the substrate and thermally annealing the surface to form an oxide-containing interface. The method can include delivering a nitrogen-containing precursor or an oxygen-containing precursor to a substrate housed in a semiconductor processing chamber. The method can include forming reactive ligands on an exposed surface of the substrate using the nitrogen-containing precursor or the oxygen-containing precursor. The method can further include forming a high-k dielectric material covering the substrate.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 910,974, filed on October 4, 2019, the content of which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] This technology relates to semiconductor systems, processing, and devices. More specifically, this technology relates to processes for the formation of materials in enhanced gate structures. Background Art

[0004] The performance of logic gates is related to the properties of the materials used and the thickness and area of the structural layers. However, as some gate characteristics are adjusted to accommodate device scaling, challenges arise. For example, for silicon oxide gate dielectrics, as the thickness decreases, the capacitance can increase, which can result in higher channel mobility and faster device performance. However, as the thickness continues to decrease, gate leakage can affect the device and may lead to a decrease in device yield. High - k materials have been used as gate dielectrics to reduce the effective oxide thickness while limiting the impact on gate leakage. Due to morphological issues related to the formation of high - k materials, efforts to maximize a particular high - k material have been limited.

[0005] Accordingly, there is a need for improved systems and methods that can be used to maximize the performance of high - k materials and are capable of producing high - quality devices and structures. These and other needs are addressed by this technology. Summary of the Invention

[0006] A processing method can be performed to produce a semiconductor structure that can include a high - k dielectric material. The method can include removing a native oxide from a surface of a substrate. The method can include delivering nitrous oxide to the substrate and thermally annealing the surface to form an oxide - containing interface. The method can include delivering a nitrogen - containing precursor or an oxygen - containing precursor to a substrate housed in a semiconductor processing chamber. The method can include introducing a reactive ligand on an exposed surface of the substrate with the nitrogen - containing precursor or the oxygen - containing precursor. The method can further include forming a high - k dielectric material covering the substrate.

[0007] In some embodiments, removing the native oxide can include in - situ dry chemical processing. The removing step can be performed in a first processing chamber, and the method can further include transferring the substrate from the first processing chamber to a second processing chamber before forming the high - k dielectric material. The method can also include methods performed in one or more processing chambers without exposing the substrate surface to the atmosphere. The method can include removing the native oxide from the surface of the substrate up to or about 20 angstroms Depth. In some embodiments, the method may include delivering nitrous oxide to a substrate and thermally annealing the surface to form an oxide-containing interface having a thickness up to about 5 angstroms. The method may include forming a high-k dielectric material, which includes performing an atomic layer deposition process. In some embodiments, the nitrogen-containing precursor may be ammonia or include ammonia. The method may include maintaining the substrate at a temperature above or about 300 °C while delivering ammonia. In some embodiments, the substrate may be or include a silicon-containing material. In some embodiments, the high-k dielectric material may be or include at least one element selected from the group consisting of hafnium, zirconium, silicon, lanthanum, aluminum, titanium, and strontium.

[0008] Some embodiments of the present technology may further include a method of forming a semiconductor structure. The method may include removing a native oxide from the surface of a substrate contained in a semiconductor processing chamber. The method may include delivering nitrous oxide to the substrate and thermally annealing the surface to form an oxide-containing interface. The method may include pre-processing the substrate by contacting the substrate with a nitrogen-containing precursor or an oxygen-containing precursor. The method may include forming a high-k dielectric material covering the pre-processed substrate in a first semiconductor processing chamber containing the pre-processed substrate. The method may include transferring the substrate to a second semiconductor processing chamber. The method may further include post-processing the high-k dielectric material.

[0009] In some embodiments, removing the native oxide may include an in-situ dry chemical process. The removal may be performed in a first processing chamber, and the method may further include transferring the substrate from the first processing chamber to a second processing chamber before forming the high-k dielectric material. The method may also include methods performed in one or more processing chambers without exposing the substrate surface to the atmosphere. In some embodiments, the post-processing step may include exposing the substrate and the high-k dielectric material to an oxygen-containing precursor or a nitrogen-containing precursor. The method may include annealing the high-k dielectric material after post-processing. The nitrogen-containing precursor for pre-processing may be ammonia or include ammonia.

[0010] Some embodiments of the present technology may further include a method of forming a semiconductor structure. The method may remove a native oxide from the surface of a substrate contained in a semiconductor processing chamber. The method may include delivering nitrous oxide onto the substrate and thermally annealing the surface to form an oxide-containing interface. The method may include pre-processing a substrate including a silicon-containing material by contacting the substrate with a nitrogen-containing precursor or an oxygen-containing precursor while maintaining the substrate at a first temperature greater than or about 400 °C. The method may include forming a high-k dielectric material covering the pre-processed substrate while maintaining the pre-processed substrate at a second temperature less than the first temperature. The method may further include post-processing the high-k dielectric material by annealing at a third temperature greater than or about equal to the first temperature.

[0011] Such techniques can provide many benefits over conventional systems and techniques. For example, the method can produce a more preferred structure of a high-k dielectric material. Additionally, compared to the same high-k dielectric material formed conventionally, the resulting high-k material is characterized by reduced gate leakage. These and other embodiments, as well as many of their advantages and features, are described in more detail in conjunction with the following description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A further understanding of the nature and advantages of the disclosed technology can be realized by reference to the remainder of the specification and the drawings.

[0013] Figure 1 A top view of an exemplary processing system in accordance with an embodiment of the present technology is shown.

[0014] Figure 2 Selected operations in a method of forming a semiconductor structure in accordance with an embodiment of the present technology are shown.

[0015] Figures 3A - 3F A schematic cross-sectional view of an exemplary substrate in accordance with an embodiment of the present technology is shown.

[0016] Several drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes only and should not be considered to be drawn to scale unless specifically stated otherwise. Additionally, as schematic diagrams, the drawings are provided to aid understanding and may not include all aspects or information compared to an actual representation, and may include exaggerated material for illustrative purposes.

[0017] In the drawings, like components and / or features may have the same reference numerals. Additionally, various components of the same type may be distinguished by adding a letter after the reference numeral to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any similar component having the same first reference numeral, regardless of the letter. DETAILED DESCRIPTION

[0018] As logic gate structures are scaled down to smaller dimensions, new material structures are being sought to provide improvements. Compared to conventional gate stacks using materials such as silicon oxide, the use of high-k dielectrics increases the dielectric constant of the gate stack. However, similar to silicon oxide, as the thickness of the material decreases, gate leakage increases. For example, gate leakage increases as the effective oxide thickness decreases. Thus, the inverse relationship between gate leakage and effective oxide thickness may limit the performance of transistors and the components produced.

[0019] High-k dielectric materials can provide greater channel mobility than silicon oxide at similar thicknesses. As the industry continues to seek to reduce the effective oxide thickness without increasing gate leakage, efforts to maximize the k-value of known high-k materials have reached a limit due to morphological characteristics. Conventional techniques have been trying to overcome the natural properties of high-k materials, which may set an upper limit on the dielectric constant, and have attempted to introduce new thin films in subsequent device modifications.

[0020] The present technology overcomes these problems by improving the properties of the high-k dielectric material itself. According to embodiments of the present technology, by producing a high-k dielectric material that exhibits a specific morphology or grain structure, a higher dielectric constant and consequent improved device performance can be achieved. To control grain formation in an exemplary device, processing can be performed to provide an activated substrate surface that can induce specific grain growth, and to stabilize the thin film after formation, which can achieve a higher dielectric constant.

[0021] Although the remainder of the disclosure will routinely determine specific deposition and processing treatments using the disclosed technology, it will be readily understood that the system and method are equally applicable to a variety of other processes that may occur in the described chambers. Therefore, the technology should not be considered limited to the techniques used in conjunction with the described processing and deposition treatments. The present disclosure will discuss a possible system for certain elements that can be used with the present technology to perform deposition or processing operations before describing the operation of an exemplary processing sequence according to the present technology. It should be understood that the technology is not limited to the described apparatus, and the discussed processes can be performed in any number of processing chambers and systems.

[0022] Figure 1 A top view of one embodiment of a processing system 100 for a deposition, etching, baking, and / or curing chamber according to an embodiment is shown. Figure 1 The tool or processing system 100 depicted therein can include a plurality of processing chambers 114A-D, a transfer chamber 110, a service chamber 116, an integrated metrology chamber 117, and a pair of load lock chambers 106A-B. The processing chambers can include any number of structures or components, as well as any number or combination of processing chambers.

[0023] To transfer substrates between chambers, the transfer chamber 110 can include a robotic transfer mechanism 113. The transfer mechanism 113 can have a pair of substrate transfer blades 113A, which are respectively attached to the distal ends of extensible arms 113B. The blades 113A can be used to transport a single substrate to and from a processing chamber. In operation, a substrate transfer blade such as the blade 113A of the transfer mechanism 113 can retrieve a substrate W from one of the load lock chambers such as chambers 106A-B and transport the substrate W to the first stage of processing, for example, the processing performed in chambers 114A-D as described below. These chambers can be included to perform the individual operations or combined operations of the described techniques. For example, although one or more chambers can be configured to perform deposition or formation operations, one or more other chambers can be configured to perform the described pre-processing operations and / or one or more post-processing operations. The present technology encompasses any number of configurations, which can also perform any number of additional manufacturing operations typically performed in semiconductor processing.

[0024] If the chamber is occupied, the robot can wait until the processing is complete, then remove the processed substrate from the chamber with one blade 113A and can insert a new substrate using a second blade (not shown). Once the substrate has been processed, it can be moved to the second stage of processing. For each move, the transfer mechanism 113 can typically have one blade carrying the substrate and one empty blade to perform substrate replacement. The transfer mechanism 113 can wait at each chamber until the replacement can be completed.

[0025] Once processing is complete within the processing chamber, the transfer mechanism 113 can remove the substrate W from the last processing chamber and transfer the substrate W to a cassette within the load lock chambers 106A-B. The substrate can be moved from the load lock chambers 106A-B to the factory interface 104. The factory interface 104 is typically used to transfer substrates between the cassette loaders (podloaders) 105A-D in an atmospheric pressure clean environment and the load lock chambers 106A-B. The clean environment in the factory interface 104 can typically be provided by, for example, air filtration treatment with HEPA filtration. The factory interface 104 can also include a substrate orienter / aligner (not shown), which can be used to properly align the substrate before processing. At least one substrate robot (e.g., robots 108A-B) can be positioned in the factory interface 104 to transfer substrates between various positions / locations within the factory interface 104 and between other locations in communication therewith. The robots 108A-B can be configured to travel along a track system within the factory interface 104 from a first end to a second end of the factory interface 104.

[0026] The processing system 100 may further include an integrated metrology chamber 117 to provide a control signal that can provide adaptive control over any processing being performed in the processing chamber. The integrated metrology chamber 117 may include any one of a variety of metrology devices for measuring various thin film properties (such as thickness, roughness, composition), and the metrology device may also be capable of characterizing grating parameters, such as critical dimension, sidewall angle, and feature height, in an automated manner under vacuum.

[0027] Each of the processing chambers 114A - D may be configured to perform one or more processing steps in the fabrication of semiconductor structures, and any number and combination of processing chambers may be used on the multi - chamber processing system 100. By way of example, any processing chamber may be configured to perform a number of substrate processing operations, including any number of deposition processes, including cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and other operations, including etching, pre - cleaning, pre - processing, post - processing, annealing, plasma processing, degassing, orientation, and other substrate processing. Some specific processes that may be performed in any chamber or any combination of chambers may be metal deposition, surface cleaning and preparation, thermal annealing such as rapid thermal processing, and plasma processing. As will be readily understood by those skilled in the art, any other processes, including any of the processes described below, may be similarly performed in specific chambers incorporated in the multi - chamber processing system 100.

[0028] Figure 2 A method 200 of forming a semiconductor structure is shown, and the operations of the method may be performed, for example, in one or more chambers incorporated in the multi - chamber processing system 100 as previously described. Method 200 may include one or more operations prior to the start of the method operations, including front - end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the operations. The method may include a number of optional operations as shown, which may or may not be specifically associated with the method according to the present technology. For example, a number of operations are described to provide a wider range of structure - forming processes, but this is not critical to the technology or may be performed by alternative methods, as will be discussed further below. Method 200 describes Figures 3A - 3F the operations schematically shown in, and its illustration will be described in connection with the operations of method 200. It should be understood that FIG. 3 shows only a partial schematic, and the substrate may include any number of transistor portions and additional materials having the front face as shown.

[0029] Method 200 may involve optional operations for developing a semiconductor structure for a particular manufacturing operation. Although in some embodiments, method 200 may be performed on a base structure, in some embodiments, the method may be performed after other materials are formed. As Figure 3AAs shown, the semiconductor structure may represent element 300 after certain processing. For example, substrate 305 may be a flat material or may be a structured device that may include one or more materials configured to or for defining pillars, trenches, or other structures, as would be similarly covered by the present technology. Substrate 305 may include any number of materials, including silicon or silicon-containing materials, such as oxides, nitrides, and carbides of silicon, as well as any other materials that may be incorporated within the structure.

[0030] One or more material layers may be formed on some or all of substrate 305 and at least partially within the substrate to produce a structure of material that may be planarized or structured in an embodiment. As a non-limiting example, substrate 305 may be silicon or may include silicon, or may include a surface amount of silicon formed on an additional material such as silicon oxide, and it may be a reduced portion of the silicon oxide that leaves a silicon-exposed surface. Substrate 305 may include native oxide 310 as Figure 3A shown. In some embodiments, the exposed material at the surface of substrate 305 may be etched, planarized, or otherwise processed to produce an interrupted pattern. Although shown as a single instance, it should be understood that element 300 may include a small portion of a larger processing integration that may include any number of additional portions similar or different from the objects shown. Substrate 305 may be housed or positioned within the processing region of a semiconductor processing chamber, and method 200 may be performed to produce a semiconductor material, such as a high-k dielectric material, on the substrate.

[0031] Method 200 may include removing from substrate 305 in operation 205 (as Figure 3ANative oxide 310 (as shown). Removal of native oxide 310 can be or include flowing a fluorine-containing precursor and a hydrogen-containing precursor. The fluorine-containing precursor can be or include nitrogen trifluoride and any other fluorine-containing precursor. The hydrogen-containing precursor can be characterized by an amine group [-NH2] or other nitrogen- or hydrogen-containing group. For example, the hydrogen-containing precursor can be or include a nitrogen- and hydrogen-containing precursor such as ammonia as a non-limiting example. The flowing can include flowing the fluorine-containing precursor and the hydrogen-containing precursor into a remote plasma region. The remote plasma region can be fluidly coupled to a substrate processing region. A plasma can be formed to generate a plasma effluent. The flow rate of the fluorine-containing precursor and the flow rate of the hydrogen-containing precursor can be characterized by a hydrogen-to-fluorine atom flow ratio of less than 1:2. The native oxide 310 is removed by flowing the plasma effluent into the substrate processing region while forming a solid by-product on the substrate surface. Without being bound by any particular theory, the flowing can leave a layer of fluorine on the substrate surface, which promotes the formation of the interface at operation 210, where the fluorine capping is used to enhance reliability. The solid by-product is sublimated by raising the temperature of the substrate above the sublimation temperature of the solid by-product. After sublimation, the substrate 305 is free or substantially free of native oxide. The removal can be or include removing the native oxide to a depth of up to or about 20 angstroms.

[0032] Method 200 can include SiConi in operation 205 TM etching, which can be a remote plasma-assisted dry etching process that involves simultaneously exposing a substrate (such as Figure 3A substrate 305) to H2, NF3, and / or NH3 plasma by-products. The native oxide can be removed by in-situ dry chemical processing in operation 205, where the substrate surface can be not exposed to the atmosphere or an oxygen-containing environment. In some embodiments of method 200, the native oxide can be removed in operation 205 in a first processing chamber. Method 200 can include transferring the substrate from the first processing chamber to a second processing chamber as in operation 220 before forming the high-k dielectric material. Method 200 can include performing operations in one or more processing chambers without exposing the substrate surface to the atmosphere or air. Method 200 can include maintaining a vacuum within system 100 during the removal in operation 205. Maintaining an overall vacuum can advantageously reduce surface contamination. The transfer can occur between one or more chambers on a single platform or can occur between chambers on multiple platforms. However, by utilizing a single platform, better assurance can be made to avoid exposing the substrate to an oxygen environment.

[0033] Method 200 can include delivering nitrous oxide and thermally annealing the substrate surface in operation 210 to form an oxide-containing interface. Delivering to as Figure 3BNitrous oxide 315 on the substrate 305 shown can help control how much of the substrate 305 with a surface free of native oxide can be oxidized to form an oxide-containing interface 320 as shown in Figure 3C the oxide-containing interface 320 shown. Operation 210 can include a heat-based reaction using vapor, such as an in-situ vapor generation process, whereby oxidation can occur at a lower rate (compared to conventional thermal techniques using hydrogen and / or oxygen). Nitrogen can act as a carrier for oxygen and may not become part of the interface or the substrate. The formed oxide-containing interface can be of high quality and highly ordered, meaning a crystal structure with no or substantially no defects. This can provide an interface 320 that can prevent nitrogen in subsequent operations (such as preprocessing in operation 215) from approaching the channel region, thus preventing leakage. The obtained oxide-containing interface 320 can include silicon dioxide. The formed oxide-containing interface 320 can have a thickness of up to or about 5 angstroms. Method 200 can include removing a thicker native oxide in operation 205, which can be replaced by a thinner oxide-containing interface 320 in subsequent operations.

[0034] Method 200 can include delivering a preprocessing precursor to the substrate in operation 215. The preprocessing precursor can be or include a nitrogen-containing precursor or an oxygen-containing precursor. The precursor can contact the substrate and can form or introduce reactive ligands on the exposed surface of the substrate, which are shown as ligands 320 in Figure 3D . Different from conventional techniques, this technique can utilize preprocessing configured to grow high-k dielectric materials in an orderly manner in subsequent operations.

[0035] For example, in some embodiments, the substrate can be or include an exposed surface of silicon. The substrate 305 itself can be silicon, or can be some other silicon-containing material that is reduced or modified to exhibit a silicon surface. As a non-limiting example, where the substrate 305 can include silicon oxide, an initial preprocessing can include (e.g., using a hydrogen-containing precursor) removing oxygen from the surface of the structure. Then a thin silicon surface layer can be exposed. Without being bound by any particular theory, in some embodiments, silicon can provide improved fundamental properties for receiving nitrogen-containing precursors compared to silicon oxide. This can provide excellent formation of certain high-k dielectric materials.

[0036] The preprocessing precursor can be or include any nitrogen-containing or oxygen-containing precursor. The oxygen-containing precursor can be characterized by a hydroxyl group [-OH], which can be incorporated onto the surface of the substrate 305. The nitrogen-containing precursor can be characterized by an amine group [-NH2] or other nitrogen-containing groups. For example, the nitrogen-containing precursor can be or include a nitrogen- and hydrogen-containing precursor, such as ammonia as a non-limiting example, or a nitrogen- and oxygen-containing precursor, or any other precursor including nitrogen.

[0037] In some embodiments, the surface capping can be or include a hydroxyl- or amine-terminated surface. Method 200 can then include forming a high-k dielectric material over the substrate at operation 220. Although in some implementations, the forming operation 220 can be or include atomic layer deposition or any other atomic layer deposition chamber, the present technique can include any formation or deposition of high-k materials. The formation can be performed directly after preprocessing the substrate surface and can be performed in the same chamber as the preprocessing or in other chambers, such as other chambers incorporated into the same system (e.g., system 100). In some embodiments, vacuum conditions can be maintained when the substrate is transferred from the preprocessing chamber to the deposition chamber or the forming chamber, which can limit the substrate's exposure to air.

[0038] In the case of performing an atomic layer deposition process to form a high-k dielectric material, a metal-containing precursor can be delivered to the substrate to react with the preprocessed surface. For example, a transition metal-containing precursor, a metal-poor precursor, or a lanthanide metal-containing precursor can be delivered to the processing chamber to interact with the reactive ligands exposed on the substrate during preprocessing. Then an oxygen-containing precursor can be delivered in a second operation (e.g., after purging the metal-containing precursor). This can produce an oxide layer by atomic layer deposition, such as layer 330a as Figure 3E shown. In a non-limiting example, a hafnium-containing precursor can be delivered in the first operation and an oxidizer can be delivered in the second operation to produce a hafnium dioxide thin film. Additional metal-containing precursors can include zirconium-containing precursors for producing zirconium-containing materials and any number of other metal-containing precursors for producing additional metal oxide structures. For the hafnium-containing precursor, and similarly for any alternative metal, the precursor can be or include a halogen-containing precursor, an oxygen-containing precursor, a hydrogen-containing precursor, or a carbon-containing precursor in which hafnium is incorporated.

[0039] For the oxidizer, any oxygen-containing precursor that can react with the metal-containing material can be used. For example, the oxygen-containing precursor can be or include water, diatomic oxygen, ozone, a hydroxyl-containing precursor or alcohol, a nitrogen- and oxygen-containing precursor, a plasma-enhanced oxygen including locally or remotely enhanced oxygen, or any other oxygen-containing material that can bind to a metal (e.g., hafnium) to produce a layer of metal oxide material over the substrate. Again, any of the above-mentioned metal-containing materials can be used in embodiments of the present technique and can include any group of metals, which can include but are not limited to hafnium, zirconium, silicon, lanthanum, aluminum, titanium, strontium, or combinations of these materials, such as hafnium silicate.

[0040] When performing preprocessing according to an embodiment of the present technology, a structure of a metal-containing material can be formed or deposited in an orderly manner to produce a more uniform grain structure. This can be achieved by forming reactive ligands of a preprocessing precursor on a more structured surface material (such as silicon). Additionally, by performing preprocessing under certain conditions, other improvements can be provided.

[0041] The preprocessing can be carried out at a temperature configured to activate the precursor and / or the substrate surface. For example, in cases where nitrogen- and hydrogen-containing precursors can be used as preprocessing precursors, the substrate can be maintained at a temperature greater than or about 300 °C while delivering the precursor. Similarly, preprocessing can also be carried out with an oxygen-containing precursor while maintaining the substrate temperature greater than or about 300 °C. For any preprocessing operation, the substrate can also be maintained at a temperature greater than or about 400 °C, greater than or about 500 °C, greater than or about 600 °C, greater than or about 700 °C, greater than or about 800 °C, or higher. As the temperature used for preprocessing decreases to below or about 500 °C, the effectiveness may decrease. Similarly, as the temperature increases to above or about 700 °C, the nucleation property may not be improved, and excess precursors may mix into the surface, which may reduce the mobility of the device. Therefore, in some embodiments, the temperature can be maintained between about 500 °C and about 700 °C during preprocessing.

[0042] Similarly, the exposure time can affect the incorporation amount of the nitrogen-containing precursor, and thus, to limit the mobility loss of the produced device, the precursor exposure can be less than or about 3 minutes, and in some embodiments, the exposure time can be less than or about 2.5 minutes, less than or about 2 minutes, less than or about 1.5 minutes, less than or about 1 minute, less than or about 45 seconds, less than or about 30 seconds, less than or about 15 seconds, or less. Once an appropriate amount of amine groups is incorporated, the formation step can be carried out. The formation step including the atomic layer formation step can be carried out at any temperature, although in some embodiments, atomic layer deposition can be carried out at a temperature lower than or about the temperature at which preprocessing is performed, regardless of whether the operations are carried out in the same or different chambers. For example, atomic layer deposition can be performed at a second temperature relative to the preprocessing temperature, and in an embodiment, the formation temperature can be less than or about 500 °C, and can be less than or about 450 °C, less than or about 400 °C, less than or about 350 °C, less than or about 300 °C, less than or about 250 °C, or less.

[0043] After a high-k material layer has been formed or deposited, one or more post-processing operations can be performed. In some embodiments, the substrate can be transferred from the deposition chamber to another chamber or a set of chambers in optional operation 225 for post-processing the material. Similar to what was described above, the transfer can occur on a single processing system having multiple chambers, so that the transfer from any one of these chambers or between these chambers can be performed while maintaining vacuum conditions. Then, method 200 can include one or more other optional post-processing operations, as described in optional operation 230. The post-processing operations can include one or more operations performed in one or more chambers, the one or more chambers including multiple chambers on the same cluster tool. The post-processing operations can include oxidation, nitridation, and / or thermal annealing.

[0044] As described above, pre-processing operations can be performed to provide a sufficient capping portion to provide the aforementioned uniform growth while limiting the binding of excessive precursors to the substrate. For example, a combined nitrogen interface can reduce the mobility of the resulting transistors, or reduce the speed at which carriers can move through the structure. Although the aforementioned pre-processing can further improve the scaling of the high-k thin film, if not controlled, the pre-processing can actually reduce the mobility of the device. However, in some embodiments, a post-processing can include oxidizing the formed high-k material using a second oxygen-containing precursor relative to the first oxygen-containing precursor that can be used in the pre-processing operation.

[0045] For example, an oxidation operation using any of the aforementioned oxygen-containing precursors can be performed to further oxidize the thin film after formation. The deposition or formation of the high-k thin film can produce a porous thin film or a thin film including vacancies in the structure. By performing the oxidation operation, oxygen species can penetrate into the thin film to fill the vacancies, as shown in layer 330b, and produce an oxide material at the interface of the high-k material, for example if the optional layer 320 was not formed in the previous operation described above. This can improve the lower interface from amine end groups, which can increase the mobility of the device. To limit the excessive increase of the underlying oxide layer, the oxidation operation can be performed for a limited period of time, and the oxidation operation can be performed within any of the previously mentioned time ranges.

[0046] Post-processing operations (when used) may additionally include further contacting the substrate with a second nitrogen-containing precursor relative to the pre-processed nitrogen-containing precursor. The second nitrogen-containing precursor may include any of the nitrogen-containing precursors described above and may include nitrogen gas and any nitrogen-containing precursor mentioned elsewhere. The second nitrogen-containing precursor may include a plasma-activated or enhanced nitrogen-containing precursor, thermally-activated nitrogen, or some other nitrogen precursor that may allow nitrogen radicals or nitrogen atoms to be incorporated into the high-k structure, which may stabilize the film or allow the film to settle to an equilibrium state. Unlike the oxidation operation, nitridation may not increase the thickness of the underlying layer (such as silicon oxide), and may also slightly increase the k-value of the resulting film.

[0047] To maintain structural and electrical properties, the incorporation of nitrogen can be controlled to limit the incorporation in the film. In some embodiments, post-processing nitridation may incorporate less than or about 20 atomic % nitrogen in the surface region of the high-k film, and may incorporate less than or about 15 atomic % nitrogen, less than or about 10 atomic % nitrogen, less than or about 8 atomic % nitrogen, less than or about 6 atomic % nitrogen, less than or about 4 atomic % nitrogen, less than or about 2 atomic % nitrogen, or less. In some embodiments, an incorporation between about 3 atomic % and about 7 atomic % may maintain a higher k-value compared to a higher nitrogen incorporation and may better stabilize the film compared to a lower nitrogen incorporation. The surface region may refer to the exposed surface of the material (although the incorporation of nitrogen may extend any distance into the film and may be uniform or form a gradient that decreases through the material).

[0048] Post-processing oxidation or nitridation may be performed at any of the temperatures mentioned previously, although in some embodiments, post-processing oxidation or nitridation may be performed in a temperature range below or about 500 °C, and depending on the operation performed, may be performed in a temperature range below or about 400 °C, below or about 300 °C, below or about 200 °C, below or about 100 °C, or lower.

[0049] Post-processing annealing can be performed after any operation, including any of the post-processing operations described above. Post-processing annealing can be performed in any chamber in which a previous operation was performed, or can involve transfer to a different chamber, such as a chamber configured to perform rapid thermal annealing processing. Again, the chamber can be combined with other chambers on the same platform, which can allow transfer between chambers while maintaining vacuum conditions. Post-processing annealing can further align film bonding and further stabilize the film. In an embodiment, post-processing annealing can be performed at a third temperature relative to a first temperature, where the third temperature can be above or about the first temperature. For example, post-annealing can be performed at a temperature above or about 400 °C, and in embodiments can be performed at a temperature above or about 500 °C, above or about 600 °C, above or about 700 °C, above or about 800 °C, above or about 900 °C, or higher.

[0050] By performing pre-processing and / or post-processing according to embodiments of the present technology, improved high-k materials can be produced. The high-k material layer can be generated to have any thickness up to or about a few nanometers. However, due to the preferred grain structure produced by the present technology, a thinner effective oxide thickness can be produced without loss of gate leakage performance. The high-k material produced according to the present technology can be characterized as having a k value greater than or about 10, and can be characterized as having a k value greater than or about 15, greater than or about 20, greater than or about 21, greater than or about 22, greater than or about 23, greater than or about 24, greater than or about 25 or greater.

[0051] As described above, compared to conventional techniques, the present technology also allows for improved dielectric constants. Additionally, due to the grain structure produced, the gate leakage current associated with the film can be less than or about one-tenth of the gate leakage current of a silicon oxide film of a similar thickness, and the gate leakage current can be less than or about one-hundredth of the gate leakage current of a silicon oxide film of a similar thickness, less than or about one-thousandth of the gate leakage current of a silicon oxide film of a similar thickness, less than or about 1 / 5,000 of the gate leakage current of a silicon oxide film of a similar thickness, less than or about 1 / 10,000 of the gate leakage current of a silicon oxide film of a similar thickness, less than or about 1 / 20,000 of the gate leakage current of a silicon oxide film of a similar thickness, less than or about 1 / 50,000 of the gate leakage current of a silicon oxide film of a similar thickness, less than or about 1 / 100,000 of the gate leakage current of a silicon oxide film of a similar thickness or less. By producing a film according to an embodiment of the present technology, a shaped film with beneficial morphology can be produced, which can enhance the electrical properties of the film compared to conventional techniques.

[0052] In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of the various embodiments of the present technology. However, it will be apparent to one of ordinary skill in the art that some of these details may not be required or that other details may be practiced in certain embodiments.

[0053] Several embodiments have been disclosed, and those of ordinary skill in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, in order to avoid unnecessarily obscuring the present technology, many known processes and elements have not been described. Accordingly, the foregoing description should not be regarded as limiting the scope of the present technology.

[0054] Where a range of values is provided, it is to be understood that each intervening value, to the smallest fraction of the lower unit of the lower limit, between the upper and lower limits of that range is specifically disclosed, unless the context clearly dictates otherwise. Any narrower range between any of the stated values or unstated intervening values in the stated range, as well as any other stated or intervening value within the stated range, is also encompassed within the technology. The upper and lower limits of these smaller ranges may independently be included or excluded from the range, and each range where either, or both, of the limiting values are included or excluded in the smaller range is also included within the technology, subject to any specific exclusionary limitation stated in the stated range. Where the stated range includes one or both of the limiting values, ranges excluding either or both of those included limiting values are also included.

[0055] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a layer" includes a plurality of such layers, and reference to "a precursor" includes reference to one or more precursors known to those of ordinary skill in the art and their equivalents, and so forth.

[0056] Also, as used in this specification and the appended claims, the words "comprise(s)", "comprising", "contain(s)", "containing", "include(s)" and "including" are intended to specify the presence of the stated feature, integer, element, or operation, but they do not preclude the presence or addition of one or more other features, integers, elements, operations, acts, or groups.

Claims

1. A method of forming a semiconductor structure, the method comprising the following steps: Removing a native oxide from a surface of a substrate; Delivering dinitrogen monoxide to the substrate and thermally annealing the surface to form an oxide-containing interface; Delivering a nitrogen-containing precursor or an oxygen-containing precursor to the substrate; Introducing a reactive ligand at the oxide-containing interface using the nitrogen-containing precursor or the oxygen-containing precursor while maintaining the substrate at a temperature between about 500 °C and about 700 °C, wherein the oxide-containing interface into which the reactive ligand is introduced is a surface capped with hydroxyl or amine groups; and After introducing the reactive ligand, forming a high-k dielectric material covering the oxide-containing interface.

2. The method of forming a semiconductor structure according to claim 1, wherein, The removing step comprises an in-situ dry chemical treatment, wherein the removing step is performed in a first processing chamber, and wherein the method further comprises the following steps: before forming the high-k dielectric material, transferring the substrate from the first processing chamber to a second processing chamber.

3. The method of forming a semiconductor structure according to claim 1, wherein dinitrogen monoxide is delivered to the substrate and the surface is thermally annealed to form an oxide-containing interface having a thickness up to about 5 angstroms.

4. The method of forming a semiconductor structure according to claim 1, further comprising the following step: after forming the high-k dielectric material, performing a thermal annealing.

5. The method of forming a semiconductor structure according to claim 1, wherein the step of forming the high-k dielectric material comprises the following steps: performing an atomic layer deposition process using a metal halide and water.

6. The method of forming a semiconductor structure according to claim 1, wherein, The nitrogen-containing precursor comprises ammonia.

7. The method of forming a semiconductor structure according to claim 1, wherein, The high-k dielectric material comprises at least one element selected from the group consisting of hafnium, zirconium, silicon, lanthanum, aluminum, titanium, and strontium.

8. A method of forming a semiconductor structure, the method comprising the following steps: Removing a native oxide from a surface of a substrate contained in a first semiconductor processing chamber; Transferring the substrate to a second semiconductor processing chamber without breaking the vacuum condition; Delivering dinitrogen monoxide to the substrate and thermally annealing the surface to form an oxide-containing interface layer in the second semiconductor processing chamber; Pre-processing the oxide-containing interface by contacting the substrate with a nitrogen-containing precursor or an oxygen-containing precursor and maintaining the substrate at a temperature between about 500 °C and about 700 °C while substantially maintaining the thickness of the oxide-containing interface layer, wherein the pre-processing is configured to introduce a reactive ligand at the oxide-containing interface layer, and wherein the oxide-containing interface layer into which the reactive ligand is introduced is a surface capped with hydroxyl or amine groups; Transferring the substrate to a third semiconductor processing chamber without breaking the vacuum condition; In the third semiconductor processing chamber containing the pre-processed substrate, forming a high-k dielectric material covering the pre-processed oxide-containing interface; Transferring the substrate to a fourth semiconductor processing chamber without breaking the vacuum condition; and Performing post-processing on the high-k dielectric material using nitrogen processing to inject between about 10% and about 20% nitrogen.

9. The method of forming a semiconductor structure according to claim 8, wherein, The removing step includes in-situ dry chemical treatment.

10. The method of forming a semiconductor structure according to claim 8, further comprising the step of performing a thermal annealing before removing the native oxide.

11. The method of forming a semiconductor structure according to claim 8, wherein, The method is performed in one or more processing chambers without exposing the surface of the substrate to the atmosphere.

12. The method of forming a semiconductor structure according to claim 8, wherein, The post-processing step includes the step of exposing the substrate and the high-k dielectric material to a nitrogen-containing precursor.

13. The method of forming a semiconductor structure according to claim 8, further comprising the step of annealing the high-k dielectric material after the post-processing step.

14. A processing system for the method of forming a semiconductor structure according to claim 1, comprising: a first processing chamber configured to deliver dinitrogen monoxide to the surface of a substrate and thermally anneal the surface to form an oxide-containing interface; a second processing chamber configured to form a high-k dielectric material covering the oxide-containing interface; a third processing chamber configured to deliver a nitrogen-containing precursor to the substrate; and a robot configured to transfer the substrate between the processing chambers without breaking the vacuum environment.

15. The processing system according to claim 14, further comprising: a fourth processing chamber configured to perform plasma treatment to remove the native oxide from the surface of the substrate; and a processing chamber configured to deliver a nitrogen-containing precursor or an oxygen-containing precursor to the substrate, wherein the processing chamber delivers the nitrogen-containing precursor or the oxygen-containing precursor to introduce a reactive ligand on the oxide-containing interface using the nitrogen-containing precursor or the oxygen-containing precursor.

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