Alignment mark structures, masks, and semiconductor structures

Abstract

Embodiments of the present application disclose an alignment mark structure, a mask plate and a semiconductor structure for a photolithography apparatus. The alignment mark structure comprises a plurality of main marks for achieving alignment in a photolithography process; each of the main marks comprises a plurality of alignment bars arranged in parallel and at intervals; and a dummy mark for matching size requirements of the photolithography apparatus; the dummy mark comprises a plurality of dot-like structures arranged in an array at intervals.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to an alignment mark structure for a lithography apparatus, a mask plate and a semiconductor structure comprising the same. BACKGROUND

[0002] In the field of semiconductor lithography, scribe lane alignment is a widely used alignment method in current lithography technology. Scribe lane, also known as cutting path, is used for scribing to cut a wafer into multiple dies (or chips). Alignment marks such as scribe lane primary marks (SPM) in the shape of long and narrow rectangles are formed in the cutting path of each layer or multiple layers, and the alignment marks in the subsequent layer can be aligned with the alignment marks in the previous layer or layers.

[0003] In related art, a scribe lane primary mark with high precision and large size has the advantages of wide capture range and strong high-order signal. However, in some specific use scenarios, when part of the grating marks are not used for lithography alignment, these grating marks are prone to introduce too many air bubbles in the bonding process, thereby affecting the bonding quality; at the same time, the flatness during chemical mechanical planarization is also affected. SUMMARY

[0004] To solve at least part of the above technical problems, embodiments of the present application provide an alignment mark structure for a lithography apparatus, comprising:

[0005] a plurality of primary marks for realizing alignment in a lithography process; each of the plurality of primary marks comprises a plurality of alignment bars arranged in parallel and spaced apart; and

[0006] dummy marks for matching the size requirement of the lithography apparatus; the dummy marks comprise a plurality of dot-shaped structures arranged in an array.

[0007] In the above scheme, the shape of the dot-shaped structure comprises a circle, a triangle or a quadrilateral.

[0008] In the above scheme, the plurality of dot-shaped structures are uniformly spaced apart, and the spacing between the dot-shaped structures is 0.5-1.5 μm.

[0009] In the above scheme, the material of the dot-shaped structure is the same as that of the alignment bars in the primary mark; and the material of the spacer between the dot-shaped structures is the same as that of the spacer in the alignment bars of the primary mark.

[0010] In the above scheme, the plurality of main marks include a first main mark, a second main mark and a third main mark arranged side by side; the third main mark and the dummy mark are located between the first main mark and the second main mark; the first main mark and the second main mark correspond to alignment bars with a width greater than that of the third main mark.

[0011] In the above scheme, the first main mark corresponds to a first alignment bar with a width of 8 μm, the plurality of first alignment bars are uniformly spaced apart with a spacing of 8 μm; the second main mark corresponds to a second alignment bar with a width of 8 μm, the plurality of second alignment bars are uniformly spaced apart with a spacing of 8.8 μm; the third main mark corresponds to a third alignment bar with a width of 1.6 μm, the plurality of third alignment bars are uniformly spaced apart with a spacing of 1.6 μm.

[0012] In the above scheme, the length of the rectangle in which the first main mark, the third main mark and the dummy mark are located is the same, and the width of the rectangle in which the first main mark, the third main mark and the dummy mark are located is the same.

[0013] The present application also provides a mask plate comprising:

[0014] a central region having a mask pattern corresponding to a circuit pattern to be formed; and

[0015] an edge region comprising one or more alignment mark structures for a lithographic apparatus as described above.

[0016] The present application further provides a semiconductor structure comprising: a plurality of functional layers; each of the plurality of functional layers comprises:

[0017] a main chip region for forming a desired circuit pattern; and

[0018] a mark region for accommodating one or more alignment mark structures for a lithographic apparatus as described above.

[0019] In the above scheme, the mark region is located in a scribe lane of the functional layer.

[0020] The embodiment of the present application provides an alignment mark structure for a photoetching device, which comprises: a plurality of main marks for realizing alignment in a photoetching process; each of the plurality of main marks comprises a plurality of alignment bars arranged in parallel and at intervals; and a dummy mark for matching size requirements of the photoetching device and not used for realizing alignment in the photoetching process; the dummy mark comprises a plurality of point structures arranged in an array at intervals. The dummy mark is arranged in the alignment mark, the dummy mark is not used for realizing alignment in the photoetching process, the size requirements of the photoetching device can be met, the dummy mark comprises a plurality of point structures arranged in an array at intervals, and the bar-shaped structure is avoided. On one hand, for the finally formed semiconductor structure to be bonded, since a circuit pattern on a wafer surface to be bonded is different, the density of the pattern of the dummy mark with the point structures arranged in an array at intervals in the mark area is closer to a plane than the density of the bar-shaped structure, the density is closer to the plane, too many air bubbles are less likely to be introduced in a bonding process, and therefore the bonding quality can be improved. On the other hand, compared with canceling the arrangement of the dummy mark, the point structures arranged in an array at intervals in the dummy mark have closer image density than the bar-shaped structure in the main mark, the burden of etching in subsequent processes caused by too large image density difference can be reduced, in the process of chemical mechanical planarization, the recess caused by the conditions of insufficient planarization or excessive planarization in the mark area due to too large density difference can be avoided, and therefore the flatness of the semiconductor structure obtained by chemical mechanical planarization during the photoetching process is better. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 A schematic diagram of an alignment mark of a large size in the related art;

[0022] Figure 2 A schematic diagram of a main mark of the embodiment of the present application; Figure 1 A schematic diagram of the relationship of different grating sizes in the embodiment of the present application;

[0023] Figure 3 A schematic diagram of an alignment mark structure for a photoetching device provided by the embodiment of the present application;

[0024] Figure 4 A schematic diagram of a dummy mark in the embodiment of the present application; Figure 3 An enlarged partial schematic diagram of the dummy mark in the embodiment of the present application;

[0025] Figure 5 A partial schematic diagram of the distribution of point structures in a dummy mark provided by the embodiment of the present application;

[0026] Figure 6 Another partial schematic diagram of the distribution of point structures in a dummy mark provided by the embodiment of the present application;

[0027] Figure 7Another schematic view of an alignment mark structure for a lithographic apparatus according to embodiments of the invention;

[0028] Figure 8 A schematic view of a structure of a mask according to embodiments of the invention;

[0029] Figure 9 A schematic view of a semiconductor structure according to embodiments of the invention;

[0030] Figure 10 A schematic view of a wafer including a plurality of scribe lanes and dies according to embodiments of the invention. DETAILED DESCRIPTION

[0031] In order to make the objects, technical solutions and advantages of the present invention clearer, the following further describes the present invention with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and should not be used to limit the present invention.

[0032] In the description of the present invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", "left", "right", "front", "back", and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present invention and are not required to be in a specific orientation to construct and operate the present invention, and therefore should not be understood as limiting the present invention.

[0033] In the description of the present invention, when an element or layer is referred to as "on", "adjacent", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there can be an intervening element or layer. Conversely, when an element is referred to as "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part without departing from the teachings of the present application. When the second element, component, region, layer or part is discussed, it does not mean that the first element, component, region, layer or part necessarily exists.

[0034] The technical solutions of the present application can be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that the various elements are not drawn to scale and are only for the purpose of illustration, according to standard practice in the industry.

[0035] In the process of exposure by a lithography apparatus, a scribe lane master mark is widely used for alignment. In some lithography apparatuses, a large size alignment mark is used to meet the high precision alignment. Specifically, as shown in Figure 1 , Figure 1 is a schematic diagram of a large size alignment mark (AA157 type) in the related art. The alignment mark includes four grating structures, AA1-8.0, AA5, AA7, and AA1-8.8. Among them, AA1 is used to enable the lithography apparatus to capture a wafer or a die to be aligned or to perform coarse alignment.

[0036] AA1 includes two specifications of gratings, one is AA1-8.0, with a line width and a pitch of 8.0 μm (a period is a line width + a pitch, 16 μm), and a total length of 56 μm. The other is AA1-8.8, with a line width and a pitch of 8.8 μm (a period is a line width + a pitch, 17.6 μm), and a total length of 61.6 μm. In order to enable the lithography apparatus to achieve higher precision alignment, the above alignment mark further includes more precise grating structures AA5 and AA7. Among them, AA5 is used to enable the lithography apparatus to perform fine alignment on a wafer that has been coarsely aligned, with a plurality of line widths and pitches of (a period is a line width + a pitch, ), and a total length of 56 μm. AA7 is used for further alignment, with a plurality of line widths and pitches of (a period is a line width + a pitch, ), and a total length of 56 μm. The size relationship of different gratings in the alignment mark is shown in Figure 2 , Figure 2 is a schematic diagram of the size relationship of different gratings in Figure 1 , in which the line width of the AA1 grating is equivalent to the line width of 5 AA5 gratings, or equivalent to the line width of 7 AA7 gratings. Since the line width and the pitch of each group of gratings are equal, their respective pitches also satisfy the above relationship. It should be noted that, for the purpose of intuitive comparison, Figure 2 , the size of the gratings and their proportions are simply illustrated and are not drawn to scale.

[0037] In some process procedures, only the three groups of gratings AA1-8.0, AA5, and AA1-8.8 can meet the alignment requirements. In other words, without using the AA7 grating for alignment, the products processed by the lithography apparatus can meet the requirements in terms of performance and yield, etc.

[0038] However, the AA7 grating not used for alignment is not used for alignment, but in the actual lithography process, the groove-shaped structure corresponding to the AA7 grating will still be formed in the scribe lane of the wafer. The groove-shaped structure will cause excessive air bubbles to be introduced in the bonding process, thereby affecting the bonding quality; meanwhile, it is easy to affect the flatness during chemical mechanical planarization.

[0039] In some embodiments, the grating mark not used in the alignment mark, such as the aforementioned AA7 grating not used for alignment, is removed to avoid the adverse effects caused by the unused grating. However, at this time, the grating mark removed is easy to cause a large difference between the pattern density of the scribe lane and the density of the main chip area used to form the required circuit pattern, and the large difference makes the finally formed semiconductor structure to be bonded easy to introduce excessive air bubbles in the bonding process, thereby affecting the bonding quality; meanwhile, the large difference is also not conducive to the flatness control during chemical mechanical planarization.

[0040] Based on this, the embodiments of the present application provide an alignment mark structure for a lithography device, as shown in Figure 3 As shown, the alignment mark 30 comprises:

[0041] a plurality of main marks 301 for realizing alignment in a lithography process; each of the plurality of main marks comprises a plurality of alignment bars arranged in parallel and at intervals; and

[0042] a dummy mark 302 for matching the size requirement of the lithography device; the dummy mark comprises a plurality of dot-shaped structures arranged in an array at intervals.

[0043] The lithography device involved in the embodiments of the present application can include a step-and-scan lithography device (Scanner), in the exposure process of the step-and-scan lithography device, the mask pattern is not exposed and imaged at one time, but is imaged through the scanning movement of the projection light field. In the imaging process of the mask pattern, the mask and the wafer are moved relative to the projection system and the projection light beam at the same time, and the wafer exposure is completed.

[0044] Here, the alignment mark structure for the lithography device is mainly applied in the scribe groove alignment mode.

[0045] Here, the main mark 301 is used to realize alignment in the lithography process. The main mark 301 can comprise a grating, and the plurality of main marks 301 can comprise a plurality of different levels of gratings. Here, the different levels can be understood as different periods of the gratings. Based on this, the alignment mode adopted by the lithography device is grating alignment.

[0046] In practical applications, grating alignment refers to the diffraction of illumination light that does not strike the grating-type alignment mark. The diffracted light carries all the information about the alignment mark's structure. Multiple orders of diffracted light scatter from the phase alignment grating at different angles. After filtering out the zero-order light with a spatial filter, ±1st-order diffracted light is collected. Alternatively, as size requirements increase, multiple orders of diffracted light (including higher orders) are simultaneously collected and interferometrically imaged on a reference plane. The image is then scanned in a certain direction with the corresponding reference grating. After detection by a photodetector and signal processing, the alignment center position is determined.

[0047] In some embodiments, multiple master markers 301 can be arranged side by side. In some embodiments, the number of master markers can be multiple, for example, 2 to 4. In a specific embodiment, the number of master markers is 3. Here, the dummy marker 302 is not used to achieve alignment in the photolithography process. The dummy marker 302 is used to match the size requirements of the photolithography equipment, and also to match the size requirements of the scribing groove. Here, the use of the dummy marker 302 to match the size requirements of the photolithography equipment can be understood as matching that when the dummy marker 302 is not present, the photolithography equipment cannot perform normal scanning and alignment.

[0048] In practical applications, the dummy marker 302 may include multiple dot-like structures arranged in an array.

[0049] In practical applications, the shape of the dot-like structure can include various shapes, including regular or irregular shapes. In some embodiments, the shape of the dot-like structure includes a circle, a triangle, or a quadrilateral. In some specific embodiments, the shape of the dot-like structure can include a square, a rectangle, or a rhombus, etc.

[0050] For example, Figure 4 The diagram shows a dotted structure that includes squares; Figure 5 The diagram shows the case where the dotted structure includes a circle; Figure 6 The diagram illustrates the case where a point-like structure includes triangles.

[0051] In practical applications, the arrangement of the dot-like structures can include various methods. In some embodiments, the arrangement can include a rhomboid arrangement, a triangular arrangement, or a square arrangement.

[0052] For example, such as Figure 4 As shown, Figure 4 The lines connecting the centers of the square dot structures X1, X2, X3, and X4 form a rhombus.

[0053] For example, such as Figure 5 As shown, Figure 5 The line connecting the centers of the circular point structures C1, C2, and C3 forms an equilateral triangle.

[0054] As shown in Figure 6 , Figure 6 the line connecting the centers of the triangular dot-like structures T1, T2, T3, T4 in the main mark is a square.

[0055] In some embodiments, the plurality of dot-like structures are evenly spaced apart, and the spacing δ between the dot-like structures satisfies: 0.5 μm≤δ≤1.5 μm. In some embodiments, δ = 1 μm.

[0056] In some embodiments, the material of the dot-like structures is the same as the material of the alignment bars in the main mark; the material of the spacers between the dot-like structures is the same as the material of the spacers between the alignment bars in the main mark.

[0057] In practical applications, in the process of a series of semiconductor processes, taking the case of alignment marks located in the metal layer of a semiconductor as an example, if the alignment bars in the main mark are formed of metal and the material of all the spacers between the alignment bars can include an oxide, the material of the dot-like structures can be the same metal, and the material of the spacers between the dot-like structures can be the same oxide.

[0058] In one embodiment, the alignment mark structure for a lithographic apparatus includes three main marks, i.e., a first main mark, a second main mark, and a third main mark and a dummy mark, wherein the third main mark and the dummy mark are located between the first main mark and the second main mark; the width of the alignment bars corresponding to the first main mark and the second main mark is greater than the width of the alignment bars corresponding to the third main mark.

[0059] In some embodiments, as shown in Figure 7 , the first main mark can be AA1-8.0, the second main mark can be AA1-8.8, the third main mark can be AA5, and the dummy mark can be D1. Here, the first main mark AA1-8.0 and the second main mark AA1-8.8 are respectively located on the two sides of the alignment mark, while the third main mark AA5 and the dummy mark D1 are respectively located in the middle region of the alignment mark, so the first main mark AA1-8.0 and the second main mark AA1-8.8 are located on the two sides of the third main mark AA5 and the dummy mark D1. The first main mark AA1-8.0, the second main mark AA1-8.8, and the third main mark AA5 are respectively composed of different gratings, and they have different functions, so they have different grating structures. In some embodiments, the width of the alignment bars corresponding to the first main mark AA1-8.0 and the second main mark AA1-8.8 is greater than the width of the alignment bars corresponding to the third main mark AA5.

[0060] In some embodiments, the first alignment bars corresponding to the first main mark AA1-8.0 have a width of 8 μm, the first alignment bars are uniformly spaced apart, and the spacing between the first alignment bars is 8 μm; the second alignment bars corresponding to the second main mark AA1-8.8 have a width of 8 μm, the second alignment bars are uniformly spaced apart, and the spacing between the second alignment bars is 8.8 μm; the third alignment bars corresponding to the third main mark AA5 have a width of 1.6 μm, the third alignment bars are uniformly spaced apart, and the spacing between the third alignment bars is 1.6 μm. Here, the first main mark AA1-8.0 and the third main mark AA5 have a more visual proportional relationship, which can be combined with Figure 2 wherein the width of the first alignment bars corresponding to the first main mark AA1-8.0 is 5 times the width of the third alignment bars corresponding to the third main mark AA5, i.e., when the width of the first alignment bars corresponding to the first main mark AA1-8.0 is 8 μm, the width of the third alignment bars corresponding to the third main mark AA5 is 1.6 μm.

[0061] As mentioned above, the first main mark AA1-8.0 and the second main mark AA1-8.8 are preferably gratings that can both achieve coarse alignment, and in order to distinguish the direction of the alignment marks, the spacing between the alignment bars corresponding to the two marks preferably has a slight difference. In some embodiments, the spacing between the first alignment bars is 8 μm, and the spacing between the second alignment bars is 8.8 μm.

[0062] In some embodiments, as Figure 7 For the sizes of the first main mark, the third main mark, and the dummy mark, the projection size in the alignment marks is the same, i.e., in the direction of the long side of the elongated alignment mark, the length of the first main mark AA1-8.0, the third main mark AA5, and the dummy mark D1 is the same.

[0063] In some embodiments, in the direction of the short side of the elongated alignment mark, the width of the rectangle in which the first main mark AA1-8.0, the third main mark AA5, and the dummy mark D1 are located is the same.

[0064] In one embodiment, the length of the three is equivalent to 7 times the spacing (8 μm) between the first alignment bars corresponding to the first main mark, i.e., 56 μm, and the width of the three is 72 μm.

[0065] This invention provides an alignment mark for a photolithography apparatus, comprising: multiple main marks for alignment in the photolithography process; each main mark includes multiple parallel and spaced alignment gates; and dummy marks for matching the size requirements of the photolithography apparatus and not for alignment in the photolithography process; the dummy marks include multiple dot-like structures arranged in an array at intervals. This invention incorporates dummy marks within the alignment mark, which are not used for alignment in the photolithography process, thus meeting the size requirements of the photolithography apparatus. The dummy marks, including multiple dot-like structures arranged in an array at intervals, avoid the use of gate-like structures. On the one hand, for the final semiconductor structure to be bonded, this avoids introducing excessive air bubbles during the bonding process, thereby improving bonding quality. On the other hand, it allows for better flatness of the semiconductor structure obtained by chemical mechanical planarization during the photolithography process.

[0066] This invention also provides a photomask, comprising:

[0067] The central region has a mask pattern corresponding to the circuit pattern to be formed; and

[0068] The edge region includes the alignment mark structure used in the photolithography equipment.

[0069] The following will combine Figure 8 A detailed description of the mask plate 400 in an embodiment of the invention. Figure 8 This is a schematic diagram of a mask 400 according to an embodiment of the invention. The mask 400 includes a central region A and edge regions B. It can be understood that the central region A may include multiple edge regions B around it. For ease of explanation, only one edge region B is shown in the figure.

[0070] The central region A contains a mask pattern corresponding to the circuit pattern to be formed, and the edge region B, which is a non-circuit pattern region, includes an alignment mark structure 200 for a photolithography apparatus according to an embodiment of the present invention.

[0071] It should be noted that, Figure 8 The mask shown is merely schematic according to an embodiment of the present invention. The dimensions of the central region A and the edge region B of the mask, as well as the alignment mark structure 200 for the photolithography apparatus, are not drawn according to actual applications. In reality, the dimensions of the alignment mark structure 200 for the photolithography apparatus relative to the central region A are much smaller than those shown.

[0072] In the space allowed in the edge area B of the mask plate 400, a plurality of alignment mark structures 200 for a lithography apparatus according to embodiments of the present application can be placed. In some embodiments, alignment marks 200 arranged perpendicularly to each other can be simultaneously fabricated on one mask plate 400, and then it is decided according to the process requirement which alignment mark should be used to implement alignment.

[0073] Embodiments of the present application also provide a semiconductor structure, comprising: a plurality of functional layers; each of the plurality of functional layers comprises:

[0074] a main chip area for forming a required circuit pattern; and

[0075] a mark area for accommodating one or more alignment mark structures 200 for a lithography apparatus as described above.

[0076] Figure 9 For the schematic diagram of the functional layer according to embodiments of the present application, the semiconductor structure with the alignment mark according to embodiments of the present application will be described below. Figure 9

[0077] The semiconductor structure generally comprises a plurality of functional layers. Figure 9 Any one of the plurality of functional layers will be shown in the following description, and hereinafter, the functional layer will be referred to as 500 in general without specific reference to a certain functional layer. Each functional layer 500 comprises a main chip area X and a mark area Y Figure 9 which comprises mark sub-areas Y1 and Y2, and the main chip area X forms a required circuit pattern after exposure and development. The mark area Y can be used to accommodate one or more alignment mark structures 200 for a lithography apparatus Figure 9 which comprises 200-1 and 200-2, and the alignment mark 200 has been described in detail above and will not be described here again.

[0078] It should be noted that, Figure 9 The semiconductor structure according to embodiments of the present application is only schematically shown, and the size ratio of the main chip area X and the mark area Y of the functional layer 500 and the alignment mark structure 200 for a lithography apparatus is not drawn according to the actual application. In fact, the size ratio of the alignment mark structure 200 for a lithography apparatus and the main chip area X and the mark area Y is much smaller than the shown case.

[0079] As Figure 9 shown in one embodiment, the two mark sub-areas Y1 and Y2 of the functional layer 500 are located in the area adjacent to the chip area X, and the two mark sub-areas Y1 and Y2 are perpendicular to each other. In one embodiment, the mark area Y can be composed of a plurality of mark sub-areas, and these mark sub-areas are distributed in at least two independent areas of the functional layer 500, preferably in at least two adjacent areas perpendicular to each other. As​Figure 9 As shown in the example in FIG. 5, the marking area Y is composed of a first marking sub-area Y1 and a second marking sub-area Y2, and the first marking sub-area Y1 and the second marking sub-area Y2 are respectively located at the left side and the upper side of the functional layer 500. In other examples, the first marking sub-area Y1 and the second marking sub-area Y2 can also be respectively located at the right side and the lower side of the functional layer 500.

[0080] In some embodiments, the marking area is located in the scribe lane of the functional layer.

[0081] Here, Figure 10 FIG. 6 is a schematic diagram of a wafer including a plurality of scribe lanes and dies, in which the scribe lanes L are located between adjacent dies Q in the wafer W.

[0082] It can be understood that the above-mentioned marking area can be located in the horizontal and / or vertical scribe lane L.

[0083] By providing the semiconductor structure of the present application, in particular, by providing the alignment mark of the embodiment of the present application in the marking area in the scribe lane of the functional area of the semiconductor structure, the photolithography equipment can easily realize the alignment of the semiconductor structure, facilitate the subsequent process, and thus improve the yield.

[0084] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An alignment mark structure for a lithographic apparatus, characterized in that, Comprising: a plurality of main marks for achieving alignment in a lithography process; each of the plurality of main marks comprising a plurality of alignment bars arranged in parallel and at intervals; and dummy marks for matching size requirements of the lithography apparatus; the dummy marks comprising a plurality of dot-like structures arranged in an array at intervals; the plurality of main marks comprising a first main mark, a second main mark and a third main mark arranged side by side; the third main mark and the dummy marks being located between the first main mark and the second main mark; the widths of the alignment bars corresponding to the first main mark and the second main mark being greater than the width of the alignment bars corresponding to the third main mark; and the intervals of the alignment bars corresponding to the first main mark being different from the intervals of the alignment bars corresponding to the second main mark.

2. The alignment mark structure for a lithographic apparatus according to claim 1, characterized in that, The shapes of the dot-like structures comprise circles, triangles or quadrilaterals.

3. The alignment mark structure for a lithographic apparatus according to claim 2, characterized in that, The plurality of dot-like structures are uniformly spaced apart, and the intervals δ between the dot-like structures satisfy: 0.5 μm ≤ δ ≤ 1.5 μm.

4. The alignment mark structure for a lithographic apparatus according to claim 2, characterized in that, The materials of the dot-like structures are the same as the materials of the alignment bars in the main marks; and the materials of the spacers between the dot-like structures are the same as the materials of the spacers of the alignment bars in the main marks.

5. The alignment mark structure for a lithographic apparatus according to claim 1, characterized in that, The widths of the first alignment bars corresponding to the first main mark are 8 μm, the plurality of first alignment bars are uniformly spaced apart, and the intervals between the first alignment bars are 8 μm; The widths of the second alignment bars corresponding to the second main mark are 8 μm, the plurality of second alignment bars are uniformly spaced apart, and the intervals between the second alignment bars are 8.8 μm; The widths of the third alignment bars corresponding to the third main mark are 1.6 μm, the plurality of third alignment bars are uniformly spaced apart, and the intervals between the third alignment bars are 1.6 μm.

6. The alignment mark structure for a lithographic apparatus according to claim 5, wherein, The lengths of the rectangles in which the first main mark, the third main mark and the dummy marks are located are the same, and the widths of the rectangles in which the first main mark, the third main mark and the dummy marks are located are the same.

7. A mask, characterized in that Comprising: a central region having a mask pattern corresponding to a circuit pattern to be formed; and an edge region comprising one or more alignment mark structures for a lithography apparatus as claimed in any one of claims 1-6.

8. A semiconductor structure, characterized by Comprising: a plurality of functional layers; each of the plurality of functional layers comprising: a main chip region for forming a required circuit pattern; and a mark region for accommodating one or more alignment mark structures for a lithography apparatus as claimed in any one of claims 1-6.

9. The semiconductor structure of claim 8, wherein, The mark region is located in a scribe lane of the functional layer.

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