Plc system capable of automatically assigning addresses and control method thereof

Abstract

The application discloses a PLC system capable of automatically allocating addresses and a control method thereof, and belongs to the field of PLC systems.The PLC system capable of automatically allocating addresses comprises a main controller, N I / O modules and an LCD display, the N I / O modules are connected in series, the first I / O module is connected with the main controller, the first I / O module is connected with the LCD display, and N is greater than or equal to 2; wherein each I / O module comprises a single-chip microcomputer and a backplane bus, the single-chip microcomputer is connected with the backplane bus, and the single-chip microcomputer can automatically allocate addresses to the I / O module according to a frequency division signal output by the backplane bus.The application can not only simplify wiring, but also automatically allocate addresses to the I / O module, thereby improving the stability of system operation.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a PLC system capable of automatically allocating addresses and a control method thereof. Background Art

[0002] Programmable logic controller (PLC) systems typically use a star-shaped architecture, where the PLC master controller is connected to multiple I / O modules simultaneously. The PLC accesses each independent I / O module via an RS485 or CAN bus. In this architecture, each I / O module requires its own power supply, and the PLC master controller must assign an address to each independent I / O module before accessing it.

[0003] There are two existing ways to assign addresses to I / O modules: (1) using a DIP switch method, in which the address of each I / O module is set by rotating the DIP switch. When the I / O module is powered on, the status of each pin of the DIP switch is first sampled and then resolved into the address of the I / O module; (2) using a communication setting method, in which a PC or other host is connected to the I / O module through a serial port, and the "address" to be configured is sent to the "I / O module". The "I / O module" saves the received "address" into its own FLASH.

[0004] The above two address allocation methods have at least the following shortcomings:

[0005] (1) The PLC main controller is connected to multiple I / O modules through a bus. The physical wiring requires additional "wiring blocks" to connect the PLC main controller bus to the I / O modules, which makes the wiring complex and unsightly.

[0006] (2) When there are a large number of I / O modules, the data on the bus is busy, and the PLC main controller needs to allocate a large amount of resources to be responsible for polling data, receiving data, and processing data, which adds uncontrollable factors to the operation of the system and increases the risk of instability.

[0007] (2) During on-site installation, each I / O module needs to be manually configured with an address based on on-site requirements. This will inevitably lead to duplicate or incorrect address settings, which in turn will cause system operation errors. Summary of the Invention

[0008] The technical problem to be solved by the present invention is: in order to solve the technical problem that the way of connecting the PLC main controller with multiple I / O modules in the existing technology is complicated in wiring and may lead to unstable system operation, the present invention provides a PLC system capable of automatically assigning addresses and a control method thereof, which can not only simplify the wiring, but also automatically assign addresses to I / O modules, thereby improving the stability of system operation.

[0009] The present invention solves the technical problem by adopting a technical solution: a PLC system capable of automatically assigning addresses, comprising: a main controller, N I / O modules, and an LCD display, wherein the N I / O modules are connected in series, with the first I / O module connected to the main controller and the second I / O module connected to the LCD display, where N is greater than or equal to 2. Each I / O module includes a single-chip microcomputer and a backplane bus, the single-chip microcomputer being connected to the backplane bus, and capable of automatically assigning addresses to the I / O modules based on a frequency-divided signal output by the backplane bus. This not only simplifies wiring but also automatically assigns addresses to I / O modules, improving the stability of system operation.

[0010] Furthermore, the backplane bus includes a power supply module, a communication module and a frequency division module. The power supply module is connected to the communication module, and the power supply module is connected to the frequency division module.

[0011] Furthermore, each of the I / O modules further includes an input connector XS1 and an output connector XS2, wherein the input connector XS1 is connected to the communication module, the input connector XS1 is connected to the frequency division module, and the frequency division module is connected to the output connector XS2.

[0012] Furthermore, the communication module includes a communication chip U2, and the communication chip U2 has an RO pin, a RE pin, a DE pin, a DI pin, a first GND pin, an A output end, a B output end and a first VCC pin. The RO pin, RE pin, DE pin and DI pin are all connected to the microcontroller, the RE pin is connected to the DE pin, the first GND pin is grounded, the first VCC pin is connected to the power module, and the A output end and the B output end are both connected to the input connector XS1.

[0013] Furthermore, the frequency division module includes a frequency division chip U1, the frequency division chip U1 has a CLK pin, a second GND pin, an input pin D, an output pin Q, a second VCC pin and a CLR pin, the CLK pin is connected to the input connector XS1, the CLR pin and the second VCC pin are both connected to the power module, the second GND pin is grounded, the input pin D is connected to the output pin Q, and the output pin Q is connected to the output connector XS2.

[0014] Furthermore, the frequency division module also includes a resistor R46, a resistor R48, a transistor V4, a diode VD14 and a resistor R44, one end of the resistor R48 is connected to the input pin D, the other end of the resistor R48 is connected to the cathode of the diode VD14, the anode of the diode VD14 is grounded, one end of the resistor R46 is connected to the output pin Q, the other end of the resistor R46 is connected to the base of the transistor V4, the collector of the transistor V4 is connected to one end of the resistor R44, the emitter of the transistor V4 is connected to the anode of the diode VD14, the cathode of the diode VD14 is connected to the collector of the transistor V4, and the other end of the resistor R44 is connected to the output connector XS2.

[0015] Furthermore, the CLK pin of the frequency dividing chip U1 of the first I / O module is connected to the single chip microcomputer, and the frequency dividing chip U1 of the first I / O module can receive an initial frequency f1.

[0016] The present invention also provides a control method for a PLC system capable of automatically allocating addresses, comprising the following steps:

[0017] S1. The first I / O module is marked as the master module. Each I / O module can collect data. When N I / O modules are powered on, the microcontroller of the I / O module can read the frequency-divided signal output by the backplane bus. The microcontroller automatically assigns the corresponding address to the I / O module based on the frequency-divided signal.

[0018] S2: The first I / O module receives a control signal from the main controller, and the first I / O module can send the control signal to the second to Nth I / O modules respectively through the communication protocol; the first I / O module can receive data information collected by the second to Nth I / O modules respectively through the communication protocol, and send the data information to the main controller after aggregation;

[0019] S3. The first I / O module sends the aggregated data information to the LCD display for display.

[0020] Furthermore, in step S1, the single chip microcomputer automatically assigns a corresponding address to the I / O module according to the frequency division signal, specifically including:

[0021] The first I / O module can generate an initial frequency f1. The initial frequency f1 is output from the output pin Q of the frequency dividing chip U1 to the first frequency dividing signal f1 / 2. The first frequency dividing signal f1 / 2 is input to the second I / O module. The output pin Q of the second I / O module outputs the second frequency dividing signal f1 / 4. And so on. The output pin Q of the N-1th I / O module outputs the N-1th frequency dividing signal f1 / 2. N-1, the N-1th frequency division signal f1 / 2 N-1 Input to the Nth I / O module, the Nth I / O module outputs the Nth frequency division signal f1 / 2 N ;

[0022] Each frequency division signal corresponds to an address. When the I / O module is powered on, each I / O module can generate a corresponding frequency division signal. The microcontroller assigns the corresponding address to the I / O module by reading the frequency division signal.

[0023] The beneficial effect of the present invention is that the present invention cascades N I / O modules through the backplane bus, which, on the one hand, facilitates wiring and improves the overall aesthetics of the system; on the other hand, the single-chip microcomputer can automatically assign addresses to the I / O modules by identifying the divided frequency signals output by the corresponding I / O modules, which not only improves work efficiency but also reduces errors caused by human factors and ensures the accuracy of the PLC system operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention will be further described below with reference to the accompanying drawings and examples.

[0025] Figure 1 It is a schematic structural diagram of a PLC system capable of automatically allocating addresses according to the present invention;

[0026] Figure 2 It is a structural diagram of the I / O module of the present invention;

[0027] Figure 3 It is a structural diagram of the backplane bus of the present invention;

[0028] Figure 4 It is a circuit schematic diagram of the backplane bus of the present invention;

[0029] Figure 5 The present invention is a flow chart of a control method of a PLC system capable of automatically allocating addresses.

[0030] In the figure: 1. Main controller; 2. I / O module; 3. LCD display; 21. Microcontroller; 22. Backplane bus; 221. Power module; 222. Communication module; 223. Frequency division module. DETAILED DESCRIPTION

[0031] The present invention will now be described in further detail with reference to the accompanying drawings, which are simplified schematic diagrams that illustrate the basic structure of the present invention in a schematic manner.

[0032] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, features defined as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0033] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0034] like Figures 1 to 4As shown, a PLC system capable of automatically assigning addresses includes: a main controller 1, N I / O modules 2, and an LCD display 3. The N I / O modules 2 are connected in series, with the first I / O module 2 connected to the main controller 1, and the first I / O module 2 connected to the LCD display 3, where N ≥ 2. Each I / O module 2 includes a single-chip microcomputer 21 and a backplane bus 22. The single-chip microcomputer 21 is connected to the backplane bus 22, and the single-chip microcomputer 21 is capable of automatically assigning addresses to the I / O modules 2 based on the frequency-divided signal output by the backplane bus 22. In other words, in this embodiment, the first I / O module 2 is connected to the second I / O module 2, the second I / O module 2 is connected to the third I / O module 2, and so on, until the N-1th I / O module 2 is connected to the Nth I / O module 2. Each I / O module 2 can be connected to a sensor device to collect data collected by the sensor device, and can also receive control signals issued by the main controller 1 to regulate the sensor device. N I / O modules 2 are connected via a backplane bus 22, with only the first I / O module 2 connected to the main controller 1. The first I / O module 2 can collect data received by the second to Nth I / O modules 2 via the backplane bus 22, aggregate the data, and then send it to the main controller 1. Furthermore, the first I / O module 2 can receive control signals from the main controller 1 and then send them to the second to Nth I / O modules 2. In other words, although the present invention has multiple I / O modules 2, the main controller 1 still only transmits signals to one I / O module 2, reducing the resources occupied by the main controller 1 and improving the stability of system operation. In other words, for the main controller 1, N I / O modules 2 are equivalent to one I / O module.

[0035] In this embodiment, the backplane bus 22 includes a power module 221, a communication module 222, and a frequency divider module 223. The power module 221 is connected to the communication module 222, which in turn is connected to the frequency divider module 223. Each I / O module 2 also includes an input connector XS1 and an output connector XS2. The input connector XS1 is connected to the communication module 222, which in turn is connected to the frequency divider module 223, which in turn is connected to the output connector XS2. It should be noted that each I / O module 2 has the same structure. The communication module 222 and the frequency divider module 223 can be connected via the input connector XS1, and the first I / O module 2 can be connected to the second I / O module 2 via the output connector XS2. In this manner, N I / O modules 2 can be connected in series. The power module 221 can be, for example, a 3.3V power supply.

[0036] Specifically, communication module 222 includes a communication chip U2 having an RO pin, a RE pin, a DE pin, a DI pin, a first GND pin, an output terminal A, an output terminal B, and a first VCC pin. The RO pin, RE pin, DE pin, and DI pin are all connected to the microcontroller 21. The RE pin is connected to the DE pin. The first GND pin is grounded. The first VCC pin is connected to the power module 221. The output terminals A and B are both connected to the input connector XS1. The RO pin is used for receiving data, and the DI pin is used for sending data. Communication module 222 is capable of RS485 communication. Communication module 222 also includes a resistor R35, a transistor V3, a resistor R40, a resistor R30, a resistor R32, a resistor R38, a resistor R41, a resistor R33, a resistor R36, a resistor R31, a resistor R39, a resistor R34, a resistor R37, a diode VD12, and a diode VD13. One end of resistor R32 is connected to the microcontroller 21, and the other end of resistor R32 is connected to the RO pin. One end of resistor R30 is connected to the power module 221, and the other end of resistor R30 is connected to one end of resistor R32. One end of resistor R38 is connected to the microcontroller 21, and the other end of resistor R38 is connected to the DI pin. One end of resistor R41 is connected to the DI pin, and the other end of resistor R41 is connected to the power module 221. One end of resistor R35 is connected to the power module 221, and the other end of resistor R35 is connected to the DE pin. The emitter of transistor V3 is connected to the DE pin, the collector of transistor V3 is grounded, and the base of transistor V3 is connected to the microcontroller 21. One end of resistor R40 is connected to the base of transistor V3, and the other end of resistor R40 is connected to the collector of transistor V3. When the base input of transistor V3 is low, transistor V3 is turned on, the RE and DE pins are low, the RO pin is in the working state, and the communication chip U2 is in the receiving state. When the base input of transistor V3 is high, transistor V3 is turned off, the RE and DE pins are high, the DI pin is in the working state, and the communication chip U2 is in the transmitting state. At this time, the communication chip U2 can send signals through the A output terminal and the B output terminal. One end of resistor R33 is connected to the B input terminal, and the other end of resistor R33 is connected to the cathode of diode VD12. The anode of diode VD12 is grounded. One end of resistor R31 is grounded, and the other end of resistor R31 is connected to the cathode of diode VD12. One end of resistor R34 is connected to the cathode of diode VD12, and the other end of resistor R34 is connected to the input connector XS1. One end of the resistor R36 is connected to the A output terminal, the other end of the resistor R36 is connected to the cathode of the diode VD13, the anode of the diode VD13 is grounded, one end of the resistor R39 is connected to the cathode of the diode VD13, the other end of the resistor R39 is connected to the power module 221, one end of the resistor R37 is connected to the cathode of the diode VD13, and the other end of the resistor R37 is connected to the input connector XS1.In the communication module 222 , the resistor can play the role of current limiting and voltage dividing, so that the electronic components in the circuit can work normally, and the diode VD12 and the diode VD13 can play the role of anti-reverse.

[0037] The frequency division module 223 includes a frequency division chip U1, which has a CLK pin, a second GND pin, an input pin D, an output pin Q, a second VCC pin and a CLR pin. The CLK pin is connected to the input connector XS1, the CLR pin and the second VCC pin are both connected to the power module 221, the second GND pin is grounded, the input pin D is connected to the output pin Q, and the output pin Q is connected to the output connector XS2. Frequency divider module 223 also includes resistor R46, resistor R48, transistor V4, diode VD14, and resistor R44. One end of resistor R48 is connected to input pin D, the other end of resistor R48 is connected to the cathode of diode VD14, and the anode of diode VD14 is grounded. One end of resistor R46 is connected to output pin Q, the other end of resistor R46 is connected to the base of transistor V4, the collector of transistor V4 is connected to one end of resistor R44, the emitter of transistor V4 is connected to the anode of diode VD14, the cathode of diode VD14 is connected to the collector of transistor V4, and the other end of resistor R44 is connected to output connector XS2. Diode VD14 has a reverse feedback function.

[0038] The operating principle of the frequency divider module 223 in this embodiment is as follows: when the CLR pin is at a high level and the CLK pin receives a clock signal, data can be transmitted from input pin D to output pin Q when the clock signal on the CLK pin is on a rising edge. For example, if input pin D is "1" (i.e., a high level), output pin Q will be "1" at the first rising edge of the clock signal. At this point, transistor VD14 can be turned on, causing input pin D to become "0" (i.e., a low level). At the second rising edge of the clock signal, output pin Q outputs "0," turning off transistor VD14 and causing input pin D to become "1" again. In other words, the frequency of output pin Q is half that of the CLK pin.

[0039] In this embodiment, the frequency divider module 223 is designed to have a frequency of output pin Q that is half the input frequency. Since N I / O modules 2 are connected in series, the output frequency of the first I / O module 2 can be transmitted to the second I / O module 2. The output frequency of the second I / O module 2 is also half the input frequency (i.e., the output frequency of the first I / O module 2). Similarly, the output frequency of the Nth I / O module 2 is half the output frequency of the N-1th I / O module 2. The output frequency is the frequency-divided signal.

[0040] The CLK pin of the frequency divider chip U1 of the first I / O module 2 is connected to the single-chip microcomputer 21. The frequency divider chip U1 of the first I / O module 2 can receive an initial frequency f1. In other words, the initial frequency f1 is input to the BackBusMCU of the frequency divider module 223. The initial frequency f1 passes through the frequency divider chip U1 and can output the first frequency-divided signal f1 / 2 at the output pin Q. Please refer to Table 1. The output frequency of each I / O module 2 is different. For example, when the initial frequency is 4KHz, the output frequency of the first I / O module 2 is 2KHz, the output frequency of the second I / O module 2 is 1KHz, the output frequency of the third I / O module 2 is 500Hz, the output frequency of the fourth I / O module 2 is 250Hz, and so on. The output frequency of the eighth I / O module 2 is 15Hz (the error is within 5%). The specific number of I / O modules 2 can be set according to the size of the initial frequency f1, and the output frequency of the last I / O module 2 cannot be too small (for example, not less than 5Hz), otherwise it cannot be collected by the microcontroller 21. When N I / O modules 2 are powered on, each I / O module 2 can output a corresponding frequency-divided signal, which can be collected by the microcontroller 21 of the I / O module 2 itself. After the microcontroller 21 collects the frequency-divided signal, it can assign a corresponding address to the I / O module 2 according to the corresponding relationship (i.e., Table 2). The corresponding relationship between frequency and address has been stored in each microcontroller 21 in advance.

[0041] Table 1

[0042]

[0043] This embodiment connects N I / O modules in series and, in combination with the characteristics of frequency division module 223, enables each of the N I / O modules 2 to output different frequency division signals. The single-chip microcontroller 21 then assigns different addresses to the I / O modules 2 based on these frequency division signals. This simplifies the wiring of the PLC system and improves the overall aesthetics of the PLC system. Furthermore, the address of each I / O module 2 is automatically assigned, preventing duplicate addresses. Furthermore, this embodiment directly transmits and receives data between the first I / O module 2 and the main controller 1, reducing memory resource consumption within the main controller 1, improving the stability of the OLC system, and reducing the risk of system failure.

[0044] like Figure 5 As shown, the present invention also provides a control method for the above-mentioned PLC system capable of automatically allocating addresses, comprising the following steps:

[0045] S1. The first I / O module 2 is recorded as the main module. Each I / O module 2 can perform data acquisition. When N I / O modules 2 are powered on, the microcontroller 21 of the I / O module 2 can read the frequency-divided signal output by the backplane bus 22. The microcontroller 21 automatically assigns the corresponding address to the I / O module 2 according to the frequency-divided signal.

[0046] S2. The first I / O module 2 receives the control signal issued by the main controller 1. The first I / O module 2 can send the control signal to the second to N-th I / O modules 2 through the communication protocol; the first I / O module 2 can receive the data information collected by the second to N-th I / O modules 2 through the communication protocol, and summarize the data information and send it to the main controller 1.

[0047] S3. The first I / O module 2 sends the aggregated data information to the LCD display 3 for display.

[0048] It should be noted that the single chip microcomputer 21 automatically assigns the corresponding address to the I / O module 2 according to the frequency division signal, specifically including: the first I / O module 2 can generate an initial frequency f1, the initial frequency f1 is output from the output pin Q through the frequency division chip U1, the first frequency division signal f1 / 2 is input to the second I / O module 2, the output pin Q of the second I / O module 2 outputs the second frequency division signal f1 / 4, and so on, the output pin Q of the N-1th I / O module 2 outputs the N-1th frequency division signal f1 / 2 N-1 , the N-1th frequency division signal f1 / 2 N-1 Input to the Nth I / O module 2, the Nth I / O module 2 outputs the Nth frequency division signal f1 / 2 N Each frequency-divided signal corresponds to an address. When the I / O modules 2 are powered on, each can generate a corresponding frequency-divided signal. The microcontroller 21 reads the frequency-divided signal and assigns the corresponding address to the I / O module 2. For the corresponding technical effects, please refer to the description of the PLC system capable of automatic address assignment, which will not be repeated here.

[0049] It should be noted that, since the N I / O modules 2 of the present invention are connected in series and the first I / O module 2 collects or sends data information of the second to Nth I / O modules 2, a new communication protocol needs to be defined.

[0050] First, determine the data frame format of the communication protocol, as shown in Table 2. The device address refers to the address of I / O module 2. The address in Table 1 is expressed in hexadecimal and can be converted into binary representation (i.e. 8 bits). The function number can be set to 0x2B and 0x2C. 0x2B indicates that the host sends a command, and 0x2C indicates that the slave replies to a command. The data format indicates the data representation format collected or received by the I / O module. CRC check L and CRC check H are used to verify whether the received data is correct. If the verification is correct, the next step can be performed.

[0051] Table 2

[0052] Device Address Function Code Data Frame CRC check L CRC check H 8bit 8bit n*8bit 8bit 8bit

[0053] The data transmission and reception protocol between the main I / O module 2 and other I / O modules 2 can be set as:

[0054] Each AI / AO channel's data occupies 2 bytes, with one byte containing 8 bits, arranged in low-endian order. Each DI / DO channel occupies 1 bit, with bit 0 representing the low-end port number. DI stands for digital signal input, DO for digital signal output, AI for analog signal input, and AO for analog signal output.

[0055] If the main I / O module 2 sends data to other I / O modules 2, the meaning of the first byte in the data frame is: Bit0: whether the main I / O module has DO control data to send to other I / O modules (1 indicates DO data, 0 indicates no DO data); Bit1: whether the main I / O module has AO control data to send to other I / O modules (1 indicates AO data, 0 indicates no AO data) Bit2 to Bit7: reserved.

[0056] If Bit 0 and Bit 1 of Byte 1 of the data frame are both 1, the DO data is transmitted first, followed by the AO data. Starting from Byte 2 of the data frame, the channel counts of the DO (available only when Bit 0 of Byte 1 of the data frame is 1) and the channel count of the AO (available only when Bit 1 of Byte 1 of the data frame is 1) are displayed. The remaining bits of Byte 2 represent the data for each DO and AO, respectively. The receiver must verify the relationship between the total number of bytes, number of channels, and number of data in the data frame according to the protocol before setting the local DO and AO. It should be noted that only after the master I / O module has read the data from another I / O module and based on the data it responds to, can the master I / O module determine the channel count of the DI / AI / DO / AO of that other I / O module.

[0057] For example,

[0058] Example 1: The main I / O module reads the second I / O module and needs to send the data: Ox01 0x2B 0x00 0x3E 0xF0, then:

[0059] Device Address Function Code Data Frame CRC check L CRC check H 0x01 0x2B 0x00 0x3E 0xFO

[0060] Example 2: The main I / O module reads the second I / O module and controls the first relay output of the second I / O module. The data to be sent is: 0x01 0x2B 0x01 0x01 0x01 0x81 0xB4. Then:

[0061] Device Address Function Code Data Frame CRC check L CRC check H 0x01 0x2B 0x01 0x01 0x01 0x81 0xB4

[0062] Example 3: The master I / O module reads the second I / O module and controls the AO channel of the second master I / O module to output 2.56V (0x00 0x01). The data to be sent is: 0x01 0x2B 0x02 0x01 0x00 0x01 0xB4 0x74. Then:

[0063] Device Address Function Code Data Frame CRC check L CRC check H 0X01 0X2B 0x02 0x01 0x00 0x01 0xB4 0x74

[0064] If other I / O modules need to send data to the main I / O module, the meaning of the first byte (byte1) in the data frame is as follows: Bit0: whether other I / O modules have DI data sent to the main I / O module (1 indicates DI data, 0 indicates no DI data); Bit1: whether other I / O modules have AI data sent to the main I / O module (1 indicates AI data, 0 indicates no AI data); Bit2: whether other I / O modules have DO status data sent to the main I / O module (1 indicates DO status data, 0 indicates no DO status data); Bit3: whether other I / O modules have AO status data sent to the main I / O module (1 indicates AO status data, 0 indicates no AO status data); Bit4~7: reserved.

[0065] If bit0\bit1 are both 1 and bit2\bit3 are both 0, DI comes first and AI comes second; byte2 of the data frame starts to indicate the number of DI channels and the number of AI channels, followed by the data of each DI and the data of each AI.

[0066] For example, if the second I / O module supports 1 DI, 1 AI, 2 DO, and 1 AO on its hardware, and the DI data is 0x01 0x02, the AI ​​data is 0x03 0x04, the DO data is 0x03, and the AO data is 0x05 0x06, then when the second I / O module receives the 0x2B command from the main I / O module, the second I / O module replies: 0x01 0x2C 0x0F 0x01 0x01 0x02 0x01 0x01 0x02 0x03 0x04 0x03 0x05 0x06 0x7B 0xAD, then

[0067]

[0068] When communication with other I / O modules is interrupted for 3 seconds, their data output should be reset. The main I / O module controls the communication output of other I / O modules that are continuously online starting from the second I / O module. The main I / O module automatically transfers data to the DI / DO / AI / AO channels of the main I / O module based on the number of channels of other I / O modules.

[0069] In other words, the present invention can realize data transmission and reception between the main I / O module and other I / O modules through a customized communication protocol, so that the main controller 1 only needs to communicate with the first I / O module 2, which can reduce the memory usage of the main controller 1 and improve the overall operation stability of the PLC system.

[0070] To sum up, the PLC system capable of automatically assigning addresses and the control method thereof of the present invention cascade N I / O modules 2 through the backplane bus 22. On the one hand, it can facilitate wiring and improve the overall aesthetics of the system. On the other hand, the single-chip microcomputer 21 can automatically assign addresses to the I / O modules 2 by identifying the frequency-divided signals output by the corresponding I / O modules 2, which can not only improve work efficiency, but also reduce errors caused by human factors and ensure the accuracy of the operation of the PLC system.

[0071] With the above-described preferred embodiments of the present invention as a guide, and with reference to the above description, relevant personnel are fully capable of making various changes and modifications without departing from the technical spirit of this invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A PLC system capable of automatically allocating addresses, characterized in that: include: A main controller (1), N I / O modules (2) and an LCD display (3), wherein the N I / O modules (2) are sequentially connected in series, the first I / O module (2) is connected to the main controller (1), and the first I / O module (2) is connected to the LCD display (3), and N is greater than or equal to 2; Each of the I / O modules (2) comprises a single-chip microcomputer (21) and a backplane bus (22), the single-chip microcomputer (21) being connected to the backplane bus (22), and the single-chip microcomputer (21) being capable of automatically allocating an address to the I / O module (2) according to a frequency-divided signal output by the backplane bus (22); The data transmission and reception protocol between the first I / O module (2) and the remaining N-1 I / O modules (2) is set as: The data of each AI / AO channel occupies 2 bytes, one byte contains 8 bits, arranged in low-end order; each DI / DO occupies 1 bit, with bit 0 being the low-end port number data; DI represents digital signal input, DO represents digital signal output, AI represents analog signal input, and AO represents analog signal output; If the first I / O module 2 sends data to other I / O modules 2, the meaning of the first byte Byte1 in the data frame is as follows: Bit0, indicating whether the first I / O module (2) has DO control data to send to other I / O modules; Bit1, indicating whether the first I / O module (2) has AO control data to send to other I / O modules; Bit2 to Bit7 are reserved; If Bit 0 and Bit 1 of Byte 1 of the data frame are both 1, DO data is transmitted first, followed by AO data. Starting from Byte 2 of the data frame, the numbers of DO channels and AO channels are respectively transmitted. The other bits of Byte 2 of the data frame represent the data of each DO and each AO. The receiver must verify the relationship between the total number of bytes, number of channels, and number of data in the data frame according to the protocol before setting the local DO and AO.

2. The PLC system capable of automatically allocating addresses according to claim 1, wherein: The backplane bus (22) comprises a power module (221), a communication module (222) and a frequency division module (223); the power module (221) is connected to the communication module (222); and the power module (221) is connected to the frequency division module (223).

3. The PLC system capable of automatically allocating addresses according to claim 2, characterized in that: Each of the I / O modules (2) further comprises an input connector XS1 and an output connector XS2, wherein the input connector XS1 is connected to the communication module (222), the input connector XS1 is connected to the frequency division module (223), and the frequency division module (223) is connected to the output connector XS2.

4. The PLC system capable of automatically allocating addresses according to claim 3, wherein: The communication module (222) includes a communication chip U2, and the communication chip U2 has an RO pin, a RE pin, a DE pin, a DI pin, a first GND pin, an A output terminal, a B output terminal, and a first VCC pin. The RO pin, RE pin, DE pin, and DI pin are all connected to the single-chip computer (21), the RE pin is connected to the DE pin, the first GND pin is grounded, the first VCC pin is connected to the power module (221), and the A output terminal and the B output terminal are both connected to the input connector XS1.

5. The PLC system capable of automatically allocating addresses according to claim 4, characterized in that: The frequency division module (223) includes a frequency division chip U1, the frequency division chip U1 having a CLK pin, a second GND pin, an input pin D, an output pin Q, a second VCC pin and a CLR pin, the CLK pin being connected to the input connector XS1, the CLR pin and the second VCC pin being connected to the power module (221), the second GND pin being grounded, the input pin D being connected to the output pin Q, and the output pin Q being connected to the output connector XS2.

6. The PLC system capable of automatically allocating addresses according to claim 5, characterized in that: The frequency division module (223) further includes a resistor R46, a resistor R48, a transistor V4, a diode VD14, and a resistor R44, one end of the resistor R48 is connected to the input pin D, the other end of the resistor R48 is connected to the cathode of the diode VD14, the anode of the diode VD14 is grounded, one end of the resistor R46 is connected to the output pin Q, the other end of the resistor R46 is connected to the base of the transistor V4, the collector of the transistor V4 is connected to one end of the resistor R44, the emitter of the transistor V4 is connected to the anode of the diode VD14, the cathode of the diode VD14 is connected to the collector of the transistor V4, and the other end of the resistor R44 is connected to the output connector XS2.

7. The PLC system capable of automatically allocating addresses according to claim 5, characterized in that: The CLK pin of the frequency dividing chip U1 of the first I / O module (2) is connected to the single chip computer (21), and the frequency dividing chip U1 of the first I / O module (2) can receive an initial frequency f1.

8. A control method for a PLC system capable of automatically allocating addresses according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1. The first I / O module (2) is recorded as the main module, and each I / O module (2) can perform data acquisition; when N I / O modules (2) are powered on, the single-chip microcomputer (21) of the I / O module (2) can read the frequency-divided signal output by the backplane bus (22), and the single-chip microcomputer (21) automatically assigns a corresponding address to the I / O module (2) according to the frequency-divided signal; S2, the first I / O module (2) receives a control signal sent by the main controller (1), and the first I / O module (2) can send the control signal to the second to Nth I / O modules (2) respectively through the communication protocol; the first I / O module (2) can receive data information collected by the second to Nth I / O modules (2) respectively through the communication protocol, and send the data information to the main controller (1) after aggregating the data information; S3. The first I / O module (2) sends the aggregated data information to the LCD display (3) for display.

9. The control method of a PLC system capable of automatically allocating addresses according to claim 8, characterized in that: In step S1, the single chip microcomputer (21) automatically assigns a corresponding address to the I / O module (2) according to the frequency division signal, specifically including: The first I / O module (2) can generate an initial frequency f1. The initial frequency f1 outputs the first frequency-divided signal f1 / 2 from the output pin Q through the frequency-dividing chip U1. The first frequency-divided signal f1 / 2 is input to the second I / O module (2). The output pin Q of the second I / O module (2) outputs the second frequency-divided signal f1 / 4. Similarly, the output pin Q of the N-1th I / O module (2) outputs the N-1th frequency-divided signal f1 / 2. N-1 , the N-1th frequency division signal f1 / 2 N-1 Input to the Nth I / O module (2), the Nth I / O module (2) outputs the Nth frequency division signal f1 / 2 N ; Each frequency division signal corresponds to an address. When the I / O module (2) is powered on, each I / O module (2) can generate a corresponding frequency division signal. The single chip microcomputer (21) allocates a corresponding address to the I / O module (2) by reading the frequency division signal.

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