Master-slave system and slave integrated circuit thereof

Abstract

The present invention discloses a master-slave system, comprising a master integrated circuit, a first slave integrated circuit and a second slave integrated circuit. The first interrupt pin of the master integrated circuit is connected to the second interrupt pin of the first slave integrated circuit, and the first multi-function pin of the master integrated circuit is connected to the second multi-function pin of the second slave integrated circuit. In a normal mode, the first interrupt pin and the first multi-function pin are used to receive a first interrupt signal and a second interrupt signal respectively, and the second interrupt pin and the second multi-function pin are used to send the first interrupt signal and the second interrupt signal respectively. In an addressing mode, the first multi-function pin is used to transmit an address signal, and the second multi-function pin is used to receive the address signal. The second slave integrated circuit changes the original preset address to a new address according to the address signal.

Description

Technical Field

[0001] The present invention relates to a master-slave system, and more particularly to a master-slave system with good expandability. Background Art

[0002] Figure 1 A conventional master-slave system 10 is shown, which includes a master integrated circuit 12 and two slave integrated circuits 14 and 16. The master integrated circuit 12 is connected to the master integrated circuit via an inter-integrated circuit bus (ICB). 2 C bus) to communicate with the slave integrated circuits 14 and 16. The clock pin CLK_h1 of the master integrated circuit 12 is connected to the clock pin CLK_s1 of the slave integrated circuit 14 and the clock pin CLK_s2 of the slave integrated circuit 16. The master integrated circuit 12 transmits a clock signal SCL1 to the slave integrated circuits 14 and 16 through the clock pin CLK_h1. The data pin D_h1 of the master integrated circuit 12 is connected to the data pin D_s1 of the slave integrated circuit 14 and the data pin D_s2 of the slave integrated circuit 16. The master integrated circuit 12 transmits a data signal SDA1 to the slave integrated circuits 14 and 16 through the data pin D_h1. The pins INT_h1 and INT_h2 of the master integrated circuit 12 are connected to the pin INT_s1 of the slave integrated circuit 14 and the pin INT_s2 of the slave integrated circuit 16, respectively. The master integrated circuit 12 receives an interrupt signal SINT1 from the slave integrated circuit 14 and an interrupt signal SINT2 from the slave integrated circuit 16 through the pins INT_h1 and INT_h2, respectively.

[0003] However, the addresses of the slave ICs 14 and 16 are set at the factory, and the addresses of the slave ICs 14 and 16 of the same model are the same. Therefore, when the slave ICs 14 and 16 share the pins CLK_h1 and D_h1 of the main IC 12, the main IC 12 cannot select to communicate with the slave IC 14 or 16 according to the address. A known solution is that the main IC 12 determines whether to communicate with the slave IC 14 or 16 by changing the sequence of the clock signal SCL1 and the data signal SDA1. For example, Figure 2 As shown, when the data signal SDA1 becomes low level earlier than the clock signal SCL1, it means that the master integrated circuit 12 selects the slave integrated circuit 14 for communication. On the contrary, when the data signal SDA1 becomes low level later than the clock signal SCL1, it means that the master integrated circuit 12 selects the slave integrated circuit 16 for communication.

[0004] However, there are only two situations for the change order of the clock signal SCL1 and the data signal SDA1, so the traditional master-slave system 10 can only have two slave integrated circuits 14 and 16 at most. Once there are more than two slave integrated circuits, the master integrated circuit 12 cannot choose which slave integrated circuit to communicate with, which limits the scalability of the master-slave system 10. Summary of the invention

[0005] One of the objectives of the present invention is to provide a master-slave system and a slave integrated circuit thereof with good expandability.

[0006] According to the present invention, a master-slave system includes a master integrated circuit, a first slave integrated circuit and a second slave integrated circuit. The master integrated circuit has a first interrupt pin and a first multi-function pin. The first slave integrated circuit has a preset address and a second interrupt pin connected to the first interrupt pin. The second slave integrated circuit has the preset address and a second multi-function pin connected to the first multi-function pin. In a normal mode, the first interrupt pin and the first multi-function pin are used to receive a first interrupt signal and a second interrupt signal respectively, and the second interrupt pin and the second multi-function pin are used to send the first interrupt signal and the second interrupt signal respectively. In an addressing mode, the first multi-function pin is used to transmit an address signal, the second multi-function pin is used to receive the address signal, and the second slave integrated circuit determines a new address different from the preset address according to the address signal.

[0007] According to the present invention, a secondary integrated circuit with a preset address includes a multifunctional pin and a main control unit. The multifunctional pin is used to receive an address signal in an addressing mode and to send an interrupt signal in a normal mode. The main control unit is connected to the multifunctional pin and switches the secondary integrated circuit from the normal mode to the addressing mode according to a change address command, wherein in the addressing mode, the main control unit determines a new address different from the preset address according to the address signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Shows a traditional master-slave system.

[0009] Figure 2 Shows the traditional master-slave system method of selecting a slave integrated circuit.

[0010] Figure 3 The configuration of the first embodiment of the master-slave system of the present invention in the normal mode is shown.

[0011] Figure 4 The configuration of the first embodiment of the master-slave system of the present invention in the addressing mode is shown.

[0012] Figure 5 The operating flow of dynamic addressing of the master-slave system of the present invention is shown.

[0013] Figure 6 The configuration of the second embodiment of the master-slave system of the present invention in the addressing mode is shown.

[0014] Explanation of the reference numerals: 10 - master-slave system; 12 - master integrated circuit; 14 - slave integrated circuit; 16 - slave integrated circuit; 20 - master-slave system; 22 - master integrated circuit; 24 - slave integrated circuit; 26 - slave integrated circuit; 262 - master control unit; 30 - master-slave system; 32 - master integrated circuit; 34 - slave integrated circuit; 36 - slave integrated circuit. DETAILED DESCRIPTION

[0015] Figure 3 The first embodiment of the master-slave system of the present invention is shown. Figure 3 In the master-slave system 20, a master integrated circuit 22 and two slave integrated circuits 24 and 26 are included. The clock pin CLK_h1 of the master integrated circuit 22 is connected to the clock pin CLK_s1 of the slave integrated circuit 24 and the clock pin CLK_s2 of the slave integrated circuit 26. The master integrated circuit 22 transmits a clock signal SCL1 to the slave integrated circuits 24 and 26 via the clock pin CLK_h1. The data pin D_h1 of the master integrated circuit 22 is connected to the data pin D_s1 of the slave integrated circuit 24 and the data pin D_s2 of the slave integrated circuit 26. The master integrated circuit 22 transmits a data signal SDA1 to the slave integrated circuits 24 and 26 via the data pin D_h1. The interrupt pin INT_h1 of the main integrated circuit 22 is connected to the interrupt pin INT_s1 of the slave integrated circuit 24, and the multi-function pin MF_h1 of the main integrated circuit 22 is connected to the multi-function pin MF_s2 of the slave integrated circuit 26, wherein the multi-function pins MF_h1 and MF_s2 can be but are not limited to general-purpose input / output (GPIO) pins. Figure 3 As shown, when the master-slave system 20 operates in the normal mode, the slave integrated circuits 24 and 26 transmit interrupt signals SINT1 and SINT2 to the interrupt pin INT_h1 and the multi-function pin MF_h1 of the master integrated circuit 22 through the interrupt pin INT_s1 and the multi-function pin MF_s2, respectively. In other words, the multi-function pins MF_h1 and MF_s2 are used as interrupt pins in the normal mode, wherein the multi-function pin MF_h1 is set as an input pin, and the multi-function pin MF_s2 is set as an output pin.

[0016] The slave ICs 24 and 26 have the same preset address, such as “1000001”. To distinguish the slave ICs 24 and 26 , the master-slave system 10 of the present invention has a certain addressing mode to reset the address of the slave IC 24 and / or the slave IC 26 . Figure 4 show Figure 3 Configuration of the master-slave system in addressing mode. Figure 5 The operation flow of dynamic addressing of the master-slave system of the present invention is shown. Figure 4 and Figure 5 When the master-slave system 20 is activated, the master integrated circuit 22 enters the addressing mode to set the multi-function pin MF_h1 as an output pin, and sends a change address command Add_ch to the slave integrated circuit 26 through the data pin D_h1, as shown in step S10. The main control unit 262 in the slave integrated circuit 26 switches the slave integrated circuit 26 from the normal mode to the addressing mode according to the change address command Add_ch received by the data pin D_s2, and sets the multi-function pin MF_s2 as an input pin, as shown in step S12. The main control unit 262 is connected to each pin CLK_s2, D_s2 and MF_s2 of the slave integrated circuit 26 to receive signals on the pins or provide signals to the pins. After the slave integrated circuit 26 sets the multi-function pin MF_s2 as an input pin, the master integrated circuit 22 sends an address signal Add_n to the multi-function pin MF_s2 of the slave integrated circuit 26 through the multi-function pin MF_h1, as shown in step S14. After receiving the address signal Add_n, the main control unit 262 of the slave integrated circuit 26 modifies the default address "1000001" of the slave integrated circuit 26 according to the address signal Add_n to generate a new address, as shown in step S16. After the address of the slave integrated circuit 26 is set, the main integrated circuit 22 and the slave integrated circuit 26 will switch back to normal mode, the main integrated circuit 22 will set the multi-function pin MF_h1 as an input pin, and the slave integrated circuit 26 will set the multi-function pin MF_s2 as an output pin. Although Figure 3 and Figure 4 Although not shown in the embodiment, the slave integrated circuit 24 also has a main control unit connected to each of the pins CLK_s1, D_s1 and MF_s1 of the slave integrated circuit 24 to receive signals on the pins or provide signals to the pins.

[0017] There are many ways to modify the preset address "1000001" of the secondary integrated circuit 26. Only two ways are listed here, but the present invention is not limited to these two ways. In one embodiment, the address signal Add_n provided by the main integrated circuit 22 is a bit "0", and the secondary integrated circuit 26 can replace the last bit in the preset address "1000001" with the bit "0" to generate a new address "1000000". In one embodiment, a look-up table can be set in the secondary integrated circuit 26, and the secondary integrated circuit 26 can select a new address from the look-up table according to the address signal Add_n.

[0018] In one embodiment, the interrupt pin INT_h1 of the main integrated circuit 22 and the interrupt pin INT_s1 of the sub-integrated circuit 24 can also be used as multi-function pins with input / output functions. After the main integrated circuit 22 and the sub-integrated circuit 24 enter the addressing mode, the interrupt pin INT_h1 is changed to an output pin to send out the address signal, and the interrupt pin INT_s1 is changed to an input pin to receive the address signal. In this case, the operation of the sub-integrated circuit 24 is similar to that of the sub-integrated circuit 26, so it is not repeated.

[0019] The master-slave system of the present invention has good expandability and can be configured with more than two slave integrated circuits. Figure 6 The second embodiment of the master-slave system of the present invention is shown in the configuration of the addressing mode. Figure 6 In the embodiment, the master-slave system 30 includes a master integrated circuit 32 and four slave integrated circuits 24 , 26 , 34 and 36 . Figure 6 The circuit structure and control of the auxiliary integrated circuits 24 and 26 are Figure 3 and Figure 4The master integrated circuit 32 has the same clock pin CLK_h1 as the slave integrated circuit 24 and 26. The clock pin CLK_h1 of the master integrated circuit 32 is connected to the clock pin CLK_s1 of the slave integrated circuit 24, the clock pin CLK_s2 of the slave integrated circuit 26, the clock pin CLK_s3 of the slave integrated circuit 34, and the clock pin CLK_s4 of the slave integrated circuit 36. The data pin D_h1 of the master integrated circuit 32 is connected to the data pin D_s1 of the slave integrated circuit 24, the data pin D_s2 of the slave integrated circuit 26, the data pin D_s3 of the slave integrated circuit 34, and the data pin D_s4 of the slave integrated circuit 36. The interrupt pin INT_h1 of the main integrated circuit 32 is connected to the interrupt pin INT_s1 of the sub-integrated circuit 24, the multi-function pin MF1_h1 of the main integrated circuit 32 is connected to the multi-function pin MF_s2 of the sub-integrated circuit 26, the multi-function pin MF2_h1 of the main integrated circuit 32 is connected to the multi-function pin MF_s3 of the sub-integrated circuit 34, and the multi-function pin MF3_h1 of the main integrated circuit 32 is connected to the multi-function pin MF_s4 of the sub-integrated circuit 36, wherein the multi-function pins MF1_h1, MF2_h1, MF3_h1, MF_s2, MF_s3 and MF_s4 can be but are not limited to general-purpose input and output pins. Figure 6 In the embodiment of the present invention, the sub-IC 34 has a main control unit connected to each pin CLK_s3, D_s3 and MF_s3 of the sub-IC 34 to receive a signal on the pin or provide a signal to the pin. Similarly, the sub-IC 36 also has a main control unit connected to each pin CLK_s4, D_s4 and MF_s4 of the sub-IC 36 to receive a signal on the pin or provide a signal to the pin. The operation of the main control units of the sub-ICs 34 and 36 can refer to the main control unit 262 of the sub-IC 26, so it will not be repeated.

[0020] The slave integrated circuits 24, 26, 34 and 36 have the same preset address, for example, "1000001". When the master-slave system 30 performs dynamic addressing, the master integrated circuit 32 enters the addressing mode to set the multi-function pins MF1_h1, MF2_h1 and MF3_h1 as output pins, and sends the address change command Add_ch to the slave integrated circuits 26, 34 and 36 through the data pin D_h1. After receiving the address change command Add_ch, the slave integrated circuits 26, 34 and 36 switch from the normal mode to the addressing mode, and set the multi-function pins MF_s2, MF_s3 and MF_s4 as input pins. Then, the master integrated circuit 32 sends the address signals Add_n1, Add_n2 and Add_n3 to the slave integrated circuits 26, 34 and 36 through the multi-function pins MF1_h1, MF2_h1 and MF3_h1, respectively. The sub-ICs 26, 34 and 36 will respectively modify the preset address "1000001" to generate a new address according to the address signals Add_n1, Add_n2 and Add_n3. For example, the address signal Add_n1 is "00", the address signal Add_n2 is "10", and the address signal Add_n3 is "11". The sub-IC 26 can replace the last two bits of the preset address "1000001" with the two bits "00" of the address signal Add_n1 to generate a new address "1000000", the sub-IC 34 can replace the last two bits of the preset address "1000001" with the two bits "10" of the address signal Add_n2 to generate a new address "1000010", and the sub-IC 36 can replace the last two bits of the preset address "1000001" with the two bits "11" of the address signal Add_n3 to generate a new address "1000011". After the addresses of the slave integrated circuits 26, 34 and 36 are modified, the master integrated circuit 32 and the slave integrated circuits 26, 34 and 36 will switch back to the normal mode. The configuration of the master-slave system 30 in the normal mode can refer to Figure 3 , so I will not go into details.

[0021] Figure 6 The master-slave system of the present invention has only four slave integrated circuits 24, 26, 34 and 36. When more slave integrated circuits need to be connected, the master integrated circuit 32 only needs to increase the number of bits of the address signal. For example, when the address signal has three bits, the master-slave system of the present invention can have a maximum of 9 (i.e., 2 3 +1) Secondary integrated circuit.

[0022] The above description of the preferred embodiments of the present invention is for the purpose of explanation and is not intended to limit the present invention to the precise form disclosed. Modifications or changes based on the above teachings or learning from the embodiments of the present invention are possible. The embodiments are for explaining the principles of the present invention and allowing those skilled in the art to select and describe various embodiments to utilize the present invention in practical applications. The technical concept of the present invention is determined by the claims and their equivalents.

Claims

1. A master-slave system, It is characterized in that include: A main integrated circuit having a first interrupt pin and a first multi-function pin; A first sub-IC has a preset address and a second interrupt pin connected to the first interrupt pin; a second sub-IC having the preset address and a second multi-function pin connected to the first multi-function pin; Wherein, in a normal mode, the first interrupt pin and the first multi-function pin are used to receive a first interrupt signal and a second interrupt signal respectively, and the second interrupt pin and the second multi-function pin are used to send the first interrupt signal and the second interrupt signal respectively; Wherein, in a certain addressing mode, the first multifunctional pin is used to transmit an address signal, the second multifunctional pin is used to receive the address signal, and the second sub-IC determines a new address different from the preset address according to the address signal.

2. The master-slave system according to claim 1, It is characterized in that The second sub-IC changes at least one bit of the preset address of the second sub-IC to generate the new address.

3. The master-slave system according to claim 2, It is characterized in that The second sub-IC uses a bit of the address signal to replace a bit of the preset address to generate the new address.

4. The master-slave system according to claim 1, It is characterized in that The main integrated circuit also includes a first data pin for outputting a change address command in the addressing mode, and the second sub-integrated circuit also includes a second data pin for receiving the change address command. The second sub-integrated circuit determines the new address according to the address signal in response to the change address command.

5. The master-slave system according to claim 1, It is characterized in that The master integrated circuit sets the first multi-function pin as an input pin in the normal mode, and sets the first multi-function pin as an output pin in the addressing mode.

6. The master-slave system according to claim 1, It is characterized in that The second sub-IC sets the second multi-function pin as an output pin in the normal mode, and sets the second multi-function pin as an input pin in the addressing mode.

7. The master-slave system according to claim 4, It is characterized in that The second sub-IC also includes a main control unit connected to the second multi-function pin. The main control unit switches the second sub-IC from the normal mode to the addressing mode according to the address change command, and determines the new address according to the address signal in the addressing mode.

8. A secondary integrated circuit having a preset address, It is characterized in that The secondary integrated circuit includes: a first multi-function pin, coupled to a second multi-function pin of a master integrated circuit, for receiving an address signal from the master integrated circuit in an address mode, and for sending an interrupt signal to the master integrated circuit in a normal mode; and A main control unit is connected to the first multifunctional pin, and switches the auxiliary integrated circuit from the normal mode to the addressing mode according to a change address command, wherein in the addressing mode, the main control unit determines a new address different from the preset address according to the address signal.

9. The secondary integrated circuit as claimed in claim 8, It is characterized in that The device also includes a data pin for receiving the address change command.

10. The secondary integrated circuit as claimed in claim 8, It is characterized in that The slave integrated circuit sets the first multi-function pin as an output pin in the normal mode, and sets the first multi-function pin as an input pin in the addressing mode.

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