Watchdog timeout restart scene capture system, method, device and storage medium

Abstract

The present invention discloses a watchdog timeout restart scene capture system, method, device and storage medium. The system includes: a watchdog counting module, which is used to count when the watchdog is started, and when the count value reaches a preset timeout threshold, generates a first timeout signal; a watchdog timeout processing module, which is used to respond to the first timeout signal, save the current scene information of the CPU as abnormal scene information to the watchdog SRAM storage module, set the watchdog timeout flag to 1, and send a first reset signal to the CPU; a watchdog information acquisition module, which is used to read the watchdog timeout flag when the CPU is reset. If the watchdog timeout flag is 1, the abnormal scene information is obtained from the watchdog SRAM storage module and sent to the CPU memory, the watchdog timeout flag is set to 0, and the watchdog is restarted by the watchdog startup module. The present invention is conducive to the recovery of the CPU abnormal scene and the analysis of the abnormal cause, improves the reliability of the system, and can be widely used in the field of computer technology.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a watchdog timeout restart scene capture system, method, device and storage medium. Background Art

[0002] The hardware watchdog is a timer circuit. The watchdog feeding program periodically updates the watchdog counter to prevent the watchdog timer from timing out. If the watchdog feeding program fails and stops feeding, it triggers watchdog exception handling, such as resetting the system. The exception information is lost after the system is reset. Fault analysis is typically performed by printing and recording information before the restart.

[0003] In the prior art, when a system operation anomaly causes the watchdog to time out and restart, the system will lose the abnormal scene, making it impossible to locate the cause of the abnormality and the location of the program running before the restart, which is not conducive to the debugger's subsequent fault analysis and debugging. Summary of the Invention

[0004] The purpose of the present invention is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0005] Therefore, an object of an embodiment of the present invention is to provide a watchdog timeout restart scene capture system that can save abnormal scenes.

[0006] Another object of an embodiment of the present invention is to provide a method for capturing a watchdog timeout restart scene.

[0007] In order to achieve the above technical objectives, the technical solutions adopted by the embodiments of the present invention include:

[0008] In a first aspect, an embodiment of the present invention provides a watchdog timeout restart scene capture system, comprising:

[0009] A watchdog counting module, configured to count when the watchdog is started, and generate a first timeout signal when the count value reaches a preset timeout threshold;

[0010] Watchdog SRAM storage module, used to store CPU abnormality field information;

[0011] a watchdog timeout processing module, configured to respond to the first timeout signal, save the current field information of the CPU as the abnormal field information to the watchdog SRAM storage module, set the watchdog timeout flag to 1, and send a first reset signal to the CPU;

[0012] A watchdog startup module, used to control the startup of the watchdog;

[0013] A watchdog information acquisition module is used to read the watchdog timeout flag when the CPU is reset. If the watchdog timeout flag is 1, the abnormal field information is obtained from the watchdog SRAM storage module and sent to the CPU memory, the watchdog timeout flag is set to 0, and the watchdog is restarted through the watchdog startup module.

[0014] Furthermore, in one embodiment of the present invention, the exception context information includes program counter information, program status register information, and stack register information.

[0015] Furthermore, in one embodiment of the present invention, the watchdog information processing module is further configured to: read the watchdog timeout flag when the CPU is reset; if the watchdog timeout flag is 0, start the watchdog via the watchdog start module.

[0016] Furthermore, in one embodiment of the present invention, the watchdog timeout restart scene capture system further comprises:

[0017] The abnormal scene information viewing module is used to receive the user's operation instruction, obtain the abnormal scene information from the CPU register according to the operation instruction, and return it to the user.

[0018] In a second aspect, an embodiment of the present invention provides a method for capturing a watchdog timeout restart scene, comprising the following steps:

[0019] When the watchdog starts counting, when the count value reaches a preset timeout threshold, a first timeout signal is generated;

[0020] In response to the first timeout signal, the current field information of the CPU is saved as abnormal field information in the watchdog SRAM storage module, the watchdog timeout flag is set to 1, and a first reset signal is sent to the CPU;

[0021] Used to read the watchdog timeout flag when the CPU is reset. If the watchdog timeout flag is 1, obtain the abnormal field information from the watchdog SRAM storage module and send it to the CPU memory, set the watchdog timeout flag to 0, and restart the watchdog.

[0022] Furthermore, in one embodiment of the present invention, the exception context information includes program counter information, program status register information, and stack register information.

[0023] Furthermore, in one embodiment of the present invention, the watchdog timeout restart scene capture method further includes the following steps:

[0024] When the CPU is reset, the watchdog timeout flag is read. If the watchdog timeout flag is 0, the watchdog is started by the watchdog starting module.

[0025] Furthermore, in one embodiment of the present invention, the watchdog timeout restart scene capture method further includes the following steps:

[0026] Receive the user's operation instruction, obtain the abnormal scene information from the CPU register according to the operation instruction, and return it to the user.

[0027] In a third aspect, an embodiment of the present invention provides a watchdog timeout restart scene capture device, comprising:

[0028] at least one processor;

[0029] at least one memory for storing at least one program;

[0030] When the at least one program is executed by the at least one processor, the at least one processor implements the above-mentioned watchdog timeout restart scene capture method.

[0031] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium storing a program executable by a processor, wherein the program executable by the processor is used to execute the above-mentioned watchdog timeout restart scene capture method when executed by the processor.

[0032] The advantages and benefits of the present invention will be described in part in the following description and will become apparent from the following description or learned through practice of the present invention:

[0033] The embodiment of the present invention counts when the watchdog is started, and when the count value reaches the timeout threshold, the current abnormal scene information of the CPU is saved to the watchdog SRAM storage module, and the watchdog timeout flag is set to 1, and then the CPU is reset; the watchdog timeout flag is read when the CPU is reset, and when the watchdog timeout flag is 1, the abnormal scene information is obtained from the watchdog SRAM storage module and sent to the CPU memory for storage, and the watchdog timeout flag is set to 0, and then the watchdog is restarted. The embodiment of the present invention backs up the abnormal scene information of the CPU to the watchdog SRAM module immediately after the watchdog times out, and then resets the CPU, and stores the backed-up abnormal scene information to the CPU memory after the CPU is reset, so that the debugger can directly read the abnormal scene information from the CPU memory, which is convenient for the recovery of the CPU abnormal scene and the analysis of the abnormal cause; because the watchdog SRAM module is added to the watchdog architecture, the abnormal scene can be saved when the CPU has a hardware abnormality or a software abnormality, thereby improving the reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following introduction is made to the drawings required for use in the embodiments of the present invention. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.

[0035] Figure 1 A structural block diagram of a watchdog timeout restart scene capture system provided by an embodiment of the present invention;

[0036] Figure 2 A schematic diagram illustrating the working principle of a watchdog timeout restart scene capture system provided by an embodiment of the present invention;

[0037] Figure 3 A schematic diagram of a state machine for a watchdog timeout restart scene capture system provided by an embodiment of the present invention;

[0038] Figure 4 A flowchart of a method for capturing a watchdog timeout restart scene provided by an embodiment of the present invention;

[0039] Figure 5 This is a structural block diagram of a watchdog timeout restart scene capture device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention and are not to be construed as limiting the present invention. The step numbers in the following embodiments are provided for ease of explanation only and do not limit the order of the steps. The order of execution of the steps in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0041] In the description of the present invention, "a plurality" means two or more. The terms "first" and "second" are used solely to distinguish technical features and are not to be construed as indicating or implying relative importance, or as implicitly indicating the number of the indicated technical features, or as implicitly indicating the order of the indicated technical features. Furthermore, unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art.

[0042] Reference Figure 1 The embodiment of the present invention provides a watchdog timeout restart scene capture system, comprising:

[0043] A watchdog counting module, configured to count when the watchdog is started, and generate a first timeout signal when the count value reaches a preset timeout threshold;

[0044] Watchdog SRAM storage module, used to store CPU abnormality field information;

[0045] A watchdog timeout processing module, configured to respond to a first timeout signal, save the current field information of the CPU as abnormal field information to the watchdog SRAM storage module, set the watchdog timeout flag to 1, and send a first reset signal to the CPU;

[0046] Watchdog startup module, used to control the startup of the watchdog;

[0047] The watchdog information acquisition module is used to read the watchdog timeout flag when the CPU is reset. If the watchdog timeout flag is 1, the abnormal field information is obtained from the watchdog SRAM storage module and sent to the CPU memory, the watchdog timeout flag is set to 0, and the watchdog is restarted through the watchdog start module.

[0048] The embodiment of the present invention counts when the watchdog is started, and when the count value reaches the timeout threshold, the current abnormal scene information of the CPU is saved to the watchdog SRAM storage module, and the watchdog timeout flag is set to 1, and then the CPU is reset; the watchdog timeout flag is read when the CPU is reset, and when the watchdog timeout flag is 1, the abnormal scene information is obtained from the watchdog SRAM storage module and sent to the CPU memory for storage, and the watchdog timeout flag is set to 0, and then the watchdog is restarted. The embodiment of the present invention backs up the abnormal scene information of the CPU to the watchdog SRAM module immediately after the watchdog times out, and then resets the CPU, and stores the backed-up abnormal scene information to the CPU memory after the CPU is reset, so that the debugger can directly read the abnormal scene information from the CPU memory, which is convenient for the recovery of the CPU abnormal scene and the analysis of the abnormal cause; because the watchdog SRAM module is added to the watchdog architecture, the abnormal scene can be saved when the CPU has a hardware abnormality or a software abnormality, thereby improving the reliability of the system.

[0049] In some optional embodiments, the watchdog SRAM storage module is set in the power domain and is not subject to system reset control, which can ensure stable backup of abnormal field information and further improve the reliability of the system.

[0050] As a further optional implementation, the exception context information includes program counter information, program status register information, and stack register information.

[0051] Specifically, after receiving the timeout signal, the watchdog timeout processing module will save the CPU current scene, such as the program counter, program status register, stack register and other CPU internal registers to the watchdog SRAM storage module. The information saved in the SRAM can be saved according to a predefined format, for example, in ascending order according to the format of CPU general registers, CPU special registers, and the current 1024-byte stack information.

[0052] As a further optional implementation, the watchdog information processing module is further configured to: read the watchdog timeout flag when the CPU is reset, and if the watchdog timeout flag is 0, start the watchdog via the watchdog start module.

[0053] Specifically, when the watchdog timeout flag is 0, it indicates that the CPU is not restarted due to a watchdog timeout, and therefore there is no need to read and transfer abnormal scene information.

[0054] Further as an optional implementation manner, the watchdog timeout restart scene capture system further includes:

[0055] The abnormal scene information viewing module is used to receive the user's operation instructions, obtain the abnormal scene information from the CPU register according to the operation instructions, and return it to the user.

[0056] Specifically, the user (debugging personnel) can view the abnormal scene information stored in the CPU memory through instructions, and perform CPU abnormal scene recovery and abnormal cause analysis based on the abnormal scene information.

[0057] like Figure 2 The figure shows a schematic diagram of the working principle of a watchdog timeout restart scene capture system provided by an embodiment of the present invention. It can be understood that when the CPU is reset and started normally (i.e., not restarted due to watchdog timeout), the watchdog timeout flag is not 1. At this time, the watchdog is directly started, and then the watchdog counting module starts counting; if the CPU continues to feed the dog normally, the watchdog count value will not reach the timeout threshold, and the CPU continues to operate normally at this time; if the CPU has a hardware or software abnormality and cannot continue to feed the dog, the watchdog count value continues to increase. When the timeout threshold is reached, the CPU abnormality scene information is backed up to the watchdog SRAM storage module, and the watchdog timeout flag is set to 1, and then a reset signal is sent to the reset port of the CPU, so that the CPU is reset and restarted; when the CPU is reset and restarted, the watchdog timeout flag is 1, and at this time the abnormality scene information backed up by the watchdog SRAM storage module is transferred to the CPU memory for storage, and the watchdog timeout flag is set to 0, and then the watchdog is restarted, and counting is restarted and the above process is executed cyclically.

[0058] It can be recognized that the embodiment of the present invention can back up the abnormal scene information in time after each watchdog timeout restart, and when the CPU is reset and restarted, the abnormal scene information can be promptly transferred to the CPU memory for subsequent viewing. In this way, even if multiple timeout restarts occur within a period of time, the abnormal scene information at each timeout restart will be backed up and transferred through the watchdog SRAM storage module, and will not be overwritten in the watchdog SRAM storage module, thereby further improving the reliability of the system.

[0059] like Figure 3 FIG. 1 is a state machine diagram of a watchdog timeout restart scene capture system provided by an embodiment of the present invention. It can be understood that there are a total of five states in the embodiment of the present invention, namely, initial state, start state, counting state, timeout state, and SRAM read / write state, among which:

[0060] The initial state is the reset state, which is similar to the shutdown state. The system is not working and registers cannot be read or written.

[0061] The open state is the reset release state, and the registers in the system can be read and written;

[0062] In counting state, when the timeout threshold is configured, the counter starts the accumulation operation;

[0063] Timeout state: When the counter value is equal to the timeout threshold, the system enters the timeout state. The timeout state is a protection operation after the timeout.

[0064] SRAM read-write state. After entering the timeout state, it is necessary to save the CPU scene and enter the SRAM read-write state. In addition, the system can also receive user operation instructions to enter the read-write state and read the SRAM contents.

[0065] The system structure and working principle of the embodiment of the present invention are described above. It can be understood that the embodiment of the present invention immediately backs up the abnormal scene information of the CPU to the watchdog SRAM module after the watchdog times out, and then resets the CPU. After the CPU is reset, the backed-up abnormal scene information is stored in the CPU memory, so that the debugging personnel can directly read the abnormal scene information from the CPU memory, which is convenient for the recovery of the CPU abnormal scene and the analysis of the abnormal cause; since the watchdog SRAM module is added to the watchdog architecture, the abnormal scene can be saved when the CPU has a hardware abnormality or a software abnormality, thereby improving the reliability of the system.

[0066] The embodiments of the present invention can be applied to system-on-chips, such as ARM chips, X86 chips, MIPS chips, etc. Compared with the existing technology, the embodiments of the present invention also have the following advantages:

[0067] 1) Innovation: There is no technology in the prior art that can save the abnormal scene through hardware and then reset the system;

[0068] 2) Reliability: The embodiment of the present invention can save the abnormal scene when the CPU software is abnormal and the hardware is abnormal, while the existing technology cannot save the abnormal scene when the hardware is abnormal;

[0069] 3) High efficiency: The embodiment of the present invention can be implemented through hardware to ensure that the system can be quickly reset after an abnormal timeout, thereby achieving foolproofing.

[0070] Reference Figure 4 The embodiment of the present invention provides a method for capturing a watchdog timeout restart scene, comprising the following steps:

[0071] S101, when the watchdog starts, it counts, and when the count value reaches a preset timeout threshold, it generates a first timeout signal;

[0072] S102, in response to the first timeout signal, saving the current scene information of the CPU as abnormal scene information to the watchdog SRAM storage module, setting the watchdog timeout flag to 1, and sending a first reset signal to the CPU;

[0073] S103, used to read the watchdog timeout flag when the CPU is reset. If the watchdog timeout flag is 1, obtain abnormal scene information from the watchdog SRAM storage module and send it to the CPU memory, set the watchdog timeout flag to 0, and restart the watchdog.

[0074] As a further optional implementation, the exception context information includes program counter information, program status register information, and stack register information.

[0075] As an optional implementation, the watchdog timeout restart scene capture method further includes the following steps:

[0076] When the CPU is reset, the watchdog timeout flag is read. If the watchdog timeout flag is 0, the watchdog is started through the watchdog start module.

[0077] As an optional implementation, the watchdog timeout restart scene capture method further includes the following steps:

[0078] Receive the user's operation instructions, obtain abnormal scene information from the CPU register according to the operation instructions, and return it to the user.

[0079] The contents of the above system embodiments are all applicable to the present method embodiments. The functions specifically implemented by the present method embodiments are the same as those of the above system embodiments, and the beneficial effects achieved are also the same as those achieved by the above system embodiments.

[0080] Reference Figure 5 The embodiment of the present invention provides a watchdog timeout restart scene capture device, comprising:

[0081] at least one processor;

[0082] at least one memory for storing at least one program;

[0083] When the at least one program is executed by the at least one processor, the at least one processor implements the watchdog timeout restart scene capture method.

[0084] The contents of the above method embodiments are all applicable to the present device embodiments. The functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0085] An embodiment of the present invention further provides a computer-readable storage medium storing a program executable by a processor. When the program is executed by the processor, it is used to execute the above-mentioned watchdog timeout restart scene capture method.

[0086] A computer-readable storage medium according to an embodiment of the present invention can execute a watchdog timeout restart on-site capture method provided by an embodiment of the method of the present invention, can execute any combination of implementation steps of the method embodiment, and has the corresponding functions and beneficial effects of the method.

[0087] The embodiment of the present invention also discloses a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs Figure 4 The method shown.

[0088] In some optional embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the above-mentioned boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the present invention is provided in an exemplary manner for the purpose of providing a more comprehensive understanding of the technology. The disclosed method is not limited to the operation and logic flow presented herein. Optional embodiments are contemplated in which the order of the various operations is changed and the sub-operations described as a part of a larger operation are performed independently.

[0089] In addition, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the above-mentioned functions and / or features can be integrated into a single physical device and / or software module, or one or more functions and / or features can be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present invention. More specifically, given the properties, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the module will be understood within the routine skills of an engineer. Therefore, a person skilled in the art can implement the present invention set forth in the claims using ordinary skills without undue experimentation. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0090] If the above functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the above methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program code.

[0091] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0092] More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic devices), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable media on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, deciphering, or processing in another suitable manner as necessary, and then stored in a computer memory.

[0093] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0094] In the above description of this specification, reference to the terms "one embodiment / example," "another embodiment / example," or "certain embodiments / examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0095] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

[0096] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A watchdog timeout restart scene capture system, characterized in that: include: A watchdog counting module, configured to count when the watchdog is started, and generate a first timeout signal when the count value reaches a preset timeout threshold; Watchdog SRAM storage module, used to store CPU abnormality field information; a watchdog timeout processing module, configured to respond to the first timeout signal, save the current field information of the CPU as the abnormal field information to the watchdog SRAM storage module, set the watchdog timeout flag to 1, and send a first reset signal to the CPU; A watchdog startup module, used to control the startup of the watchdog; A watchdog information acquisition module is used to read the watchdog timeout flag when the CPU is reset. If the watchdog timeout flag is 1, the abnormal field information is obtained from the watchdog SRAM storage module and sent to the CPU memory, the watchdog timeout flag is set to 0, and the watchdog is restarted through the watchdog startup module. If the watchdog timeout flag is 0, the watchdog is started through the watchdog startup module.

2. The watchdog timeout restart scene capture system according to claim 1, characterized in that: The exception context information includes program counter information, program status register information, and stack register information.

3. A watchdog timeout restart scene capture system according to claim 1, characterized in that: The watchdog timeout restart scene capture system also includes: The abnormal scene information viewing module is used to receive the user's operation instruction, obtain the abnormal scene information from the CPU memory according to the operation instruction, and return it to the user.

4. A watchdog timeout restart scene capture method, characterized in that: The following steps are involved: When the CPU is reset, the watchdog timeout flag is read, and if the watchdog timeout flag is 0, the watchdog is started by the watchdog starting module; When the watchdog starts counting, when the count value reaches a preset timeout threshold, a first timeout signal is generated; In response to the first timeout signal, the current field information of the CPU is saved as abnormal field information in the watchdog SRAM storage module, the watchdog timeout flag is set to 1, and a first reset signal is sent to the CPU; When the CPU is reset, the watchdog timeout flag is read. If the watchdog timeout flag is 1, the abnormal scene information is obtained from the watchdog SRAM storage module and sent to the CPU memory, the watchdog timeout flag is set to 0, and the watchdog is restarted.

5. The method for capturing a watchdog timeout restart according to claim 4, wherein: The exception context information includes program counter information, program status register information, and stack register information.

6. A method for capturing a watchdog timeout restart scene according to claim 4, characterized in that: The watchdog timeout restart scene capture method further comprises the following steps: Receive the user's operation instruction, obtain the abnormal scene information from the CPU memory according to the operation instruction, and return it to the user.

7. A watchdog timeout restart scene capture device, characterized in that: include: at least one processor; at least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements a watchdog timeout restart scene capture method according to any one of claims 4 to 6.

8. A computer-readable storage medium storing a program executable by a processor, characterized in that: The program executable by the processor is used to perform a watchdog timeout restart scene capture method according to any one of claims 4 to 6 when executed by the processor.

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