Group control circuit and semiconductor memory device including the same

Abstract

The present application relates to a group control circuit and a semiconductor memory device including the group control circuit. A group control circuit includes a selection signal generation circuit, and a first activation selection circuit and a second activation selection circuit. The selection signal generation circuit generates a source selection signal by synchronizing an incoming control signal. The first activation selection circuit generates a plurality of first activation selection signals in synchronization with a first edge clock signal. The second activation selection circuit generates a plurality of second activation selection signals in synchronization with a second edge clock signal. The first activation selection circuit and the second activation selection circuit have a parallel structure.

Description

Technical Field

[0001] Various embodiments of the present disclosure generally relate to a group control circuit and a semiconductor memory device including the group control circuit, and more particularly, to a group control circuit capable of generating control signals for sequentially controlling a plurality of circuits and a semiconductor memory device including the group control circuit. Background Art

[0002] Typically, integrated circuits, including semiconductor devices and semiconductor memory devices, have multiple internal circuits therein to perform various functions. These multiple internal circuits are designed to be activated at preset time points and to perform preset operations. Some of these multiple internal circuits have substantially the same activation point. Furthermore, some of these multiple internal circuits have different activation points.

[0003] Furthermore, integrated circuits receive power supply voltage and control the various operations of multiple internal circuits. In this case, when multiple internal circuits are activated at the same time, the power supply voltage suddenly drops due to the sudden increase in the amount of current supplied to the multiple internal circuits. Recently, as the voltage level of the power supply voltage applied to integrated circuits has become increasingly lower, this drop in power supply voltage has caused integrated circuit malfunctions. Summary of the Invention

[0004] In an embodiment of the present disclosure, a group control circuit may include: a selection signal generating circuit, which is configured to generate a source selection signal by synchronizing an entry control signal with one of a first edge clock signal and a second edge clock signal; a first activation selection circuit, which is configured to generate a plurality of first activation selection signals that are activated in sequence by synchronizing the source selection signal with the first edge clock signal; and a second activation selection circuit, which is configured to generate a plurality of second activation selection signals that are activated in sequence by synchronizing the source selection signal with the second edge clock signal, wherein the first activation selection circuit and the second activation selection circuit have a parallel structure, and the first edge clock signal and the second edge clock signal have different phases.

[0005] In an embodiment of the present disclosure, a group control circuit may include: a selection clock generation circuit, which is configured to generate a first selection clock signal and a second selection clock signal from a first edge clock signal and a second edge clock signal in the original order or in reverse order based on a mode control signal; a selection signal generation circuit, which is configured to generate a source selection signal by synchronizing an entry control signal with one of the first edge clock signal and the second edge clock signal; a first activation selection circuit, which is configured to generate a plurality of first activation selection signals that are activated in sequence by synchronizing the source selection signal alternately with the first edge clock signal and the first selection clock signal; and a second activation selection circuit, which is configured to generate a plurality of second activation selection signals that are activated in sequence by synchronizing the source selection signal alternately with the second edge clock signal and the second selection clock signal, wherein the first activation selection circuit and the second activation selection circuit have a parallel structure, and the first edge clock signal and the second edge clock signal have different phases.

[0006] In an embodiment of the present disclosure, a semiconductor memory device may include a group control circuit and multiple page buffer circuits, the group control circuit including: a selection signal generating circuit configured to generate a source selection signal by synchronizing an entry control signal with one of a first edge clock signal and a second edge clock signal; a first activation selection circuit configured to generate multiple first activation selection signals that are activated in sequence by synchronizing the source selection signal with the first edge clock signal; and a second activation selection circuit configured to generate multiple second activation selection signals that are activated in sequence by synchronizing the source selection signal with the second edge clock signal, and the multiple page buffer circuits are activated based on the multiple first activation selection signals and the multiple second activation selection signals and are configured to control read operations and write operations of the memory array circuit, wherein the first activation selection circuit and the second activation selection circuit have a parallel structure, and the first edge clock signal and the second edge clock signal have different phases.

[0007] In an embodiment of the present disclosure, a semiconductor memory device may include a group control circuit and a plurality of page buffer circuits, the group control circuit including: a selection clock generation circuit configured to generate a first selection clock signal and a second selection clock signal from a first edge clock signal and a second edge clock signal in an original order or in a reverse order, respectively, based on a mode control signal; a selection signal generation circuit configured to generate a source selection signal by synchronizing an entry control signal with one of the first edge clock signal and the second edge clock signal; a first activation selection circuit configured to generate a source selection signal by synchronizing an entry control signal with one of the first edge clock signal and the second edge clock signal; and a first activation selection circuit configured to generate a source selection signal by synchronizing the source selection signal with the first edge clock signal and the second edge clock signal alternately. a first activation selection circuit synchronized with a selection clock signal to generate a plurality of first activation selection signals that are activated in sequence; and a second activation selection circuit configured to generate a plurality of second activation selection signals that are activated in sequence by synchronizing the source selection signal alternately with the second edge clock signal and the second selection clock signal, and a plurality of page buffer circuits are activated based on the plurality of first activation selection signals and the plurality of second activation selection signals and are configured to control the read operation and the write operation of the memory array circuit, wherein the first activation selection circuit and the second activation selection circuit have a parallel structure, and the first edge clock signal and the second edge clock signal have different phases.

[0008] In an embodiment of the present disclosure, an integrated circuit may include: a source pulse circuit configured to generate a source pulse from a control pulse at an edge of one of a first source clock and a second source clock having phases opposite to each other; a series of first circuits configured to be activated to sequentially generate first pulses from the source pulse; and a series of second circuits configured to be activated to sequentially generate second pulses from the source pulse, wherein the even-numbered first circuits in the first circuits are sequentially activated in each cycle of the first even clock, and the odd-numbered first circuits in the first circuits are activated in each cycle of the first odd clock, and wherein the even-numbered second circuits in the second circuits are sequentially activated in each cycle of the second even clock, and the odd-numbered second circuits in the second circuits are activated in each cycle of the second odd clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a configuration of a group control circuit according to an embodiment of the present disclosure.

[0010] Figure 2 is a block diagram illustrating a configuration of a group control circuit according to an embodiment of the present disclosure.

[0011] Figure 3 This is an example of an embodiment according to the present disclosure. Figure 2 FIG4 is a waveform diagram of the circuit operation of the group control circuit.

[0012] Figure 4is a block diagram illustrating a configuration of a group control circuit according to an embodiment of the present disclosure.

[0013] Figure 5 This is an example of an embodiment according to the present disclosure. Figure 4 FIG. 5 is a diagram showing the structure of the selection clock generation circuit in FIG.

[0014] Figure 6 This is an example of an embodiment according to the present disclosure. Figure 4 1 is a block diagram showing the configuration of a selection signal generating circuit and a first activation selection circuit and a second activation selection circuit in FIG.

[0015] Figure 7 This is an example of an embodiment according to the present disclosure. Figure 4 Waveform diagram of the 4-split operation mode of the group control circuit.

[0016] Figure 8 is a block diagram illustrating a configuration of an interval control circuit according to an embodiment of the present disclosure.

[0017] Figure 9 This is an example of an application according to an embodiment of the present disclosure. Figure 8 The interval control circuit in Figure 4 FIG4 is a waveform diagram of the circuit operation of the group control circuit.

[0018] Figure 10 is a block diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The present disclosure provides structural and functional details for various embodiments. However, the scope of the present invention is not limited to any disclosed embodiment or is not limited by any disclosed embodiment, nor is it limited to any specific details provided herein. That is, it will be understood by those skilled in the art in light of this disclosure that any embodiment can be modified in various ways and any embodiment can have various forms. Therefore, the present invention covers all such variations that fall within the scope of the claims (including their equivalents). In addition, a particular embodiment does not necessarily include all the purposes or effects mentioned, nor does it only include such purposes or effects. Therefore, the scope of the present invention is not limited thereto.

[0020] Throughout the specification, references to "(one) embodiment" and the like are not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment. When the term "(s) embodiment" is used herein, it does not necessarily refer to all embodiments.

[0021] Terms such as "first" and "second" are used to distinguish one element from another element with the same or similar name. A first element in one instance may be named a second element in another instance without indicating any substantial change in the element itself.

[0022] The singular is intended to include the plural, unless explicitly stated otherwise or the context clearly indicates that only one is intended. Open-ended terms such as "including" or "having" should be understood to indicate the presence of the mentioned features, quantities, steps, operations, elements, components, or combinations thereof, but do not exclude the possibility that one or more other features, quantities, steps, operations, elements, components, or combinations thereof exist or can be added.

[0023] In each step, for ease of description, symbols (e.g., a, b, and c) are used, which do not necessarily indicate any particular order of steps or operations. According to the teachings herein, steps / operations can be performed in any suitable order unless a specific order is explicitly described or indicated by the context. In some cases, two or more steps / operations can be performed substantially simultaneously.

[0024] Unless otherwise defined, all terms used herein (including technical or scientific terms) have the same meaning as those generally understood by those skilled in the art. Unless explicitly defined in the application, terms defined in commonly used dictionaries should be interpreted in the context of the relevant technology and should not be interpreted as ideal or in an overly formal manner.

[0025] Various embodiments of the present disclosure are directed to providing a group control circuit having a parallel structure and capable of generating a plurality of activation selection signals that are activated in sequence.

[0026] Various embodiments of the present disclosure are directed to providing a semiconductor memory device capable of activating a plurality of page buffer circuits sequentially or in divisions of a preset number of activation points of the page buffer circuits.

[0027] Figure 1 is a block diagram illustrating a configuration of a group control circuit 100 according to an embodiment of the present disclosure.

[0028] Reference Figure 1 The group control circuit 100 has a parallel structure and can be configured to generate a plurality of activation selection signals SEL1_1 to SEL1_N and SEL2_1 to SEL2_M (N and M are each a natural number equal to or greater than 1) that are sequentially activated based on the incoming control signal CTR_ET. In more detail, the group control circuit 100 may include a selection signal generating circuit 110, a first activation selection circuit 120, and a second activation selection circuit 130.

[0029] First, the selection signal generation circuit 110 may be configured to generate the source selection signal SEL_S by synchronizing the entry control signal CTR_ET with the clock signal. The entry control signal CTR_ET may be a pulse signal activated at an entry point of an activation control operation of the group control circuit 100 .

[0030] For reference, the selection signal generation circuit 110 may use a clock signal synchronized with the entry control signal CTR_ET. Figure 3 As shown in , the entry control signal CTR_ET can be synchronized with the clock signal, so that the clock signal transitions when the entry control signal CTR_ET or the pulse signal is enabled. For example, the clock signal can be the first edge clock signal CLK_OD or the second edge clock signal CLK_EV, which will be described below. For reference, in this specification, as an example, the entry control signal CTR_ET is synchronized with the second edge clock signal CLK_EV.

[0031] Next, the first activation selection circuit 120 may be configured to generate a plurality of first activation selection signals SEL1_1 to SEL1_N that are sequentially activated by synchronizing the source selection signal SEL_S with the first edge clock signal CLK_OD.

[0032] Next, the second activation selection circuit 130 may be configured to generate a plurality of second activation selection signals SEL2_1 to SEL2_M that are sequentially activated by synchronizing the source selection signal SEL_S with the second edge clock signal CLK_EV.

[0033] The first activation selection circuit 120 and the second activation selection circuit 130 can each have a parallel structure for receiving the source select signal SEL_S. Furthermore, the first edge clock signal CLK_OD and the second edge clock signal CLK_EV can have different phases. For example, the first edge clock signal CLK_OD and the second edge clock signal CLK_EV can have a phase difference of 180°. That is, the phase of the first edge clock signal CLK_OD and the phase of the second edge clock signal CLK_EV can be in anti-phase relation.

[0034] Figure 2 is a block diagram illustrating a configuration of a group control circuit 200 according to an embodiment of the present disclosure.

[0035] Reference Figure 2 The group control circuit 200 may include a selection signal generating circuit 210, a first activation selection circuit 220, and a second activation selection circuit 230. The selection signal generating circuit 210, the first activation selection circuit 220, and the second activation selection circuit 230 may correspond to Figure 1The selection signal generating circuit 110, the first activation selection circuit 120 and the second activation selection circuit 130 in the embodiment.

[0036] First, the selection signal generating circuit 210 may include a first synchronization circuit 211 .

[0037] The first synchronization circuit 211 may be configured to output the source select signal SEL_S by synchronizing the input control signal CTR_ET based on the second edge clock signal CLK_EV. The second edge clock signal CLK_EV may be inverted by the inversion circuit INV and input to the first synchronization circuit 211. The first synchronization circuit 211 may be composed of, for example, a D flip-flop capable of performing a synchronization operation based on the output signal of the inversion circuit INV.

[0038] Next, the first activation selection circuit 220 can be configured to generate a plurality of first activation selection signals by shifting the source select signal SEL_S based on the first edge clock signal CLK_OD. As an example, the number of the plurality of first activation selection signals is, for example, three. That is, the first activation selection circuit 220 can generate the first to third activation selection signals SEL1_1 to SEL1_3 by shifting the source select signal SEL_S based on the first edge clock signal CLK_OD.

[0039] In more detail, the first activation selection circuit 220 may include second to fourth synchronization circuits 221 to 223. The second synchronization circuit 221 may output a first activation selection signal SEL1_1 by synchronizing the source selection signal SEL_S with the first edge clock signal CLK_OD. The third synchronization circuit 222 may output a second activation selection signal SEL1_2 by synchronizing the first activation selection signal SEL1_1 with the first edge clock signal CLK_OD. The fourth synchronization circuit 223 may output a third activation selection signal SEL1_3 by synchronizing the second activation selection signal SEL1_2 with the first edge clock signal CLK_OD. The second to fourth synchronization circuits 221 to 223 may each include, for example, a D-type flip-flop capable of performing synchronization operations based on the first edge clock signal CLK_OD.

[0040] Next, the second activation selection circuit 230 can be configured to generate a plurality of second activation selection signals by shifting the source select signal SEL_S based on the second edge clock signal CLK_EV. As an example, the number of the plurality of second activation selection signals is four. That is, the second activation selection circuit 230 can generate the fourth to seventh activation selection signals SEL2_1 to SEL2_4 by shifting the source select signal SEL_S based on the second edge clock signal CLK_EV.

[0041] In more detail, the second activation selection circuit 230 may include fifth to eighth synchronization circuits 231 to 234. The fifth synchronization circuit 231 may output a fourth activation selection signal SEL2_1 by synchronizing the source selection signal SEL_S with the second edge clock signal CLK_EV. The sixth synchronization circuit 232 may output a fifth activation selection signal SEL2_2 by synchronizing the fourth activation selection signal SEL2_1 with the second edge clock signal CLK_EV. The seventh synchronization circuit 233 may output a sixth activation selection signal SEL2_3 by synchronizing the fifth activation selection signal SEL2_2 with the second edge clock signal CLK_EV. The eighth synchronization circuit 234 may output a seventh activation selection signal SEL2_4 by synchronizing the sixth activation selection signal SEL2_3 with the second edge clock signal CLK_EV. The fifth to eighth synchronization circuits 231 to 234 may each include, for example, a D flip-flop capable of performing synchronization operations based on the second edge clock signal CLK_EV.

[0042] Figure 3 It is an example Figure 2 2 is a waveform diagram of the circuit operation of the group control circuit 200. Figure 3 A first edge clock signal CLK_OD, a second edge clock signal CLK_EV, an entry control signal CTR_ET, first to third active selection signals SEL1_1 to SEL1_3 , and fourth to seventh active selection signals SEL2_1 to SEL2_4 are illustrated.

[0043] In the following, for the convenience of description, reference will be made to Figure 2 and Figure 3 The circuit operation of the group control circuit 200 is described.

[0044] First, the first edge clock signal CLK_OD and the second edge clock signal CLK_EV may be clock signals having opposite phases to each other. Figure 2 The first synchronization circuit 211 of the selection signal generation circuit 210 in FIG. 1 can generate the source selection signal SEL_S by synchronizing the input control signal CTR_ET with the second edge clock signal CLK_EV. At this time, the second edge clock signal CLK_EV can be inverted by the inversion circuit INV and input to the first synchronization circuit 211. Therefore, the input control signal CTR_ET can be output as the source selection signal SEL_S in synchronization with the falling edge of the second edge clock signal CLK_EV.

[0045] Next, Figure 2The second synchronization circuit 221 in the embodiment can generate the first activation selection signal SEL1_1 by synchronizing the source selection signal SEL_S with the first edge clock signal CLK_OD. At this time, the second synchronization circuit 221 can perform a synchronization operation based on the rising edge of the first edge clock signal CLK_OD. Therefore, the source selection signal SEL_S can be output synchronously with the rising edge of the first edge clock signal CLK_OD as the first activation selection signal SEL1_1. Subsequently, the third synchronization circuit 222 can output the second activation selection signal SEL1_2 by synchronizing the first activation selection signal SEL1_1 with the rising edge of the first edge clock signal CLK_OD. Then, the fourth synchronization circuit 223 can output the third activation selection signal SEL1_3 by synchronizing the second activation selection signal SEL1_2 with the rising edge of the first edge clock signal CLK_OD.

[0046] That is, the first activation selection circuit 220 including the second to fourth synchronization circuits 221 to 223 can shift the source selection signal SEL_S in synchronization with the first edge clock signal CLK_OD. That is, the first activation selection circuit 220 can generate the first to third activation selection signals SEL1_1 to SEL1_3 that are sequentially activated by shifting the source selection signal SEL_S based on the first edge clock signal CLK_OD.

[0047] Next, Figure 2 The fifth synchronization circuit 231 in the embodiment can generate the fourth activation selection signal SEL2_1 by synchronizing the source selection signal SEL_S with the second edge clock signal CLK_EV. At this time, the fifth synchronization circuit 231 can perform a synchronization operation based on the rising edge of the second edge clock signal CLK_EV. Therefore, the source selection signal SEL_S can be output synchronously with the rising edge of the second edge clock signal CLK_EV as the fourth activation selection signal SEL2_1. Subsequently, the sixth synchronization circuit 232 can output the fifth activation selection signal SEL2_2 by synchronizing the fourth activation selection signal SEL2_1 with the rising edge of the second edge clock signal CLK_EV. Then, the seventh synchronization circuit 233 can output the sixth activation selection signal SEL2_3 by synchronizing the fifth activation selection signal SEL2_2 with the rising edge of the second edge clock signal CLK_EV. Then, the eighth synchronization circuit 234 may output the seventh activation selection signal SEL2_4 by synchronizing the sixth activation selection signal SEL2_3 with the rising edge of the second edge clock signal CLK_EV.

[0048] The second activation selection circuit 230, including the fifth to eighth synchronization circuits 231 to 234, can shift the source selection signal SEL_S in synchronization with the second edge clock signal CLK_EV. That is, the second activation selection circuit 230 can generate the fourth to seventh activation selection signals SEL2_1 to SEL2_4 that are sequentially activated by shifting the source selection signal SEL_S based on the second edge clock signal CLK_EV.

[0049] Hereinafter, for the sake of convenience of description and as an example, the first edge clock signal CLK_OD and the second edge clock signal CLK_EV each have a period of 100ns. In this case, the activation interval for each of the first to third activation selection signals SEL1_1 to SEL1_3 to transition from logic "low" to logic "high" may be 100ns. In addition, the activation interval for each of the fourth to seventh activation selection signals SEL2_1 to SEL2_4 to transition from logic "low" to logic "high" may also be 100ns. Therefore, as shown in FIG. Figure 3 It can be seen that the activation interval of each of the first to third activation selection signals SEL1_1 to SEL1_3 as multiple first activation selection signals and the activation interval of each of the fourth to seventh activation selection signals SEL2_1 to SEL2_4 as multiple second activation selection signals can each be 50ns.

[0050] Therefore, the group control circuit 200 according to the embodiment has a parallel structure and may generate first to third activation selection signals SEL1_1 to SEL1_3 and fourth to seventh activation selection signals SEL2_1 to SEL2_4 that are sequentially activated.

[0051] Figure 4 is a block diagram illustrating a configuration of a group control circuit 400 according to an embodiment of the present disclosure.

[0052] Reference Figure 4 , the group control circuit 400 may include a selection clock generation circuit 410 , a selection signal generation circuit 420 , a first activation selection circuit 430 , and a second activation selection circuit 440 .

[0053] Before describing the configuration of the group control circuit 400, the group control circuit 400 may be configured as follows: Figure 1 , a plurality of first activation selection signals SEL1_1 to SEL1_N and a plurality of second activation selection signals SEL2_1 to SEL2_M are generated. Figure 4 In the example, the number of the plurality of first activation selection signals is three, and the number of the plurality of second activation selection signals is four, as shown in FIG. Figure 2 That is, Figure 4 The group control circuit 400 may generate first to third active selection signals SEL1_1 to SEL1_3 and fourth to seventh active selection signals SEL2_1 to SEL2_4 .

[0054] First, the selection clock generation circuit 410 can be configured to generate a first selection clock signal CLK_S1 and a second selection clock signal CLK_S2 from the first edge clock signal CLK_OD and the second edge clock signal CLK_EV in the original order or in the reverse order, respectively, based on the mode control signal CTR_MD. The mode control signal CTR_MD can be a signal for controlling the division of activation of the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4.

[0055] In more detail, Figure 3 , the activation points of the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4 may be different from each other. That is, the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4 may divide the activation points for the plurality of internal circuits into seven. As will be described below, the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4 may divide the activation points for the plurality of internal circuits into a number less than seven (e.g., four) and control the divided activation points.

[0056] Hereinafter, for ease of description, a mode in which the activation points are divided into seven is defined as a "7-split operation mode," and a mode in which the activation points are divided into four is defined as a "4-split operation mode." The group control circuit 400 according to an embodiment can control the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4 in the 7-split operation mode or the 4-split operation mode based on the mode control signal CTR_MD. That is, the mode control signal CTR_MD can be a signal for controlling the split operation mode of the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4.

[0057] Next, the selection signal generation circuit 420 may be configured to generate a source selection signal SEL_S by synchronizing the entry control signal CTR_ET with the second edge clock signal CLK_EV. The selection signal generation circuit 420 may correspond to Figure 2 The selection signal generating circuit 210 in FIG. Figure 4 The selection signal generating circuit 420 in FIG. 4 may generate the source selection signal SEL_S by a synchronization operation on the incoming control signal CTR_ET based on the second edge clock signal CLK_EV.

[0058] Next, the first activation selection circuit 430 may be configured to generate first to third activation selection signals SEL1_1 to SEL1_3 that are sequentially activated by alternately synchronizing the source selection signal SEL_S with the first edge clock signal CLK_OD and the first selection clock signal CLK_S1 .

[0059] Next, the second activation selection circuit 440 may be configured to generate fourth to seventh activation selection signals SEL2_1 to SEL2_4 that are sequentially activated by alternately synchronizing the source selection signal SEL_S with the second edge clock signal CLK_EV and the second selection clock signal CLK_S2 .

[0060] As will be described below, the group control circuit 400 according to the embodiment can generate the first selection clock signal CLK_S1 and the second selection clock signal CLK_S2 based on the mode control signal CTR_MD. In addition, the group control circuit 400 can selectively control the 7-split operation mode and the 4-split operation mode based on the first selection clock signal CLK_S1 and the second selection clock signal CLK_S2.

[0061] Figure 5 This is an example of an embodiment according to the present disclosure. Figure 4 FIG. 4 is a diagram showing the configuration of the selection clock generation circuit 410.

[0062] Reference Figure 5 , the selection clock generation circuit 410 may include a multiplexing circuit 510 and an inverting circuit 520 .

[0063] First, the multiplexing circuit 510 may be configured to output the first edge clock signal CLK_OD or the second edge clock signal CLK_EV as the first selection clock signal CLK_S1 based on the mode control signal CTR_MD. The multiplexing circuit 510 may include, for example, a multiplexer MUX.

[0064] Next, the inversion circuit 520 can be configured to output the second selection clock signal CLK_S2 by inverting the first selection clock signal CLK_S1. The inversion circuit 520 can include an inversion circuit INV that receives the first selection clock signal CLK_S1, inverts the first selection clock signal CLK_S1, and outputs the inverted signal as the second selection clock signal CLK_S2.

[0065] Figure 6 This is an example of an embodiment according to the present disclosure. Figure 4 4 is a block diagram showing the configuration of the selection signal generation circuit 420 and the first activation selection circuit 430 and the second activation selection circuit 440 in FIG.

[0066] Reference Figure 6 , the selection signal generating circuit 420 may include a first synchronization circuit 421 .

[0067] The first synchronization circuit 421 may be configured to output the source selection signal SEL_S by synchronizing the input control signal CTR_ET based on the second edge clock signal CLK_EV. The second edge clock signal CLK_EV may be inverted by the inversion circuit INV and input to the first synchronization circuit 421.

[0068] Next, the first activation selection circuit 430 may be configured to generate a plurality of first activation selection signals by shifting the source selection signal SEL_S based on the first edge clock signal CLK_OD and the first selection clock signal CLK_S1. The plurality of first activation selection signals may include first to third activation selection signals SEL1_1 to SEL1_3.

[0069] In more detail, the first activation selection circuit 430 may include second to fourth synchronization circuits 431 to 433 as a plurality of activation circuits. The second synchronization circuit 431 may output a first activation selection signal SEL1_1 by synchronizing the source selection signal SEL_S with the first selection clock signal CLK_S1. The third synchronization circuit 432 may output a second activation selection signal SEL1_2 by synchronizing the first activation selection signal SEL1_1 with the first edge clock signal CLK_OD. The fourth synchronization circuit 433 may output a third activation selection signal SEL1_3 by synchronizing the second activation selection signal SEL1_2 with the first selection clock signal CLK_S1.

[0070] Next, the second activation selection circuit 440 can be configured to generate a plurality of second activation selection signals by shifting the source selection signal SEL_S based on the second edge clock signal CLK_EV and the second selection clock signal CLK_S2. The plurality of second activation selection signals can include fourth to seventh activation selection signals SEL2_1 to SEL2_4.

[0071] In more detail, the second activation selection circuit 440 may include fifth to eighth synchronization circuits 441 to 444. The fifth synchronization circuit 441 may output a fourth activation selection signal SEL2_1 by synchronizing the source selection signal SEL_S with the second edge clock signal CLK_EV. The sixth synchronization circuit 442 may output a fifth activation selection signal SEL2_2 by synchronizing the fourth activation selection signal SEL2_1 with the second selection clock signal CLK_S2. The seventh synchronization circuit 443 may output a sixth activation selection signal SEL2_3 by synchronizing the fifth activation selection signal SEL2_2 with the second edge clock signal CLK_EV. The eighth synchronization circuit 444 may output a seventh activation selection signal SEL2_4 by synchronizing the sixth activation selection signal SEL2_3 with the second selection clock signal CLK_S2.

[0072] Hereinafter, the embodiment will be described. Figure 4 7-split operation mode and 4-split operation mode of the group control circuit 400.

[0073] First, the 7-split operation mode will be described.

[0074] Reference Figure 4 Based on the mode control signal CTR_MD, the selection clock generation circuit 410 can generate a first selection clock signal CLK_S1 corresponding to the first edge clock signal CLK_OD and a second selection clock signal CLK_S2 corresponding to the second edge clock signal CLK_EV. Figure 5 As can be seen, in the 7-split operation mode, the multiplexing circuit 510 of the selection clock generation circuit 410 can output the first edge clock signal CLK_OD as the first selected clock signal CLK_S1 based on the mode control signal CTR_MD. Therefore, the first selected clock signal CLK_S1 can correspond to the first edge clock signal CLK_OD, and the second selected clock signal CLK_S2 can correspond to the second edge clock signal CLK_EV.

[0075] Therefore, something like Figure 2 The second synchronization circuit 221 to the fourth synchronization circuit 223, Figure 6The second synchronization circuit 431 to the fourth synchronization circuit 433 in the embodiment can perform a shift operation based on the first edge clock signal CLK_OD. Figure 2 The fifth to eighth synchronization circuits 231 to 234 , the fifth to eighth synchronization circuits 441 to 444 may perform a shift operation based on the second edge clock signal CLK_EV.

[0076] Therefore, if Figure 3 As shown, the first to third activation selection signals SEL1_1 to SEL1_3, which are a plurality of first activation selection signals output from the second to fourth synchronization circuits 431 to 433, may be sequentially activated. Figure 3 As shown, the fourth to seventh activation selection signals SEL2_1 to SEL2_4 , which are a plurality of second activation selection signals output from the fifth to eighth synchronization circuits 441 to 444 , may also be sequentially activated.

[0077] Therefore, the group control circuit 400 according to the embodiment can generate the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4, whose seven transition points are sequentially activated, based on the mode control signal CTR_MD. In addition, the group control circuit 400 can control the 7-split operation mode for multiple internal circuits through the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4.

[0078] Next, the 4-split operation mode will be described.

[0079] Reference Figure 4 Based on the mode control signal CTR_MD, the selection clock generation circuit 410 can generate a first selection clock signal CLK_S1 corresponding to the second edge clock signal CLK_EV and a second selection clock signal CLK_S2 corresponding to the first edge clock signal CLK_OD. Figure 5 As can be seen, in the 4-split operation mode, the multiplexing circuit 510 of the selection clock generation circuit 410 can output the second edge clock signal CLK_EV as the first selected clock signal CLK_S1 based on the mode control signal CTR_MD. Therefore, the first selected clock signal CLK_S1 can correspond to the second edge clock signal CLK_EV, and the second selected clock signal CLK_S2 can correspond to the first edge clock signal CLK_OD.

[0080] therefore, Figure 6The second synchronization circuit 431 and the fourth synchronization circuit 433 in the embodiment can receive the first selection clock signal CLK_S1 corresponding to the second edge clock signal CLK_EV and perform an activation operation, and the third synchronization circuit 432 can receive the first edge clock signal CLK_OD and perform a synchronization operation. In addition, the fifth synchronization circuit 441 and the seventh synchronization circuit 443 can receive the second edge clock signal CLK_EV and perform a synchronization operation, and the sixth synchronization circuit 442 and the eighth synchronization circuit 444 can receive the second selection clock signal CLK_S2 corresponding to the first edge clock signal CLK_OD and perform a synchronization operation.

[0081] Figure 7 This is an example of an embodiment according to the present disclosure. Figure 4 4-split operation mode waveform diagram of the group control circuit 400. Figure 7 A first edge clock signal CLK_OD, a second edge clock signal CLK_EV, an entry control signal CTR_ET, and first to third active selection signals SEL1_1 to SEL1_3 and fourth to seventh active selection signals SEL2_1 to SEL2_4 are illustrated.

[0082] In the following, for the convenience of description, reference will be made to Figure 6 and Figure 7 The 4-split operation mode of the group control circuit 400 is described.

[0083] First, the first edge clock signal CLK_OD and the second edge clock signal CLK_EV may be clock signals having opposite phases to each other. Figure 6 The first synchronization circuit 421 of the selection signal generation circuit 420 in FIG. 1 can generate the source selection signal SEL_S by synchronizing the input control signal CTR_ET with the second edge clock signal CLK_EV. At this time, the second edge clock signal CLK_EV can be inverted by the inversion circuit INV and input to the first synchronization circuit 421. Therefore, the input control signal CTR_ET can be output as the source selection signal SEL_S in synchronization with the falling edge of the second edge clock signal CLK_EV.

[0084] Next, Figure 6The second synchronization circuit 431 in the embodiment can generate the first activation selection signal SEL1_1 by synchronizing the source selection signal SEL_S with the first selection clock signal CLK_S1 corresponding to the second edge clock signal CLK_EV. At this time, the second synchronization circuit 431 can perform a synchronization operation based on the rising edge of the first selection clock signal CLK_S1. Therefore, the source selection signal SEL_S can be output synchronously with the rising edge of the first selection clock signal CLK_S1 as the first activation selection signal SEL1_1. Subsequently, the third synchronization circuit 432 can output the second activation selection signal SEL1_2 by synchronizing the first activation selection signal SEL1_1 with the rising edge of the first edge clock signal CLK_OD. Then, the fourth synchronization circuit 433 can output the third activation selection signal SEL1_3 by synchronizing the second activation selection signal SEL1_2 with the rising edge of the first selection clock signal CLK_S1.

[0085] The first activation selection circuit 430, including the second to fourth synchronization circuits 431 to 433, can shift the source selection signal SEL_S by alternately synchronizing the source selection signal SEL_S with the first edge clock signal CLK_OD and the first selection clock signal CLK_S1. That is, the first activation selection circuit 430 can generate first to third activation selection signals SEL1_1 to SEL1_3, which are activated sequentially, by shifting the source selection signal SEL_S based on the first edge clock signal CLK_OD and the first selection clock signal CLK_S1.

[0086] Next, Figure 6 The fifth synchronization circuit 441 in the embodiment can generate the fourth activation selection signal SEL2_1 by synchronizing the source selection signal SEL_S with the second edge clock signal CLK_EV. At this time, the fifth synchronization circuit 441 can perform a synchronization operation based on the rising edge of the second edge clock signal CLK_EV. Therefore, the source selection signal SEL_S can be output synchronously with the rising edge of the second edge clock signal CLK_EV as the fourth activation selection signal SEL2_1. Subsequently, the sixth synchronization circuit 442 can output the fifth activation selection signal SEL2_2 by synchronizing the fourth activation selection signal SEL2_1 with the rising edge of the second selection clock signal CLK_S2 corresponding to the first edge clock signal CLK_OD. Then, the seventh synchronization circuit 443 can output the sixth activation selection signal SEL2_3 by synchronizing the fifth activation selection signal SEL2_2 with the rising edge of the second edge clock signal CLK_EV. Then, the eighth synchronization circuit 444 may output the seventh activation selection signal SEL2_4 by synchronizing the sixth activation selection signal SEL2_3 with the rising edge of the second selection clock signal CLK_S2 .

[0087] The second activation selection circuit 440, which includes the fifth to eighth synchronization circuits 441 to 444, can shift the source selection signal SEL_S by alternately synchronizing the source selection signal SEL_S with the second edge clock signal CLK_EV and the second selection clock signal CLK_S2. That is, the second activation selection circuit 440 can generate the fourth to seventh activation selection signals SEL2_1 to SEL2_4 that are sequentially activated by shifting the source selection signal SEL_S based on the second edge clock signal CLK_EV and the second selection clock signal CLK_S2.

[0088] Hereinafter, for ease of description, the first edge clock signal CLK_OD and the second edge clock signal CLK_EV each have a period of 100 ns. In this case, the interval at which each of the first to third activation selection signals SEL1_1 to SEL1_3 transitions from logic "low" to logic "high" may be 50 ns. In addition, the activation interval at which each of the fourth to seventh activation selection signals SEL2_1 to SEL2_4 transitions from logic "low" to logic "high" may also be 50 ns. At this time, the first activation selection signal SEL1_1 and the fourth activation selection signal SEL2_1 may have substantially the same transition point, the second activation selection signal SEL1_2 and the fifth activation selection signal SEL2_2 may have substantially the same transition point, and the third activation selection signal SEL1_3 and the sixth activation selection signal SEL2_3 may have substantially the same transition point. That is, the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4 may have four transition points.

[0089] Therefore, the group control circuit 400 according to the embodiment can generate the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4, whose four transition points are sequentially activated, based on the mode control signal CTR_MD. In addition, the group control circuit 400 can control the 4-split operation mode for the plurality of internal circuits through the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4.

[0090] As from Figure 3 and Figure 7As can be seen, the source select signal SEL_S can be the first signal to be activated before the first to third activation select signals SEL1_1 to SEL1_3 and the fourth to seventh activation select signals SEL2_1 to SEL2_4. Furthermore, the source select signal SEL_S can be synchronized with the second edge clock signal CLK_EV. Therefore, similar to the first to third activation select signals SEL1_1 to SEL1_3 and the fourth to seventh activation select signals SEL2_1 to SEL2_4, the source select signal SEL_S can be used to divide the operation of multiple internal circuits.

[0091] In more detail, as Figure 3 It can be seen that the source selection signal SEL_S and the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4 can be activated in sequence at eight transition points. Figure 4 The group control circuit 400 may control an 8-division operation mode for a plurality of internal circuits through the source selection signal SEL_S and the first to third active selection signals SEL1_1 to SEL1_3 and the fourth to seventh active selection signals SEL2_1 to SEL2_4 .

[0092] Then, as from Figure 7 It can be seen that the source selection signal SEL_S and the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4 can be activated in sequence at five transition points. Figure 4 The group control circuit 400 may control a 5-split operation mode for a plurality of internal circuits through the source selection signal SEL_S and the first to third active selection signals SEL1_1 to SEL1_3 and the fourth to seventh active selection signals SEL2_1 to SEL2_4 .

[0093] According to the embodiment Figure 1 The group control circuit 100 in the embodiment can adjust the respective activation intervals of the source selection signal SEL_S and the plurality of first activation selection signals SEL1_1 to SEL1_N and the plurality of second activation selection signals SEL2_1 to SEL2_M. Figure 4The group control circuit 400 in the embodiment can adjust the activation intervals of the source selection signal SEL_S and the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4. The group control circuit according to the embodiment may further include an interval control circuit for adjusting the activation interval. Figure 8 Describe the interval control circuit.

[0094] Figure 8 is a block diagram illustrating a configuration of an interval control circuit 800 according to an embodiment of the present disclosure.

[0095] Reference Figure 8 , the interval control circuit 800 may include a first clock control circuit 810 and a second clock control circuit 820 .

[0096] First, the first clock control circuit 810 can be configured to output the first edge clock signal CLK_OD as is, or can divide the frequency based on the frequency division control signal CTR_DV and output the first edge clock signal CLK_OD. Here, frequency division can mean adjusting the period of the first edge clock signal CLK_OD to, for example, twice or 0.5 times. That is, the first clock control circuit 810 can be configured to adjust the period of the first edge clock signal CLK_OD based on the frequency division control signal CTR_DV. In more detail, the first clock control circuit 810 can include a first frequency division circuit 811 and a first selection circuit 812.

[0097] The first frequency dividing circuit 811 may be configured to divide the first edge clock signal CLK_OD and output it. That is, the first frequency dividing circuit 811 may be configured to change the first edge clock signal CLK_OD to have a period different from the original period. The first selection circuit 812 may be configured to selectively output the output signal of the first frequency dividing circuit 811 or the first edge clock signal CLK_OD based on the frequency dividing control signal CTR_DV. The output signal OUT_OD of the first selection circuit 812 may be provided as Figure 1 The first edge clock signal CLK_OD of the group control circuit 100 is provided as Figure 4 The first edge clock signal CLK_OD of the group control circuit 400 in.

[0098] Next, the second clock control circuit 820 can be configured to output the second edge clock signal CLK_EV as is, or to divide the second edge clock signal CLK_EV based on the frequency division control signal CTR_DV and output it. In other words, the second clock control circuit 820 can be configured to adjust the period of the second edge clock signal CLK_EV based on the frequency division control signal CTR_DV. In more detail, the second clock control circuit 820 can include a second frequency division circuit 821 and a second selection circuit 822.

[0099] The second frequency dividing circuit 821 may be configured to divide the second edge clock signal CLK_EV and output it. That is, the second frequency dividing circuit 821 may be configured to change the second edge clock signal CLK_EV to have a period different from the original period. The second selection circuit 822 may be configured to selectively output the output signal of the second frequency dividing circuit 821 or the second edge clock signal CLK_EV based on the frequency dividing control signal CTR_DV. The output signal OUT_EV of the second selection circuit 822 may be provided as Figure 1 The second edge clock signal CLK_EV of the group control circuit 100 may be provided as Figure 4 The second edge clock signal CLK_EV of the group control circuit 400 in.

[0100] exist Figure 4 In the embodiment, the mode control signal CTR_MD can be used as a control signal for controlling the split operation mode. Figure 8 The frequency division control signal CTR_DV can be used as a control signal for controlling whether to perform a frequency division operation for adjusting the period of the first edge clock signal CLK_OD and the second edge clock signal CLK_EV. The group control circuit 400 according to the embodiment can simultaneously control the mode control signal CTR_MD and the frequency division control signal CTR_DV by using substantially the same control signal. Figure 4 The split operation mode and whether to execute Figure 8 Frequency division operation.

[0101] Figure 9 This is an example of an application according to an embodiment of the present disclosure. Figure 8 The interval control circuit 800 in Figure 4 4 is a waveform diagram of the circuit operation of the group control circuit 400. As an example, the mode control signal CTR_MD and the frequency division control signal CTR_DV are control signals corresponding to each other.

[0102] First, refer to Figure 8 and Figure 9 (A), in 8-split operation mode, Figure 8The interval control circuit 800 in FIG. 8 can output the first edge clock signal CLK_OD and the second edge clock signal CLK_EV based on the frequency division control signal CTR_DV. Therefore, Figure 4 The group control circuit 400 in FIG. 4 may perform circuit operations such that the source selection signal SEL_S and the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4 have eight transition points, as shown in FIG. Figure 9 As shown in (A). Therefore, the group control circuit 400 can control the 8-split operation mode of multiple internal circuits based on the source selection signal SEL_S and the first activation selection signal SEL1_1 to the third activation selection signal SEL1_3 and the fourth activation selection signal SEL2_1 to the seventh activation selection signal SEL2_4. For reference, Figure 9 (A) can correspond to Figure 3 .

[0103] Next, refer to Figure 8 and Figure 9 (B), in 5-split operation mode, Figure 8 The interval control circuit 800 in FIG. 1 can divide the frequency of the first edge clock signal CLK_OD and output it, and divide the frequency of the second edge clock signal CLK_EV and output it, based on the frequency division control signal CTR_DV. That is, the first clock control circuit 810 can generate the output signal OUT_OD obtained by adjusting the period of the first edge clock signal CLK_OD, and the second clock control circuit 820 can generate the output signal OUT_EV obtained by adjusting the period of the second edge clock signal CLK_EV.

[0104] Then, Figure 4 The group control circuit 400 in FIG. 1 may generate the source selection signal SEL_S and the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4 based on the output signal OUT_OD of the first clock control circuit 810 and the output signal OUT_EV of the second clock control circuit 820. The group control circuit 400 may perform circuit operations such that the source selection signal SEL_S and the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4 have five transition points, such as Figure 9 Here, with Figure 9Compared to (A) in FIG. 1 , the activation intervals of the source select signal SEL_S and the first to third activation select signals SEL1_1 to SEL1_3 and the fourth to seventh activation select signals SEL2_1 to SEL2_4 can be controlled to be twice as large. Therefore, the group control circuit 400 can control the 5-split operation mode for the plurality of internal circuits based on the source select signal SEL_S and the first to third activation select signals SEL1_1 to SEL1_3 and the fourth to seventh activation select signals SEL2_1 to SEL2_4.

[0105] Hereinafter, for convenience of description, the first edge clock signal CLK_OD and the second edge clock signal CLK_EV each have a period of 100 ns.

[0106] exist Figure 9 In the case of (A), the source selection signal SEL_S and the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4 may each have an activation interval of 50 ns. Figure 9 In the case of (B), the source selection signal SEL_S and the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4 may each have an activation interval of 100 ns. By doing so, the group control circuit 400 according to the embodiment can adjust the activation interval in various ways along with the split operation mode.

[0107] Figure 10 is a block diagram illustrating a configuration of a semiconductor memory device 1000 according to an embodiment of the present disclosure.

[0108] Reference Figure 10 , the semiconductor memory device 1000 may include a memory array circuit 1010 , a plurality of page buffer circuits 1020 , and a group control circuit 1030 .

[0109] First, the memory array circuit 1010 may be configured to store data. The memory array circuit 1010 may include a plurality of memory cells. The semiconductor memory device 1000 may store data in the plurality of memory cells during a write operation and may output the data stored in the plurality of memory cells during a read operation.

[0110] Next, a plurality of page buffer circuits 1020 may be electrically connected to memory cells included in the memory array circuit 1010. The plurality of page buffer circuits 1020 may be configured to control read and write operations of the memory array circuit 1010. The plurality of page buffer circuits 1020 may be activated based on a plurality of activation selection signals SEL.

[0111] Next, the group control circuit 1030 may be configured to generate a plurality of activation selection signals SEL. The group control circuit 1030 may correspond to the reference Figures 1 to 9 The multiple activation selection signals SEL may include Figure 1 The plurality of activation selection signals SEL1_1 to SEL1_N and SEL2_1 to SEL2_M in the embodiment may include a reference Figures 2 to 9 The source selection signal SEL_S and the first to third activation selection signals SEL1_1 to SEL1_3 and the fourth to seventh activation selection signals SEL2_1 to SEL2_4 described above are described. Figures 1 to 9 A plurality of activation selection signals SEL are described, and thus a detailed description thereof will be omitted.

[0112] Therefore, the semiconductor memory device 1000 according to the embodiment may control activation operations of the plurality of page buffer circuits 1020 corresponding to the plurality of internal circuits in various manners based on the plurality of activation selection signals SEL.

[0113] According to an embodiment, a plurality of internal circuits are activated sequentially to prevent a power supply voltage drop, thereby improving stability and reliability of circuit operation.

[0114] Effects of the present disclosure are not limited to the above-described effects, and other effects that are not described above can be clearly understood from the above description by those skilled in the art to which the present disclosure pertains.

[0115] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the disclosure as defined by the following claims.

[0116] CROSS-REFERENCE TO RELATED APPLICATIONS

[0117] This application claims priority from Korean Application No. 10-2021-0003948, filed on January 12, 2021, which is hereby incorporated by reference in its entirety.

Claims

1. A group control circuit, comprising: a selection signal generating circuit that generates a source selection signal by synchronizing an incoming control signal with one of a first edge clock signal and a second edge clock signal; a first activation selection circuit configured to generate a plurality of first activation selection signals that are sequentially activated by synchronizing the source selection signal with the first edge clock signal; as well as a second activation selection circuit that generates a plurality of second activation selection signals that are sequentially activated by synchronizing the source selection signal with the second edge clock signal; The first activation selection circuit and the second activation selection circuit have a parallel structure, and the first edge clock signal and the second edge clock signal have different phases.

2. The group control circuit according to claim 1, wherein: The first edge clock signal and the second edge clock signal have a phase difference of 180°.

3. The group control circuit according to claim 1, wherein: The selection signal generation circuit includes a synchronization circuit that outputs the source selection signal by synchronizing the entry control signal with one of the first edge clock signal and the second edge clock signal.

4. The group control circuit according to claim 1, wherein: The first activation selection circuit includes a plurality of synchronization circuits configured to output the plurality of first activation selection signals by performing a shift operation on the source selection signal based on the first edge clock signal.

5. The group control circuit according to claim 1, wherein: The second activation selection circuit includes a plurality of synchronization circuits configured to output the plurality of second activation selection signals by performing a shift operation on the source selection signal based on the second edge clock signal. 6 . The group control circuit according to claim 1 , further comprising an interval control circuit that adjusts activation intervals of the source selection signal and the plurality of first activation selection signals and the plurality of second activation selection signals.

7. The group control circuit according to claim 6, wherein: The interval control circuit includes: a first clock control circuit, the first clock control circuit adjusting a period of the first edge clock signal based on a frequency division control signal; and A second clock control circuit is configured to adjust a period of the second edge clock signal based on the frequency division control signal.

8. A group control circuit, the group control circuit comprising: a selection clock generation circuit that generates a first selection clock signal and a second selection clock signal from the first edge clock signal and the second edge clock signal in an original order or in a reverse order based on a mode control signal; a selection signal generating circuit that generates a source selection signal by synchronizing an incoming control signal with one of the first edge clock signal and the second edge clock signal; a first activation selection circuit configured to generate a plurality of first activation selection signals that are sequentially activated by alternately synchronizing the source selection signal with the first edge clock signal and the first selection clock signal; as well as a second activation selection circuit that generates a plurality of second activation selection signals that are sequentially activated by alternately synchronizing the source selection signal with the second edge clock signal and the second selection clock signal; The first activation selection circuit and the second activation selection circuit have a parallel structure, and the first edge clock signal and the second edge clock signal have different phases.

9. The group control circuit according to claim 8, wherein: The first edge clock signal and the second edge clock signal have a phase difference of 180°.

10. The group control circuit according to claim 8, wherein: The selection clock generation circuit includes: a multiplexing circuit configured to output the first edge clock signal or the second edge clock signal as the first selection clock signal based on the mode control signal; and An inverting circuit outputs the second selection clock signal by inverting the first selection clock signal.

11. The group control circuit according to claim 8, wherein: The selection signal generation circuit includes a synchronization circuit that outputs the source selection signal by synchronizing the entry control signal with one of the first edge clock signal and the second edge clock signal.

12. The group control circuit according to claim 8, wherein: The first activation selection circuit includes a plurality of synchronization circuits configured to output the plurality of first activation selection signals by performing a shift operation on the source selection signal based on the first edge clock signal and the first selection clock signal.

13. The group control circuit according to claim 8, wherein: The second activation selection circuit includes a plurality of synchronization circuits configured to output the plurality of second activation selection signals by performing a shift operation on the source selection signal based on the second edge clock signal and the second selection clock signal. 14 . The group control circuit according to claim 8 , further comprising an interval control circuit that adjusts activation intervals of the source selection signal and the plurality of first activation selection signals and the plurality of second activation selection signals.

15. The group control circuit according to claim 14, wherein: The interval control circuit includes: a first clock control circuit configured to adjust a period of the first edge clock signal based on a frequency division control signal; and A second clock control circuit is configured to adjust a period of the second edge clock signal based on the frequency division control signal.

16. The group control circuit according to claim 15, wherein: The frequency division control signal and the mode control signal are control signals corresponding to each other.

17. A semiconductor memory device, comprising: A group control circuit, the group control circuit comprising: a selection signal generating circuit that generates a source selection signal by synchronizing an incoming control signal with one of a first edge clock signal and a second edge clock signal, a first activation selection circuit that generates a plurality of first activation selection signals that are sequentially activated by synchronizing the source selection signal with the first edge clock signal, and a second activation selection circuit that generates a plurality of second activation selection signals that are sequentially activated by synchronizing the source selection signal with the second edge clock signal; and a plurality of page buffer circuits that are activated based on the plurality of first activation selection signals and the plurality of second activation selection signals and control read operations and write operations of a memory array circuit, The first activation selection circuit and the second activation selection circuit have a parallel structure, and the first edge clock signal and the second edge clock signal have different phases.

18. A semiconductor memory device, comprising: A group control circuit, the group control circuit comprising: a selection clock generation circuit, the selection clock generation circuit generating a first selection clock signal and a second selection clock signal from the first edge clock signal and the second edge clock signal in original order or in reverse order, based on a mode control signal; a selection signal generating circuit that generates a source selection signal by synchronizing an incoming control signal with one of the first edge clock signal and the second edge clock signal, a first activation selection circuit that generates a plurality of first activation selection signals that are sequentially activated by alternately synchronizing the source selection signal with the first edge clock signal and the first selection clock signal; and a second activation selection circuit that generates a plurality of second activation selection signals that are sequentially activated by alternately synchronizing the source selection signal with the second edge clock signal and the second selection clock signal; and a plurality of page buffer circuits that are activated based on the plurality of first activation selection signals and the plurality of second activation selection signals and control read operations and write operations of a memory array circuit, The first activation selection circuit and the second activation selection circuit have a parallel structure, and the first edge clock signal and the second edge clock signal have different phases.

19. The semiconductor memory device according to claim 18, wherein The first activation selection circuit includes a plurality of synchronization circuits configured to output the plurality of first activation selection signals by performing a shift operation on the source selection signal based on the first edge clock signal and the first selection clock signal.

20. The semiconductor memory device according to claim 18, wherein The second activation selection circuit includes a plurality of synchronization circuits configured to output the plurality of second activation selection signals by performing a shift operation on the source selection signal based on the second edge clock signal and the second selection clock signal.

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