A fast-writing single-event upset resistant SRAM cell circuit

Abstract

A single-event upset resistant SRAM cell circuit with fast writing of the present invention includes eight NMOS transistors and six PMOS transistors, sequentially denoted as N1 to N8 and P1 to P6. For storage nodes Q and QB, PMOS transistors P1 and P2 serve as pull-up transistors, NMOS transistors N3 and N4 are controlled and reinforced by redundant nodes S0 and S1, and NMOS transistors N1 and N2 are cross-coupled as pull-down transistors; for redundant nodes S0 and S1, PMOS transistors P3 and P4 are cross-coupled as pull-up transistors, NMOS transistors N5 and N6 serve as pull-down transistors, and are controlled and reinforced by storage nodes Q and QB. Storage nodes Q and QB are connected to two bit lines BL and BLB through NMOS transistors N7 and N8, and the on / off of NMOS transistors N7 and N8 is controlled by word line WL. Storage nodes Q and QB are completely surrounded by NMOS transistors, and this structure is called a polarity reinforcement structure. In the present invention, PMOS transistors P5 and P6 control the on / off of the branches where redundant nodes S0 and S1 are located through storage nodes Q and QB, improving the pull-down ability of the redundant nodes and achieving a faster writing speed.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit radiation-resistant reinforced memory, and in particular to a fast-write single-event upset (SRAM) unit circuit. Background Art

[0002] Static Random Access Memory (SRAM), which occupies the largest area on a chip, has a bistable structure. Due to its high packaging density and lack of error shielding, SRAM circuits are highly susceptible to radiation exposure and single-event upsets (SEEs). Current solutions fail to provide SRAM circuits with both radiation resistance and fast write speeds. The present invention addresses the problem of designing an SRAM memory cell circuit that combines both radiation resistance and fast write speeds.

[0003] Currently, single-event effects (SEEs) caused by high-energy radiation particles have seriously impacted the reliability of integrated circuits used in space environments. When high-energy heavy ions from space strike semiconductor materials, they deposit energy and ionize them, generating electron-hole pairs. These ionized charges are collected by the device's electrodes, leading to a single-event effect (SEE), which can ultimately cause performance malfunction or degradation of the integrated circuit, resulting in loss of functionality or even a blockage. A SEE (Single Event Upset) occurs when the ionized charges generated by high-energy heavy ion impact are collected by transistor electrodes, generating a pulsed current that changes the logical state of the electrodes, causing errors in the integrated circuit system. SEEs are recoverable soft errors and a common form of SEE.

[0004] SRAM (Static Random Access Memory) memory has a bistable structure and lacks an error shielding mechanism. When a single-particle upset occurs in a storage node, the instantaneous error pulse will be transmitted to another storage node, causing an error upset in the other storage node; the upset of the other storage node will further maintain the error state of the irradiated node, and eventually all storage nodes in the SRAM will experience an error upset. The storage cell array in the memory chip based on SRAM technology occupies the largest area, so the probability of errors caused by radiation is the highest. As the process node shrinks, the packaging density of SRAM becomes higher and higher, and the possibility of a single particle incident interfering with multiple SRAM cells at the same time becomes greater and greater, thereby increasing the soft error rate of the SRAM chip. Current radiation hardening technologies mostly use the design method of adding redundant nodes, which often results in a significant reduction in write speed. The existing technologies mainly include the following solutions:

[0005] As Figure 1 shown, the Quatro-10T memory cell structure with radiation resistance was proposed by Shah M. Jahinuzzaman, David J. Rennie, Manoj Sachdev, etc. in 2009.

[0006] (2) As Figure 2 shown, the RH-12T memory cell structure with radiation resistance was proposed by Chunyan Hu, Suge Yue, Shijin Lu, etc. in 2017.

[0007] (3) As Figure 3 shown, the RHD-12T memory cell structure with radiation resistance was proposed by Chunhua Qi, Liyi Xiao, Tianqi Wang, Jie Li, Linzhe Li, etc. in 2016.

[0008] (4) As Figure 4 shown, the RSP-14T memory cell structure with radiation resistance was proposed by Chunyu Peng, Jiati Huang, Changyong Liu, etc. in 2017.

[0009] None of the above four technical solutions can simultaneously possess the characteristics of radiation resistance and fast writing. Therefore, we proposed an SRAM memory cell circuit that simultaneously has the characteristics of radiation resistance and fast writing.

[0010] The disadvantages of the existing technologies are as follows:

[0011] The existing radiation-resistant SRAM memory cell circuits cannot simultaneously possess the characteristics of complete radiation resistance and fast writing. The specific disadvantages of the existing cell circuits are as follows:

[0012] (1) Quatro-10T cell: The Quatro-10T cell has a certain radiation resistance, but the storage node does not have a complete recovery and inversion ability, and the writing speed is slow.

[0013] (2) RH-12T cell: Compared with the Quatro-10T cell, the RH-12T cell is strengthened by the polarity strengthening technology and has a complete single-event upset resistance, but the writing speed is slow.

[0014] (3) RHD-12T cell: The RHD-12T cell has a certain radiation resistance, but the storage node does not have a complete recovery and inversion ability, and the writing speed is slow.

[0015] (4) RSP-14T unit: The RSP-14T unit has a certain degree of radiation resistance, but the storage node does not have complete recovery flip capability. However, compared with the RHD-12T unit, the write speed is faster. Summary of the Invention

[0016] The present invention proposes a fast-write single-event upset (SEP)-resistant SRAM cell circuit. This circuit improves the radiation resistance of the SRAM structure through polarity reinforcement technology. By adding additional transistors, the pull-down capability of redundant nodes is enhanced, thereby increasing the write speed. This results in an SRAM storage cell structure that is both SEP-resistant and fast-write capable, addressing the aforementioned drawbacks.

[0017] To achieve the above object, the present invention adopts the following technical solutions:

[0018] A fast-write single-event upset-resistant SRAM cell circuit of the present invention includes eight NMOS transistors and six PMOS transistors, wherein the eight NMOS transistors are defined as first to eighth NMOS transistors, and the six PMOS transistors are defined as first to sixth PMOS transistors.

[0019] The electrical connection point between the first NMOS transistor and the third NMOS transistor is recorded as a storage node Q, the electrical connection point between the second NMOS transistor and the fourth NMOS transistor is recorded as a storage node QB, the electrical connection point between the fifth NMOS transistor and the fourth PMOS transistor is recorded as a redundant node S0, and the electrical connection point between the sixth NMOS transistor and the third PMOS transistor is recorded as a redundant node S1;

[0020] Redundant node S0 controls the fourth NMOS transistor and the first PMOS transistor, and redundant node S1 controls the third NMOS transistor and the second PMOS transistor, reinforcing storage nodes Q and QB. Storage nodes Q and QB are surrounded by the first NMOS transistor, the third NMOS transistor, the second NMOS transistor, and the fourth NMOS transistor, respectively. This structure is called a polarity reinforcement structure.

[0021] The storage nodes Q and QB control the fifth PMOS transistor and the sixth PMOS transistor respectively, directly controlling the on-off of the branch where the redundant nodes S0 and S1 are located, thereby improving the pull-down capability of the redundant nodes and increasing the writing speed;

[0022] The storage nodes Q and QB are connected to the two bit lines BL and BLB through the seventh and eighth NMOS transistors, and the on and off of the seventh and eighth NMOS transistors are controlled by the word line WL, wherein:

[0023] The seventh and eighth NMOS transistors are two transfer transistors, and the circuit uses these two transfer transistors for reading and writing. During the process of writing data, the bit lines BL and BLB write data to the storage nodes Q and QB simultaneously through the two transfer transistors.

[0024] The specific connection relationships of the above eight NMOS transistors and six PMOS transistors are as follows:

[0025] The drain of the first PMOS transistor is electrically connected to the source of the third NMOS transistor, and the gate of the first PMOS transistor is electrically connected to the drain of the fourth PMOS transistor;

[0026] The drain of the second PMOS transistor is electrically connected to the source of the fourth NMOS transistor, and the gate of the second PMOS transistor is electrically connected to the drain of the third PMOS transistor;

[0027] The source of the third PMOS transistor is electrically connected to the drain of the fifth PMOS transistor. The drain of the third PMOS transistor is electrically connected to the gate of the fourth PMOS transistor, and the gate of the third PMOS transistor is electrically connected to the drain of the fourth PMOS transistor;

[0028] The source of the fourth PMOS transistor is electrically connected to the drain of the sixth PMOS transistor. The drain of the fourth PMOS transistor is electrically connected to the gate of the third PMOS transistor and the gate of the fourth PMOS transistor is electrically connected to the drain of the third PMOS transistor;

[0029] The drain of the fifth PMOS transistor is electrically connected to the source of the third PMOS transistor, and the gate of the fifth PMOS transistor is electrically connected to the gate of the first NMOS transistor;

[0030] The drain of the sixth PMOS transistor is electrically connected to the source of the fourth PMOS transistor, and the gate of the sixth PMOS transistor is electrically connected to the gate of the second NMOS transistor;

[0031] The drain of the first NMOS transistor is electrically connected to the drain of the third NMOS transistor, and the gate of the first NMOS transistor is electrically connected to the gate of the second NMOS transistor;

[0032] The drain of the second NMOS transistor is electrically connected to the drain of the fourth NMOS transistor, and the gate of the second NMOS transistor is electrically connected to the gate of the first NMOS transistor;

[0033] The drain of the third NMOS transistor is electrically connected to the drain of the first NMOS transistor, the source of the third NMOS transistor is electrically connected to the drain of the first PMOS transistor, and the gate of the third NMOS transistor is electrically connected to the drain of the third PMOS transistor;

[0034] The drain of the fourth NMOS transistor is electrically connected to the drain of the second NMOS transistor, the source of the fourth NMOS transistor is electrically connected to the drain of the second PMOS transistor, and the gate of the fourth NMOS transistor is electrically connected to the drain of the fourth PMOS transistor;

[0035] The drain of the fifth NMOS transistor is electrically connected to the gate of the third PMOS transistor, and the gate of the fifth NMOS transistor is electrically connected to the drain of the first NMOS transistor;

[0036] The drain of the sixth NMOS transistor is electrically connected to the gate of the fourth PMOS transistor, and the gate of the sixth NMOS transistor is electrically connected to the drain of the second NMOS transistor;

[0037] The electrical connection point of the first NMOS transistor and the third NMOS transistor is denoted as the storage node Q, the electrical connection point of the second NMOS transistor and the fourth NMOS transistor is denoted as the storage node QB, the electrical connection point of the fifth NMOS transistor and the fourth PMOS transistor is denoted as the redundant node S0, and the electrical connection point of the sixth NMOS transistor and the third PMOS transistor is denoted as the redundant node S1.

[0038] The operation of a fast-write single-event upset resistant SRAM cell circuit according to the present invention is divided into three stages: a write stage, a hold stage, and a read stage.

[0039] When a fast-write single-event upset resistant SRAM cell circuit according to the present invention is in the write stage, the word line WL is at a high level. Assuming that the bit line BL is at a high level and BLB is at a low level, then through the first NMOS transistor, the third NMOS transistor, the seventh NMOS transistor, and the first PMOS transistor, a logic '1' is written to the storage node Q and the redundant node S1 respectively, and a logic '0' is written to the storage node QB and the redundant node S0; Assuming that the bit line BL is at a low level and BLB is at a high level, then through the second NMOS transistor, the fourth NMOS transistor, the eighth NMOS transistor, and the second PMOS transistor, a logic '0' is written to the storage node Q and the redundant node S1 respectively, and a logic '1' is written to the storage node QB and the redundant node S0;

[0040] When the fast-write single-event upset-resistant SRAM cell circuit of the present invention is in the holding phase, the bit lines BL and BLB are precharged to a high level, while the word line WL is at a low level, the circuit storage maintains the original state, and the circuit is in a closed state.

[0041] During the read phase of a fast-write, single-event upset-resistant SRAM cell circuit of the present invention, both bit lines BL and BLB are precharged to a high level, and word line WL is at a high level. Assuming the data stored at storage node Q of the circuit is a logic "1," storage node QB is at a low level, the seventh NMOS transistor is turned off, and the eighth NMOS transistor is turned on, causing the bit line BLB to discharge to ground through the eighth NMOS transistor. Assuming the data stored at storage node Q of the circuit is a logic "0," storage node QB is at a high level, the seventh NMOS transistor is turned on, and the eighth NMOS transistor is not turned on, causing the bit line BL to discharge to ground through the seventh NMOS transistor. When a certain voltage difference exists between the two bits, the small voltage difference can be amplified by a sense amplifier to read the stored data.

[0042] In a fast-write single-event upset-resistant SRAM cell circuit of the present invention, the storage nodes Q / QB and the redundant nodes S0 / S1 are both radiation-sensitive nodes. Assuming a data state of: Q=0, QB=1, S0=1, S1=0, the recovery process of each sensitive node after being irradiated by heavy ions is as follows:

[0043] (1) Note that the storage nodes Q / QB are completely surrounded by NMOS transistors. When heavy ions bombard the drain of the NMOS transistor, only a 1-0 flip occurs. Therefore, Q / QB is a node with a logic "0" and cannot flip under any circumstances. This effectively prevents the circuit state from flipping. This structure is called a polarity reinforcement structure. Therefore, in this data state, the logic level of the storage node Q is not affected by the radiation and always maintains the original logic "0" state.

[0044] (2) When the drain of the second NMOS transistor is affected by heavy ion irradiation, the logic level of the storage node QB of a fast-write anti-single event upset SRAM cell circuit of the present invention is pulled low and flipped, and the logic level becomes "0", thereby causing the fifth PMOS transistor to turn on and the first NMOS transistor and the sixth NMOS transistor to turn off. For the branch where the storage node Q is located, all transistors are in the off state, so the branch is in the off state and the logic level of the Q node will not change; for the branch where the redundant node S0 is located, the sixth PMOS transistor and the fourth PMOS transistor are on and the fifth NMOS transistor is off, so the branch is in the off state and the logic level of the S0 node will not flip; for the branch where the redundant node S1 is located, the fifth PMOS transistor is on, the third PMOS transistor is off, and the sixth NMOS transistor is off, so the branch is in the off state and the logic level of the S1 node will not flip. Since the storage nodes not affected by irradiation maintain their original logic levels and the PMOS transistor P2 and the NMOS transistor N4 are in the on state, the QB node can finally restore the correct logic level "1".

[0045] (3) When the drain of the fifth NMOS transistor is affected by heavy ion irradiation, the logic level of the redundant node S0 is pulled low and flipped, and the logic level becomes "0", thereby causing the first PMOS transistor and the third PMOS transistor to turn on and the fourth NMOS transistor to turn off. For the branch where the storage node Q is located, the first PMOS transistor is on, the first NMOS transistor is on, and the third NMOS transistor is off, so the branch is in the off state and the logic level of the Q node will not change; for the branch where the storage node QB is located, the second PMOS transistor is on, the second NMOS transistor and the fourth NMOS transistor are off, so the branch is in the off state and the logic level of the QB node will not change; for the branch where the redundant node S1 is located, the third PMOS transistor is on, the fifth PMOS transistor is off, and the sixth NMOS transistor is off, so the branch is in the off state and the logic level of the S1 node will not change; the storage nodes not affected by irradiation maintain their original logic levels, and the fourth PMOS transistor and the sixth PMOS transistor are on. Finally, the S0 node can restore the correct logic level "1".

[0046] (4) When the drain of the third PMOS transistor is affected by heavy ion irradiation, the logic level of the redundant node S1 of the fast-write single-particle upset-resistant SRAM unit circuit of the present invention is pulled up and flipped, and the logic level becomes "1", thereby causing the second PMOS transistor and the fourth PMOS transistor of the fast-write single-particle upset-resistant SRAM unit circuit of the present invention to be turned off, and the third NMOS transistor to be turned on. For the branch where the storage node Q is located, the first NMOS transistor and the third NMOS transistor are in the on state, and the first PMOS transistor is in the off state, so the branch is in the off state, and the logic level of the Q node will not change; for the branch where the storage node QB is located, the fourth NMOS transistor is in the on state, the second PMOS transistor is in the on state, and the second NMOS transistor is in the off state, so the branch is in the off state, and the logic level of the QB node will not change; for the branch where the redundant node S0 is located, the sixth PMOS transistor is in the on state, the fourth PMOS transistor is in the off state, and the fifth NMOS transistor is in the off state, so the branch is in the off state, and the logic level of the S0 node will not change; the storage nodes that are not affected by the radiation all maintain the original logic level, the sixth NMOS transistor is in the on state, the third PMOS transistor and the fifth PMOS transistor are in the off state, and finally the S1 node can restore the correct logic level "0".

[0047] From the above technical solution, it can be seen that the fast-write single-event upset-resistant SRAM unit circuit of the present invention has the following beneficial effects:

[0048] (1) The present invention utilizes polarity reinforcement technology and improves the pull-down capability of the redundant node through a pair of additional PMOS transistors, thereby improving the single-event upset resistance of the memory cell and increasing the write speed at a very small area cost.

[0049] (2) In a fast-write single-event upset-resistant SRAM cell circuit of the present invention, when any sensitive node is affected by radiation, the logic levels of other sensitive nodes can remain unchanged, thereby restoring the sensitive node that has been upset by radiation, and the data stored in the storage unit remains unchanged, thereby achieving the single-event upset resistance function.

[0050] (3) In a fast-write single-event upset-resistant SRAM unit circuit of the present invention, an additional transistor structure is used to improve the pull-down capability of the redundant node, thereby having a fast-write characteristic compared to a traditional SRAM storage structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 This is a schematic diagram of the Quatro-10T storage unit structure;

[0052] Figure 2 This is a schematic diagram of the RH-12T storage unit structure;

[0053] Figure 3 This is a schematic diagram of the RHD-12T storage unit structure;

[0054] Figure 4 This is a schematic diagram of the RSP-14T storage unit structure;

[0055] Figure 5 A schematic diagram of a fast-write single-event upset-resistant SRAM unit circuit of the present invention;

[0056] Figure 6 This is a functional verification waveform diagram of a fast-write single-event upset-resistant SRAM unit circuit of the present invention;

[0057] Figure 7 A verification waveform diagram of single event upset resistance when storage node Q=0 and QB=1 of a fast-write single event upset resistance SRAM unit circuit of the present invention;

[0058] Figure 8 A verification waveform diagram of single event upset resistance when storage node Q=1 and QB=0 of a fast-write single event upset resistance SRAM unit circuit of the present invention;

[0059] Q: represents the storage node;

[0060] QB: represents the inverted signal of the storage node;

[0061] S0: represents a redundant node, which is the inverted signal of the storage node Q;

[0062] S1: represents a redundant node, which is the inverted signal of the storage node QB;

[0063] BL: stands for bit line, which is the abbreviation of Bit-Line;

[0064] BLB: represents the bit line, which is the inverted signal of BL.

[0065] WL: stands for word line, which is the abbreviation of Word-Line;

[0066] NMOS: stands for N-type metal oxide semiconductor NMOS, which is N-Mental-

[0067] Oxide-Semiconductor abbreviation;

[0068] PMOS: P-type metal oxide semiconductor PMOS, P-Mental-

[0069] Abbreviation of Oxide - Semiconductor;

[0070] V DD : Represents the supply voltage;

[0071] GND: Represents the ground voltage;

[0072] SEU: Represents single - event upset, which is the abbreviation of Single Event Upset. Detailed implementation manners

[0073] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention.

[0074] A fast - write single - event - upset - resistant SRAM cell circuit of the present invention will be further described in detail below. The fast - write single - event - upset - resistant SRAM cell circuit of the present invention can not only achieve a fast - speed write function, but also has the ability to resist single - event upsets during data storage. The substantial features of the present invention will be further explained below according to the accompanying drawings and specific implementation cases.

[0075] Please refer to Figures 5 to 8 . A fast - write single - event - upset - resistant SRAM cell circuit of the present invention, whose circuit diagram is as Figure 5 shown. A fast - write single - event - upset - resistant SRAM cell circuit of the present invention includes eight NMOS transistors and six PMOS transistors. The eight NMOS transistors are respectively defined as the first to the eighth NMOS transistors, and the six PMOS transistors are respectively defined as the first to the sixth PMOS transistors.

[0076] The electrical connection point of the first NMOS transistor and the third NMOS transistor is denoted as the storage node Q, the electrical connection point of the second NMOS transistor and the fourth NMOS transistor is denoted as the storage node QB, the electrical connection point of the fifth NMOS transistor and the fourth PMOS transistor is denoted as the redundant node S0, and the electrical connection point of the sixth NMOS transistor and the third PMOS transistor is denoted as the redundant node S1.

[0077] The redundant node S0 controls the fourth NMOS transistor and the first PMOS transistor, and the redundant node S1 controls the third NMOS transistor and the second PMOS transistor to reinforce the storage nodes Q and QB; the storage nodes Q and QB are respectively surrounded by the first NMOS transistor, the third NMOS transistor and the second NMOS transistor, the fourth NMOS transistor, and this structure is called a polarity reinforcement structure;

[0078] The storage nodes Q and QB respectively control the fifth PMOS transistor and the sixth PMOS transistor, directly controlling the on / off of the branches where the redundant nodes S0 and S1 are located, improving the pull-down ability of the redundant nodes and the write speed.

[0079] The storage nodes Q and QB are connected to two bit lines BL and BLB through the seventh and eighth NMOS transistors, and the word line WL controls the on / off of the seventh and eighth NMOS transistors, where:

[0080] The seventh and eighth NMOS transistors are two transfer transistors, and the circuit uses these two transfer transistors for reading and writing. During the process of writing data, the bit lines BL and BLB write data to the storage nodes Q and QB simultaneously through the two transfer transistors.

[0081] The following is a specific description, including eight NMOS transistors and six PMOS transistors. The eight NMOS transistors are respectively defined as N1 to N8, and the six PMOS transistors are respectively defined as P1 to P6, where:

[0082] For the storage nodes Q and QB, the PMOS transistors P1 and P2 are used as pull-up transistors, the NMOS transistors N3 and N4 are controlled and reinforced by the redundant nodes S0 and S1, and the NMOS transistors N1 and N2 are cross-coupled as pull-down transistors; for the redundant nodes S0 and S1, the PMOS transistors P3 and P4 are cross-coupled as pull-up transistors, the NMOS transistors N5 and N6 are used as pull-down transistors, and are controlled and reinforced by the storage nodes Q and QB. The storage nodes Q and QB are respectively surrounded by the NMOS transistors N1, N3 and N2, N4, and this structure is called a polarity reinforcement structure. The PMOS transistors P5 and P6 control the on / off of the branches of the redundant nodes through the storage nodes, improving the pull-down ability of the redundant nodes and achieving a faster write speed.

[0083] The storage nodes Q and QB are connected to two bit lines BL and BLB through the NMOS transistors N7 and N8, and the word line WL controls the switching of the transistors N7 and N8, where:

[0084] The bit line BL is electrically connected to the source electrode of the NMOS transistor N7, and the bit line BLB is electrically connected to the source electrode of the NMOS transistor N8;

[0085] The drain of the NMOS transistor N7 is electrically connected to the gate of the NMOS transistor N2; the drain of the NMOS transistor N8 is electrically connected to the gate of the NMOS transistor N1; the word line WL is electrically connected to the gates of the NMOS transistors N7 and N8;

[0086] The power supply VDD is electrically connected to the sources of the PMOS transistors P1 , P2 , P5 , and P6 ; the ground GND is electrically connected to the sources of the NMOS transistors N1 , N2 , N5 , and N6 .

[0087] In specific implementation, such as Figure 5 The specific connection relationship between the eight NMOS transistors and the six PMOS transistors in the above structure is as follows:

[0088] The drain of the PMOS transistor P1 is electrically connected to the source of the NMOS transistor N3, and the gate of the PMOS transistor P1 is electrically connected to the drain of the PMOS transistor P4;

[0089] The drain of the PMOS transistor P2 is electrically connected to the source of the NMOS transistor N4, and the gate of the PMOS transistor P2 is electrically connected to the drain of the PMOS transistor P3;

[0090] The source of the PMOS transistor P3 is electrically connected to the drain of the PMOS transistor P5, the drain of the PMOS transistor P3 is electrically connected to the gate of the PMOS transistor P4, and the gate of the PMOS transistor P3 is electrically connected to the drain of the PMOS transistor P4;

[0091] The source of the PMOS transistor P4 is electrically connected to the drain of the PMOS transistor P6, the drain of the PMOS transistor P4 is electrically connected to the gate of the PMOS transistor P3, and the gate of the PMOS transistor P4 is electrically connected to the drain of the PMOS transistor P3;

[0092] The drain of the PMOS transistor P5 is electrically connected to the source of the PMOS transistor P3, and the gate of the PMOS transistor P5 is electrically connected to the gate of the NMOS transistor N1;

[0093] The drain of the PMOS transistor P6 is electrically connected to the source of the PMOS transistor P4, and the gate of the PMOS transistor P6 is electrically connected to the gate of the NMOS transistor N2;

[0094] The drain of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N3, and the gate of the NMOS transistor N1 is electrically connected to the gate of the NMOS transistor N2;

[0095] The drain of NMOS transistor N2 is electrically connected to the drain of NMOS transistor N4, and the gate of NMOS transistor N2 is electrically connected to the gate of NMOS transistor N1;

[0096] The drain of NMOS transistor N3 is electrically connected to the drain of NMOS transistor N1, the source of NMOS transistor N3 is electrically connected to the drain of PMOS transistor P1, and the gate of NMOS transistor N3 is electrically connected to the drain of PMOS transistor P3;

[0097] The drain of NMOS transistor N4 is electrically connected to the drain of NMOS transistor N2, the source of NMOS transistor N4 is electrically connected to the drain of PMOS transistor P2, and the gate of NMOS transistor N4 is electrically connected to the drain of PMOS transistor P4;

[0098] The drain of NMOS transistor N5 is electrically connected to the gate of PMOS transistor P3, and the gate of NMOS transistor N5 is electrically connected to the drain of NMOS transistor N1;

[0099] The drain of NMOS transistor N6 is electrically connected to the gate of PMOS transistor P4, and the gate of NMOS transistor N6 is electrically connected to the drain of NMOS transistor N2;

[0100] The electrical connection point of NMOS transistor N1 and NMOS transistor N3 is denoted as storage node Q, the electrical connection point of NMOS transistor N2 and NMOS transistor N4 is denoted as storage node QB, the electrical connection point of NMOS transistor N5 and the fourth PMOS transistor P4 is denoted as redundant node S0, and the electrical connection point of NMOS transistor N6 and PMOS transistor N3 is denoted as redundant node S1.

[0101] The operation of a fast-write single-event upset resistant SRAM cell circuit of the present invention is divided into three stages: write stage, hold stage, and read stage.

[0102] In the data writing stage of a fast-write single-event upset resistant SRAM cell circuit of the present invention, the word line WL is at a high level. Assuming that the bit line BL is at a high level and BLB is at a low level, then through transistors P1, N1, N3, and N7, logic "1" is written to storage node Q and redundant node S1 respectively, and logic "0" is written to storage node QB and redundant node S0; assuming that the bit line BL is at a low level and BLB is at a high level, then through transistors P2, N2, N4, and N8, logic "0" is written to storage node Q and redundant node S1 respectively, and logic "1" is written to storage node QB and redundant node S0;

[0103] When the fast-write single-event upset-resistant SRAM cell circuit of the present invention is in the holding phase, the bit lines BL and BLB are precharged to a high level, while the word line WL is at a low level, the circuit storage maintains the original state, and the circuit is in a closed state.

[0104] During the data reading phase of a fast-write, single-event upset-resistant SRAM cell circuit of the present invention, both bit lines BL and BLB are precharged to a high level, and word line WL is at a high level. Assuming the data stored at storage node Q in the circuit is a logic "1," storage node QB is at a low level, NMOS transistor N7 is turned off, and N8 is turned on, causing bit line BLB to discharge to ground through N8. Assuming the data stored at storage node Q in the circuit is a logic "0," storage node QB is at a high level, NMOS transistor N7 is turned on, and N8 is not turned on, causing bit line BL to discharge to ground through N7. When a certain voltage difference exists between the two bits, the small voltage difference can be amplified by a sense amplifier to read the stored data.

[0105] Specific implementation case 1:

[0106] When a fast-write single-event upset-resistant SRAM cell circuit of the present invention performs a write operation, the logic levels of the storage node are Q=0, QB=1, and the logic levels of the redundant node are S0=1, S1=0. In this case, the recovery process of each sensitive node after being irradiated by heavy ions is as follows:

[0107] (1) Note that the storage nodes Q / QB are completely surrounded by NMOS transistors. Heavy ion bombardment of the drain of the NMOS transistor can only produce a 1-0 flip. Therefore, Q / QB is a node at logic "0" and cannot flip under any circumstances. This effectively prevents the circuit state from flipping. This structure is called a polarity reinforcement structure. Therefore, in this data state, the logic level of the storage node Q of the fast-write single-event upset-resistant SRAM cell circuit of the present invention is not affected by radiation and always maintains the original logic "0" state.

[0108] (2) When the drain of the NMOS transistor N2 is affected by heavy ion irradiation, the logic level of the storage node QB of a fast-write single-event upset resistant SRAM cell circuit of the present invention is pulled low and flipped, and the logic level becomes "0", thereby causing the PMOS transistor P5 of a fast-write single-event upset resistant SRAM cell circuit of the present invention to turn on, and the NMOS transistors N1 and N6 to turn off. For the branch where the storage node Q is located, all transistors are in the off state, so the branch is in the off state and the logic level of the Q node will not change; for the branch where the redundant node S0 is located, the PMOS transistors P6 and P4 are on, and the NMOS transistor N5 is off, so the branch is in the off state and the logic level of the S0 node will not flip; for the branch where the redundant node S1 is located, the PMOS transistor P5 is on, the PMOS transistor P3 is off, and the NMOS transistor N6 is off, so the branch is in the off state and the logic level of the S1 node will not flip. Since the storage nodes not affected by irradiation maintain their original logic levels, the PMOS transistor P2 and the NMOS transistor N4 are in the on state, and finally the QB node can restore the correct logic level "1".

[0109] (3) When the drain of the NMOS transistor N5 is affected by heavy ion irradiation, the logic level of the redundant node S0 of a fast-write single-event upset resistant SRAM cell circuit of the present invention is pulled low and flipped, and the logic level becomes "0", thereby causing the PMOS transistors P3 and P1 of a fast-write single-event upset resistant SRAM cell circuit of the present invention to turn on, and the NMOS transistor N4 to turn off. For the branch where the storage node Q is located, the PMOS transistor P1 is on, the NMOS transistor N1 is on, and the NMOS transistor N3 is off, so the branch is in the off state and the logic level of the Q node will not change; for the branch where the storage node QB is located, the PMOS transistor P2 is on, and the NMOS transistors N2 and N4 are off, so the branch is in the off state and the logic level of the QB node will not change; for the branch where the redundant node S1 is located, the PMOS transistor P3 is on, the PMOS transistor P5 is off, and the NMOS transistor N6 is off, so the branch is in the off state and the logic level of the S1 node will not change; the storage nodes not affected by irradiation maintain their original logic levels, the PMOS transistors P4 and P6 are on, and finally the S0 node can restore the correct logic level "1".

[0110] (4) When the drain of the PMOS transistor P3 is affected by heavy ion irradiation, the logic level of the redundant node S1 of the fast-write single-particle upset-resistant SRAM unit circuit of the present invention is pulled up and flipped, and the logic level becomes "1", thereby causing the PMOS transistors P2 and P4 of the fast-write single-particle upset-resistant SRAM unit circuit of the present invention to be turned off and the NMOS transistor N3 to be turned on. For the branch where the storage node Q is located, NMOS transistors N1 and N3 are in the on state, and PMOS transistor P1 is in the off state, so the branch is in the off state, and the logic level of the Q node does not change; for the branch where the storage node QB is located, NMOS transistor N4 is in the on state, PMOS transistor P2 is in the on state, and NMOS transistor N2 is in the off state, so the branch is in the off state, and the logic level of the QB node does not change; for the branch where the redundant node S0 is located, PMOS transistor P6 is in the on state, PMOS transistor P4 is in the off state, and NMOS transistor N5 is in the off state, so the branch is in the off state, and the logic level of the S0 node does not change; the storage nodes that are not affected by the radiation all maintain the original logic level, NMOS transistor N6 is in the on state, and PMOS transistors P3 and P5 are in the off state, and finally the S1 node can restore the correct logic level "0".

[0111] Specific implementation case 2:

[0112] A fast-write single-event upset-resistant SRAM cell circuit of the present invention performs a write operation. The logic levels of the storage node are Q=1, QB=0, and the logic levels of the redundant node are S0=0, S1=1. In this case, the recovery process of each sensitive node after being irradiated by heavy ions is as follows:

[0113] (1) When the drain of the NMOS transistor N2 is affected by heavy ion irradiation, the logic level of the storage node Q of a fast-write single-event upset resistant SRAM cell circuit of the present invention is pulled low and flipped, and the logic level becomes "0", resulting in the turn-on of the PMOS transistor P6 of a fast-write single-event upset resistant SRAM cell circuit of the present invention, and the turn-off of the NMOS transistors N2 and N5. For the branch where the storage node QB is located, all transistors are in the off state, so the branch is in the off state and the logic level of the QB node will not change; for the branch where the redundant node S0 is located, the PMOS transistor P6 is on, the PMOS transistor P4 is off, and the NMOS transistor N5 is off, so the branch is in the off state and the logic level of the S0 node will not flip; for the branch where the redundant node S1 is located, the PMOS transistors P5 and P3 are on, and the NMOS transistor N6 is off, so the branch is in the off state and the logic level of the S1 node will not flip. Since the storage nodes not affected by irradiation maintain their original logic levels, the PMOS transistor P1 and the NMOS transistor N3 are in the on state, and finally the Q node can restore the correct logic level "1".

[0114] (2) Note that the storage nodes Q / QB are completely surrounded by NMOS transistors. When a heavy ion bombards the drain of the NMOS transistor, only a 1-0 flip can occur. Therefore, the nodes with Q / QB being logic "0" cannot be flipped under any circumstances, which effectively avoids the flip of the circuit state. This structure is called a polarity-reinforced structure. Therefore, in this data state, the logic level of the storage node QB of a fast-write single-event upset resistant SRAM cell circuit of the present invention will not be affected by irradiation and always maintains the original logic "0" state.

[0115] (3) When the drain of PMOS transistor P4 is affected by heavy ion irradiation, the logic level of the redundant node S0 of a fast-write single-event upset resistant SRAM cell circuit of the present invention is pulled high and flipped, and the logic level becomes "1", resulting in the turn-off of PMOS transistors P1 and P3 and the turn-on of NMOS transistor N4 in a fast-write single-event upset resistant SRAM cell circuit of the present invention. For the branch where the storage node Q is located, NMOS transistor N3 is in the on state, PMOS transistor P3 is in the on state, and NMOS transistor N3 is in the off state, so the branch is in the off state and the logic level of the Q node does not change; for the branch where the storage node QB is located, NMOS transistors N2 and N4 are in the on state, and PMOS transistor P2 is in the off state, so the branch is in the off state and the logic level of the QB node does not change; for the branch where the redundant node S1 is located, PMOS transistor P5 is in the on state, PMOS transistor P3 is in the off state, and NMOS transistor N6 is in the off state, so the branch is in the off state and the logic level of the S1 node does not change; the storage nodes not affected by irradiation maintain their original logic levels, NMOS transistor N5 is in the on state, and PMOS transistors P4 and P6 are in the off state. Finally, the S0 node can restore the correct logic level "0".

[0116] (4) When the drain of NMOS transistor N6 is affected by heavy ion irradiation, the logic level of the redundant node S1 of a fast-write single-event upset resistant SRAM cell circuit of the present invention is pulled low and flipped, and the logic level becomes "0", resulting in the turn-on of PMOS transistors P2 and P4 and the turn-off of NMOS transistor N3 in a fast-write single-event upset resistant SRAM cell circuit of the present invention. For the branch where the storage node QB is located, PMOS transistor P2 is in the on state, NMOS transistor N2 is in the on state, and NMOS transistor N4 is in the off state, so the branch is in the off state and the logic level of the QB node does not change; for the branch where the storage node Q is located, PMOS transistor P1 is in the on state, and NMOS transistors N1 and N3 are in the off state, so the branch is in the off state and the logic level of the Q node does not change; for the branch where the redundant node S0 is located, PMOS transistor P4 is in the on state, PMOS transistor P6 is in the off state, and NMOS transistor N5 is in the off state, so the branch is in the off state and the logic level of the S0 node does not change; the storage nodes not affected by irradiation maintain their original logic levels, and PMOS transistors P3 and P5 are in the on state. Finally, the S0 node can restore the correct logic level "1".

[0117] In summary, a single-event upset resistant SRAM cell circuit with fast writing of the present invention has the following main features:

[0118] 1. A single-event upset resistant SRAM cell circuit of the present invention includes eight NMOS transistors and six PMOS transistors. The eight NMOS transistors are respectively defined as the first to the eighth NMOS transistors, and the six PMOS transistors are respectively defined as the first to the sixth PMOS transistors, where:

[0119] The storage nodes Q and QB are connected to two bit lines BL and BLB through the seventh and eighth NMOS transistors, and the on / off states of the seventh NMOS transistor and the eighth NMOS transistor are controlled by a word line WL, where:

[0120] The bit line BL is electrically connected to the source of the seventh NMOS transistor, and the bit line BLB is electrically connected to the source of the eighth NMOS transistor;

[0121] The drain of the seventh NMOS transistor is electrically connected to the gate of the second NMOS transistor; the drain of the eighth NMOS transistor is electrically connected to the gate of the first NMOS transistor; the word line WL is electrically connected to the gates of the seventh and eighth NMOS transistors;

[0122] The power supply VDD is electrically connected to the sources of the first, second, fifth, and sixth PMOS transistors; the ground GND is electrically connected to the sources of the first, second, fifth, and sixth NMOS transistors.

[0123] In a specific implementation, as Figure 5 shown, the specific connection relationships of the eight NMOS transistors and the six PMOS transistors in the above structure are:

[0124] The drain of the first PMOS transistor is electrically connected to the source of the third NMOS transistor, and the gate of the first PMOS transistor is electrically connected to the drain of the fourth PMOS transistor;

[0125] The drain of the second PMOS transistor is electrically connected to the source of the fourth NMOS transistor, and the gate of the second PMOS transistor is electrically connected to the drain of the third PMOS transistor;

[0126] The source of the third PMOS transistor is electrically connected to the drain of the fifth PMOS transistor. The drain of the third PMOS transistor is electrically connected to the gate of the fourth PMOS transistor, and the gate of the third PMOS transistor is electrically connected to the drain of the fourth PMOS transistor;

[0127] The source of the fourth PMOS transistor is electrically connected to the drain of the sixth PMOS transistor, the drain of the fourth PMOS transistor is electrically connected to the gate of the third PMOS transistor, and the gate of the fourth PMOS transistor is electrically connected to the drain of the third PMOS transistor;

[0128] a drain of the fifth PMOS transistor is electrically connected to the source of the third PMOS transistor, and a gate of the fifth PMOS transistor is electrically connected to the gate of the first NMOS transistor;

[0129] a drain of the sixth PMOS transistor is electrically connected to the source of the fourth PMOS transistor, and a gate of the sixth PMOS transistor is electrically connected to the gate of the second NMOS transistor;

[0130] The drain of the first NMOS transistor is electrically connected to the drain of the third NMOS transistor, and the gate of the first NMOS transistor is electrically connected to the gate of the second NMOS transistor;

[0131] The drain of the second NMOS transistor is electrically connected to the drain of the fourth NMOS transistor, and the gate of the second NMOS transistor is electrically connected to the gate of the first NMOS transistor;

[0132] The drain of the third NMOS transistor is electrically connected to the drain of the first NMOS transistor, the source of the third NMOS transistor is electrically connected to the drain of the first PMOS transistor, and the gate of the third NMOS transistor is electrically connected to the drain of the third PMOS transistor;

[0133] The drain of the fourth NMOS transistor is electrically connected to the drain of the second NMOS transistor, the source of the fourth NMOS transistor is electrically connected to the drain of the second PMOS transistor, and the gate of the fourth NMOS transistor is electrically connected to the drain of the fourth PMOS transistor;

[0134] a drain of the fifth NMOS transistor is electrically connected to the gate of the third PMOS transistor, and a gate of the fifth NMOS transistor is electrically connected to the drain of the first NMOS transistor;

[0135] a drain of the sixth NMOS transistor is electrically connected to the gate of the fourth PMOS transistor, and a gate of the sixth NMOS transistor is electrically connected to the drain of the second NMOS transistor;

[0136] The electrical connection point between the first NMOS transistor and the third NMOS transistor is recorded as the storage node Q, the electrical connection point between the second NMOS transistor and the fourth NMOS transistor is recorded as the storage node QB, the electrical connection point between the fifth NMOS transistor and the fourth PMOS transistor is recorded as the redundant node S0, and the electrical connection point between the sixth NMOS transistor and the third PMOS transistor is recorded as the redundant node S1.

[0137] 2. A single-event upset resistant SRAM cell circuit with fast writing of the present invention utilizes a polarity reinforcement technique and improves the pull-down ability of redundant nodes through a pair of additional PMOS transistors. With a very small area cost, the single-event upset resistance of the storage cell is improved and the writing speed is increased.

[0138] 3. The operation of a single-event upset resistant SRAM cell circuit with fast writing of the present invention is divided into three stages: a writing stage, a holding stage, and a reading stage.

[0139] When a single-event upset resistant SRAM cell circuit with fast writing of the present invention is in the writing stage, the word line WL is at a high level. Assuming that the bit line BL is at a high level and BLB is at a low level, then through the first NMOS transistor, the third NMOS transistor, the seventh NMOS transistor, and the first PMOS transistor, logic "1" is written into the storage node Q and the redundant node S1 respectively, and logic "0" is written into the storage node QB and the redundant node S0 respectively; assuming that the bit line BL is at a low level and BLB is at a high level, then through the second NMOS transistor, the fourth NMOS transistor, the eighth NMOS transistor, and the second PMOS transistor, logic "0" is written into the storage node Q and the redundant node S1 respectively, and logic "1" is written into the storage node QB and the redundant node S0 respectively;

[0140] When a single-event upset resistant SRAM cell circuit with fast writing of the present invention is in the holding stage, the bit lines BL and BLB are both pre-charged to a high level, while the word line WL is at a low level. The circuit stores and maintains the original state, and the circuit is in an off state.

[0141] When a single-event upset resistant SRAM cell circuit with fast writing of the present invention is in the reading stage, the bit lines BL and BLB are both pre-charged to a high level, and the word line WL is at a high level. Assuming that the data stored in the storage node Q of the circuit is logic "1", then the storage node QB is at a low level, then the seventh NMOS transistor is turned off and the eighth NMOS transistor is turned on, causing the bit line BLB to discharge to ground through the eighth NMOS transistor; assuming that the data stored in the storage node Q of the circuit is logic "0", then the storage node QB is at a high level, then the seventh NMOS transistor is turned on and the eighth NMOS transistor is not turned on, causing the bit line BL to discharge to ground through the seventh NMOS transistor. When there is a certain voltage difference between the two bit lines, the tiny voltage difference can be amplified by a sense amplifier, thereby reading out the stored data.

[0142] 4. When the logic level of the storage node Q in a single-event upset resistant SRAM cell circuit with fast writing of the present invention is "0" and the recovery process after being flipped by ion radiation is as follows:

[0143] It is noted that the storage nodes Q / QB are completely surrounded by NMOS transistors. When the drain of the NMOS transistor is bombarded by heavy ions, only a 1-0 flip can occur. Therefore, for the node where Q / QB is at logic "0", it cannot be flipped under any circumstances, which effectively avoids the flipping of the circuit state. This structure is called a polarity-reinforced structure. Therefore, in this data state, the logic level of the storage node Q of a fast-writing single-event upset resistant SRAM cell circuit of the present invention will not be affected by irradiation and always remains in the original logic "0" state.

[0144] 5. When the logic level of the storage node QB in a fast-writing single-event upset resistant SRAM cell circuit of the present invention is "1" and undergoes the recovery process after being flipped by ion radiation:

[0145] When the drain of the second NMOS transistor is affected by heavy ion irradiation, the logic level of the storage node QB in a fast-writing single-event upset resistant SRAM cell circuit of the present invention is pulled low and flipped, and the logic level becomes "0", which causes the fifth PMOS transistor in a fast-writing single-event upset resistant SRAM cell circuit of the present invention to turn on, and the first NMOS transistor and the sixth NMOS transistor to turn off. For the branch where the storage node Q is located, all transistors are in the off state, so the branch is in the off state and the logic level of the Q node will not change; for the branch where the redundant node S0 is located, the sixth PMOS transistor and the fourth PMOS transistor turn on, and the fifth NMOS transistor turns off, so the branch is in the off state and the logic level of the S0 node will not be flipped; for the branch where the redundant node S1 is located, the fifth PMOS transistor turns on, the third PMOS transistor turns off, and the sixth NMOS transistor turns off, so the branch is in the off state and the logic level of the S1 node will not be flipped. Since the storage nodes not affected by irradiation all maintain their original logic levels, the PMOS transistor P2 and the NMOS transistor N4 are in the on state, and finally the QB node can recover to the correct logic level "1".

[0146] 6. When the logic level of the redundant node S0 in a fast-writing single-event upset resistant SRAM cell circuit of the present invention is "1" and undergoes the recovery process after being flipped by ion radiation:

[0147] When the drain of the fifth NMOS transistor is affected by heavy ion irradiation, the logic level of the redundant node S0 of the fast-write single-particle upset-resistant SRAM unit circuit of the present invention is pulled down and flipped, and the logic level becomes "0", thereby causing the first PMOS transistor and the third PMOS transistor of the fast-write single-particle upset-resistant SRAM unit circuit of the present invention to be turned on, and the fourth NMOS transistor to be turned off. For the branch where the storage node Q is located, the first PMOS transistor is in the on state, the first NMOS transistor is in the on state, and the third NMOS transistor is in the off state, so the branch is in the off state, and the logic level of the Q node does not change; for the branch where the storage node QB is located, the second PMOS transistor is in the on state, the second NMOS transistor and the fourth NMOS transistor are in the off state, so the branch is in the off state, and the logic level of the QB node does not change; for the branch where the redundant node S1 is located, the third PMOS transistor is in the on state, the fifth PMOS transistor is in the off state, and the sixth NMOS transistor is in the off state, so the branch is in the off state, and the logic level of the S1 node does not change; the storage nodes that are not affected by the radiation all maintain the original logic level, the fourth PMOS transistor and the sixth PMOS transistor are in the on state, and finally the S0 node can restore the correct logic level "1".

[0148] 7. When the logic level of the redundant node S1 of the fast-write single-event upset-resistant SRAM cell circuit of the present invention is "0", the recovery process after being upset by ion radiation is as follows:

[0149] When the drain of the third PMOS transistor is affected by heavy ion irradiation, the logic level of the redundant node S1 of a fast-writing single-event upset resistant SRAM cell circuit of the present invention is pulled high and flipped, and the logic level becomes "1", resulting in the turn-off of the second PMOS transistor and the fourth PMOS transistor of a fast-writing single-event upset resistant SRAM cell circuit of the present invention, and the turn-on of the third NMOS transistor. For the branch where the storage node Q is located, the first NMOS transistor and the third NMOS transistor are in the on state, and the first PMOS transistor is in the off state, so the branch is in the off state and the logic level of the Q node will not change; for the branch where the storage node QB is located, the fourth NMOS transistor is in the on state, the second PMOS transistor is in the on state, and the second NMOS transistor is in the off state, so the branch is in the off state and the logic level of the QB node will not change; for the branch where the redundant node S0 is located, the sixth PMOS transistor is in the on state, the fourth PMOS transistor is in the off state, and the fifth NMOS transistor is in the off state, so the branch is in the off state and the logic level of the S0 node will not change; the storage nodes not affected by irradiation all maintain their original logic levels, the sixth NMOS transistor is in the on state, and the third PMOS transistor and the fifth PMOS transistor are in the off state. Finally, the S1 node can restore the correct logic level "0".

[0150] It can be seen that the advantages of the present invention are as follows:

[0151] In a fast-writing single-event upset resistant SRAM cell circuit of the present invention, when any sensitive node is affected by irradiation, the logic levels of other sensitive nodes can remain unchanged, and then the sensitive node that has been flipped by irradiation can be restored, and the data stored in the storage unit remains unchanged, thus realizing the function of single-event upset resistance.

[0152] In a fast-writing single-event upset resistant SRAM cell circuit of the present invention, an additional transistor structure is adopted to improve the pull-down ability of the redundant node, so that it has the characteristic of fast writing compared with the traditional SRAM storage structure.

[0153] It should be noted that the structures, proportions, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those familiar with this technology to understand and read, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they do not have substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed in the present invention. At the same time, terms such as "left" and "right" cited in this specification are also only for the convenience of description and are not used to limit the scope of implementation of the present invention. Changes or adjustments in their relative relationships, without substantial changes in the technical content, should also be regarded as the scope within which the present invention can be implemented.

[0154] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A single-event upset resistant SRAM cell circuit with fast writing, characterized in that: It includes eight NMOS transistors and six PMOS transistors. The eight NMOS transistors are respectively defined as the first to the eighth NMOS transistors, and the six PMOS transistors are respectively defined as the first to the sixth PMOS transistors; The electrical connection point of the first NMOS transistor and the third NMOS transistor is denoted as the storage node Q, the electrical connection point of the second NMOS transistor and the fourth NMOS transistor is denoted as the storage node QB, the electrical connection point of the fifth NMOS transistor and the fourth PMOS transistor is denoted as the redundant node S0, and the electrical connection point of the sixth NMOS transistor and the third PMOS transistor is denoted as the redundant node S1; The redundant node S0 controls the fourth NMOS transistor and the first PMOS transistor to reinforce the storage node QB; the redundant node S1 controls the third NMOS transistor and the second PMOS transistor to reinforce the storage node Q; the storage nodes Q and QB are respectively surrounded by the first NMOS transistor, the third NMOS transistor and the second NMOS transistor, the fourth NMOS transistor to form a polarity reinforcement structure; The storage nodes Q and QB respectively control the fifth PMOS transistor and the sixth PMOS transistor to directly control the on-off of the branches where the redundant nodes S0 and S1 are located, improve the pull-down ability of the redundant nodes, and improve the writing speed; The storage nodes Q and QB are connected to two bit lines BL and BLB through the seventh and eighth NMOS transistors, and the on-off of the seventh and eighth NMOS transistors is controlled by the word line WL, where: The seventh and eighth NMOS transistors are two transfer transistors, and the circuit uses these two transfer transistors for reading and writing. During the process of writing data, the bit lines BL and BLB write data to the storage nodes Q and QB simultaneously through the two transfer transistors; The specific connection relationship of the above eight NMOS transistors and six PMOS transistors is as follows: The bit line BL is electrically connected to the source of the seventh NMOS transistor, and the bit line BLB is electrically connected to the source of the eighth NMOS transistor; The drain of the seventh NMOS transistor is electrically connected to the gate of the second NMOS transistor; the drain of the eighth NMOS transistor is electrically connected to the gate of the first NMOS transistor; the word line WL is electrically connected to the gates of the seventh and eighth NMOS transistors; The power supply VDD is electrically connected to the sources of the first, second, fifth and sixth PMOS transistors; The ground GND is electrically connected to the sources of the first, second, fifth and sixth NMOS transistors; The drain of the first PMOS transistor is electrically connected to the source of the third NMOS transistor, and the gate of the first PMOS transistor is electrically connected to the drain of the fourth PMOS transistor; The drain of the second PMOS transistor is electrically connected to the source of the fourth NMOS transistor, and the gate of the second PMOS transistor is electrically connected to the drain of the third PMOS transistor; The source of the third PMOS transistor is electrically connected to the drain of the fifth PMOS transistor, the drain of the third PMOS transistor is electrically connected to the gate of the fourth PMOS transistor, and the gate of the third PMOS transistor is electrically connected to the drain of the fourth PMOS transistor; The source of the fourth PMOS transistor is electrically connected to the drain of the sixth PMOS transistor, the drain of the fourth PMOS transistor is electrically connected to the gate of the third PMOS transistor and the gate of the fourth PMOS transistor is electrically connected to the drain of the third PMOS transistor; The drain of the fifth PMOS transistor is electrically connected to the source of the third PMOS transistor, and the gate of the fifth PMOS transistor is electrically connected to the gate of the first NMOS transistor; The drain of the sixth PMOS transistor is electrically connected to the source of the fourth PMOS transistor, and the gate of the sixth PMOS transistor is electrically connected to the gate of the second NMOS transistor; The drain of the first NMOS transistor is electrically connected to the drain of the third NMOS transistor, and the gate of the first NMOS transistor is electrically connected to the gate of the second NMOS transistor; The drain of the second NMOS transistor is electrically connected to the drain of the fourth NMOS transistor, and the gate of the second NMOS transistor is electrically connected to the gate of the first NMOS transistor; The drain of the third NMOS transistor is electrically connected to the drain of the first NMOS transistor, the source of the third NMOS transistor is electrically connected to the drain of the first PMOS transistor, and the gate of the third NMOS transistor is electrically connected to the drain of the third PMOS transistor; The drain of the fourth NMOS transistor is electrically connected to the drain of the second NMOS transistor, the source of the fourth NMOS transistor is electrically connected to the drain of the second PMOS transistor, and the gate of the fourth NMOS transistor is electrically connected to the drain of the fourth PMOS transistor; The drain of the fifth NMOS transistor is electrically connected to the gate of the third PMOS transistor, and the gate of the fifth NMOS transistor is electrically connected to the drain of the first NMOS transistor; The drain of the sixth NMOS transistor is electrically connected to the gate of the fourth PMOS transistor, and the gate of the sixth NMOS transistor is electrically connected to the drain of the second NMOS transistor.

2. The fast-write single-event upset resistant SRAM cell circuit according to claim 1, wherein: When the circuit is in the write phase, the word line WL is at a high level. If the bit line BL is at a high level and BLB is at a low level, then through the first NMOS transistor, the third NMOS transistor, the seventh NMOS transistor and the first PMOS transistor, logic "1" is written to the storage node Q and the redundant node S1 respectively, and logic "0" is written to the storage node QB and the redundant node S0; if the bit line BL is at a low level and BLB is at a high level, then through the second NMOS transistor, the fourth NMOS transistor, the eighth NMOS transistor and the second PMOS transistor, logic "0" is written to the storage node Q and the redundant node S1 respectively, and logic "1" is written to the storage node QB and the redundant node S0.

3. A single-event upset resistant SRAM cell circuit for fast writing according to claim 1, characterized in that: When the circuit is in the hold stage, the bit lines BL and BLB are both precharged to a high level, while the word line WL is at a low level, and the circuit stores and maintains its original state, and the circuit is in the off state.

4. A single-event upset resistant SRAM cell circuit for fast writing according to claim 1, characterized in that: When the circuit is in the readout stage, the bit lines BL and BLB are both precharged to a high level, and the word line WL is at a high level. If the data stored in the storage node Q of the circuit is logic "1", then the storage node QB is at a low level, and the seventh NMOS transistor is not turned on, and the eighth NMOS transistor is turned on, causing the bit line BLB to discharge to ground through the eighth NMOS transistor; if the data stored in the storage node Q of the circuit is logic "0", then the storage node QB is at a high level, and the seventh NMOS transistor is turned on, and the eighth NMOS transistor is not turned on, causing the bit line BL to discharge to ground through the seventh NMOS transistor; when there is a certain voltage difference between the two bit lines, the small voltage difference can be amplified by a sense amplifier to read out the stored data.

Images