Power semiconductor device and PFC circuit of integrated gate drive chip

Abstract

The present invention relates to a power semiconductor device integrated with a gate driver chip and a PFC circuit. The power semiconductor device includes an IGBT chip, a gate driver chip, and a dielectric isolation layer. A gate is provided on the surface of the IGBT chip. The gate driver chip is disposed on one side of the IGBT chip, and a drive output terminal is provided on the surface of the gate driver chip. The drive output terminal is electrically connected to the gate, and the dielectric isolation layer is disposed between the IGBT chip and the gate driver chip. By integrating the IGBT chip and the gate driver chip, and achieving isolation between the two through the dielectric isolation layer, the power semiconductor device of the present invention effectively reduces the volume of two separate chips, thereby reducing the area of PCB wiring applied to control circuits such as PFC circuits.

Description

Technical Field

[0001] The present invention relates to a power semiconductor device integrated with a gate driver chip and a PFC circuit, belonging to the technical field of semiconductor circuit applications. Background Art

[0002] The gate drive circuit for an IGBT (Insulated Gate Bipolar Transistor) is an integrated circuit product that converts an MCU signal into a driving signal for the IGBT. The gate driver chip integrates PMOS transistors, NMOS transistors, triodes, diodes, voltage regulators, resistors, and capacitors to form a Schmitt and filtering circuit. On the one hand, the gate drive circuit receives the control signal of the MCU and drives the subsequent IGBT to work. It is a key chip for IGBT drive. In traditional IGBT application circuits, a gate driver chip and driving resistors are set outside the IGBT, thus occupying a relatively large area on the PCB of the circuit. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to solve the problem that the existing IGBT tube has an external gate drive circuit, resulting in the corresponding control circuit occupying too much PCB area.

[0004] Specifically, the present invention discloses a power semiconductor device integrated with a drive chip, including:

[0005] An IGBT chip, on the surface of which a gate is provided;

[0006] A gate driver chip, which is arranged on one side of the IGBT chip, and a drive output pole is provided on the surface of the gate driver chip, wherein the drive output pole is electrically connected to the gate;

[0007] A dielectric isolation layer, which is arranged between the IGBT chip and the gate driver chip.

[0008] Optionally, the IGBT chip and the gate driver chip include a shared P-type substrate, and a buried oxide layer is provided on the front surface of the P-type substrate;

[0009] The IGBT chip includes LIGBT cells, and the gate driver chip includes a drive signal processing unit and CMOS cells. Among them, the CMOS cells serve as the gate drive unit of the LIGBT cells, the drive output pole is the output end of the gate drive unit, and the LIGBT cells and the CMOS cells are respectively arranged on both sides of the dielectric isolation layer.

[0010] Optionally, the LIGBT cells include:

[0011] A first N-type drift region;

[0012] An N-type buffer region, a collector region, a first P-well region, and an emitter region that form the front surface of the first N-type drift region, where the collector region is disposed within the N-type buffer region and the emitter region is disposed within the first P-well region.

[0013] Optionally, a first insulating layer is further disposed on the surface of the first N-type drift region, and conductive electrodes passing through the first insulating layer are disposed on the surfaces of the emitter region and the first P-well region to form an emitter, and a conductive electrode passing through the first insulating layer is disposed on the surface of the collector region to form a collector. A gate dielectric layer passing through the first insulating layer is further disposed on the front surface of the first P-well region, and a gate connected to the gate dielectric layer is disposed above the first insulating layer.

[0014] Optionally, the CMOS cell includes:

[0015] A second N-type drift region;

[0016] A second P-well region formed in the second N-type drift region and arranged in sequence, where a first body region, a first source region, and a first drain region are disposed within the second P-well region;

[0017] A second source region, a second drain region, and a second body region formed in the second N-type drift region and arranged in sequence.

[0018] Optionally, a second insulating layer is further disposed on the surface of the second N-type drift region;

[0019] Conductive electrodes passing through the second insulating layer are disposed on the surfaces of the first body region and the first source region to form an N-type source electrode, and a conductive electrode passing through the second insulating layer is disposed on the surface of the first drain region to form an N-type drain electrode. An N-type gate dielectric layer passing through the second insulating layer is disposed between the first source region and the first drain region, and an N-type gate connected to the N-type gate dielectric layer is disposed on the second insulating layer;

[0020] Conductive electrodes passing through the second insulating layer are disposed on the surface of the second source region to form a P-type source electrode, the P-type source electrode is electrically connected to the N-type drain electrode, and conductive electrodes passing through the second insulating layer are disposed on the surfaces of the second drain region and the second body region to form a P-type drain electrode. A P-type gate dielectric layer passing through the second insulating layer is disposed between the second source region and the second drain region, and a P-type gate connected to the P-type gate dielectric layer is disposed on the surface of the second insulating layer.

[0021] Optionally, the main component of the dielectric isolation layer is silicon dioxide, and the thickness of the dielectric isolation layer is 50 nm to 100 nm.

[0022] Optionally, the gate driver chip includes a power supply circuit, a Schmitt circuit, a filtering circuit, a level conversion circuit, and a half-bridge driving circuit. The power supply circuit supplies power for the operation of other circuits. The input end of the Schmitt circuit is the input end of the gate driver chip. The Schmitt circuit shapes the input control signal. The output end of the Schmitt circuit is connected to the filtering circuit. The filtering circuit filters the signal output by the Schmitt circuit. The output end of the filtering circuit is connected to the level conversion circuit. The level conversion circuit boosts the signal output by the filtering circuit. The output end of the level conversion circuit is connected to the half-bridge driving circuit. The output end of the half-bridge driving circuit is the driving output terminal of the gate driver chip.

[0023] The present invention also provides a PFC circuit, and the PFC circuit is provided with the above-mentioned power semiconductor device.

[0024] The power semiconductor device of the present invention includes an IGBT chip, a gate driver chip, and a dielectric isolation layer. A gate is provided on the surface of the IGBT chip. The gate driver chip is disposed on one side of the IGBT chip, and a driving output terminal is provided on the surface of the gate driver chip. The driving output terminal is electrically connected to the gate. The dielectric isolation layer is disposed between the IGBT chip and the gate driver chip. By integrating the IGBT chip and the gate driver chip, isolation is achieved between the two through the dielectric isolation layer, effectively reducing the volume of the two separate chips, thereby reducing the PCB wiring area in the control circuit such as the PFC circuit. Description of the Drawings

[0025] Figure 1 It is a structural block diagram of the power semiconductor device according to an embodiment of the present invention;

[0026] Figure 2 It is a structural schematic diagram of the power semiconductor device according to an embodiment of the present invention;

[0027] Figure 3 It is a circuit schematic diagram of the driving chip of the power semiconductor device according to an embodiment of the present invention;

[0028] Figure 4 It is a circuit schematic diagram of the PFC circuit according to an embodiment of the present invention.

[0029] Reference Signs:

[0030] IGBT chip 100, first N-type drift region 101, collector 102, collector region 103, N-type buffer region 104, first insulating layer 105, gate 106, gate dielectric layer 107, emitter region 108, emitter 109, first P-well region 110, gate drive chip 200, power supply circuit 220, Schmitt circuit 230, filter circuit 240, level conversion circuit 250, half-bridge drive circuit 260, first body region 261, N-type source 262, first source region 263, N-type gate 264, N-type gate dielectric layer 265, first drain region 266, N-type drain 267, P-type source 268, second source region 269, second drain region 26A, P-type drain 26B, second body region 26C, second insulating layer 26D, second P-well region 26E, P-type gate dielectric layer 26F, P-type gate 26G, second N-type drift region 26H, dielectric isolation layer 300, buried oxide layer 410, P-type substrate 420. Detailed implementation manners

[0031] To enable those skilled in the art to better understand the solution of this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application.

[0032] It should be noted that, without conflict in structure or function, the embodiments in the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0033] The present invention proposes a power semiconductor device integrated with a gate drive chip 200, where the power semiconductor device here is an IGBT transistor, as Figure 1 shown, the IGBT transistor includes an IGBT chip 100, a gate drive chip 200, and a dielectric isolation layer 300. The dielectric isolation layer 300 is vertically arranged, and the IGBT chip 100 and the gate drive chip 200 are respectively arranged on the left and right sides of the dielectric isolation layer 300. The main component of the dielectric isolation layer 300 is silicon dioxide, and its thickness is generally between 50 nm and 100 nm, playing an insulating isolation role between the two. A gate 106 is arranged near the dielectric isolation layer 300 on the IGBT chip 100, and a drive output terminal is arranged near the dielectric isolation layer 300 on the gate drive chip 200. The gate 106 and the drive output terminal are electrically connected, specifically, the two are connected through a resistor, so as to realize the drive of the IGBT transistor by the gate drive chip 200.

[0034] The power semiconductor device of the present invention integrates the IGBT chip 100 and the gate drive chip 200, and the isolation between the two is achieved through the dielectric isolation layer 300, thereby effectively reducing the volume of the two separate chips, and thus reducing the PCB wiring area applied to control circuits such as PFC circuits. Moreover, due to the integration of the IGBT chip 100 and the gate drive chip 200, the transmission distance of the drive signal transmitted from the gate drive chip 200 to the IGBT chip 100 is greatly shortened, thereby improving the anti-interference ability of the gate drive circuit where the gate drive chip 200 is located, and contributing to improving the working reliability of the control circuit. Further, since the gate 106 of the IGBT chip 100 and the drive output pole of the gate drive chip 200 are both arranged close to the dielectric isolation layer 300, the signal line connecting the two is further shortened, thereby further reducing the transmission distance of the drive signal, and thus further improving the anti-interference ability of the gate drive circuit.

[0035] Specifically, in some embodiments of the present invention, as Figure 3 shown, the internal circuit of the gate drive chip 200 includes a power supply circuit 220, a Schmitt circuit 230, a filtering circuit 240, a level conversion circuit 250, and a half-bridge drive circuit 260. Among them, the power supply circuit 220 converts the input power supply, such as boosting or bucking it into a stable direct current, to provide power for the operation of other circuits. The Schmitt circuit 230 realizes signal shaping, converting the input control signal into a regular square wave. The output end of the Schmitt circuit 230 is connected to the filtering circuit 240 to further filter out the interference clutter in the square wave signal. The output end of the filtering circuit 240 is connected to the level conversion circuit 250 to boost the square wave signal to meet the level requirements for driving the subsequent stage. The output end of the level conversion circuit 250 is connected to the half-bridge drive circuit 260. The half-bridge drive circuit 260 is mainly composed of a CMOS (Complementary Metal Oxide Semiconductor) unit composed of a PMOS (Positive-channel Metal Oxide Semiconductor, P-channel metal oxide semiconductor) transistor and an NMOS (Negative-channel-Metal-Oxide-Semiconductor, N-channel metal oxide semiconductor) transistor to realize the half-bridge drive function. Among them, the output end HO is the output pole where the source of the PMOS transistor and the drain of the NMOS transistor are commonly connected.

[0036] In some embodiments of the present invention, as Figure 2As shown, the IGBT chip 100 and the gate driver chip 200 include a common P-type substrate 420, and a common buried oxide layer 410 is disposed on the front surface of the P-type substrate 420. The IGBT chip 100 includes LIGBT cells, and the gate driver chip 200 includes a drive signal processing unit and a gate driver unit. The LIGBT cells and the CMOS cells are disposed on the surface of the buried oxide layer 410, and the LIGBT cells and the CMOS cells are respectively disposed on both sides of the dielectric isolation layer 300. Among them, the drive signal processing unit mainly includes the power supply circuit 220, the Schmitt circuit 230, the filter circuit 240, and the level conversion circuit 250 mentioned in the above embodiments, and the gate driver unit is mainly composed of CMOS cells.

[0037] Among them, the P-type substrate 420 is made of a P-type silicon wafer with a relatively low doping concentration. For example, the silicon wafer material can be pure silicon or synthetic silicon such as silicon, silicon carbide, silicon germanide, etc. For example, the P-type substrate 420 can be a silicon substrate. The buried oxide layer 410, as an insulating isolation layer, can be made of silicon dioxide, and its thickness is generally 2 μm. The LIGBT cell is the main unit that constitutes the IGBT chip 100 to perform its functions, and its structure can be a lateral or vertical structure. In this embodiment, it is a lateral structure, that is, an LIGBT cell. A collector 102, a gate 106, and an emitter 109 are disposed on the front surface of the LIGBT cell, and the gate 106 is disposed close to the dielectric isolation layer 300. The CMOS cell is the gate driver unit of the gate driver chip 200, and the drive output terminal of the gate driver chip 200 is the output terminal HO of the gate driver unit. The positive power supply and the negative power supply of the CMOS cell are respectively connected to the positive electrode VB of the high-voltage direct current and the negative electrode VS of the high-voltage direct current.

[0038] Specifically, as Figure 2As shown, the LIGBT cell includes a first N-type drift region 101, and an N-type buffer region 104, a collector region 103, a first P-well region 110, an emitter region 108, a gate dielectric layer 107, and a gate 106 formed on the front surface of the first N-type drift region 101. The collector region 103 is disposed within the N-type buffer region 104, and the emitter region 108 is disposed within the first P-well region 110. The first N-type drift region 101 is an N-type with a low doping concentration, and the bottom surface of the first N-type drift region 101 is connected to the surface of the dielectric isolation layer 300. On the front surface of the first N-type drift region 101, the N-type buffer region 104, the collector region 103, the first P-well region 110, and the emitter region 108 made of silicon material can be fabricated through a photolithography and diffusion process respectively. The N-type buffer region 104 is an N-type with a low doping concentration. The collector region 103 is disposed within the N-type buffer region 104 and is a P-type with a high doping concentration. The first P-well region 110 serves as a local substrate and is a P-type with a relatively low doping concentration. The emitter region 108 is disposed within the first P-well region 110 and is an N-type with a high doping concentration. The first P-well region 110 is disposed close to the dielectric isolation layer 300, so that the emitter region 108 located in the first P-well region 110 is disposed close to the dielectric isolation layer 300. The N-type buffer region 104 functions to increase the distance between the electric ions in the depletion region of the PN junction during conduction, that is, to reduce the electric field strength under the same conduction voltage, thereby increasing the on-resistance of the LIGBT cell during conduction and avoiding too rapid a change in dv / dt.

[0039] Furthermore, a relatively thin first insulating layer 105 is also disposed on the surface of the first N-type drift region 101. The first insulating layer 105 can be made of silicon dioxide material. A conducting electrode passing through the first insulating layer 105 is disposed on the surface of the collector region 103 to form a collector 102, that is, the collector 102 is connected to the surface of the collector region 103. Conducting electrodes passing through the first insulating layer 105 are disposed on the surfaces of the emitter region 108 and the first P-well region 110 to form an emitter 109, that is, the emitter 109 is simultaneously connected to the surfaces of the first P-well region 110 and the emitter region 108. A gate dielectric layer 107 passing through the first insulating layer 105 is also disposed on the front surface of the first P-well region 110, and a gate 106 connected to the gate dielectric layer 107 is disposed above the first insulating layer 105. The gate 106, the collector 102, and the emitter 109 are made of a metal material such as aluminum or conductive polysilicon.

[0040] In some embodiments of the present invention, such as Figure 2As shown in the figure, the CMOS cell includes a second N-type drift region 26H, a second P-well region 26E, a first body region 261, a first source region 263, a first drain region 266, a second source region 269, a second drain region 26A, and a second body region 26C. The second N-type drift region 26H and the first N-type drift region 101 are arranged in parallel. The second N-type drift region 26H is a low-doped N-type, and the two are isolated by a dielectric isolation layer 300. On the front surface of the second N-type drift region 26H, the above-mentioned second P-well region 26E, first body region 261, first source region 263, N-type gate dielectric layer 265, first drain region 266, second source region 269, P-type gate dielectric layer 26F, second drain region 26A, and second body region 26C made of silicon material can be fabricated through a photolithography and diffusion process. The second P-well region 26E serves as a local substrate, which is a P-type with a relatively low doping concentration. The first body region 261, first source region 263, and first drain region 266 are located within the second P-well region 26E. The first body region 261 is a P-type with a high doping concentration, and the first source region 263 and first drain region 266 are N-types with a high doping concentration. The second source region 269 and second drain region 26A are P-types with a high doping concentration, and the second body region 26C is an N-type with a high doping concentration.

[0041] Furthermore, as Figure 2 shown in the figure, a second insulating layer 26D is provided on the surface of the second N-type drift region 26H. The second insulating layer 26D and the first insulating layer 105 can be integrally formed. A conducting electrode penetrating the second insulating layer 26D is provided on the surfaces of the first body region 261 and the first source region 263 to form an N-type source electrode 262. The N-type source electrode 262 is simultaneously connected to the first body region 261 and the first source region 263. The N-type source electrode 262 serves as the negative power supply of the CMOS cell and is connected to the negative electrode VS of the high-voltage direct current. A conducting electrode penetrating the second insulating layer 26D is provided on the surface of the first drain region 266 to form an N-type drain electrode 267. An N-type gate dielectric layer 265 penetrating the second insulating layer 26D is provided between the first source region 263 and the first drain region 266. The second insulating layer 26D is provided with an N-type gate 264 connected to the N-type gate dielectric layer 265. A conducting electrode penetrating the second insulating layer 26D is provided on the surface of the second source region 269 to form a P-type source electrode 268. The P-type source electrode 268 is electrically connected to the N-type drain electrode 267. The electrical connection method can be through a wire connection, or as Figure 2The two electrodes are directly connected as shown. The electrode formed by electrically connecting the P-type source 268 and the N-type drain 267 serves as the output terminal HO of the gate driving unit. A conductive electrode penetrating the second insulating layer 26D is provided on the surfaces of the second drain region 26A and the second body region 26C to form a P-type drain 26B, and the P-type drain 26B is connected to both the second drain region 26A and the second body region 26C. A P-type gate dielectric layer 26F penetrating the second insulating layer 26D is provided between the second source region 269 and the second drain region 26A, and a P-type gate 26G connected to the P-type gate dielectric layer 26F is provided on the surface of the second insulating layer 26D. Among them, the N-type source 262, the N-type gate 264, the N-type drain 267, the P-type source 268, the P-type drain 26B, and the P-type gate 26G are made of a metal material such as aluminum or conductive polysilicon. The N-type gate 264 and the P-type gate 26G are simultaneously connected to the components of other circuits of the gate driving chip 200, specifically to the output terminal of the level conversion circuit 250. Figure 2 The structures of other circuit components of the gate driving chip 200 are not shown. The electrode formed by electrically connecting the P-type source 268 and the N-type drain 267 is connected to the gate of the LIGBT cell through a metal wire connection resistor R1 to form a driving connection between the gate driving chip 200 and the IGBT chip 100. Further, by reasonably designing the gate oxide length parameters of the two gates of the CMOS cell to adjust the resistance of the gate conduction, thereby controlling the current passing through the gate during conduction, the connection resistor R1 can also be removed.

[0042] The present invention also proposes a PFC circuit applying the above-mentioned power semiconductor device, such as Figure 4 shown, including the power semiconductor device mentioned in the above embodiment composed of the gate driving chip 200 and the IGBT chip 100, specifically an IGBT tube. The collector 102 of the IGBT tube is simultaneously connected to the cathode of the freewheeling diode D1, the anode of the output diode D2, and one end of the energy storage inductor L1. The emitter 109 of the IGBT tube is simultaneously connected to the anode of the freewheeling diode D1 and the negative electrode of the electrolytic capacitor C1. The cathode of the output diode D2 is connected to the positive electrode of the electrolytic capacitor C1. By integrating the gate driving chip 200 and the IGBT chip 100 inside the IGBT tube, the PCB wiring of the PFC circuit is effectively reduced, thereby reducing the PCB board area of the PFC circuit, which is beneficial to the miniaturization of the corresponding controller. At the same time, due to the integration of the gate driving chip 200 and the IGBT chip 100, the length of the driving signal connecting the two is greatly shortened, the transmission distance of the driving signal can be effectively reduced, and the anti-interference ability of the gate driving circuit can be further improved, thereby improving the working reliability of the PFC circuit.

[0043] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.

[0044] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0045] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0046] In the present invention, unless otherwise clearly specified and limited, the terms "mounted", "connected", "connected to", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0047] In the present invention, unless otherwise clearly specified or limited, the first feature being "on" or "under" the second feature may mean that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may mean that the first feature is directly above or obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature may mean that the first feature is directly below or obliquely below the second feature, or merely indicates that the horizontal height of the first feature is less than that of the second feature.

[0048] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A power semiconductor device integrated with a drive chip, characterized in that, it includes: an IGBT chip, on the surface of which a gate is provided; a gate drive chip, which is arranged on one side of the IGBT chip, and on the surface of the gate drive chip, a drive output terminal is provided, wherein the drive output terminal is electrically connected to the gate; a dielectric isolation layer, which is arranged between the IGBT chip and the gate drive chip; the IGBT chip and the gate drive chip include a common P-type substrate, and on the front surface of the P-type substrate, a buried oxide layer with a thickness of 2 μm is provided; the IGBT chip includes LIGBT cells, and the gate drive chip includes a drive signal processing unit and CMOS cells, wherein the CMOS cells serve as the gate drive unit of the LIGBT cells, the drive output terminal is the output terminal of the gate drive unit, and the LIGBT cells and the CMOS cells are respectively arranged on both sides of the dielectric isolation layer; the LIGBT cells include: a first N-type drift region; an N-type buffer region, a collector region, a first P-well region, and an emitter region formed on the front surface of the first N-type drift region, wherein the collector region is arranged in the N-type buffer region, the emitter region is arranged in the first P-well region, and the first P-well region is arranged close to the dielectric isolation layer; a first insulating layer is further provided on the surface of the first N-type drift region, and electrodes passing through the first insulating layer are provided on the surfaces of the emitter region and the first P-well region to form an emitter, and an electrode passing through the first insulating layer is provided on the surface of the collector region to form a collector. A gate dielectric layer passing through the first insulating layer is further provided on the front surface of the first P-well region, and a gate connecting the gate dielectric layer is provided above the first insulating layer.

2. The power semiconductor device according to claim 1, characterized in that, the CMOS cells include: a second N-type drift region; a second P-well region formed in the second N-type drift region in sequence, and a first body region, a first source region, and a first drain region are arranged in the second P-well region; a second source region, a second drain region, and a second body region formed in the second N-type drift region in sequence.

3. The power semiconductor device according to claim 2, characterized in that, a second insulating layer is further provided on the surface of the second N-type drift region; electrodes passing through the second insulating layer are provided on the surfaces of the first body region and the first source region to form an N-type source electrode, and an electrode passing through the second insulating layer is provided on the surface of the first drain region to form an N-type drain electrode. An N-type gate dielectric layer passing through the second insulating layer is provided between the first source region and the first drain region, and an N-type gate connected to the N-type gate dielectric layer is provided on the second insulating layer; A conductive electrode penetrating through the second insulating layer is provided on the surface of the second source region to form a P-type source electrode, the P-type source electrode is electrically connected to the N-type drain electrode, and conductive electrodes penetrating through the second insulating layer are provided on the surfaces of the second drain region and the second body region to form a P-type drain electrode. A P-type gate dielectric layer penetrating through the second insulating layer is provided between the second source region and the second drain region, and a P-type gate electrode connected to the P-type gate dielectric layer is provided on the surface of the second insulating layer.

4. The power semiconductor device according to claim 1, characterized in that the main component of the dielectric isolation layer is silicon dioxide, and the thickness of the dielectric isolation layer is 50 nm to 100 nm.

5. The power semiconductor device according to claim 1, characterized in that the gate driving chip includes a power supply circuit, a Schmitt circuit, a filtering circuit, a level conversion circuit, and a half-bridge driving circuit. The power supply circuit supplies power for the operation of other circuits. The input end of the Schmitt circuit is the input end of the gate driving chip. The Schmitt circuit shapes the input control signal. The output end of the Schmitt circuit is connected to the filtering circuit. The filtering circuit filters the signal output by the Schmitt circuit. The output end of the filtering circuit is connected to the level conversion circuit. The level conversion circuit boosts the signal output by the filtering circuit. The output end of the level conversion circuit is connected to the half-bridge driving circuit. The output end of the half-bridge driving circuit is the driving output terminal of the gate driving chip.

6. A PFC circuit, characterized in that the PFC circuit is provided with the power semiconductor device according to any one of claims 1 to 5.

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