Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device and a manufacturing method thereof are provided. The semiconductor memory device includes a plurality of gate stacks separated by a plurality of slit structures, and each gate stack includes a first stack including three or more first conductive patterns spaced apart from each other at substantially the same height, a second stack formed on the first stack and including second conductive patterns and interlayer dielectric layers alternately stacked, and a plurality of channel structures penetrating through the first stack to the third stack.

Description

Technical Field

[0001] This disclosure relates generally to electronic devices, and more specifically to semiconductor memory devices and methods of manufacturing the same. Background Technology

[0002] To meet consumers' demands for superior performance and low cost, it is necessary to increase the integration level of semiconductor memory devices. Specifically, in semiconductor memory devices, integration level is a crucial factor in determining product performance and cost. Therefore, various efforts have been continuously undertaken to improve integration level. For example, in semiconductor memory devices comprising multiple memory cells, three-dimensional semiconductor memory devices have been actively researched, which can reduce the size occupied by memory cells per unit area by arranging memory cells in three dimensions. Summary of the Invention

[0003] This disclosure aims to provide a semiconductor memory device and a method for manufacturing the same, which can improve operational reliability.

[0004] A semiconductor memory device according to an embodiment of the present disclosure may include: a plurality of gate stacks separated by a plurality of slit structures, wherein each gate stack may include: a first stack including three or more first conductive patterns spaced apart from each other at substantially the same height; a second stack formed on the first stack and including alternately stacked second conductive patterns and interlayer dielectric layers; a third stack formed on the second stack and including a plurality of third conductive patterns spaced apart from each other at another substantially the same height; and a plurality of channel structures extending through the first stack to the third stack.

[0005] A semiconductor memory device according to an embodiment of the present disclosure may include: a plurality of gate stacks separated by a plurality of slit structures, wherein each gate stack may include: a first stack having a multilayer structure and including three or more first conductive patterns spaced apart from each other for each layer; a second stack formed on the first stack and including alternately stacked second conductive patterns and interlayer dielectric layers; a third stack formed on the second stack having a monolayer structure and including a plurality of third conductive patterns spaced apart from each other; and a plurality of channel structures extending from the first stack to the third stack. The first conductive patterns may include: three or more first patterns located on a lower layer; a second pattern located on an upper layer and located at two edges of the first stack; and a plurality of third patterns located on an upper layer and located between the second patterns.

[0006] A method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure may include the following steps: forming a first stack comprising at least three or more first conductive patterns spaced apart from each other at substantially the same height; forming a stack layer comprising alternating interlayer dielectric layers and sacrificial layers on the first stack; forming a plurality of channel structures through the stack layer and the first stack; forming slit trenches in two sidewalls of the stack layer and the first stack; removing the sacrificial layers through the slit trenches; and forming a second stack comprising alternating second conductive patterns and interlayer dielectric layers by filling the gaps in the space where the sacrificial layers have been removed with a conductive material.

[0007] In this disclosure, which addresses the aforementioned problems, each of the plurality of memory blocks includes at least three or more first conductive patterns serving as source select lines at substantially the same height, thereby substantially preventing an increase in read interference due to increased integration density of the semiconductor memory device. Therefore, the operational reliability of the semiconductor memory device can be improved.

[0008] In addition to reducing read interference, forming a first stack comprising at least three or more first conductive patterns before forming the second stack, slit structure, and channel structure improves the operational reliability of the semiconductor memory device while essentially preventing the addition of process steps, thereby ensuring price competitiveness. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 2 This is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 3 This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0012] Figure 4 This is a perspective view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figures 5 to 7 This is a perspective view illustrating a modified example of a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figure 8 This is a flowchart illustrating, schematically, a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 9 This is a flowchart illustrating, schematically, a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Figures 10A to 10F This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figure 11 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0018] Figure 12 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0019] In the following detailed description, taken in conjunction with the accompanying drawings, the advantages and features of this disclosure, as well as the methods for implementing them, will become apparent. However, this disclosure is not limited to such embodiments, and this disclosure can be implemented in various forms. The embodiments described below are merely provided to perfect the disclosure of this technology and to help those skilled in the art to fully understand the scope of this disclosure. This disclosure is limited only by the scope of the appended claims. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. Throughout the specification, the same reference numerals refer to the same components.

[0020] The embodiments of this disclosure described below can provide semiconductor memory devices and methods of manufacturing the same that improve operational reliability. More specifically, embodiments of this disclosure can provide semiconductor memory devices and methods of manufacturing the same that include source select lines separated at substantially the same height as or higher than drain select lines to improve read interference caused by the increased number of cell strings integrated in a memory block of a non-volatile semiconductor memory device (e.g., a three-dimensional (3D) NAND) with a three-dimensional structure. Therefore, the structure of this disclosure reduces read interference to improve performance and reduces area usage through its three-dimensional structure, thus providing a very useful and well-designed product.

[0021] For reference, since semiconductor memory devices (e.g., NAND) operate on a block-by-block basis, block density increases with increasing integration density. As block density increases, read interference inevitably increases. In this case, when the source select lines are not separated within the block, read interference increases several times or more with increasing integration density, making it difficult to ensure the required performance. That is, it becomes difficult to ensure operational reliability.

[0022] While striving to improve the quality of one chip, the quality of another chip may decrease. For example, when increasing the integration density of a semiconductor memory device using methods that increase the number of cell strings integrated within a memory block of finite size, the size occupied by the source select lines and the limitations of the process sequence may inevitably require additional process steps to separate the source select lines. Therefore, ensuring price competitiveness becomes difficult.

[0023] Therefore, in order to fundamentally prevent the increase in read interference due to the increased integration of semiconductor memory devices, a method is needed that can ensure operational reliability while simultaneously ensuring price competitiveness by separating the source select line at a height substantially the same as or higher than the drain select line.

[0024] In the following description, a semiconductor memory device according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, the first direction D1, the second direction D2, and the third direction D3 can refer to directions that intersect each other. For example, in the XYZ coordinate system, the first direction D1, the second direction D2, and the third direction D3 can be the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively.

[0025] Figure 1 This is a block diagram illustrating a semiconductor memory device 10 according to an embodiment of the present disclosure.

[0026] like Figure 1 As shown, the semiconductor memory device 10 according to this embodiment may include peripheral circuitry PC and memory cell array 20.

[0027] The peripheral circuit PC can be configured to control programming operations for storing data in the memory cell array 20, reading operations for outputting data stored in the memory cell array 20, and erasing operations for erasing data stored in the memory cell array 20. For example, the peripheral circuit PC may include a voltage generator 31, a line decoder 33, a control circuit 35, and a page buffer group 37.

[0028] The memory cell array 20 may include multiple memory blocks. The memory cell array 20 can be electrically connected to the row decoder 33 via word line WL, and can be electrically connected to the page buffer group 37 via bit line BL.

[0029] In response to the command CMD and the address ADD, the control circuit 35 can control the peripheral circuit PC.

[0030] Voltage generator 31 can generate various operating voltages for programming, reading and erasing operations in response to control of control circuit 35, such as pre-erase voltage, erase voltage, ground voltage, programming voltage, verification voltage, pass voltage and read voltage.

[0031] The row decoder 33 can select memory blocks of the memory cell array 20 in response to the control of the control circuit 35. The row decoder 33 can be configured to apply an operating voltage to the word line WL electrically connected to the selected memory block.

[0032] like Figure 1 As shown, page buffer group 37 can be electrically connected to memory cell array 20 via bit line BL. In response to control by control circuitry 35, page buffer group 37 can temporarily store data received from input / output circuitry (not shown) during programming operations. Page buffer group 37 can sense the voltage or current of bit line BL during read or verification operations in response to control by control circuitry 35. Page buffer group 37 can select bit line BL in response to control by control circuitry 35.

[0033] Structurally, the memory cell array 20 can be arranged parallel to the peripheral circuit PC, or it can overlap with a part of the peripheral circuit PC.

[0034] Figure 2 This is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0035] like Figure 2 As shown, a memory block may include a source layer SL and multiple cell strings CS1 to CS4 that are commonly electrically connected to multiple word lines WL1 to WLn. The multiple cell strings CS1 to CS4 may be electrically connected to multiple bit lines BL.

[0036] like Figure 2 As shown, each of the multiple cell strings CS1 to CS4 may include at least one or more source selection transistors SST electrically connected to the source layer SL, at least one or more drain selection transistors DST electrically connected to the bit line BL, and multiple memory cells MC1 to MCn electrically connected in series between the source selection transistors SST and the drain selection transistors DST.

[0037] The gates of multiple memory cells MC1 to MCn can be electrically connected to multiple word lines WL1 to WLn, which are stacked at a distance from each other. The multiple word lines WL1 to WLn can be positioned between three or more source select lines SSL1 to SSL4 and three or more drain select lines DSL1 to DSL4. The three or more source select lines SSL1 to SSL4 can be spaced apart from each other at substantially the same height. Similarly, the three or more drain select lines DSL1 to DSL4 can be spaced apart from each other at substantially the same height.

[0038] The gate of a source-select transistor (SST) can be electrically connected to the corresponding source-select line. The gate of a drain-select transistor (DST) can be electrically connected to the drain-select line corresponding to the gate of the drain-select transistor (DST).

[0039] The source layer SL can be electrically connected to the source of the source select transistor SST. The drain of the drain select transistor DST can be electrically connected to the bit line corresponding to the drain of the drain select transistor DST.

[0040] Multiple unit strings CS1 to CS4 can be divided into string groups electrically connected to three or more source select lines SSL1 to SSL4 and three or more drain select lines DSL1 to DSL4, such that strings electrically connected to substantially identical word lines and substantially identical bit lines can be independently controlled by different source select lines and drain select lines. Furthermore, unit strings electrically connected to substantially identical source select lines and substantially identical drain select lines can be independently controlled by different bit lines. For example, three or more source select lines SSL1 to SSL4 may include first source select lines SSL1 to fourth source select lines SSL4, and three or more drain select lines DSL1 to DSL4 may include first drain select lines DSL1 to fourth drain select lines DSL4. Multiple unit strings CS1 to CS4 may include a first unit string CS1 electrically connected to a first string group of a first source select line SSL1 and a first drain select line DSL1, a second unit string CS2 electrically connected to a second string group of a second source select line SSL2 and a second drain select line DSL2, a third unit string CS3 electrically connected to a third string group of a third string group of a third source select line SSL3 and a third drain select line DSL3, and a fourth unit string CS4 electrically connected to a fourth string group of a fourth source select line SSL4 and a fourth drain select line DSL4.

[0041] Figure 3 This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0042] like Figure 3 As shown, the semiconductor memory device 10 may include peripheral circuitry PC disposed on a substrate SUB and a gate stack GST overlapping the peripheral circuitry PC.

[0043] Each of the gate stacks (GSTs) may include three or more source select lines SSL1 to SSL4 separated from each other at substantially the same height via a first slit S1, multiple word lines WL1 to WLn, and three or more drain select lines DSL1 to DSL4 separated from each other at substantially the same height via a second slit S2. For reference, this embodiment illustrates a case where each of the gate stacks (GSTs) includes four source select lines SSL1 to SSL4 and four drain select lines DSL1 to DSL4.

[0044] Three or more source select lines SSL1 to SSL4, multiple word lines WL1 to WLn, and three or more drain select lines DSL1 to DSL4 can extend in the first direction D1 and the second direction D2, and can form a flat plate shape parallel to the upper surface of the substrate SUB.

[0045] like Figure 3 As shown, multiple word lines WL1 to WLn can be stacked on a third-direction D3 at intervals. Multiple word lines WL1 to WLn can be positioned between three or more drain select lines DSL1 to DSL4 and three or more source select lines SSL1 to SSL4.

[0046] The gate stack (GST) can be separated from each other through the third slit S3. For example... Figure 3 As shown, the first slit S1 and the second slit S2 can be formed to be shorter than the third slit S3 in the third direction D3, and can overlap with multiple word lines WL1 to WLn.

[0047] Each of the first slits S1 to the third slits S3 may extend in a straight line, a zigzag shape (not shown), or a wavy shape (not shown). The width of each of the first slits S1 to the third slits S3 may be varied in various ways according to design rules.

[0048] Three or more source select lines SSL1 to SSL4 can be positioned closer to the peripheral circuit PC than three or more drain select lines DSL1 to DSL4. The semiconductor memory device 10 may include a source layer SL disposed between the gate stack GST and the peripheral circuit PC, and multiple bit lines BL spaced further from the peripheral circuit PC than the source layer SL. The gate stack GST may be disposed between the multiple bit lines BL and the source layer SL.

[0049] Multiple bit lines BL can be formed from various conductive materials, such as, for example, doped semiconductor layers, metal layers, metal alloy layers, etc. The source layer SL may include a doped semiconductor layer, such as, for example, an n-type doped silicon layer.

[0050] Although not shown in the figure, the peripheral circuit PC can be electrically connected to multiple bit lines BL, source layer SL, and multiple word lines WL1 to WLn through interconnects with various structures.

[0051] Figure 4 This is a perspective view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0052] like Figure 4 As shown, each of the gate stacks GST can be separated by multiple slit structures 140 and may include a first stack ST1, a second stack ST2, and a third stack ST3 stacked sequentially. Each of the gate stacks GST can be separated by the slit structures 140 and may correspond to a memory block. The source layer SL may be located below the gate stacks GST, and multiple bit lines BL may be located above the gate stacks GST. The source layer SL, the gate stacks GST, and the bit lines BL may overlap each other.

[0053] Furthermore, this embodiment illustrates a case where the source layer SL and the bit line BL are located below and above the gate stack GST, respectively; however, this disclosure is not limited thereto. As a modification, the bit line BL and the source layer SL may be located below and above the gate stack GST, respectively.

[0054] The source layer SL can overlap with the gate stack GST and have a flat plate shape extending in the first direction D1 and the second direction D2. The source layer SL can have a structure with a first source layer SL1, a second source layer SL2, and a third source layer SL3 stacked, such as... Figure 7 As shown. Here, the source layer SL can have a structure in which a third source layer SL3 is inserted between the first source layer SL1 and the second source layer SL2. The third source layer SL3 can be electrically connected to the channel layer 154 through the memory layer 152 that runs through each channel structure CH.

[0055] Each of the first source layers SL1 to the third source layer SL3 may include a doped semiconductor layer, such as, for example, each of the first source layers SL1 to the third source layer SL3 may include an N-type doped silicon layer. In this case, the impurity doping concentration of the third source layer SL3, which is interposed between the first source layer SL1 and the second source layer SL2, may be greater than the impurity doping concentration of the first source layer SL1 and the second source layer SL2.

[0056] Furthermore, this embodiment illustrates a case where the first source layer SL1 to the third source layer SL3 are all formed of substantially the same conductive material; however, this disclosure is not limited thereto. As a modification, the first source layer SL1 and the second source layer SL2 may comprise substantially the same conductive material, while the third source layer SL3, interposed between them, may comprise a conductive material different from the conductive materials of the first source layer SL1 and the second source layer SL2.

[0057] The slit structure 140 that separates the gate stacks GST from each other can correspond to Figure 3 The third slit S3 is shown. Each of the slit structures 140 can be a linear pattern extending in the second direction D2, wherein the slit structure 140 can be located on two sidewalls of the gate stack GST in the first direction D1. The end of the slit structure 140 in the third direction D3 can have a shape extending into the source layer SL. For example, the bottom surface of the slit structure 140 can contact the third source layer SL3 interposed between the first source layer SL1 and the second source layer SL2.

[0058] like Figure 7 As shown, each of the slit structures 140 may include a linear slit groove 142 extending in the second direction D2, a slit spacer 144 formed on either side of the slit groove 142, and a slit layer 146 for gap filling the slit groove 142. The slit spacer 144 may include an insulating material, and the slit layer 146 may include a conductive material.

[0059] Furthermore, this embodiment illustrates a case where the slit layer 146 comprises a conductive material; however, this disclosure is not limited thereto. As a modification, the slit layer 146 may comprise an insulating material.

[0060] In each gate stack GST, the first stack ST1 may provide a plurality of source select transistors and at least three or more source select lines. To this end, the first stack ST1 may include a first lower insulating layer 110 formed on the source layer SL, at least three or more first conductive patterns 112 formed on the first lower insulating layer 110 and spaced apart from each other at substantially the same height, a gap-filling insulating layer 114 for gap filling between the first conductive patterns 112, and a first upper insulating layer 116 formed on the first conductive patterns 112 and the gap-filling insulating layer 114.

[0061] The first lower insulating layer 110 serves to electrically isolate the source layer SL from the first conductive pattern 112. The gap-filling insulating layer 114 can correspond to... Figure 3The first slit S1 shown serves to electrically isolate the first conductive patterns 112 from each other. The first upper insulating layer 116 serves to electrically isolate the second laminate ST2 from the first conductive patterns 112. The gap-filling insulating layer 114 and the first upper insulating layer 116 can be formed by a single insulating layer deposition process, which is a cost-effective process. That is, the gap-filling insulating layer 114 and the first upper insulating layer 116 can be integrally formed with each other. The first lower insulating layer 110, the gap-filling insulating layer 114, and the first upper insulating layer 116 can each include an oxide layer. Furthermore, when the interlayer dielectric layer 120 is disposed on the bottom layer of the second laminate ST2, the first upper insulating layer 116 can be omitted from the first laminate ST1.

[0062] Each of the first conductive patterns 112 can be used as the gate and source select line of a source select transistor, such that the first conductive pattern 112 can correspond to Figure 3 The first conductive pattern 112 has multiple source selection lines SSL1 to SSL4. Each of the first conductive patterns 112 may include a doped semiconductor layer or a metal silicide layer, and each of the first conductive patterns 112 may also include a stack in which a doped semiconductor layer and a metal silicide layer are stacked. For example, the doped semiconductor layer may include an n-type doped silicon layer, and the metal silicide layer may include a tungsten silicide layer. Using a doped semiconductor layer and / or a metal silicide layer instead of a metal layer with low resistivity as the first conductive pattern 112 is to substantially prevent the first conductive pattern 112 from deteriorating due to external forces applied to the first conductive pattern 112 between processes (especially at high temperatures). For reference, the doped semiconductor layer and the metal silicide layer have higher high-temperature heat resistance than the metal layer, making it advantageous to use a doped semiconductor layer and a metal silicide layer instead of a metal layer.

[0063] The first conductive patterns 112 may be spaced apart from each other at substantially the same height in a first direction D1, and each may have a flat plate shape extending in the first direction D1 and the second direction D2. In the first direction D1, one or both sidewalls of each first conductive pattern 112 may have a straight shape, a zigzag shape, or a wavy shape, and the sidewalls of the first conductive patterns 112 located at the edge of the first laminate ST1 may be spaced apart from the sidewalls of the facing slit structure 140. That is, the gap-filling insulating layer 114 may also gap-fill between the slit structure 140 and the first conductive patterns 112, possibly due to a manufacturing method for forming at least three or more source selection lines at substantially the same height in a memory block, as described below. For example, by a manufacturing method that forms the first laminate including the first conductive patterns before forming the second laminate ST2, the third laminate ST3, the slit structure 140, and the channel structure CH, the sidewalls of the first conductive patterns 112 located at the edge of the first laminate ST1 may be spaced apart from the sidewalls of the facing slit structure 140. For reference, the source select line can typically be formed by replacing the sacrificial layer with a conductive layer during the process of forming the slit structure 140. However, in the method of replacing the sacrificial layer with a conductive layer, three or more first conductive patterns 112 may not be physically formed in the first stack ST1. Therefore, it should be noted that there are limitations in substantially preventing an increase in read interference due to the increased integration density of the semiconductor memory device.

[0064] In each gate stack GST, the second stack ST2 can provide corresponding gates and multiple word lines for multiple memory cells. For this purpose, the second stack ST2 can have a structure in which an interlayer dielectric layer 120 and a second conductive pattern 122 are alternately stacked on a third direction D3. The interlayer dielectric layer 120 can be located on each of the bottommost and topmost layers of the second stack ST2. The interlayer dielectric layer 120 may include an oxide layer.

[0065] Furthermore, this embodiment illustrates a case where the interlayer dielectric layer 120 is located on each of the bottommost and topmost layers of the second laminate ST2; however, this disclosure is not limited thereto. As a modification, the second conductive pattern 122 may be located on each of the bottommost and / or topmost layers of the second laminate ST2.

[0066] In the second stack ST2, each of the second conductive patterns 122 can be used as the gate and word line of a memory cell, such that the second conductive pattern 122 can correspond to Figure 3The first conductive pattern 112 consists of multiple letter lines WL1 to WLn. Each of the second conductive patterns 122 may overlap with at least three or more first conductive patterns 112 and has a flat plate shape extending in a first direction D1 and a second direction D2. In the first direction D1, one or both sidewalls of each second conductive pattern 122 may have a straight shape, a zigzag shape, or a wavy shape, and the sidewall of each second conductive pattern 122 may contact the sidewall of the facing slit structure 140 because the second conductive pattern 122 is formed using a method of replacing the sacrificial layer with a conductive layer during the process of forming the slit structure 140. Each of the second conductive patterns 122 may include a metal layer, wherein each of the second conductive patterns 122 may include a tungsten layer.

[0067] In each gate stack GST, the third stack ST3 may provide a plurality of drain select transistors and at least three or more drain select lines. For this purpose, the third stack ST3 may include a second lower insulating layer 130 formed on the second stack ST2, at least three or more third conductive patterns 132 formed on the second lower insulating layer 130 and spaced apart from each other at substantially the same height, a second upper insulating layer 136 covering the third conductive patterns 132, and a separation layer 134 that separates the third conductive patterns 132 from each other by penetrating the second upper insulating layer 136. The third conductive patterns 132 may correspond to the first conductive patterns 112 respectively and may overlap each other. Furthermore, each of the second conductive patterns 122 may overlap with at least three or more third conductive patterns 132.

[0068] The second lower insulating layer 130 serves to electrically isolate the second conductive pattern 122 and the third conductive pattern 132 formed on the uppermost layer of the second laminate ST2. The second upper insulating layer 136 serves to electrically isolate the structures formed on the third laminate ST3 from each other, for example, to isolate the bit line BL from the third conductive pattern 132, and may have a thickness greater than that of the second lower insulating layer 130 or the interlayer dielectric layer 120. This provides space for the capping layer 158 to be formed in the channel structure CH. The separation layer 134 serves to electrically isolate the third conductive patterns 132 from each other, thereby the separation layer 134 can correspond to Figure 3 The second slit S2 is located in the second layer. One end of the separating layer 134 can extend into the second lower insulating layer 130. The second lower insulating layer 130, the separating layer 134, and the second upper insulating layer 136 can each include an oxide layer. Furthermore, when the interlayer dielectric layer 120 is disposed on the uppermost layer of the second laminate ST2, the second lower insulating layer 130 can be omitted from the third laminate ST3.

[0069] Each of the third conductive patterns 132 can be used as the gate and drain select line of a drain select transistor, such that the third conductive pattern 132 can correspond to Figure 3 The system contains multiple drain selection lines DSL1 to DSL4. Third conductive patterns 132 can be configured to be spaced apart from each other at substantially the same height in a first direction D1, and each can have a flat plate shape extending in both the first and second directions D1. In the first direction D1, one or both sidewalls of each third conductive pattern 132 can have a straight, zigzag, or wavy shape, and the sidewalls of the third conductive patterns 132 located at the edge of the third stack ST3 can contact or be spaced apart from the sidewalls of the facing slit structure 140. For reference, when the third conductive pattern 132 is formed using a method of replacing the sacrificial layer with a conductive layer during the formation of the slit structure 140, the sidewalls of the third conductive pattern 132 can contact the sidewalls of the facing slit structure 140. On the other hand, when the third conductive pattern 132 is formed using a method substantially the same as that used to form the first conductive pattern 112, the sidewalls of the third conductive pattern 132 can be spaced apart from the sidewalls of the facing slit structure 140. Each of the third conductive patterns 132 may include a metal layer, such as, for example, a tungsten layer.

[0070] Furthermore, this embodiment illustrates a case where the third conductive pattern 132 is formed as a single layer; however, this disclosure is not limited thereto. As a modification, two or more layers of the third conductive pattern 132 may be stacked on the third-party D3.

[0071] Each gate stack GST, consisting of a first stack ST1, a second stack ST2, and a third stack ST3, can be penetrated by multiple channel structures CH. In the first stack ST1, the channel structures CH can penetrate the first conductive pattern 112, and the number of channel structures CH penetrating each of the first conductive patterns 112 can be substantially the same. Similarly, in the third stack ST3, the channel structures CH can penetrate the third conductive pattern 132, and the number of channel structures CH penetrating each of the third conductive patterns 132 can be substantially the same.

[0072] Channel structures (CH) can form multiple channel sequences. The channel structures (CH) arranged within each channel sequence can be arranged in a row along the extension directions of multiple bit lines (BL). For example... Figure 4 As shown, each of the multiple bit lines BL can be electrically connected to the channel structure CH via the drain contact plug DCP.

[0073] like Figure 5As shown, each channel structure CH through the gate stack GST may include: a channel via 150 through the first stack ST1, the second stack ST2, and the third stack ST3; a memory layer 152 formed along the surface of the channel via 150; a channel layer 154 formed on the memory layer 152; a core insulating layer 156 formed on the channel layer 154 to gap fill a portion of the channel via 150; and a capping layer 158 formed on the core insulating layer 156 to gap fill the remaining portion of the channel via 150.

[0074] The channel hole 150 can penetrate from the first stack ST1 to the third stack ST3, and a portion thereof can have a shape that extends into the source layer SL. Specifically, the channel hole 150 can penetrate the second source layer SL2 and the third source layer SL3, as well as the first stack ST1 to the third stack ST3, and the bottom surface of the channel hole 150 can be located in the first source layer SL1.

[0075] The memory layer 152 formed along the surface of the channel via 150 may include a stack of layers in which a barrier layer (not shown), a charge trapping layer (not shown), and a tunnel insulating layer (not shown) are sequentially stacked. The tunnel insulating layer may contact the channel layer 154, and the barrier layer may contact the first conductive pattern 112, the second conductive pattern 122, and the third conductive pattern 132. The tunnel insulating layer and the barrier layer may each include an oxide layer, and the charge trapping layer may include a nitride layer.

[0076] Furthermore, this embodiment illustrates a case where the memory layer 152 has an ONO structure in which oxide layers, nitride layers, and oxide layers are stacked; however, this disclosure is not limited thereto. The memory layer 152 may include various material layers and may have various stacked structures, depending on the characteristics required by the semiconductor memory device.

[0077] The channel layer 154 may be formed on the memory layer 152 along the surface of the channel via 150 and may have a cylindrical shape. The channel layer 154 may include an intrinsic semiconductor layer or a doped semiconductor layer, such as, for example, a silicon layer or p-type doped silicon.

[0078] The core insulating layer 156 may have a cylindrical shape and may be formed on the channel layer 154 to partially fill the channel holes 150. The channel layer 154 may have a shape surrounding the side and bottom surfaces of the core insulating layer 156. The core insulating layer 156 may include an oxide layer.

[0079] Capping layer 158 can be used as the drain of a drain-select transistor. Capping layer 158 can be formed on core insulating layer 156 to fill the remainder of channel via 150 and can be electrically connected to channel layer 154. The interface between capping layer 158 and core insulating layer 156 can be adjacent to the interface between third conductive pattern 132 and second upper insulating layer 136, but can be located above the interface between third conductive pattern 132 and second upper insulating layer 136. Capping layer 158 may include a doped silicon layer, such as, for example, an n-type doped silicon layer.

[0080] As described above, in the semiconductor memory device according to this embodiment, each gate stack GST separated by the slit structure 140 includes at least three or more first conductive patterns 112, thereby substantially preventing an increase in read interference due to the increased integration density of the semiconductor memory device, thus improving the operational reliability of the semiconductor memory device.

[0081] Figures 5 to 7 This is a perspective view illustrating a modified example of a semiconductor memory device according to an embodiment of the present disclosure.

[0082] first, Figure 4 An example is illustrated where each gate stack GST separated by slit structure 140 includes four first conductive patterns 112 and four third conductive patterns 132 located at substantially the same height. Figure 4 An example is shown where the first conductive pattern 112 and the third conductive pattern 132 correspond to each other in a one-to-one manner and have substantially the same size. Furthermore, Figure 4 An example is shown where the number of channel structures CH through the first conductive pattern 112 is substantially equal to the number of channel structures CH through the third conductive pattern 132.

[0083] However, the semiconductor memory device according to this embodiment is not limited to... Figure 4 The structure shown.

[0084] As an example of modification, such as Figure 5 As shown, each gate stack GST separated by the slit structure 140 may also include four first conductive patterns 112 located at substantially the same height and two third conductive patterns 132 located at substantially the same height. In other words, in each gate stack GST, the number of third conductive patterns 132 may be less than the number of first conductive patterns 112, and any one of the third conductive patterns 132 may overlap with two or more first conductive patterns 112. For example, two first conductive patterns 112 may correspond to any one of the third conductive patterns 132 and may have different sizes.

[0085] As another example of modification, such as Figure 6 As shown, each gate stack GST separated by slit structure 140 may include four first conductive patterns 112 located at substantially the same height and four third conductive patterns 132 located at substantially the same height. The third conductive patterns 132 may have the same... Figure 4 The shapes shown are basically the same.

[0086] Here, the number of channel structures CH through each first conductive pattern 112 can be different from each other. Specifically, each first conductive pattern 112 may include an outer pattern 112A adjacent to the two edges (i.e., slit structures 140) of the first stack ST1 and an inner pattern 112B located between the outer patterns 112A. In this case, the linewidth and size of the outer pattern 112A can be smaller than the linewidth and size of the inner pattern 112B, such that the number of channel structures CH through the inner pattern 112B, which is further apart from the slit structure 140, can be greater than the number of channel structures CH through the outer pattern 112A adjacent to the slit structure 140. Therefore, the operational reliability of the semiconductor memory device can be further improved by substantially preventing the degradation of the characteristics of the cell string including the channel structures CH adjacent to the slit structure 140.

[0087] In each gate stack (GST), the number of third conductive patterns 132 can be substantially equal to the number of first conductive patterns 112, and the third conductive pattern 132 adjacent to the slit structure 140 can overlap with two first conductive patterns 112. That is, the third conductive pattern 132 adjacent to the slit structure 140 can overlap with a portion of the outer pattern 112A and the inner pattern 112B.

[0088] As another example of modification, such as Figure 7 As shown, each gate stack GST separated by slit structure 140 may include a first conductive pattern 112 having a multilayer structure and a third conductive pattern 132 having a single-layer structure. The third conductive pattern 132 may have the same characteristics as... Figure 4 The shapes shown are basically the same.

[0089] like Figure 7As shown, the first conductive pattern 112 may include three or more first patterns 112-1 located on the lower layer, second patterns 112-2 located on the upper layer and on the two edges of the first stack ST1, and a plurality of third patterns 112-3 located on the upper layer and between the second patterns 112-2. The upper and lower layers may be electrically isolated by an interlayer dielectric layer 118. Each of the third patterns 112-3 may overlap a portion of two first patterns 112-1, and the third patterns 112-3 and the first patterns 112-1 may be arranged in a zigzag pattern on a third-direction D3. The linewidth and size of each first pattern 112-1 may be substantially equal to the linewidth and size of each third pattern 112-3. The linewidth and size of each second pattern 112-2 may be smaller than the linewidth and size of each third pattern 112-3. In each gate stack GST, the number of third conductive patterns 132 may be substantially equal to the number of first patterns 112-1. Each third conductive pattern 132 may overlap with each corresponding first pattern 112-1. In each gate stack GST, the third conductive pattern 132 adjacent to the slit structure 140 may overlap with a portion of the first pattern 112-1, the second pattern 112-2, and the third pattern 112-3, thereby further improving the operational reliability of the semiconductor memory device by substantially preventing the degradation of the characteristics of the cell string including the channel structure CH adjacent to the slit structure 140.

[0090] The channel structure CH may each include a first channel structure and a second channel structure adjacent to the first channel structure, and the first and second channel structures may pass through substantially the same third pattern 112-3. In this case, the first and second channel structures may pass through different first patterns 112-1, so that the operational reliability of the semiconductor memory device can be further improved by improving the controllability of the source selection transistors used for the channel structure.

[0091] Figure 8 This is a flowchart illustrating, schematically, a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0092] like Figure 8 As shown, a method for manufacturing a semiconductor memory device may include step S1 of forming peripheral circuitry on a substrate and step S3 of forming an array of memory cells on the peripheral circuitry.

[0093] First, in step S1, peripheral circuitry can be formed on the substrate. The peripheral circuitry may include multiple transistors, wherein the corresponding source and drain of the transistors can be formed in a local region of the substrate, and the corresponding gate of the transistors can be formed on the substrate.

[0094] Subsequently, in step S3, a memory cell array can be formed on the peripheral circuitry. Step S3 may include forming... Figure 3 The steps and formation of the source layer SL shown are as follows. Figure 3 The steps of forming the gate stack GST shown, and the steps of forming the gate stack GST. Figure 3 The steps of bit line BL are shown.

[0095] Although not shown in the accompanying drawings, conductive patterns for interconnects can be formed on the peripheral circuit prior to step S3, and memory cell arrays can be formed on the interconnects.

[0096] Figure 9 This is a flowchart illustrating, schematically, a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0097] like Figure 9 As shown, a method for manufacturing a semiconductor memory device may include: step S11 of forming a first chip including peripheral circuitry, step S13 of forming a second chip including a memory cell array, step S15 of bonding the first chip and the second chip, and step S17 of removing an auxiliary substrate from the second chip.

[0098] First, in step S11, peripheral circuitry can be disposed on the main substrate. The first chip may include a first interconnect electrically connected to the peripheral circuitry.

[0099] Subsequently, in step S13, a memory cell array can be formed on the auxiliary substrate. Step S13 may include: forming Figure 3 The steps and formation of the source layer SL shown are as follows. Figure 3 The steps of forming the gate stack GST shown, and the steps of forming the gate stack GST. Figure 3 The steps of bit line BL are shown. The second chip may further include a second interconnect electrically connected to the memory cell array.

[0100] also, Figure 3 An example is illustrated where a source layer SL, a gate stack GST, and a bit line BL are sequentially stacked in a memory cell array; however, this disclosure is not limited thereto. As a modification, in step S13, the memory cell array may have a structure in which the gate stack is formed on the bit line and no source layer is formed.

[0101] Subsequently, in step S15, the second chip can be aligned on the first chip such that the first interconnect and the second interconnect face each other, and a portion of the first interconnect and a portion of the second interconnect can be engaged with each other.

[0102] Subsequently, in step S17, the auxiliary substrate of the second chip can be removed to form a semiconductor memory device in which peripheral circuits and memory cell arrays overlap each other.

[0103] Furthermore, as a modification, when the memory cell array has a structure in step S13 in which gate stacks are formed on bit lines and no source layer is formed, a source layer electrically connected to the channel structure can be formed after step S17.

[0104] Figures 10A to 10F This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. Figures 10A to 10F This is a cross-sectional view illustrating a method for manufacturing a memory cell array for a semiconductor memory device, and the following refers to... Figures 10A to 10F The method for manufacturing memory cell arrays described herein may include Figure 8 Step S3 shown may include or may include Figure 9 In step S13 shown.

[0105] like Figure 10A As shown, a pre-source layer SL' is formed on a substrate (not shown) on which a predetermined structure has already been formed. The predetermined structure can be... Figure 3 The peripheral circuit PC, and the pre-source layer SL′ can be formed on the peripheral circuit PC.

[0106] A pre-source layer SL′ can be formed by sequentially stacking a first source layer SL1, a sacrificial source layer 202, and a second source layer SL2. The first source layer SL1 and the second source layer SL2 can be formed from doped semiconductor layers, such as an n-type doped silicon layer. The sacrificial source layer 202 can be formed from an insulating layer, such as a nitride layer.

[0107] Next, a first lower insulating layer 110, such as an oxide layer, is formed on the pre-source layer SL′.

[0108] Next, a conductive layer 112A is formed on the first lower insulating layer 110. The conductive layer 112A can be formed from a doped semiconductor layer or a metal silicide layer to substantially prevent the properties of the conductive layer 112A from deteriorating in subsequent processes (especially high-temperature processes). Furthermore, the conductive layer 112A can be formed as a stack of doped semiconductor layers and metal silicide layers, wherein an n-type doped silicon layer can be used as the doped semiconductor layer, and a tungsten silicide layer can be used as the metal silicide layer.

[0109] like Figure 10BAs shown, after a hard mask pattern (not shown) is formed on the conductive layer 112A, the conductive layer 112A is etched using the hard mask pattern as an etch stop to form a plurality of first conductive patterns 112, such that the plurality of first conductive patterns 112 can be spaced apart from each other at substantially the same height.

[0110] Next, after removing the hard mask pattern (not shown), a gap-filling insulating layer 114 is formed to fill the gaps between the plurality of first conductive patterns 112. Subsequently, a first upper insulating layer 116 is formed on the plurality of first conductive patterns 112 and the gap-filling insulating layer 114. The gap-filling insulating layer 114 and the first upper insulating layer 116 can each be formed from an oxide layer, or they can be formed together by a single oxide layer deposition process. That is, the gap-filling insulating layer 114 and the first upper insulating layer 116 can be integrally formed with each other.

[0111] Therefore, multiple first stacks can be formed, each first stack comprising at least three or more first conductive patterns 112 spaced apart from each other at substantially the same height.

[0112] like Figure 10C As shown, a first stack 206 in which an interlayer dielectric layer 120 and a sacrificial layer 204 are alternately stacked can be formed on the first upper insulating layer 116. The interlayer dielectric layer 120 can be formed on each of the uppermost and lowermost layers of the first stack 206, wherein the interlayer dielectric layer 120 can be formed from an oxide layer, and the sacrificial layer 204 can be formed from a nitride layer.

[0113] Furthermore, this embodiment illustrates a case where an interlayer dielectric layer 120 is formed on each of the bottommost and topmost layers of the first layer stack 206; however, this disclosure is not limited thereto. As a modification, the sacrificial layer 204 may be formed on each of the bottommost and topmost layers of the first layer stack 206.

[0114] Next, after the process of forming the first laminate 206, a second laminate 208 is formed on the first laminate 206, wherein a second lower insulating layer 130, a sacrificial layer 204, and a second upper insulating layer 136 are sequentially stacked. The second lower insulating layer 130 and the second upper insulating layer 136 can each be formed from oxide layers, and the sacrificial layer 204 can be formed from a nitride layer. The second upper insulating layer 136 can be formed to have a greater thickness than the second lower insulating layer 130 or the interlayer dielectric layer 120.

[0115] Next, after forming a hard mask pattern (not shown) on the second upper insulating layer 136, the hard mask pattern is used as an etching stop to etch the second stacked layer 208, the first stacked layer 206, the first upper insulating layer 116, the first conductive pattern 112, the first lower insulating layer 110, and the pre-source layer SL' to form a plurality of vias 150. Each of the plurality of vias 150 may be formed to penetrate the second stacked layer 208, the first stacked layer 206, the first upper insulating layer 116, the first conductive pattern 112, the first lower insulating layer 110, the second source layer SL2, and the sacrificial source layer 202. Furthermore, the end (or bottom surface) of each of the plurality of vias 150 may be formed inside the first source layer SL1.

[0116] Next, after removing the hard mask pattern (not shown), a memory layer 152 of uniform thickness is formed along the surfaces (i.e., the bottom and side surfaces) of each of the plurality of vias 150. The memory layer 152 may be formed as a stack of layers in which a barrier layer (not shown), a charge trapping layer (not shown), and a tunnel insulating layer (not shown) are sequentially stacked. The tunnel insulating layer and the barrier layer may each be formed from an oxide layer, and the charge trapping layer may be formed from a nitride layer.

[0117] Next, a channel layer 154 of uniform thickness is formed on the memory layer 152 along the surface of each of the plurality of channel vias 150. The channel layer 154 may be formed of a semiconductor layer such as, for example, a silicon layer.

[0118] Next, a core insulating layer 156 for gap filling of each of the plurality of channel holes 150 can be formed on the channel layer 154. The core insulating layer 156 can be formed of an oxide layer.

[0119] Next, a portion of the core insulating layer 156 is recessed, and then a conductive material is used to fill the recessed space to form a capping layer 158. The core insulating layer 156 can be recessed such that the interface between the core insulating layer 156 and the capping layer 158 is adjacent to the interface between the sacrificial layer 204 and the second upper insulating layer 136, but located above the interface between the sacrificial layer 204 and the second upper insulating layer 136. The capping layer 158 can be formed of a doped semiconductor layer, such as, for example, an n-type doped silicon layer.

[0120] Therefore, multiple channel structures CH can be formed, each channel structure CH including a channel hole 150, a memory layer 152, a channel layer 154, a core insulating layer 156, and a capping layer 158.

[0121] like Figure 10DAs shown, after forming a hard mask pattern (not shown) on the second upper insulating layer 136, the hard mask pattern is used as an etching barrier to etch the second stacked layer 208, the first stacked layer 206, the first upper insulating layer 116, the first conductive pattern 112, the first lower insulating layer 110, and the pre-source layer SL' to form a plurality of slot trenches 142. Each of the plurality of slot trenches 142 can be formed to penetrate the second stacked layer 208, the first stacked layer 206, the first upper insulating layer 116, the first conductive pattern 112, the first lower insulating layer 110, and the second source layer SL2. Furthermore, the end (or bottom surface) of each of the plurality of slot trenches 142 can be formed inside the sacrificial source layer 202.

[0122] Next, the sacrificial layer 204 is removed from the first laminate 206 and the second laminate 208 through multiple slit trenches 142, and then a conductive material fills the gaps where the sacrificial layer 204 has been removed. Therefore, multiple second conductive patterns 122 separated by the interlayer dielectric layer 120 can be formed in the first laminate 206. Then, a conductive layer 132A can be formed in the second laminate 208.

[0123] Next, an etching process is performed to remove the conductive material remaining on the sidewalls of each of the plurality of slot trenches 142, wherein the etching process can be performed as a back etching process.

[0124] like Figure 10E As shown, slit spacers 144, for example, insulating layers, are formed on the two sidewalls of each of the plurality of slit trenches 142.

[0125] Next, the sacrificial source layer 202 is removed through the bottom surface of each of the plurality of slit trenches 142, and then the memory layer 152 exposed by removing the sacrificial source layer 202 is removed to expose the channel layer 154.

[0126] like Figure 10F As shown, conductive material fills the gaps in the space where the sacrificial source layer 202 has been removed, thereby forming a third source layer SL3 electrically connected to the channel layer 154, the first source layer SL1, and the second source layer SL2. The third source layer SL3 can be formed from a doped semiconductor layer, such as an n-type doped silicon layer.

[0127] Next, a slit layer 146, such as a conductive layer, is formed to fill the gaps in the slit trench 142. Thus, a plurality of slit structures 140, each including the slit trench 142, the slit spacer 144, and the slit layer 146, can be formed.

[0128] Next, multiple separation layers 134 are formed, each penetrating the second upper insulating layer 136, the conductive layer 132A, and the second lower insulating layer 130. With the formation of the separation layers 134, multiple third conductive patterns 132 can be formed. The third conductive patterns 132 can be formed in a number corresponding to the number of the first conductive patterns 112.

[0129] Therefore, it can form Figure 4 The array shown includes a gate stack GST, a slit structure 140 separating each gate stack GST from each other, and a plurality of channel structures CH through the gate stack GST. Each gate stack GST includes: a first stack ST1, which includes at least three or more first conductive patterns 112 spaced apart from each other at substantially the same height; a second stack ST2, which includes alternately stacked second conductive patterns 122 and interlayer dielectric layers 120; and a third stack ST3, which includes a plurality of third conductive patterns 132 separated by a separating layer 134 to have a number corresponding to the number of first conductive patterns 112.

[0130] Then, semiconductor memory devices can be manufactured using known methods.

[0131] As described above, according to the method for manufacturing a semiconductor memory device according to embodiments of the present disclosure, a plurality of first conductive patterns 112 spaced apart from each other at substantially the same height are formed earlier than the second conductive pattern 122, the third conductive pattern 132, the slit structure 140, and the channel structure CH. This improves the operational reliability of the semiconductor memory device while substantially preventing the increase of process steps, thereby ensuring price competitiveness. For reference, by replacing the sacrificial layer with a conductive layer, only two first conductive patterns 112 can be formed in the gate stack (GST). However, in this embodiment, at least three or more first conductive patterns 112 can be formed.

[0132] Furthermore, since the first conductive pattern 112 is formed from a semiconductor layer and / or a metal silicide layer, even if the first conductive pattern 112 is formed earlier than the second conductive pattern 122, the third conductive pattern 132, the slit structure 140, and the channel structure CH, the operational reliability of the semiconductor memory device can be improved by substantially preventing the characteristics of the first conductive pattern 112 from deteriorating between processes.

[0133] Figure 11 This is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0134] like Figure 11 As shown, the memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0135] The memory device 1120 may include a plurality of gate stacks separated by a plurality of slit structures. As an example, each gate stack may include: a first stack including three or more first conductive patterns spaced apart from each other at substantially the same height; a second stack formed on the first stack and including alternately stacked second conductive patterns and interlayer dielectric layers; a third stack formed on the second stack and including a plurality of third conductive patterns spaced apart from each other at substantially the same height; and a plurality of channel structures extending from the first stack to the third stack. As another example, each gate stack may include: a first stack having a multilayer structure and including three or more first conductive patterns spaced apart from each other for each layer; a second stack formed on the first stack and including alternately stacked second conductive patterns and interlayer dielectric layers; a third stack formed on the second stack having a single-layer structure and including a plurality of third conductive patterns spaced apart from each other; and a plurality of channel structures extending from the first stack to the third stack. The memory device 1120 includes at least three or more first conductive patterns in each gate stack, thus improving operational reliability by substantially preventing increased read interference due to increased integration of the memory device 1120.

[0136] The memory device 1120 may be a multi-chip package consisting of multiple flash memory chips.

[0137] Memory controller 1110 is configured to control memory device 1120 and may include static random access memory (SRAM) 1111, central processing unit (CPU) 1112, host interface 1113, error correction block 1114, and memory interface 1115. SRAM 1111 can serve as working memory for CPU 1112, which can perform various control operations for data exchange with memory controller 1110. Host interface 1113 may include a data exchange protocol for a host electrically connected to memory system 1100. Furthermore, error correction block 1114 can detect and correct errors included in data read from memory device 1120, and memory interface 1115 can perform interface connections with memory device 1120. Additionally, memory controller 1110 may include read-only memory (ROM) storing code data for connection with the host interface.

[0138] Figure 12 This is a block diagram illustrating the configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0139] likeFigure 12 As shown, the computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. The computing system 1200 may be a mobile device.

[0140] Memory system 1210 may include memory device 1212 and memory controller 1211. Memory device 1212 may include a plurality of gate stacks separated by a plurality of slit structures. As an example, each gate stack may include: a first stack including three or more first conductive patterns spaced apart from each other at substantially the same height; a second stack formed on the first stack and including alternately stacked second conductive patterns and interlayer dielectric layers; a third stack formed on the second stack and including a plurality of third conductive patterns spaced apart from each other at substantially the same height; and a plurality of channel structures extending from the first stack to the third stack. As another example, each gate stack may include: a first stack having a multilayer structure and including three or more first conductive patterns spaced apart from each other for each layer; a second stack formed on the first stack and including alternately stacked second conductive patterns and interlayer dielectric layers; a third stack formed on the second stack having a single-layer structure and including a plurality of third conductive patterns spaced apart from each other; and a plurality of channel structures extending from the first stack to the third stack. The memory device 1212 includes at least three or more first conductive patterns in each gate stack, thus improving operational reliability by substantially preventing an increase in read interference due to the increased integration density of the memory device 1212.

[0141] Although the present disclosure has been described in detail with reference to preferred embodiments, the present disclosure is not limited to these embodiments, and various modifications can be made by those skilled in the art within the technical spirit of the present disclosure.

[0142] Cross-references to related applications

[0143] This application claims priority to Korean Patent Application No. 10-2021-0002554, filed on January 8, 2021, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: Multiple gate stacks, said multiple gate stacks being separated by multiple slit structures. Each of the plurality of gate stacks includes: A first stack comprising three or more first conductive patterns spaced apart from each other at the same height; A second stack is formed on the first stack and includes alternating layers of second conductive patterns and interlayer dielectric layers. A third layer, formed on the second layer, and comprising a plurality of third conductive patterns spaced apart from each other at another equal height; and Multiple channel structures, the multiple channel structures extending from the first stack to the third stack. The first conductive pattern has a multilayer structure, which includes at least a first layer and a second layer with the interlayer dielectric layer inserted therebetween, wherein the first layer is located above the second layer, and The channel structure includes a first channel structure and a second channel structure adjacent to the first channel structure, wherein the first channel structure and the second channel structure pass through the same first conductive pattern located in the first layer and pass through different first conductive patterns located in the second layer.

2. The semiconductor memory device according to claim 1, wherein, In each of the plurality of gate stacks, the number of the third conductive patterns is equal to the number of the first conductive patterns in the second layer, and each of the third conductive patterns overlaps with each corresponding first conductive pattern in the second layer.

3. The semiconductor memory device according to claim 1, wherein, In the first layer, the first conductive pattern adjacent to the slit structure in the first conductive pattern has a smaller linewidth than the other first conductive patterns.

4. The semiconductor memory device according to claim 1, wherein, In the first and second layers, the sidewalls of each of the first conductive patterns located at the two edges of the first stack are spaced apart from the sidewalls of the facing slit structure.

5. The semiconductor memory device according to claim 1, wherein, The first stack includes: The first conductive pattern is formed on the first lower insulating layer; A gap-filling insulating layer is formed on the sidewall of each of the first conductive patterns to fill the gaps between the first conductive patterns; and A first upper insulating layer is formed on the gap-filling insulating layer and the first conductive pattern.

6. The semiconductor memory device according to claim 5, wherein, The gap-filling insulating layer is integrally formed with the first upper insulating layer.

7. The semiconductor memory device according to claim 1, wherein, Each of the first conductive patterns includes a doped semiconductor layer, a metal silicide layer, or a stacked layer in which the doped semiconductor layer and the metal silicide layer are stacked.

8. The semiconductor memory device according to claim 1, wherein, In the second layer, the number of channel structures penetrating each of the first conductive patterns is the same.

9. The semiconductor memory device according to claim 1, wherein, In the first layer, the number of channel structures penetrating the first conductive pattern adjacent to the slit structure is less than the number of channel structures penetrating the remaining first conductive patterns.

10. The semiconductor memory device according to claim 1, wherein, Each of the plurality of channel structures includes: A channel hole that penetrates from the first stack to the third stack; A memory layer is formed along the surface of the channel aperture; A channel layer is formed on the memory layer; A core insulating layer formed on the channel layer to fill a portion of the channel apertures; and A capping layer is formed on the core insulation layer to fill the remaining portion of the channel holes with gaps and is electrically connected to the channel layer.

11. A semiconductor memory device, the semiconductor memory device comprising: Multiple gate stacks, said multiple gate stacks being separated by multiple slit structures. Each of the plurality of gate stacks includes: The first stack has a multi-layer structure and includes three or more first conductive patterns spaced apart from each other for each layer; A second stack is formed on the first stack and includes alternating layers of second conductive patterns and interlayer dielectric layers; A third laminate, formed on the second laminate, having a single-layer structure and including a plurality of third conductive patterns spaced apart from each other; and Multiple channel structures, the multiple channel structures extending from the first stack to the third stack. The first conductive pattern includes: Three or more first patterns, wherein the three or more first patterns are located on the lower layer; A second pattern, the second pattern being located on the upper layer and situated at both edges of the first layer; and Multiple third patterns, which are located on the upper layer and between the second patterns.

12. The semiconductor memory device according to claim 11, wherein, The sidewalls of each of the first conductive patterns located at the two edges of the first stack are spaced apart from the sidewalls of the facing slit structure.

13. The semiconductor memory device according to claim 11, wherein, Each of the third patterns overlaps with a portion of the two first patterns, and the third patterns and the first patterns are arranged in a Z-shape in the vertical direction.

14. The semiconductor memory device of claim 11, wherein, The line width of each of the first patterns is equal to the line width of each of the third patterns, and the line width of each of the second patterns is less than the line width of each of the third patterns.

15. The semiconductor memory device according to claim 11, wherein, In each of the plurality of gate stacks, the number of the third conductive patterns is equal to the number of the first patterns, and each of the third conductive patterns overlaps with each corresponding first pattern.

16. The semiconductor memory device of claim 11, wherein, In each of the plurality of gate stacks, the third conductive pattern adjacent to the slit structure overlaps with a portion of the first pattern, the second pattern, and the third pattern.

17. The semiconductor memory device of claim 11, wherein, The channel structure includes a first channel structure and a second channel structure adjacent to the first channel structure, wherein the first channel structure and the second channel structure pass through the same third pattern and pass through different first patterns.

18. The semiconductor memory device of claim 11, wherein, Each of the first conductive patterns includes a doped semiconductor layer, a metal silicide layer, or a stacked layer in which the doped semiconductor layer and the metal silicide layer are stacked.

19. A method for manufacturing a semiconductor memory device, the method comprising the following steps: Forming a first stack comprising at least three or more first conductive patterns spaced apart from each other at the same height; A laminate layer comprising alternating interlayer dielectric layers and sacrificial layers is formed on the first laminate; Forming a plurality of channel structures that penetrate the laminate layers and the first laminate; Slits and grooves are formed in the two sidewalls of the laminate and the first laminate; The sacrificial layer is removed through the slit trench; as well as A second stack comprising alternating layers of a second conductive pattern and interlayer dielectric layers is formed by filling the gaps in the space where the sacrificial layer has been removed with a conductive material. The first conductive pattern has a multilayer structure, which includes at least a first layer and a second layer with the interlayer dielectric layer inserted therebetween, wherein the first layer is located above the second layer, and The channel structure includes a first channel structure and a second channel structure adjacent to the first channel structure, wherein the first channel structure and the second channel structure pass through the same first conductive pattern located in the first layer and pass through different first conductive patterns located in the second layer.

20. The method of claim 19, further comprising the step of: Slit spacers are formed on either side of each of the slit grooves; Forming a slit layer for gap filling of each of the slit grooves; as well as A third stack comprising a plurality of third conductive patterns spaced apart from each other at the same height is formed by separating the second conductive patterns located on the top layer of the second stack to have the same number corresponding to the number of the first conductive patterns.

21. The method according to claim 19, wherein, The steps for forming the first laminate include the following: A conductive layer is formed on the lower insulating layer; The first conductive pattern is formed by selectively etching the conductive layer; A gap-filling insulating layer is formed to fill the gaps between the first conductive patterns; and An upper insulating layer is formed on the gap-filling insulating layer and the first conductive pattern.

22. The method according to claim 21, wherein, Simultaneously, the gap-filling insulating layer and the upper insulating layer are formed to integrally form the gap-filling insulating layer and the upper insulating layer.

23. The method according to claim 19, wherein, In the first and second layers, the sidewalls of each of the first conductive patterns located at the edge of the first stack are spaced apart from the sidewalls of the facing slit trenches.

24. The method according to claim 19, wherein, In the second layer, the number of channel structures penetrating each of the first conductive patterns is the same.

25. The method according to claim 19, wherein, Each of the first conductive patterns includes a doped semiconductor layer, a metal silicide layer, or a stacked layer in which the doped semiconductor layer and the metal silicide layer are stacked.

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