Semiconductor device and method of manufacturing the same

Abstract

This invention discloses a semiconductor device and a method for manufacturing the same. The method includes alternatingly depositing a first semiconductor layer and a second semiconductor layer on a substrate to form a stacked structure; etching the stacked structure and the substrate to form at least one trench, the trench dividing the stacked structure into at least two fins; forming a dummy gate stack on each fin and etching each fin, and filling the trench to form a shallow trench isolation region; etching back the sacrificial layer in the stacked structure and depositing inner sidewalls in the space formed after the back etching, and forming source and drain regions of a metal-oxide-semiconductor field-effect transistor on both sides of each fin; removing the sacrificial layer in the stacked structure to form a nano-stacked device, and removing part or all of the layers of the dummy gate stack; and forming a surround gate and a top gate, wherein the number of first semiconductor layers in the stacked structure is greater than the number of second semiconductor layers, thereby improving the charge mobility of the MOSFET.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to semiconductor devices and their manufacturing methods. Background Technology

[0002] Guided by Moore's Law, as integrated circuit technology continues to develop, the feature size of integrated circuits continues to shrink. When the device feature size enters the technology node of less than 10 nanometers, traditional FinFETs, due to the short-channel effect, find it difficult to achieve a good balance between chip performance and area.

[0003] To address this issue, nanosheet FETs based on vertically stacked nanosheet structures have attracted widespread attention in the industry. Nanosheet devices offer several advantages: First, they provide a larger effective channel width, enabling higher drive current without requiring quadruple exposure in the fabrication process; second, their gate-around-the-loop structure provides superior electrostatic control, allowing for better optimization of parameters such as operating voltage, gate length, and drain-induced barrier lowering (DIBL), while also approaching the theoretical limit of subthreshold swing; third, they offer greater miniaturization capabilities for digital cell libraries and memory cells; and fourth, they exhibit less process variation. Currently, nanosheet devices have become a key technology driving integrated circuits towards 5nm and more advanced technology nodes.

[0004] Current technologies still employ FinFET technology at the 7nm node, while at 3nm and more advanced nodes, a shift towards bulk silicon nanosheet technology is underway. Simultaneously, Fully Depleted Silicon on Insulator (FDSOI) technology has emerged. Compared to bulk silicon nanosheets, FDSOI nanosheets, due to their unique silicon-on-insulator structure, can better address the isolation issues between the gaps between adjacent silicon fins, effectively suppressing parasitic capacitance, improving circuit speed, and reducing device leakage current through control of the bottom parasitic channel.

[0005] Figure 1 A schematic diagram of the structure of a semiconductor device according to the prior art is shown. Figure 1The semiconductor device 100 shown is formed by epitaxially stacking silicon / silicon-germanium layers on a substrate 110, followed by fin etching, selective silicon-germanium etching, and filling with a high-dielectric-constant metal gate. The semiconductor device 100 includes a substrate 110, a gate metal layer 120, a shallow trench isolation layer 130, and three-sided gate-around nanosheets 140 and full-ring gate nanosheets 150. Because the nanosheet 140 is only controlled by three-sided gates, its gate control capability is insufficient, which may increase the leakage current risk of the semiconductor device 100 in the off-state, affecting the device's energy efficiency ratio. Furthermore, because... Figure 1 The NMOS transistor shown has a higher charge transfer efficiency than the PMOS transistor, resulting in an imbalance in the performance of the NMOS and PMOS transistors.

[0006] Therefore, there is a need to propose a new semiconductor device and its manufacturing method to solve the above problems. Summary of the Invention

[0007] In view of the above problems, the purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, thereby improving the charge mobility of a MOSFET.

[0008] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: alternately depositing a first semiconductor layer and a second semiconductor layer on a substrate to form a stacked structure; etching the stacked structure and the substrate to form at least one trench, the trench dividing the stacked structure into at least two fins; forming a dummy gate stack on each fin and etching each fin, and filling the trench to form a shallow trench isolation region; etching back a sacrificial layer in the stacked structure and depositing inner sidewalls in the space formed after the back etching, and forming source and drain regions of a metal-oxide-semiconductor field-effect transistor on both sides of each fin; removing the sacrificial layer in the stacked structure to form a nano-stacked device, and removing part or all of the layers of the dummy gate stack; and forming a surround gate and a top gate, wherein the number of the first semiconductor layers in the stacked structure is greater than the number of the second semiconductor layers.

[0009] Optionally, the substrate has a silicon substrate layer and a buried oxide layer stacked sequentially from bottom to top, and the stacked structure is formed on the buried oxide layer.

[0010] Optionally, the first semiconductor layer is made of silicon-germanium, and the second semiconductor layer is made of silicon.

[0011] Optionally, the semiconductor device is a P-type metal-oxide-semiconductor field-effect transistor and / or an N-type metal-oxide-semiconductor field-effect transistor. When the semiconductor device is a P-type metal-oxide-semiconductor field-effect transistor, the sacrificial layer is a second semiconductor layer; when the semiconductor device is an N-type metal-oxide-semiconductor field-effect transistor, the sacrificial layer is a first semiconductor layer.

[0012] Optionally, when the semiconductor device is a P-type metal-oxide-semiconductor field-effect transistor, the all-around gate is formed in the cavity formed after the sacrificial layer is removed; when the semiconductor device is an N-type metal-oxide-semiconductor field-effect transistor, the all-around gate is formed in the cavity formed after the sacrificial layer that does not contact the dummy gate stack is removed.

[0013] Optionally, when removing some or all layers of the dummy gate stack, if the semiconductor device is a P-type metal-oxide-semiconductor field-effect transistor, the gate dielectric layer in the dummy gate stack needs to be retained; if the semiconductor device is an N-type metal-oxide-semiconductor field-effect transistor, all layers in the dummy gate stack need to be removed. When forming the top gate, if the semiconductor device is a P-type metal-oxide-semiconductor field-effect transistor, the top gate is formed in the cavity formed after removing some layers of the dummy gate stack; if the semiconductor device is an N-type metal-oxide-semiconductor field-effect transistor, the all-around gate is formed in the cavity formed after removing the dummy gate stack and the sacrificial layer in contact with the dummy gate stack.

[0014] Optionally, when the semiconductor device is a P-type metal-oxide-semiconductor field-effect transistor, the source and drain regions are formed by boron-doped silicon-germanium epitaxial growth; when the semiconductor device is an N-type metal-oxide-semiconductor field-effect transistor, the source and drain regions are formed by phosphorus-doped silicon epitaxial growth.

[0015] According to another aspect of the present invention, a semiconductor device is provided, comprising a substrate; a nanosheet stack disposed on the substrate and formed by stacking nanosheets; source and drain regions disposed on both sides of the nanosheet stack; a surrounding gate surrounding the nanosheet stack; and a top gate disposed above the nanosheet stack, wherein the number of nanosheets in the semiconductor device is a P-type metal-oxide-semiconductor field-effect transistor is different from the number of nanosheets in the semiconductor device is an N-type metal-oxide-semiconductor field-effect transistor.

[0016] Optionally, the substrate has a silicon substrate layer and a buried oxide layer stacked sequentially from bottom to top, and the nanosheet stack is disposed on the buried oxide layer.

[0017] Optionally, when the semiconductor device is a P-type metal-oxide-semiconductor field-effect transistor, the number of its nanosheets is one more than when the semiconductor device is an N-type metal-oxide-semiconductor field-effect transistor.

[0018] The semiconductor device and its manufacturing method provided by this invention, for a MOS transistor with a sacrificial layer as the second semiconductor layer, with the same number of all-around gates, have an additional nanosheet layer in their nanosheet stacked structure compared to existing technologies. Therefore, the compressive / tensile stress exerted by the source / drain regions on the nanosheet stacked structure increases, correspondingly improving the charge mobility of the MOS transistor. Furthermore, this invention cleverly compensates for the inherent difference in charge mobility by setting different numbers of nanosheets in the nanosheet stacked structures of NMOS and PMOS transistors. This asymmetric design makes the performance of PMOS and NMOS transistors more matched, thereby improving the switching speed, noise margin, and stability of the entire circuit. Further, by setting the substrate as a silicon substrate layer and a buried oxide layer stacked sequentially from bottom to top, this application allows for better control of the loaded silicon, thereby reducing device leakage current. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0020] Figure 1 A schematic diagram of the structure of a semiconductor device according to the prior art is shown;

[0021] Figure 2 A schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown;

[0022] Figures 3a-3m A schematic diagram of the formation of a semiconductor device according to an embodiment of the present invention is shown. Detailed Implementation

[0023] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0024] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0025] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0026] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0027] Figure 2 A schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown; Figures 3a-3m A schematic diagram of the formation of a semiconductor device according to an embodiment of the present invention is shown.

[0028] See Figure 2 The semiconductor device manufacturing method provided in this embodiment of the invention includes steps S01-S07.

[0029] In step S01, a first semiconductor layer 240 and a second semiconductor layer 250 are alternately deposited on the substrate to form a stacked structure. See details below. Figure 3b .

[0030] In this structure, both the top and bottom layers are first semiconductor layers 240.

[0031] In one example of this application, the substrate has a silicon substrate layer 210 and a buried oxide layer 220 stacked sequentially from bottom to top, the stacked structure being formed on the buried oxide (BOX) layer 220. Figure 3a As shown, the substrate can be obtained by removing the top silicon layer 230 from the finished SOI wafer.

[0032] In other examples of this application, the substrate may also be obtained by depositing a buried oxide layer 220 over a silicon substrate layer 210. In other examples of this application, the substrate may also consist only of a silicon substrate layer 210. For example, the thickness of the silicon substrate layer 210 is approximately 725 μm. The thickness of each semiconductor layer in the stacked structure is less than 30 nm.

[0033] In step S02, the stacked structure and the substrate are etched to form at least one trench 260, which divides the stacked structure into at least two fins. See details. Figure 3c .

[0034] The trench 260 extends through the stacked structure and terminates in the silicon substrate layer 210 of the substrate. It is understood that although only one trench 260 and two fins are shown in the accompanying drawings of this application, this application does not impose specific limitations on them in practical applications.

[0035] In step S03, a dummy gate stack is formed on each fin, and each fin is etched and the trench 260 is filled to form a shallow trench isolation (STI) region 261. See details. Figure 3c and Figure 3d .

[0036] The dummy gate stack comprises a gate dielectric layer 270, a dummy gate layer 280, and a hard mask layer 290 stacked sequentially from bottom to top, with the gate dielectric layer 270 in contact with the upper surface of the fin. For example, the dummy gate stack can be formed by processes such as thermal oxidation, chemical vapor deposition, or sputtering. The material used for the dummy gate layer 280 can be polycrystalline silicon (p-si) or amorphous silicon (a-si). The material used for the gate dielectric layer 270 can be silicon dioxide (SiO2), silicon oxynitride (SiON), etc. The material used for the hard mask layer 290 can be oxides, carbides, organic materials, etc.

[0037] The etching of the fins is carried out along the stacking direction of the stacked structure (i.e., the vertical direction). After etching, the width of each fin in the horizontal direction is equal to the width of the dummy gate stack.

[0038] Furthermore, this application forms a shallow trench isolation region 261 by depositing a dielectric insulating material in the trench 260 and planarizing it (e.g., using a CMP process). The upper surface of the shallow trench isolation region 261 can be flush with the upper surface of the substrate, or slightly higher or lower than the upper surface of the substrate. The dielectric insulating material can be silicon dioxide (SiO2), silicon nitride (SiNx), etc. The function of the shallow trench isolation region 261 is to isolate the transistors formed on the fins.

[0039] Furthermore, etching each fin involves forming sidewalls 310 on both sides of the dummy gate stack, and etching the fin using the sidewalls 310 and the hard mask layer 290 as a mask. For example, the sidewalls 310 are made of silicon nitride (SiNx). The sidewalls 310 formed on both sides of the dummy gate stack have the same thickness.

[0040] In step S04, the sacrificial layer in the stacked structure is etched back, and inner sidewalls 340 / 410 are deposited in the cavity formed after the etch back, and source / drain regions 350 / 380 of metal-oxide-semiconductor (MOS transistor) are formed on both sides of each fin.

[0041] The aforementioned etchback is performed horizontally. After the etchback is completed, a portion of the sacrificial layer will be retained.

[0042] Taking an example where the first semiconductor layer 240 is made of silicon-germanium (SiGe) and the second semiconductor layer 250 is made of silicon (Si), with a stacked structure of SiGe / Si, as an example. Figure 3f As shown, for the fins used to form the PMOS transistor, the second semiconductor layer 250 is etched back, and the cavity formed after the second semiconductor layer 250 is etched is filled by the inner sidewall 340. Figure 3h As shown, for the fins used to form the NMOS transistor, the first semiconductor layer 240 is etched back, and the cavity formed after the first semiconductor layer 240 is etched is filled by the inner sidewall 410. For example, the material of the inner sidewall 410 / 340 is silicon nitride, etc.

[0043] Furthermore, such as Figure 3e As shown, during the etch-back of the second semiconductor layer 250, a protective layer needs to be formed on the surface of the stacked structure used to form the NMOS transistor, the dummy gate stack, and the substrate to prevent the second semiconductor layer 250 in the stacked structure used to form the NMOS transistor from being accidentally etched. For example, the protective layer includes sequentially deposited interlayer dielectric layers 320 and 330.

[0044] Correspondingly, such as Figure 3gAs shown, during the etch-back of the first semiconductor layer 240, a protective layer needs to be formed on the stacked structure used to form the PMOS transistor, the dummy gate stack, and the upper surface of the substrate to prevent the first semiconductor layer 240 in the stacked structure used to form the PMOS transistor from being accidentally etched. For example, the protective layer includes sequentially deposited interlayer dielectric layers 360 and 370.

[0045] Furthermore, the source / drain regions 350 / 380 of each MOS transistor are obtained by epitaxial growth on the upper surface of the substrate. The substrates between adjacent MOS transistors are isolated by shallow trench isolation regions 261.

[0046] The source / drain regions of a MOS transistor can be formed using suitable methods such as metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth (SEG), similar methods, or combinations thereof. For example, the source / drain regions 350 of a PMOS transistor are made of boron (B)-doped SiGe (SiGe:B). The source / drain regions 380 of an NMOS transistor are made of phosphorus (P)-doped silicon (Si) (Si:P).

[0047] In step S05, the sacrificial layer in the stacked structure is removed to form a nano-stacked device, and some or all of the dummy gate stacked layers are removed.

[0048] like Figure 3i As shown, before performing step S05, an isolation layer needs to be deposited on the source / drain regions 350 / 380. To reduce process complexity, isolation layers are also deposited on the upper surface and sides of the dummy gate stack while the isolation layer is deposited on the source / drain regions 350 / 380. Depositing the isolation layer on the source / drain regions 350 / 380 is primarily to prevent short circuits between the dummy gate stack and the source / drain regions 350 / 380 in subsequent steps. After the isolation layer is formed, it needs to be chemically mechanically polished to planarize it. For example, the isolation layer includes interlayer dielectric layers 420 and 430.

[0049] Furthermore, such as Figure 3j As shown, when forming a PMOS transistor, the sacrificial layer is the second semiconductor layer 250. The second semiconductor layer 250 can be removed using an etchant that selectively etches Si at a faster rate than SiGe. At this time, the mask layer 290 and the dummy gate layer 280 in the dummy gate stack need to be removed. Figure 3kAs shown, when forming an NMOS transistor, the sacrificial layer is the first semiconductor layer 240, which can be removed using an etchant that selectively etches SiGe at a faster rate than Si. At this time, the dummy gate stack needs to be completely removed. For example, the dummy gate stack or a portion thereof can be removed by selective etching or etching processes. The sacrificial layer can also be removed using conventional wet etching processes that isotropically etch the sacrificial layer.

[0050] In step S06, a surrounding gate and a top gate are formed.

[0051] In the formation of a PMOS transistor, a gate all-around 450a is formed within a cavity created after the sacrificial layer is removed. In the formation of an NMOS transistor, a gate all-around 450b is formed within a cavity created after the sacrificial layer, which is not in contact with the dummy gate stack, is removed. Specifically, a gate all-around 450a / 450b is formed by sequentially depositing an oxide layer, a high-k dielectric layer, and a metal gate layer within this cavity. The high-k dielectric layer may have a dielectric constant higher than approximately 6.0, and the high-k dielectric layer material may be one or a combination of several of HfO2, HfSiOx, HfON, HfSiON, HfAlOx, Al2O3, ZrO2, ZrSiOx, Ta2O5, or La2O3.

[0052] like Figure 3j As shown, in forming a PMOS transistor, an oxide layer, a high-k dielectric layer, and a metal gate layer are sequentially deposited in the cavity formed after removing at least a portion of the dummy gate stack to form the top gate 440a. Figure 3k As shown, when forming an NMOS transistor, an oxide layer, a high-k dielectric layer, and a metal gate layer are sequentially deposited in the cavity formed after removing the dummy gate stack and the sacrificial layer in contact with the dummy gate stack to form the top gate 440b.

[0053] The metal gate layer comprises a multilayer structure consisting of a capping layer, a barrier layer, a work function layer, and a filler layer. Different effective work functions can be formed by selecting photolithography and etching techniques to control the device threshold. Generally, processes such as chemical vapor deposition (CVD) and physical vapor deposition (PVD) are used to form the metal gate. The metal gate material is one or a combination of several of the following: TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, metal-oxide-semiconductor field-effect transistor (MOSFET) materials: iN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, Ti, Al, Cr, Au, Cu, Ag, HfRu, or RuOx.

[0054] Furthermore, such as Figure 3lAs shown, after the metal gate layer is deposited, the oxide layer, high-K dielectric layer and metal gate layer need to be chemically and mechanically polished to planarize the region and remove excess oxide layer, high-K dielectric layer and metal gate layer exposed outside the cavity on the isolation layer.

[0055] In step S07, a contact electrode 460 is formed to connect the source / drain regions 350 / 380.

[0056] Specifically, such as Figure 3m As shown, the source and drain regions of each MOS transistor are connected to a contact electrode 460. In this application, contact electrodes 460 are obtained by first depositing interlayer dielectric layers 470 and 480 on top of the MOS transistor, then performing photolithography and etching on the interlayer dielectric layer 480 to form contact trenches, and filling the contact trenches with metal silicide.

[0057] It is understood that in this application, the material of the interlayer dielectric layer 320 / 360 / 420 / 470 can be an oxide, and the material of the interlayer dielectric layer 330 / 370 / 430 / 480 can be a nitride, oxide, oxynitride, etc.

[0058] It is understood that, although this application uses a first semiconductor layer 240 as a silicon-germanium (SiGe) layer and a second semiconductor layer 250 as a silicon-Si layer, with a SiGe / Si stacked structure as an example for explanation, in other embodiments of this application, the first semiconductor layer 240 can also be a silicon-Si layer, the second semiconductor layer 250 a silicon-germanium (SiGe) layer, and the stacked structure a Si / SiGe stacked structure. In this case, the NMOS transistor is formed in the same way as the PMOS transistor described above, and the PMOS transistor is formed in the same way as the NMOS transistor described above. This can improve the charge mobility of the NMOS transistor.

[0059] Through the Figure 3m The semiconductor device (i.e., an NMOS transistor or a PMOS transistor) provided in the embodiments of the present invention can be obtained by cutting the structure in the middle. It is understood that although the manufacturing method of the semiconductor device improved in this application is described with the simultaneous formation of an NMOS and a PMOS transistor as an example, in actual applications, only a PMOS transistor or only an NMOS transistor can be formed at the same time. This application does not make specific limitations.

[0060] The semiconductor device includes a substrate; a nanosheet stack, disposed on the substrate and formed by stacking nanosheets 240 / 250; source / drain regions 350 / 380, disposed on both sides of the nanosheet stack; a surrounding gate, surrounding the nanosheet stack; and a top gate 440a / 440b, disposed above the nanosheet stack.

[0061] The substrate has a silicon substrate layer 210 and a buried oxide layer 220 stacked sequentially from bottom to top, with the nanosheet stack disposed on the buried oxide layer 220. The number of nanosheets 240 in a PMOS transistor differs from the number of nanosheets 250 in an NMOS transistor. For example, a PMOS transistor has one more nanosheet 240 than an NMOS transistor has one more nanosheet 250.

[0062] Furthermore, the semiconductor device provided in this embodiment of the invention also includes inner sidewalls 340 / 410, which can both support other layers, i.e., nanosheets, when the sacrificial layer in the stacked structure is removed, and isolate the all-around gate 450 from the source / drain regions 350 / 380 after the semiconductor device is formed.

[0063] The semiconductor device and its manufacturing method provided by this invention, for a MOS transistor with a sacrificial layer as the second semiconductor layer, with the same number of all-around gates, has an additional nanosheet layer in its nanosheet stacked structure compared to existing technologies. Therefore, the compressive / tensile stress exerted by the source / drain regions on the nanosheet stacked structure increases, and correspondingly, the charge mobility of the MOS transistor also improves. Furthermore, this invention cleverly compensates for the inherent difference in charge mobility by setting different numbers of nanosheets in the nanosheet stacked structures of NMOS and PMOS transistors. This asymmetric design makes the performance of PMOS and NMOS transistors more matched, thereby improving the switching speed, noise margin, and stability of the entire circuit. Further, by setting the substrate as a silicon substrate layer and a buried oxide layer stacked sequentially from bottom to top, this application allows for better control of the loaded silicon, thereby reducing device leakage. In addition, the PMOS and NMOS transistors in the embodiments of this invention have essentially the same height, avoiding uneven grinding or defects caused by height differences, improving process yield and structural reliability.

[0064] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising: A first semiconductor layer and a second semiconductor layer are alternately deposited on a substrate to form a stacked structure; The stacked structure and the substrate are etched to form at least one trench that divides the stacked structure into at least two fins; A dummy grid stack is formed on each fin, and each fin is etched and the trenches are filled to form a shallow trench isolation region; The sacrificial layer in the stacked structure is etched back, and inner sidewalls are deposited in the space formed after the etch back, and source and drain regions of metal oxide semiconductor field-effect transistors are formed on both sides of each fin. Removing the sacrificial layer from the stacked structure to form a nano-stacked device, and removing some or all layers of the dummy gate stack; and Forming a surround gate and a top gate, In the stacked structure, the number of the first semiconductor layers is greater than the number of the second semiconductor layers.

2. The manufacturing method according to claim 1, wherein, The substrate has a silicon substrate layer and a buried oxide layer stacked sequentially from bottom to top, and the stacked structure is formed on the buried oxide layer.

3. The manufacturing method according to claim 1, wherein, The first semiconductor layer is made of silicon-germanium, and the second semiconductor layer is made of silicon.

4. The manufacturing method according to claim 3, wherein, The semiconductor device is a P-type metal-oxide-semiconductor field-effect transistor and / or an N-type metal-oxide-semiconductor field-effect transistor. When the semiconductor device is a P-type metal-oxide-semiconductor field-effect transistor, the sacrificial layer is a second semiconductor layer; when the semiconductor device is an N-type metal-oxide-semiconductor field-effect transistor, the sacrificial layer is a first semiconductor layer.

5. The manufacturing method according to claim 4, wherein, When the semiconductor device is a P-type metal-oxide-semiconductor field-effect transistor, the all-around gate is formed in the cavity formed after the sacrificial layer is removed; When the semiconductor device is an N-type metal-oxide-semiconductor field-effect transistor, the all-around gate is formed in the cavity formed after the sacrificial layer that does not contact the dummy gate stack is removed.

6. The manufacturing method according to claim 5, wherein, When removing some or all layers of the dummy gate stack, if the semiconductor device is a P-type metal-oxide-semiconductor field-effect transistor, the gate dielectric layer in the dummy gate stack needs to be retained; if the semiconductor device is an N-type metal-oxide-semiconductor field-effect transistor, all layers in the dummy gate stack need to be removed. When forming the top gate, if the semiconductor device is a P-type metal-oxide-semiconductor field-effect transistor, the top gate is formed in a cavity formed after removing a portion of the dummy gate stack; if the semiconductor device is an N-type metal-oxide-semiconductor field-effect transistor, the all-around gate is formed in a cavity formed after removing the dummy gate stack and the sacrificial layer in contact with the dummy gate stack.

7. The manufacturing method according to claim 6, wherein, When the semiconductor device is a P-type metal-oxide-semiconductor field-effect transistor, the source and drain regions are formed by boron-doped silicon-germanium epitaxial growth; when the semiconductor device is an N-type metal-oxide-semiconductor field-effect transistor, the source and drain regions are formed by phosphorus-doped silicon epitaxial growth.

8. A semiconductor device, comprising: Substrate; The nanosheet stack is disposed on the substrate and is formed by stacking nanosheets. Source and drain regions are located on both sides of the nanosheet stack; A surrounding gate surrounds the nanosheet stack. The top gate is located above the nanosheet stack. The number of nanosheets in a P-type metal-oxide-semiconductor field-effect transistor is different from the number of nanosheets in an N-type metal-oxide-semiconductor field-effect transistor.

9. The semiconductor device according to claim 8, wherein, The substrate has a silicon substrate layer and a buried oxide layer stacked sequentially from bottom to top, and the nanosheet stack is disposed on the buried oxide layer.

10. The semiconductor device according to claim 9, wherein, When the semiconductor device is a P-type metal-oxide-semiconductor field-effect transistor, the number of its nanosheets is one more than when the semiconductor device is an N-type metal-oxide-semiconductor field-effect transistor.

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