Control unit for a switching converter operating in continuous conduction and peak current control mode

Abstract

A control unit for a switching converter operating in continuous conduction and peak current control mode. The control unit has an inductor element coupled to an input and a switching element coupled to the inductor element, generates a command signal having a switching period to switch the switching element, and determines a first time period in which an inductor current flows in the inductor element for storing energy and a second time period in which energy is delivered to a load. The input current is distorted with respect to a sinusoidal curve by a distortion factor caused by a current ripple on the inductor current. A duration of the first time period is determined based on a comparison between a value of a peak of the inductor current and a current reference dependent on an output voltage of the voltage converter. A reference modification stage modifies the current reference to compensate for the distortion introduced to the input current by the distortion factor.

Description

[0001] Divisional Application Instructions

[0002] This application is a divisional application of Chinese patent application No. 201710919667.5, filed on September 30, 2017, entitled "Control Unit of Switching Converter Operating in Continuous Conductive and Peak Current Control Modes". Technical Field

[0003] This disclosure relates to control circuitry or units for switching converters, and particularly (but not limited to) power factor correction (PFC) converters. Specifically, the control unit is a voltage converter operating in continuous conduction mode (CCM) and peak current control mode. Background Technology

[0004] In known applications, voltage converters used in power supplies that operate in switch mode (switch-mode power supplies or SMPS) in desktop computers, LED lighting equipment, or electronic medical devices typically need to meet stringent requirements related to their electrical performance.

[0005] In particular, such converters must guarantee a high quality factor with a power factor (PF) that is essentially unit 1 (e.g., greater than 0.9) and an ideal total harmonic distortion (THD) of zero input current.

[0006] Typically, such voltage converters can transform received input quantities, such as alternating current (AC) voltage from the power grid, into regulated output quantities, such as direct current (DC) voltage, which are then used to power electrical loads.

[0007] Specifically, it is known to use power converters with a two-stage architecture, for example, where high output power is required. The first stage is a PFC converter, typically a boost or boost-type PFC converter. This PFC converter boosts the line AC voltage to generate a continuously regulated output voltage. The PFC converter is controlled by a suitable control unit or module (“controller”) to adjust the power factor when the line absorbs power.

[0008] Figure 1 A wiring diagram of a voltage converter is shown, which is in particular a PFC boost converter indicated generally by reference numeral 1, controlled by an associated control unit, circuit or module indicated by reference numeral 2.

[0009] The control unit 2 is an integrated circuit with its own package and associated input and output pins. This integrated circuit can be mounted on a single printed circuit board (PCB) containing the circuit components that form the voltage converter 1 or the corresponding integrated circuit.

[0010] Specifically, in this configuration, the voltage converter 1 has an input terminal IN and an output terminal OUT, and at the input terminal IN there is a rectifier stage 3 (e.g., a diode bridge rectifier) ​​rectified according to, for example, an AC voltage V supplied by the power grid. AC The generated input voltage V IN (Having a rectified sine wave form), there exists a voltage greater than the input voltage V at the output terminal OUT. IN And the continuous output voltage V is adjusted to the desired value. OUT .

[0011] The filter capacitor 4a, which performs high-frequency filtering, is connected to the input terminal IN, while the storage capacitor 4b, which performs charge storage, is connected to the output terminal OUT. Both the filter capacitor 4a and the storage capacitor 4b are also connected to the reference or ground terminal (GND).

[0012] The voltage converter 1 includes an inductor element 5 connected between the input terminal IN and the first internal node N1, a switching element 6 (specifically a MOSFET power transistor) connected between the first internal node N1 and the second internal node N2, and a diode element 7 having a positive terminal connected to the first internal node N1 and a negative terminal connected to the output terminal OUT.

[0013] The switching element 6 has a first current-on terminal (particularly the drain terminal of the corresponding MOSFET transistor) connected to the first internal node N1, a second current-on terminal (particularly the source terminal of the corresponding MOSFET transistor) connected to the second internal node N2, and a control terminal serving as the gate terminal of the corresponding MOSFET transistor.

[0014] The first voltage divider 8 is connected between the input terminal IN and the reference terminal. It is formed by connecting the first voltage divider resistor 8a and the second voltage divider resistor 8b in series, thus forming the first voltage divider node P1, which is equal to K. p ·V IN The first voltage divider V P1 It is drawn from the first voltage divider node P1, where K p It is the voltage dividing factor of the first voltage divider 8.

[0015] Furthermore, the second voltage divider 9 is connected between the output terminal OUT and the reference terminal, and is formed by connecting the corresponding first voltage divider resistor 9a and the corresponding second voltage divider resistor 9b in series, thereby forming the second voltage divider node P2, and the second voltage divider voltage V. P2 It is drawn from the second pressure dividing node P2.

[0016] The voltage converter 1 also includes a sensing resistor 11 connected in series with the switching element 6 between the second internal node N2 and the reference terminal. The voltage at the end of the sensing resistor 11 indicates the current I flowing through the switching element 6 after passing through the inductor element 5 when the switching element 6 is closed. L (For simplicity, this current is referred to as the inductor current I) L Therefore, the above voltage is determined by R. s ·I L Given, where Rs is the resistance of sensing resistor 11.

[0017] Control unit 2 is designed to be connected to the first voltage divider node P1 and receive the first voltage divider voltage V. P1 The input (or pin) MULT is designed to be connected to the second voltage divider node P2 via compensation network 12, and the input COMP is connected to the same second voltage divider node P2 and is designed to receive the second voltage divider voltage V. P2 The input FB is designed to be coupled to the second internal node N2 and has a sensed voltage V on it. CS The input CS (which in this case is the same as the voltage at the end of the sensing resistor 11), and the control terminal designed to be connected to the switching element 6 and provide the command voltage V GD The output GD, command voltage V GD This is used to command the aforementioned switching element 6 to switch according to the appropriate timing using pulse width modulation (PWM).

[0018] Control unit 2 includes an error amplifier 10, which is connected to input FB to receive a second voltage divider V. P2 First input, received voltage reference V REF The second input, and the comparison voltage V generated thereon. C The output of the comparison voltage V C Depending on the above voltage divider V P2 With the voltage reference V mentioned above REF The difference (or error).

[0019] The control unit 2 can be configured to control the operation of the voltage converter 1 in continuous conduction mode (CCM) using peak current control.

[0020] Specifically, using each switching cycle, the control unit 2 commands the switching element 6 to operate within the time period T. ON (The "ON" cycle of the duty cycle) is closed, during which current from the input terminal IN flows in the inductor element 5 and the switching element 6 until ground, thereby causing energy to be stored in the inductor element 5.

[0021] In peak current control mode, the control unit 2 uses a suitable feedback control loop based on the voltage at the end of the sensing resistor 11 to control the on-time period T. ON The duration (or period) of stability indicates the inductor current I. L The value of this is compared with a suitable reference voltage (described in detail below). This reference voltage is determined to be compared with the aforementioned inductor current I. L The peak value is compared with the expected current reference.

[0022] Control unit 2 then commands switching element 6 to disconnect during the time period T. OFF (The "OFF" cycle of the duty cycle) is turned on, during which the energy previously stored in the inductor element 5 is transferred to the load and charge storage element 4b via the diode element 7.

[0023] Specifically, the disconnection time period T OFF The duration can be fixed (in a control mode known as fixed off time or FOT), or determined to be a fixed PWM switching frequency (in a control mode known as PWM fixed frequency or FF).

[0024] In all cases, throughout the entire duration of the switching cycle, the continuous conduction mode provides an inductor current I that is always greater than zero. L (Unlike discontinuous conduction mode (DCM), it instead involves the presence of an inductor current I.) L Off-time period T with a zero switching cycle OFF (part of)

[0025] Figure 2 The current I in inductor element 5 is shown. L The trend of the command signal GD in relation to the aforementioned continuous conduction control mode (CCM) shows the conduction time period T during which energy is stored in inductor element 5. ON and disconnection time period T OFF . Figure 2 It also shows the representation of the inductor current I. L The peak value of I L,pk (determined by the reference voltage value as shown above), and representing the inductor current I caused by PWM switch control. L The current ripple ΔI L On the other hand, I L,AVG Indicates the inductor current I L The average value.

[0026] The following is for reference Figure 3 A known embodiment of the control unit 2 (not shown here) of the voltage converter 1 that implements the above control method is described in more detail.

[0027] Control unit 2 includes a multiplier stage 14, which is connected to inputs MULT and COMP, and is designed to operate at a multiplication degree K. M Achieve the first voltage divider V P1 And compare voltage V C The product of V and V is used to generate the aforementioned reference voltage. CS_REF The instruction is therefore given by the following expression:

[0028] V CS_REF (θ)=V C ·K M ·K P ·V in,pk ·sinθ

[0029] It should be noted that the input voltage V IN It can be considered essentially a rectified sine wave, or V IN (θ)=V IN,pk ·sinθ, where the phase angle θ is in the range (0, π).

[0030] Control unit 2 also includes a comparator stage 15 and a trigger or set / reset SR latch 16. Comparator stage 15 has a first comparison terminal (e.g., positive) on which a comparison voltage V' is applied, is connected to the output of multiplier stage 14, and receives a reference voltage V. CS_REF The second comparison terminal (negative in this example) and the output that generates the reset signal for SR latch 16.

[0031] In this case, the first comparison terminal is directly coupled to the input CS, and the comparison voltage V' is compared with the sensed voltage V. CS And the voltage at the end of the sensing resistor 11 (which varies with time and has a phase angle θ) is the same.

[0032] Therefore, SR latch 16 has a reset input R connected to the output of comparator stage 15, and is connected at the appropriate time and based on the off-time period T. OFF (For example, in FOT or FF mode, see the preceding discussion) the appropriate determination of the duration of the timer stage 18 setting input S to generate the set signal S, and the supply of the driven unit (driver) 19 at the output GD to convert it into a command voltage V. GD The command signal is used to switch the output Q of the switching element 6.

[0033] Therefore, the operation of control unit 2 involves the output Q of SR latch 16 periodically going low, thereby affecting the operation of the latch when the current depends on the inductor current I. L The peak value I L,pk The comparison voltage V' and the reference voltage VCS_REF The conduction time period T is determined when the reset signal of the reset input R is high, according to a predetermined ratio. ON End and disconnection time period T OFF The beginning (in other words, the inductor current I) L The peak value I L,pk From the reference voltage V CS_REF The value is determined by the current reference provided (when timer level 18 is based on the disconnection time period T). OFF When the set signal of the setting input S of the SR latch 16 is set, the output Q goes high, thus determining the off-time period T. OFF The end and conduction time period T ON A new beginning.

[0034] It can be easily proven that the inductor current I L The peak value (during the conduction time period T) ON (At the end) is given by the following formula:

[0035]

[0036] Therefore, the value of this peak has a sinusoidal trend because, during use, and considering that the bandwidth of the compensation network 12 is sufficiently narrow, for example less than 20Hz, the comparison voltage V... C It can be considered to be essentially constant (or continuous) during the online cycle.

[0037] The inductor current I absorbed by the power network during the switching cycle L The average value of the input current I IN equal:

[0038]

[0039] The above expression can be arguably rewritten as follows:

[0040]

[0041] in:

[0042]

[0043]

[0044] Where f SW It is the switching frequency, L is the inductance of inductor element 5, and V is the switching frequency. Vin,pk It is the input voltage V IN The value of the peak value.

[0045] The above expression clearly shows that the input current I INThe trend of (θ) is particularly evident as the inductor current I L The ripple on the curve is not a sine curve, thus determining that the power factor PF < 1 and the distortion factor THD > 0%, which is undesirable.

[0046] In particular, the values ​​of the power factor PF and the distortion factor THD mentioned above may deviate significantly from their ideal values ​​under certain operating conditions of the voltage converter 1.

[0047] Therefore, known solutions for providing control based on peak current in continuous conduction mode (CCM) are not entirely satisfactory.

[0048] Although there are other control solutions, such as those based on controlling average current, these solutions are more complex to implement and usually require additional pins in control unit 2 to compensate for the current loop.

[0049] In other words, existing control solutions inevitably require a trade-off between distortion characteristics and implementation complexity / cost. Summary of the Invention

[0050] The purpose of this disclosure is to solve the above-mentioned problems, and in particular to provide a control solution that improves the performance of the control solution based on the peak current in a converter (particularly a PFC boost converter) operating in continuous conduction mode (CCM).

[0051] Therefore, this disclosure provides embodiments of a control unit for a switching converter, as well as corresponding embodiments of a switching converter and method. Attached Figure Description

[0052] The present disclosure will now be further described with reference to preferred embodiments provided purely by way of non-limiting example and the accompanying drawings, in which:

[0053] Figure 1 A schematic circuit diagram of a known type of voltage converter and its associated control unit is shown;

[0054] Figure 2 Is with Figure 1 Timing diagram of the electrical signals related to the voltage converter in the circuit;

[0055] Figure 3 It shows Figure 1 A more detailed block diagram of the control unit of the voltage converter in the diagram;

[0056] Figure 4 A switching converter according to one embodiment of this solution is shown, for example... Figure 1 A block diagram of the control unit for the same voltage converter shown;

[0057] Figure 5 It shows Figure 4 A more detailed block diagram of the stages of the control unit;

[0058] Figure 6A and Figure 6B yes Figure 4 The signal timing diagram of the power supply in the control unit;

[0059] Figure 7 It is a switching converter according to another embodiment of this solution, for example Figure 1 The block diagram of the control unit of the voltage converter shown is shown.

[0060] Figure 8 and Figure 9 It is a signal diagram showing the known type of control unit according to this solution and the corresponding trend of the power in the control unit;

[0061] Figure 10 This is a general block diagram of an electronic device using a voltage converter according to an embodiment of this solution; and

[0062] Figure 11 This is a switching converter according to another embodiment of the present solution, for example... Figure 1 The block diagram shown is of the control unit of the voltage converter. Detailed Implementation

[0063] Figure 4 A control unit, generally indicated by reference numeral 20, is shown for a switching converter, particularly for controlling a voltage converter, and more specifically for a PFC boost converter operating in continuous conduction and peak current control modes. For simplicity in the illustration, Figure 4 Only the switching element 6 of the voltage converter (with its associated sensing resistor 11) is shown; the rest can be, for example, connected to... Figure 1 The voltage converter 1 in the middle is similar (and in Figure 4 (Not shown in the image).

[0064] Control unit 20 and Figure 3 The control unit 2 is constructed in a basically similar manner (similar elements are therefore shown using the same reference numerals and will not be discussed further), but the difference is that it also includes a reference modified stage 22 coupled to the first comparison terminal of the comparator stage 15 (and the input CS of the control unit 20).

[0065] As discussed in detail below, this reference modification level 22 is configured to appropriately modify the relationship with the inductor current I. L The peak value is compared with the current reference in order to eliminate or at least significantly reduce the current ripple ΔI. L For input current IIN The influence of the expression is used to obtain the distortion factor THD, which is ideally zero, and the power factor PF, which is ideally one unit.

[0066] Specifically, given the above discussion, the input current I IN It can be represented as:

[0067]

[0068] One aspect of this solution is to add current ripple ΔI to a current reference used for comparing peak currents. L A proportional, appropriate offset is used to eliminate the ripple effect on the input current I. IN The effect of the above expression.

[0069] In other words, the above expression can also be represented as follows:

[0070]

[0071] One aspect of this solution provides a reference voltage V. CS_REF Add an offset voltage V that satisfies the following equation OS,THD_CCM :

[0072]

[0073] Therefore, the above expression becomes:

[0074]

[0075] And therefore:

[0076]

[0077] or:

[0078]

[0079] Therefore, the input current I is required. IN Ideally, it should be a sine wave to optimize the performance of voltage converter 1.

[0080] In particular, one aspect of this solution provides the generation of inductor current I. L Current ripple ΔI in L And especially with the inductor current I L Current ripple ΔI in L Proportional optimization of current I THD_CCM It also provides optimization of current I THD_CCM Generate the above offset voltage V OS,THD_CCM As a result of the optimized current I THD_CCMA voltage drop of an appropriate value is generated across the resistive element, such that the offset voltage V OS,THD_CCM The following equation is satisfied.

[0081] exist Figure 4 In the embodiment shown, the current I is optimized. THD_CCM It is absorbed (“sinking”) by the input CS of the control unit 20 and has a resistance R THD_CCM The optimized resistor 23 is connected between the second internal load N2 and the input CS of the control unit 20. Subsequently, the following expression is satisfied:

[0082] V OS,THD_CCM (θ)=R THD_CCM ·I THD_CCM (θ).

[0083] More specifically, reference modification level 22 includes features designed to generate the command voltage V. CH Proportional optimization of current I THD_CCM The command voltage V CH The first current source 24 for voltage control, and the optimized circuit or block 25 having a first input coupled to the input MULT and a second input coupled to the output Q of the SR latch 16, are connected to the input voltage V. IN The proportional first voltage divider V P1 The latch signal is received from the first input and the corresponding latch signal is received from the second input. The latch signal is also represented by the reference symbol Q and corresponds to the on-time period T. ON .

[0084] The output of optimization block 25 is used to compare with the above input voltage V. IN and the aforementioned conduction time period T ON The product of the first current source 24 is proportional to the command voltage V. CH :

[0085] V CH (θ)αV IN (θ)·T ON (θ).

[0086] Given current ripple ΔI L Given in a known manner by the following:

[0087]

[0088] Command voltage V CH And therefore optimize the current I THD_CCM As needed, with the current ripple ΔI L Proportional, where inductance L P It is the inductance of inductor element 5.

[0089] The following is for reference. Figure 5 Possible embodiments of the optimization block 25 of the reference modification level 22 of the control unit 20 are described.

[0090] Specifically, the optimization block 25 includes a second voltage-controlled current source 28, which receives a first voltage divider voltage V from the first input of the optimization block 25. P1 As a control voltage, and supplied to charging node N C Supply charging current I CH Its value depends on the input voltage V according to the following expression. IN :

[0091] I CH (θ)=g ma K P V IN (θ)

[0092] Where g ma It is the transconductance of the second current source 28.

[0093] Optimization block 25 also includes connections to charging node N C The value or capacitance C between the reference ground terminal (again indicated as GND) and the reference ground terminal is... TR The charging capacitor 29 is connected in parallel with the charging capacitor 29 at the charging node N. C The first switching signal SW between the ground reference terminal and the ground reference terminal a The first switching element 30 driven by the charging node N is connected to the charging node N. C With maintaining node N H The second switching signal SW between b The second switching element 31 driven by the above-mentioned holding node N H The capacitance C between the reference ground terminal and the reference ground terminal H The sustaining capacitor 32.

[0094] Specifically, at charging node N C There is a charging voltage V on it. CTR And in maintaining node N H There is a command voltage V on it. CH This constitutes the control voltage of the first current source 24.

[0095] Optimization block 25 further includes a delay element 34 connected to a second input of optimization block 25, receiving a latch signal Q from the second input of optimization block 25, and designed to delay the latch signal Q by an appropriate time delay ΔT, for example, 200 ns. Optimization block 25 also includes an inverter element 35 cascaded to delay element 34 to receive the appropriately delayed latch signal, thereby outputting a first switching signal SW for first switching element 30. a .

[0096] Optimization block 25 also includes a monostable element 36, which is also connected to the second input of optimization block 25, receives a latch signal Q from the second input of optimization block 25, and is designed to receive the latch signal Q at the falling edge of the latch signal Q (or at the on-time period T). ON At the end and during the disconnection time period T OFF At the beginning, a second switching signal SW is generated. b , as an example pulse signal with a duration of 100ns.

[0097] During use, the charging capacitor 29 operates during the conduction time period T. ON During this period, the device is charged using a charging current, which is assumed to be constant (assuming the switching period T). SW Much smaller than the line period T L Or input voltage V IN period V IN ,T SW <<1 / f L And with input voltage V IN Proportional.

[0098] Therefore, the charging voltage V CTR Given by the following expression:

[0099]

[0100] And therefore related to the input voltage V IN Proportional to and related to the conduction time period T ON Proportional.

[0101] At the falling edge of the latch signal Q, the holding capacitor 32 remains in place for the on-time period T. ON The voltage value at the end of the aforementioned charging capacitor 29 at the end makes the command voltage V... CH Also related to the input voltage V IN and conduction time period T ON Proportional:

[0102]

[0103] Therefore, the command voltage V CH The first current source 24 is transformed into the optimized current I through the following expression. THD_CCM :

[0104]

[0105] The input voltage V has been replaced. IN and conduction time period T ON and the inductance L of inductor element 5 P Current ripple ΔI L The expression.

[0106] Specifically, and as needed, optimize the current I. THD_CCM Therefore, it is related to the current ripple ΔI L Proportional.

[0107] Given the above, it is immediately clear that by setting the resistance R of the optimized resistor 23... THD_CCM Makes the following expressions true:

[0108]

[0109] Input current I IN It is given by the following formula:

[0110]

[0111] Therefore, assuming the comparison voltage V C Online half-cycle constant, input current I IN It is a sine wave and is related to the input voltage V. IN In phase (this is true in all standard PFC converters).

[0112] This results in ideal operation with unity power factor (PF = 1) and zero distortion factor THD (THD = 0), regardless of the inductor current I. L Current ripple ΔI L how.

[0113] Figure 6A and Figure 6B The changes or trends of the signals with the most significant waveforms related to the operation of the control unit 20 described above are shown.

[0114] It should be particularly noted that when the charging capacitor 29 is "reset" and the charging voltage V CTR Before returning to zero, the delay caused by switching the latch signal Q by closing the first switching element 30 allows for efficient transfer of charge between the charging capacitor 29 and the holding capacitor 32.

[0115] The following is for reference. Figure 7 Different embodiments of the control unit, again indicated by reference numeral 20, are described.

[0116] The difference between this embodiment and the previously described solution is that an optimized current I is supplied (“source-supplied”) at the input CS of control unit 2. THD_CCM .

[0117] In fact, in this case, for the inductor current I L The ground return performs current sensing. In other words, the sensing resistor 11 is connected in this case to the second internal node N2 (which is directly connected to the reference terminal) and the current return node N. G (Connected between the return node of rectifier stage 3) and the optimized resistor 23 is connected to the aforementioned current return node N. G Between the input CS of the control unit 20 and the input CS.

[0118] In addition, Figure 7 In the embodiment shown, there is an additional switching element 38 connected between the output of the first current source 24 and the input CS of the control unit 20 and driven by the latch signal Q.

[0119] Therefore, it is advantageous to only use the on-time period T during the switching cycle. ON During this period, the current I was optimized. THD_CCM Used for controlling operations (and thus replicating the operations of the first embodiment described above).

[0120] Furthermore, in this case, there is a converter element 39 connected between the aforementioned input CS and the first comparison terminal of the comparator stage 15, which is configured to convert the sensed voltage V present at the input CS. CS The negative value is converted to a positive value to generate the comparison voltage V' (thus replicating the operation of the first embodiment described above).

[0121] It is immediately clear that, in this case, the following expression also holds true:

[0122]

[0123] V OS,THD_CCM (θ)=R THD_CCM ·I THD_CCM (θ)

[0124] Similarly, optimize current I THD_CCM It allows the desired current offset to be added to the programmed peak current (or to the current reference) in order to optimize control performance.

[0125] The advantages of the proposed solution are clear from the description above.

[0126] In any case, it should be noted again that such a solution makes it possible to overcome the limitations of known types of control solutions, especially enabling the achievement of an ideally sinusoidal input current I in control solutions based on peak current in voltage converters operating in continuous conduction mode (CCM), particularly PFC boost converters. IN And a distortion factor that is ideally zero (and less than 5% in any case).

[0127] The applicant has conducted extensive experimental and simulation tests and examined the proposed solution.

[0128] As an example, Figure 8 and Figure 9 A comparison was made with control units based on existing technologies (particularly...) Figure 3 The performance of control unit 2 in (in Figure 8 (as shown in the diagram) and the performance of the control unit 20 according to this solution (in Figure 9 (as shown in the image).

[0129] In both cases, the voltage converter operates at full load, with an input AC voltage V. AC It is 230V.

[0130] It is immediately apparent that the proposed solution makes it possible to significantly reduce waveform distortion, thereby reducing the distortion factor THD from approximately 24% (in conventional solutions) to less than 5% (in the proposed solution), and the power factor PF is 0.981 (essentially a unit 1).

[0131] Although not shown, the applicant has verified the possibility of obtaining a distortion factor of 1.2% with a power factor PF of 0.995, where the input AC voltage V AC It is 115V.

[0132] As mentioned above, such as Figure 10 As shown, the voltage converter 1 and the associated control unit 20 can be advantageously used in the switching power supply 40.

[0133] Specifically, the switching power supply 40 includes a rectifier stage 3 (e.g., a diode bridge rectifier) ​​connected to the power grid 42 via an EMI filter 43 in this example, and an input capacitor element 4a connected to the output of the rectifier stage 3, on which an input voltage V is applied. IN .

[0134] The switching power supply 40 also includes a voltage converter 1, which has an input terminal IN connected to the input capacitor element 4a and an output terminal OUT connected to the charge storage element 4b, as defined above.

[0135] Control unit 20 controls the operation of voltage converter 1 to, for example, ensure the desired power factor in the absorption of the power grid 42.

[0136] The switching power supply 40 also includes an output power converter 46, which in this example is a DC / DC converter, having an input connected to an output capacitor element 4b, which is designed to provide a desired output voltage value, for example, relative to the output voltage V, to a load or end user (not shown). OUT The value is appropriately reduced.

[0137] Obviously, modifications and variations can be made to the subject matter described and shown without exceeding the scope of protection of this disclosure as defined by the appended claims.

[0138] In particular and as Figure 11 As shown, another embodiment of the control unit, also indicated by reference numeral 20, can provide for changing the current I used to control the inductor. L Different solutions reference the peak value of the current.

[0139] In this case, the control unit 20 has an additional pin THD_CCM, which forms an additional input dedicated to optimizing performance.

[0140] In this case, an optimized current I is provided at the additional input THD_CCM. THD_CCM (The output of the first current source 24 is connected to the same additional input), and the optimization resistor 23 is connected between the aforementioned additional input THD_CCM and the reference ground terminal.

[0141] Control unit 20 also includes a summing block 50, which has a connection to input THD_CCM and is designed to receive offset voltage V. OS,THD_CCM The subtractor input is connected to input CS and is designed to receive the sensed voltage V. CS The summation input and the output connected to the first comparison terminal of comparator stage 15 generate a summation input to the reference voltage V. CS_REF The comparison voltage V' is used for comparison.

[0142] It is immediately clear that, in this case, the following expression also holds true:

[0143]

[0144] V OS,THD_CCM (θ)=R THD_CCM ·I THD_CCM (θ)

[0145] In other words, optimize current I THD_CCMThis again allows the desired current offset to be added to the programmed peak current in a manner completely similar to the embodiments described above.

[0146] Typically, it is evident that the reference modification stage 22 operates such that the comparison voltage V' is the voltage at the end of the sensing resistor cascaded to the switching element 6 and the offset voltage V. OS,THD_CCM Combinations, especially linear combinations.

[0147] It should be noted that voltage converter 1 can be powered by a source other than the mains power grid.

[0148] Furthermore, as a non-limiting example, the switching converter involved in this solution can advantageously be formed as a voltage converter or regulator, as described above, or as a current converter or regulator (such as a driving device, driver, for an LED or battery charger).

[0149] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to these embodiments based on the detailed description above. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed as including all possible embodiments and the full scope of equivalents enjoyed with such claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A control system for a converter, comprising: A converter, comprising inductors and switches; as well as A controller, configured to drive the converter by operating the switch between a first state where the switch is on and a second state where the switch is off, the controller comprising: The first input is configured to receive a first voltage representing the current of the inductor via a sensing resistor; The second input is configured to receive a signal indicating the on or off state of the switch; and The reference modification stage, including a charging capacitor, a sustaining capacitor, and a first current source, is configured to: The charging capacitor is charged for a duration corresponding to the duration of the first state; The charge of the charging capacitor is transferred to the sustaining capacitor; The first current source absorbs a current proportional to the current ripple of the inductor's current, wherein the current source absorbs current based on the charge of the holding capacitor to generate an offset voltage; and The first voltage is reduced based on the offset voltage. The controller is configured to control the converter based on the reduced first voltage.

2. The control system according to claim 1, comprising: The third input is configured to receive a second voltage representing the input voltage of the converter; as well as A second voltage-controlled current source has a control input coupled to the third input and an output for outputting a charging current, the second voltage-controlled current source being configured to generate a charging current having a level related to the second voltage.

3. The control system according to claim 1, comprising: A delay element having an input terminal coupled to a second input terminal, and the delay element being configured as follows: Receive the signal; Delay the signal and generate a delayed signal; as well as The delayed signal is output through the output.

4. The control system according to claim 3, comprising: A charge / discharge switch, connected in parallel with the charging capacitor and having a control input coupled to the output of the delay element, is configured to operate between an on state and a non-on state based on the delay signal.

5. The control system according to claim 1, comprising: A monostable element having an input coupled to a second input, and the monostable element being configured as follows: Receive the signal; Based on the signal detection, the transition between the first state and the second state is detected; In response to detecting a transition between the first state and the second state, a switch signal with an active state is generated; as well as The switching signal is output through the output of the monostable element.

6. The control system according to claim 5, comprising: A charge transfer switch having a conducting terminal coupled between the charging capacitor and the sustaining capacitor, and the charge transfer switch having a control input coupled to the output of the monostable element, the charge transfer switch being configured to switch to a conducting state in response to a switching signal having an active state, so as to transfer the charge of the charging capacitor to the sustaining capacitor.

7. A method for controlling a converter, comprising: The controller drives the converter, which includes an inductor, by operating the switch between a first state where the switch is on and a second state where the switch is off. The controller receives a first voltage representing the current of the inductor via a sensing resistor; The controller receives a signal indicating the on or off state of the switch; The charging capacitor is charged during the duration corresponding to the duration of the first state. The charge of the charging capacitor is transferred to the sustaining capacitor; A first current source absorbs a current proportional to the current ripple of the current in the inductor, wherein the current source absorbs current based on the charge of the holding capacitor to generate an offset voltage. The first voltage is reduced based on the offset voltage; as well as The converter is controlled based on the reduced first voltage.

8. The method of claim 7, comprising: Receive a second voltage representing the input voltage of the converter; as well as A charging current with a level related to the second voltage is generated.

9. The method of claim 7, comprising: The signal is delayed and a delayed signal is generated.

10. The method of claim 9, comprising: The charging / discharging switch operates between the on and off states based on the delayed signal.

11. The method of claim 7, comprising: Based on the signal detection, the transition between the first state and the second state is detected; and In response to detecting a transition between the first state and the second state, a switch signal with an active state is generated.

12. The method of claim 11, comprising: In response to the switch signal having the activated state, the charge transfer switch is switched to the on state to transfer the charge of the charging capacitor to the sustaining capacitor.

13. A controller for a converter, comprising: The first input is configured to receive a first voltage representing the current of the inductor of the converter via a sensing resistor; The second input is configured to receive a signal indicating the state of the switch of the converter, the state being either a first state in which the switch is turned on or a second state in which the switch is turned off. as well as The reference modification stage, including a charging capacitor, a sustaining capacitor, and a first current source, is configured to: The charging capacitor is charged for a duration corresponding to the duration of the first state; The charge of the charging capacitor is transferred to the sustaining capacitor; The first current source absorbs a current proportional to the current ripple of the current in the inductor, wherein the current source absorbs current based on the charge of the holding capacitor to generate an offset voltage. as well as The first voltage is reduced based on the offset voltage. The controller is configured to control the converter based on the reduced first voltage.

14. The controller of claim 13, comprising: The third input is configured to receive a second voltage representing the input voltage of the converter; as well as A second voltage controller current source has a control input coupled to the third input and an output for outputting a charging current, the second voltage controller current source being configured to generate the charging current having a level related to the second voltage.

15. The controller according to claim 13, comprising: A delay element having an input coupled to the second input, and the delay element being configured as follows: Receive the signal; Delay the signal and generate a delayed signal; as well as The delayed signal is output through the output; as well as A charge / discharge switch, coupled in parallel with the charging capacitor and having a control input coupled to the output of the delay element, is configured to operate between an on state and a non-on state based on the delay signal.

16. The controller of claim 13, comprising: A monostable element having an input coupled to a second input, and the monostable element being configured as follows: Receive the signal; Based on the signal detection, the transition between the first state and the second state is detected; In response to detecting a transition between the first state and the second state, a switching signal with an active state is generated; and the switching signal is output through the output of the monostable element.

17. The controller of claim 16, comprising: A charge transfer switch having an on terminal coupled between the charging capacitor and the sustaining capacitor, and a control input coupled to the output of a monostable element, the charge transfer switch being configured to switch to an on state in response to a switch signal having an active state, so as to transfer charge from the charging capacitor to the sustaining capacitor.

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