An integrated biopotential chopper amplifier with enhanced input impedance

Abstract

An integrated biopotential chopper amplifier with improved input impedance provided by the present invention reduces the size of the input pair transistors of the fully differential differential amplifier located between the chopper switches and the input capacitors, so as to reduce the equivalent input capacitance. Different from the traditional equivalent input capacitance which is mainly determined by the input capacitance, the equivalent input capacitance of the present invention is determined by the gate parasitic capacitance of the input pair transistors of the DDA structure. Therefore, the equivalent input capacitance can be reduced exponentially to the fF level, thereby greatly increasing the equivalent input impedance of the amplifier.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and particularly relates to an integrated biopotential chopper amplifier with improved input impedance. Background Art

[0002] The biopotential analog front-end amplification circuit is required to have two main characteristics: low noise and anti-interference. Therefore, the chopping technique is often used to reduce the noise and offset of the preamplifier. However, the use of the chopping technique brings the problem of decreased input impedance.

[0003] Reference Figure 1 , Figure 1 is the implementation method of the biopotential analog front-end amplification circuit in the prior art. In Figure 1 , the differential voltage signal is first modulated to a high frequency by the chopper switch (12), and then enters the two-stage amplification circuit (14) in the form of capacitive coupling through the input capacitor (13); the two-stage amplification circuit (14) amplifies the differential voltage signal output by the input capacitor (13) with low noise, and the chopper switch inside it demodulates the modulated high-frequency signal back to the fundamental frequency; the negative feedback unit (16) ensures the stability of the negative feedback, and performs chopping modulation on the differential voltage signal fed back from the output end of the two-stage amplification circuit (14), and combines with the two-stage amplification circuit (14) to form a closed-loop structure of the low-noise amplifier, where C11 = C12, C15 = C16, and the closed-loop gain is Av = C11 / C15.

[0004] The switch structure introduced by the chopping technique will form a switched-capacitor structure with the capacitors C11 and C12 in the input capacitor (13). During the alternating conduction of the chopper switch, the differential input signal of the bioelectrode will charge and discharge the capacitors C11 and C12 in the input capacitor (13), generating a small-signal current, which reduces the input impedance of the low-noise amplifier. Therefore, the AC input impedance of the biopotential amplifier using the chopping technique is usually only on the order of dozens of MΩ. Assuming the chopping frequency is fclk and the parasitic capacitance introduced by the chopper switch is Cch, its input impedance expression is Zin = 1 / [2(C11 + Cch)fclk].

[0005] To increase the input impedance, from the perspective of the input impedance expression, the clock frequency can be reduced, a smaller input capacitance can be used, or the input capacitance can be pre-charged. However, in the application of multi-channel bio-signal acquisition, the equivalent frequency of the chopping frequency on each channel cannot be too small, and the minimum equivalent frequency needs to be greater than the Nyquist frequency, so reducing the clock frequency has a poor effect. Pre-charging usually has a pre-charge buffer and a positive feedback path. However, the pre-charge buffer brings additional noise, mismatch, power consumption, and complexity. There is a matching problem between the positive feedback capacitance and the input capacitance in the positive feedback path. At the same time, the positive feedback will also affect the stability of the loop. If the input capacitance is directly reduced, the amplification factor accuracy of the amplifier circuit will be affected. Summary of the Invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides an integrated bio-signal chopping amplifier with improved input impedance. The technical problems to be solved by the present invention are achieved through the following technical solutions:

[0007] An integrated bio-signal chopping amplifier with improved input impedance provided by the present invention includes: a differential input terminal 21, an input impedance boosting chopping switch 22, an input capacitance 23, a two-stage amplifier circuit 24, a differential output terminal 25, and a negative feedback unit 26; the differential input terminal 21, the input impedance boosting chopping switch 22, the input capacitance 23, the two-stage amplifier circuit 24, and the differential output terminal 25 are connected in sequence, and the negative feedback unit 26 is connected across the input and output terminals of the two-stage amplifier circuit 24;

[0008] The input impedance boosting chopping switch 22 reduces the equivalent input capacitance by reducing the size of its input pair transistors, thereby increasing the equivalent input impedance of the amplifier; it is used to perform the first chopping modulation on the differential input signal input at the differential input terminal 21.

[0009] The input capacitance 23 and the negative feedback unit 26 form a closed-loop negative feedback structure, which is used to isolate the input DC voltage of the differential input signal and transmit the differential AC voltage of the differential input signal.

[0010] The two-stage amplifier circuit 24 is used to perform low-noise amplification on the differential AC voltage transmitted by the input capacitance 22 and demodulate the amplified differential AC voltage.

[0011] The differential output terminal 25 is used to differentially output the differential AC voltage amplified and demodulated by the two-stage amplifier circuit 24.

[0012] The negative feedback unit 26 is used to perform chopping modulation on the differential signal fed back from the differential output terminal 25 of the two-stage amplifier circuit 24 and form a closed-loop negative feedback structure in combination with the input capacitance 23.

[0013] Optionally, the input impedance boosting chopper switch 22 includes a chopper switch 221 and a fully differential operational amplifier 222;

[0014] Among them, the first input port 1 and the second input port 2 of the chopper switch 221 are connected to the differential input terminal 21, and the third output port 3 and the fourth output port 4 of the chopper switch 221 are respectively connected to the fifth input port 5 and the sixth input port 6 of the fully differential operational amplifier 222;

[0015] The chopper switch 221 is used to perform chopper modulation on the differential input signal;

[0016] The ninth output port 9 and the tenth output port 10 of the fully differential operational amplifier 222 are respectively connected to the seventh input port 7 and the eighth input port 8 of the fully differential operational amplifier 222, and the ninth output port 9 and the tenth output port 10 of the fully differential operational amplifier 222 are connected to the input capacitor 23;

[0017] The fully differential operational amplifier 222 serves as a buffer stage to increase the input impedance of the integrated biopotential chopper amplifier.

[0018] Optionally, the chopper switch 221 includes a first switching transistor S1, a second switching transistor S2, a third switching transistor S3, and a fourth switching transistor S4.

[0019] Among them, the input terminal of the first switching transistor S1 is connected to the input terminal of the second switching transistor S2, the input terminal of the third switching transistor S3 is connected to the input terminal of the fourth switching transistor S4, the output terminal of the first switching transistor S1 is connected to the output terminal of the third switching transistor S3, the output terminal of the second switching transistor S2 is connected to the output terminal of the fourth switching transistor S4, the low-level effective terminal of the first switching transistor S1 is connected to the first chopping clock CLKP, the high-level effective terminal of the first switching transistor S1 is connected to the second chopping clock CLKN, the low-level effective terminal of the second switching transistor S2 is connected to the second chopping clock CLKN, the high-level effective terminal of the second switching transistor S2 is connected to the first chopping clock CLKP, the low-level effective terminal of the third switching transistor S3 is connected to the second chopping clock CLKN, the high-level effective terminal of the third switching transistor S3 is connected to the first chopping clock CLKP, the low-level effective terminal of the fourth switching transistor S4 is connected to the first chopping clock CLKP, and the high-level effective terminal of the fourth switching transistor S4 is connected to the second chopping clock CLKN;

[0020] The first input port 1 of the chopper switch 221 is connected to the input terminals of the first switching transistor S1 and the second switching transistor S2, the second input port 2 of the chopper switch 221 is connected to the input terminals of the third switching transistor S3 and the fourth switching transistor S4, the third output port 3 of the chopper switch 221 is connected to the output terminals of the first switching transistor S1 and the third switching transistor S3, and the fourth output port 4 of the chopper switch 221 is connected to the output terminals of the second switching transistor S2 and the fourth switching transistor S4.

[0021] Optionally, the fully differential amplifier 222 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first Miller capacitor C51, and a second Miller capacitor C52.

[0022] Among them, the gate of the first NMOS transistor MN1 is the fifth input port 5 of the fully differential amplifier 222. The source of the first NMOS transistor MN1 is connected to the drain of the fifth NMOS transistor MN5 and the source of the sixth NMOS transistor MN6. The drain of the first NMOS transistor MN1 is connected to the drain of the third NMOS transistor MN3, the drain of the second PMOS transistor MP2, the gate of the fourth PMOS transistor MP4, and the input terminal of the second Miller capacitor C52. The gate of the second NMOS transistor MN2 is the sixth input port 6 of the fully differential amplifier 222. The drain of the second NMOS transistor MN2 is connected to the drain of the fourth NMOS transistor MN4, the drain of the first PMOS transistor MP1, the gate of the third PMOS transistor MP3, and the input terminal of the first Miller capacitor C51. The gate of the third NMOS transistor MN3 is the seventh input port 7 of the fully differential amplifier 222, the drain of the third PMOS transistor MP3, the drain of the seventh NMOS transistor MN7, and the output terminal of the first Miller capacitor C51. The source of the third NMOS transistor MN3 is connected to the drain of the sixth NMOS transistor MN6 and the source of the fourth NMOS transistor MN4. The gate of the fourth NMOS transistor MN4 is the eighth input port 8 of the fully differential amplifier 222, the drain of the fourth PMOS transistor MP4, the drain of the eighth NMOS transistor MN8, and the output terminal of the second Miller capacitor C52. The gate of the fifth NMOS transistor MN5 is connected to the first bias voltage VBIA1. The source of the fifth NMOS transistor MN5 is connected to the ground potential. The gate of the sixth NMOS transistor MN6 is connected to the first bias voltage VBIA1. The source of the sixth NMOS transistor MN6 is connected to the ground potential. The gate of the seventh NMOS transistor MN7 is connected to the second bias voltage VBIA2. The source of the seventh NMOS transistor MN7 is connected to the ground potential. The gate of the eighth NMOS transistor MN8 is connected to the second bias voltage VBIA2. The source of the eighth NMOS transistor MN8 is connected to the ground potential. The gate of the first PMOS transistor MP1 is connected to the common-mode feedback voltage VCMFB and the gate of the second PMOS transistor MP2. The source of the first PMOS transistor MP1 is connected to the power supply potential VDD. The source of the second PMOS transistor MP2 is connected to the power supply potential VDD. The source of the third PMOS transistor MP3 is connected to the power supply potential VDD. The source of the fourth PMOS transistor MP4 is connected to the power supply potential VDD.

[0023] Optionally, the two-stage amplifier circuit 24 includes a first chopper module CS61, a second chopper module CS62, a third Miller capacitor C23, a fourth Miller capacitor C24, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, and a fourteenth NMOS transistor MN14; the eighth PMOS transistor MP8, the ninth PMOS transistor MP9;

[0024] Among them, the gates of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 are connected to the third bias voltage VB1; the drain of the fifth PMOS transistor MP5 is connected to the gate of the eighth PMOS transistor MP8 as the input signal terminal Vin+, and the drains of the eighth PMOS transistor MP8 and the ninth NMOS transistor MN9 are connected to the input terminal of the first chopper module CS61. The output terminal of the first chopper module CS61 is respectively connected to the source of the eleventh NMOS transistor MN11, the source of the twelfth NMOS transistor MN12, one end of the third Miller capacitor C23, and one end of the fourth Miller capacitor C24; the drains of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are connected to the input terminal of the second chopper module CS62, and the output terminal of the second chopper module CS62 is respectively connected to the sources of the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11; the drain of the tenth PMOS transistor MP10 is connected to the drain of the eleventh NMOS transistor MN11 and the gate of the thirteenth PMOS transistor MP13; the drain of the eleventh PMOS transistor MP11 is connected to the drain of the twelfth NMOS transistor MN12 and the gate of the twelfth PMOS transistor MP12; the other end of the third Miller capacitor C23 is connected to the drain of the twelfth PMOS transistor MP12 and the drain of the thirteenth NMOS transistor MN13 as the differential negative output terminal of the differential output terminal 25; the other end of the fourth Miller capacitor C24 is connected to the drain of the thirteenth PMOS transistor MP13 and the drain of the fourteenth NMOS transistor MN14 as the differential positive output terminal of the differential output terminal 25; the sources of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the twelfth PMOS transistor MP12, and the thirteenth PMOS transistor MP13 are connected to the power supply potential VDD; the sources of the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the thirteenth NMOS transistor MN13, and the fourteenth NMOS transistor MN14 are connected to the ground potential; the gates of the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 are connected to the first common-mode voltage VCMF1, and the gates of the thirteenth NMOS transistor MN13 and the fourteenth NMOS transistor MN14 are connected to the second common-mode voltage VCMF2.

[0025] Optionally, the implementation manners of the first chopper module CS61 and the second chopper module CS62 are the same as the implementation manner of the chopper switch 221 in the input impedance boosting chopper switch 22.

[0026] Optionally, the negative feedback unit 26 includes a chopper switch and two capacitors. Each input terminal of the chopper switch is connected to a capacitor, and the implementation manner of the chopper switch is the same as the implementation manner of the chopper switch 221 in the input impedance boosting chopper switch 22.

[0027] An integrated biopotential chopper amplifier with improved input impedance provided by the present invention reduces the size of the input pair transistors of the fully differential differential amplifier located between the chopper switch and the input capacitor, so as to reduce the equivalent input capacitance. Different from the traditional equivalent input capacitance mainly determined by the input capacitor, the equivalent input capacitance of the present invention is determined by the gate parasitic capacitance of the input pair transistors of the DDA structure. Therefore, the equivalent input capacitance can be reduced exponentially to the fF level, thereby greatly increasing the equivalent input impedance of the amplifier.

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic circuit diagram of a biopotential analog front-end amplifier circuit in the prior art;

[0030] Figure 2 is a schematic circuit diagram of an integrated biopotential chopper amplifier with improved input impedance according to the present invention;

[0031] Figure 3 is a schematic circuit diagram of the input impedance boosting chopper switch according to the present invention;

[0032] Figure 4 is the circuit schematic diagram and signal diagram of the chopper switch in the present invention;

[0033] Figure 5 is the circuit schematic diagram of the fully differential differential amplifier in the present invention;

[0034] Figure 6 is the circuit schematic diagram of the two-stage amplifier circuit in the embodiment of the present invention;

[0035] Figure 7 is the circuit schematic diagram of the common-mode feedback circuit provided by the embodiment of the present invention;

[0036] Figure 8 is the input impedance boosting simulation result diagram provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] The present invention will be further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0038] As Figure 2As shown in the figure, an integrated biopotential chopper amplifier with improved input impedance provided by the present invention includes: a differential input terminal 21, an input impedance boosting chopper switch 22, an input capacitor 23, a two-stage amplifier circuit 24, a differential output terminal 25, and a negative feedback unit 26; the differential input terminal 21, the input impedance boosting chopper switch 22, the input capacitor 23, the two-stage amplifier circuit 24, and the differential output terminal 25 are connected in sequence, and the negative feedback unit 26 is connected across the input and output terminals of the two-stage amplifier circuit 24;

[0039] The input impedance boosting chopper switch 22 reduces the size of its input pair transistors to reduce the equivalent input capacitance and improve the equivalent input impedance of the amplifier; it is used to perform the first chopping modulation on the differential input signal input at the differential input terminal 21.

[0040] It should be noted that: by reducing the size of the input pair transistors of the fully differential differential amplifier 222, the input impedance boosting chopper switch 22 can reduce the equivalent input capacitance and improve the equivalent input impedance of the amplifier. Therefore, it has the advantage of high input impedance and is also used to perform the first chopping modulation on the differential input signal.

[0041] The input capacitor 23 and the negative feedback unit 26 form a closed-loop negative feedback structure, which is used to isolate the input DC voltage of the differential input signal and transmit the differential AC voltage of the differential input signal.

[0042] The two-stage amplifier circuit 24 is used to perform low-noise amplification on the differential AC voltage transmitted by the input capacitor 22 and demodulate the amplified differential AC voltage.

[0043] The differential output terminal 25 is used to differentially output the differential AC voltage amplified and demodulated by the two-stage amplifier circuit 24.

[0044] The negative feedback unit 26 is used to perform chopping modulation on the differential signal fed back from the differential output terminal 25 of the two-stage amplifier circuit 24 and form a closed-loop negative feedback structure with the input capacitor 23.

[0045] For the integrated biopotential chopper amplifier with improved input impedance provided by the present invention, by reducing the size of the input pair transistors of the fully differential differential amplifier located between the chopper switch and the input capacitor, the equivalent input capacitance is reduced. Different from the traditional case where the equivalent input capacitance is mainly determined by the input capacitor, the equivalent input capacitance of the present invention is determined by the gate parasitic capacitance of the input pair transistors of the DDA structure. Therefore, the equivalent input capacitance can be reduced by several times to the fF level, thereby greatly increasing the equivalent input impedance of the amplifier.

[0046] As Figure 3 shown, the input impedance boosting chopper switch 22 includes a chopper switch 221 and a fully differential differential amplifier 222;

[0047] Among them, the first input port 1 and the second input port 2 of the chopper switch 221 are connected to the differential input terminal 21, and the third output port 3 and the fourth output port 4 of the chopper switch 221 are respectively connected to the fifth input port 5 and the sixth input port 6 of the fully differential differential amplifier 222;

[0048] The chopper switch 221 is used to perform chopper modulation on the differential input signal;

[0049] The ninth output port 9 and the tenth output port 10 of the fully differential differential amplifier 222 are respectively connected to the seventh input port 7 and the eighth input port 8 of the fully differential differential amplifier 222, and the ninth output port 9 and the tenth output port 10 of the fully differential differential amplifier 222 are connected to the input capacitor 23;

[0050] The fully differential differential amplifier 222 serves as a buffer stage to increase the input impedance of the integrated biopotential chopper amplifier.

[0051] It should be noted that: by combining the chopper switch and the fully differential differential amplifier, the size of the input pair transistors of the fully differential differential amplifier located between the chopper switch and the input capacitor is reduced, thereby reducing the equivalent input capacitance. The equivalent input impedance expression at this time is: Zin = 1 / [2(Ceq fclk)], where Ceq = Cg + Cch, Cg is the gate parasitic capacitance of the input pair transistors of the fully differential differential amplifier, and Cch is the parasitic capacitance introduced by the chopper switch. Since the fully differential differential amplifier of the present invention is placed within the chopper loop, its 1 / f noise and offset will also be chopped and modulated to high frequencies, so it will not affect the amplification of the biopotential front-end signal; for the thermal noise of the fully differential differential amplifier, the bias current of the first stage can be appropriately increased to reduce the equivalent input noise. Therefore, a high input impedance and a low input-referred noise are achieved, and thus it can be applied to the amplification system of the dry electrode biopotential front-end signal.

[0052] Reference Figure 4 , the chopper switch 221 includes a first switching transistor S1, a second switching transistor S2, a third switching transistor S3 and a fourth switching transistor S4,

[0053] Among them, the input end of the first switching tube S1 is connected to the input end of the second switching tube S2, the input end of the third switching tube S3 is connected to the input end of the fourth switching tube S4, the output end of the first switching tube S1 is connected to the output end of the third switching tube S3, the output end of the second switching tube S2 is connected to the output end of the fourth switching tube S4, the low-level effective end of the first switching tube S1 is connected to the first chopping clock CLKP, the high-level effective end of the first switching tube S1 is connected to the second chopping clock CLKN, the low-level effective end of the second switching tube S2 is connected to the second chopping clock CLKN, the high-level effective end of the second switching tube S2 is connected to the first chopping clock CLKP, the low-level effective end of the third switching tube S3 is connected to the second chopping clock CLKN, the high-level effective end of the third switching tube S3 is connected to the first chopping clock CLKP, the low-level effective end of the fourth switching tube S4 is connected to the first chopping clock CLKP, and the high-level effective end of the fourth switching tube S4 is connected to the second chopping clock CLKN;

[0054] The first input port 1 of the chopping switch 221 is connected to the input ends of the first switching tube S1 and the second switching tube S2, the second input port 2 of the chopping switch 221 is connected to the input ends of the third switching tube S3 and the fourth switching tube S4, the third output port 3 of the chopping switch 221 is connected to the output ends of the first switching tube S1 and the third switching tube S3, and the fourth output port 4 of the chopping switch 221 is connected to the output ends of the second switching tube S2 and the fourth switching tube S4.

[0055] Reference Figure 5 , the fully differential differential amplifier 222 includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first Miller capacitor C51 and a second Miller capacitor C52,

[0056] Among them, the gate of the first NMOS transistor MN1 is the fifth input port 5 of the fully differential differential amplifier 222. The source of the first NMOS transistor MN1 is connected to the drain of the fifth NMOS transistor MN5 and the source of the sixth NMOS transistor MN6. The drain of the first NMOS transistor MN1 is connected to the drain of the third NMOS transistor MN3, the drain of the second PMOS transistor MP2, the gate of the fourth PMOS transistor MP4, and the input end of the second Miller capacitor C52. The gate of the second NMOS transistor MN2 is the sixth input port 6 of the fully differential differential amplifier 222. The drain of the second NMOS transistor MN2 is connected to the drain of the fourth NMOS transistor MN4, the drain of the first PMOS transistor MP1, the gate of the third PMOS transistor MP3, and the input end of the first Miller capacitor C51. The gate of the third NMOS transistor MN3 is the seventh input port 7 of the fully differential differential amplifier 222, the drain of the third PMOS transistor MP3, the drain of the seventh NMOS transistor MN7, and the output end of the first Miller capacitor C51. The source of the third NMOS transistor MN3 is connected to the drain of the sixth NMOS transistor MN6 and the source of the fourth NMOS transistor MN4. The gate of the fourth NMOS transistor MN4 is the eighth input port 8 of the fully differential differential amplifier 222, the drain of the fourth PMOS transistor MP4, the drain of the eighth NMOS transistor MN8, and the output end of the second Miller capacitor C52. The gate of the fifth NMOS transistor MN5 is connected to the first bias voltage VBIA1. The source of the fifth NMOS transistor MN5 is connected to the ground potential. The gate of the sixth NMOS transistor MN6 is connected to the first bias voltage VBIA1. The source of the sixth NMOS transistor MN6 is connected to the ground potential. The gate of the seventh NMOS transistor MN7 is connected to the second bias voltage VBIA2. The source of the seventh NMOS transistor MN7 is connected to the ground potential. The gate of the eighth NMOS transistor MN8 is connected to the second bias voltage VBIA2. The source of the eighth NMOS transistor MN8 is connected to the ground potential. The gate of the first PMOS transistor MP1 is connected to the common-mode feedback voltage VCMFB and the gate of the second PMOS transistor MP2. The source of the first PMOS transistor MP1 is connected to the power supply potential VDD. The source of the second PMOS transistor MP2 is connected to the power supply potential VDD. The source of the third PMOS transistor MP3 is connected to the power supply potential VDD. The source of the fourth PMOS transistor MP4 is connected to the power supply potential VDD.

[0057] Reference Figure 6, the two-stage amplifier circuit 24 includes a first chopper module CS61, a second chopper module CS62, a third Miller capacitor C23, a fourth Miller capacitor C24, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, and a fourteenth NMOS transistor MN14; the eighth PMOS transistor MP8, the ninth PMOS transistor MP9;

[0058] Among them, the gates of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, and the seventh PMOS transistor MP7 are connected to the third bias voltage VB1; the drain of the fifth PMOS transistor MP5 is connected to the gate of the eighth PMOS transistor MP8 as the input signal terminal Vin+, and the drains of the eighth PMOS transistor MP8 and the ninth NMOS transistor MN9 are connected to the input terminal of the first chopper module CS61. The output terminal of the first chopper module CS61 is respectively connected to the source of the eleventh NMOS transistor MN11, the source of the twelfth NMOS transistor MN12, one end of the third Miller capacitor C23, and one end of the fourth Miller capacitor C24; the drains of the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are connected to the input terminal of the second chopper module CS62, and the output terminal of the second chopper module CS62 is respectively connected to the sources of the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11; the drain of the tenth PMOS transistor MP10 is connected to the drain of the eleventh NMOS transistor MN11 and the gate of the thirteenth PMOS transistor MP13; the drain of the eleventh PMOS transistor MP11 is connected to the drain of the twelfth NMOS transistor MN12 and the gate of the twelfth PMOS transistor MP12; the other end of the third Miller capacitor C23 is connected to the drain of the twelfth PMOS transistor MP12 and the drain of the thirteenth NMOS transistor MN13 as the differential negative output terminal of the differential output terminal 25; the other end of the fourth Miller capacitor C24 is connected to the drain of the thirteenth PMOS transistor MP13 and the drain of the fourteenth NMOS transistor MN14 as the differential positive output terminal of the differential output terminal 25; the sources of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventh PMOS transistor MP7, the twelfth PMOS transistor MP12, and the thirteenth PMOS transistor MP13 are connected to the power supply potential VDD; the sources of the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the thirteenth NMOS transistor MN13, and the fourteenth NMOS transistor MN14 are connected to the ground potential; the gates of the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 are connected to the first common-mode voltage VCMF1, and the gates of the thirteenth NMOS transistor MN13 and the fourteenth NMOS transistor MN14 are connected to the second common-mode voltage VCMF2.

[0059] Reference Figure 7 , Figure 7 is a schematic structural diagram of a common-mode feedback circuit. Figure 7 Provides a common-mode voltage for the two-stage amplifier circuit 24, where VCMF1 is the first common-mode voltage and VCMF2 is the second common-mode voltage.

[0060] Among them, the implementation manners of the first chopper module CS61 and the second chopper module CS62 are the same as the implementation manner of the chopper switch 221 in the input impedance boosting chopper switch 22.

[0061] Reference Figure 2, the negative feedback unit 26 includes a chopper switch and two capacitors. Each input terminal of the chopper switch is connected to a capacitor, and the implementation of the chopper switch is the same as that of the chopper switch 221 in the input impedance boosting chopper switch 22.

[0062] Based on the above embodiments, without affecting the amplification factor accuracy of the amplifier circuit, by reducing the size of the input pair transistors of the fully differential differential amplifier, the equivalent input capacitance of the amplifier circuit is reduced, and thus the equivalent input impedance of the amplifier circuit is increased.

[0063] Please refer to Figure 8 , Figure 8 is the input impedance boosting simulation result diagram provided by the embodiment of the present invention. While simulating the AC characteristics, a 200M internal resistance is added to the simulated signal source to observe the change of the AC characteristics.

[0064] By introducing an internal resistance on the simulated signal source, a small-signal series voltage division relationship is formed between the equivalent internal resistance of the signal source and the input impedance of the analog front-end amplifier. Let the internal resistance of the signal source be Rs and the equivalent input impedance of the analog front-end amplifier be Rin, then the total gain Avt of the entire analog front-end amplifier can be expressed as:

[0065]

[0066] where Av is the closed-loop gain of the amplifier circuit. By introducing the internal resistance of the signal source and simulating the AC characteristics before and after introducing the internal resistance, the gain difference ΔA before and after introducing the internal resistance can be obtained, then there is:

[0067]

[0068] The internal resistance Rs used in the simulation is 200MΩ, from Figure 8 it can be obtained that the gain without introducing the internal resistance is 33.6099dB, the gain after introducing the internal resistance is 32.7107dB, and the change amount ΔA of the gain is 0.8992dB. The input impedance of the amplifier circuit can be calculated to be about 1.6GΩ, and the input impedance is increased, meeting the requirement of the high input impedance of the biological signal analog front-end amplifier circuit.

[0069] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. An integrated biopotential chopper amplifier with improved input impedance, characterized in that, Comprising: A differential input terminal (21), an input impedance boosting chopper switch (22), an input capacitor (23), a two-stage amplifier circuit (24), a differential output terminal (25), and a negative feedback unit (26); the differential input terminal (21), the input impedance boosting chopper switch (22), the input capacitor (23), the two-stage amplifier circuit (24), and the differential output terminal (25) are connected in sequence, and the negative feedback unit (26) is connected across the input and output terminals of the two-stage amplifier circuit (24); The input impedance boosting chopper switch (22) reduces the size of its own input pair of transistors to reduce the equivalent input capacitance and increase the equivalent input impedance of the amplifier; it is used to perform the first chopper modulation on the differential input signal input at the differential input terminal (21). The input capacitor (23) and the negative feedback unit (26) form a closed-loop negative feedback structure, which is used to isolate the input DC voltage of the differential input signal and transmit the differential AC voltage of the differential input signal. The two-stage amplifier circuit (24) is used to perform low-noise amplification on the differential AC voltage transmitted by the input capacitor (22) and demodulate the amplified differential AC voltage. The differential output terminal (25) is used to differentially output the differential AC voltage amplified and demodulated by the two-stage amplifier circuit (24). The negative feedback unit (26) is used to perform chopper modulation on the differential signal fed back from the differential output terminal (25) of the two-stage amplifier circuit (24) and form a closed-loop negative feedback structure with the input capacitor (23). The input impedance boosting chopper switch (22) includes a chopper switch (221) and a fully differential differential amplifier (222); Among them, the first input port (1) and the second input port (2) of the chopper switch (221) are connected to the differential input terminal (21), and the third output port (3) and the fourth output port (4) of the chopper switch (221) are respectively connected to the fifth input port (5) and the sixth input port (6) of the fully differential differential amplifier (222); The chopper switch (221) is used to perform chopper modulation on the differential input signal. The ninth output port (9) and the tenth output port (10) of the fully differential differential amplifier (222) are respectively connected to the seventh input port (7) and the eighth input port (8) of the fully differential differential amplifier (222), and the ninth output port (9) and the tenth output port (10) of the fully differential differential amplifier (222) are connected to the input capacitor (23); The fully differential differential amplifier (222) serves as a buffer stage to increase the input impedance of the integrated bio-signal chopper amplifier. The chopper switch (221) includes a first switch transistor (S1), a second switch transistor (S2), a third switch transistor (S3), and a fourth switch transistor (S4). Among them, the input terminal of the first switching transistor (S1) is connected to the input terminal of the second switching transistor (S2), the input terminal of the third switching transistor (S3) is connected to the input terminal of the fourth switching transistor (S4), the output terminal of the first switching transistor (S1) is connected to the output terminal of the third switching transistor (S3), the output terminal of the second switching transistor (S2) is connected to the output terminal of the fourth switching transistor (S4), the low-level effective terminal of the first switching transistor (S1) is connected to the first chopping clock (CLKP), the high-level effective terminal of the first switching transistor (S1) is connected to the second chopping clock (CLKN), the low-level effective terminal of the second switching transistor (S2) is connected to the second chopping clock (CLKN), the high-level effective terminal of the second switching transistor (S2) is connected to the first chopping clock (CLKP), the low-level effective terminal of the third switching transistor (S3) is connected to the second chopping clock (CLKN), the high-level effective terminal of the third switching transistor (S3) is connected to the first chopping clock (CLKP), the low-level effective terminal of the fourth switching transistor (S4) is connected to the first chopping clock (CLKP), and the high-level effective terminal of the fourth switching transistor (S4) is connected to the second chopping clock (CLKN); The first input port (1) of the chopping switch (221) is connected to the input terminals of the first switching transistor (S1) and the second switching transistor (S2), the second input port (2) of the chopping switch (221) is connected to the input terminals of the third switching transistor (S3) and the fourth switching transistor (S4), the third output port (3) of the chopping switch (221) is connected to the output terminals of the first switching transistor (S1) and the third switching transistor (S3), and the fourth output port (4) of the chopping switch (221) is connected to the output terminals of the second switching transistor (S2) and the fourth switching transistor (S4).

2. The integrated biopotential chopper amplifier with enhanced input impedance according to claim 1, wherein The fully differential differential amplifier (222) includes a first NMOS transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), a fourth NMOS transistor (MN4), a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8), a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), a fourth PMOS transistor (MP4), a first Miller capacitor (C51), and a second Miller capacitor (C52). Among them, the gate of the first NMOS transistor (MN1) is the fifth input port (5) of the fully differential differential amplifier (222). The source of the first NMOS transistor (MN1) is connected to the drain of the fifth NMOS transistor (MN5) and the source of the sixth NMOS transistor (MN6). The drain of the first NMOS transistor (MN1) is connected to the drain of the third NMOS transistor (MN3), the drain of the second PMOS transistor (MP2), the gate of the fourth PMOS transistor (MP4), and the input terminal of the second Miller capacitor (C52). The gate of the second NMOS transistor (MN2) is the sixth input port (6) of the fully differential differential amplifier (222). The drain of the second NMOS transistor (MN2) is connected to the drain of the fourth NMOS transistor (MN4), the drain of the first PMOS transistor (MP1), the gate of the third PMOS transistor (MP3), and the input terminal of the first Miller capacitor (C51). The gate of the third NMOS transistor (MN3) is the seventh input port (7) of the fully differential differential amplifier (222), the drain of the third PMOS transistor (MP3), the drain of the seventh NMOS transistor (MN7), and the output terminal of the first Miller capacitor (C51). The source of the third NMOS transistor (MN3) is connected to the drain of the sixth NMOS transistor (MN6) and the source of the fourth NMOS transistor (MN4). The gate of the fourth NMOS transistor (MN4) is the eighth input port (8) of the fully differential differential amplifier (222), the drain of the fourth PMOS transistor (MP4), the drain of the eighth NMOS transistor (MN8), and the output terminal of the second Miller capacitor (C52). The gate of the fifth NMOS transistor (MN5) is connected to the first bias voltage (VBIA1). The source of the fifth NMOS transistor (MN5) is connected to the ground potential. The gate of the sixth NMOS transistor (MN6) is connected to the first bias voltage (VBIA1). The source of the sixth NMOS transistor (MN6) is connected to the ground potential. The gate of the seventh NMOS transistor (MN7) is connected to the second bias voltage (VBIA2). The source of the seventh NMOS transistor (MN7) is connected to the ground potential. The gate of the eighth NMOS transistor (MN8) is connected to the second bias voltage (VBIA2). The source of the eighth NMOS transistor (MN8) is connected to the ground potential. The gate of the first PMOS transistor (MP1) is connected to the common-mode feedback voltage (VCMFB) and the gate of the second PMOS transistor (MP2). The source of the first PMOS transistor (MP1) is connected to the power supply potential VDD. The source of the second PMOS transistor (MP2) is connected to the power supply potential VDD. The source of the third PMOS transistor (MP3) is connected to the power supply potential VDD. The source of the fourth PMOS transistor (MP4) is connected to the power supply potential VDD.

3. The integrated biopotential chopper amplifier with improved input impedance according to claim 1, wherein The two-stage amplifier circuit (24) includes a first chopper module (CS61), a second chopper module (CS62), a third Miller capacitor (C23), a fourth Miller capacitor (C24), a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6), a seventh PMOS transistor (MP7), an eighth PMOS transistor (MP8), a ninth PMOS transistor (MP9), a tenth PMOS transistor (MP10), an eleventh PMOS transistor (MP11), a twelfth PMOS transistor (MP12), a thirteenth PMOS transistor (MP13), a ninth NMOS transistor (MN9), a tenth NMOS transistor (MN10), an eleventh NMOS transistor (MN11), a twelfth NMOS transistor (MN12), a thirteenth NMOS transistor (MN13), and a fourteenth NMOS transistor (MN14); an eighth PMOS transistor (MP8), a ninth PMOS transistor (MP9); Among them, the gates of the fifth PMOS transistor (MP5), the sixth PMOS transistor (MP6), and the seventh PMOS transistor (MP7) are connected to the third bias voltage (VB1); the drain of the fifth PMOS transistor (MP5) is connected to the gate of the eighth PMOS transistor (MP8) as the input signal terminal Vin+, the drains of the eighth PMOS transistor (MP8) and the ninth NMOS transistor (MN9) are connected to the input terminal of the first chopper module (CS61), and the output terminal of the first chopper module (CS61) is respectively connected to the source of the eleventh NMOS transistor (MN11), the source of the twelfth NMOS transistor (MN12), one end of the third Miller capacitor (C23), and one end of the fourth Miller capacitor (C24); the drains of the sixth PMOS transistor (MP6) and the seventh PMOS transistor (MP7) are connected to the input terminal of the second chopper module (CS62), and the output terminal of the second chopper module (CS62) is respectively connected to the sources of the tenth PMOS transistor (MP10) and the eleventh PMOS transistor (MP11); the drain of the tenth PMOS transistor (MP10) is connected to the drain of the eleventh NMOS transistor (MN11) and the gate of the thirteenth PMOS transistor (MP13); the drain of the eleventh PMOS transistor (MP11) is connected to the drain of the twelfth NMOS transistor (MN12) and the gate of the twelfth PMOS transistor (MP12); the other end of the third Miller capacitor (C23) is connected to the drain of the twelfth PMOS transistor (MP12) and the drain of the thirteenth NMOS transistor (MN13) as the differential negative output terminal of the differential output terminal (25); the other end of the fourth Miller capacitor (C24) is connected to the drain of the thirteenth PMOS transistor (MP13) and the drain of the fourteenth NMOS transistor (MN14) as the differential positive output terminal of the differential output terminal (25); the sources of the fifth PMOS transistor (MP5), the sixth PMOS transistor (MP6), the seventh PMOS transistor (MP7), the twelfth PMOS transistor (MP12), and the thirteenth PMOS transistor (MP13) are connected to the power supply potential VDD; the sources of the ninth NMOS transistor (MN9), the tenth NMOS transistor (MN10), the thirteenth NMOS transistor (MN13), and the fourteenth NMOS transistor (MN14) are connected to the ground potential; the gates of the ninth NMOS transistor (MN9) and the tenth NMOS transistor (MN10) are connected to the first common-mode voltage (VCMF1), and the gates of the thirteenth NMOS transistor (MN13) and the fourteenth NMOS transistor (MN14) are connected to the second common-mode voltage (VCMF2).

4. The integrated biopotential chopper amplifier with improved input impedance according to claim 3, characterized in that, The implementation manners of the first chopper module (CS61) and the second chopper module (CS62) are the same as the implementation manner of the chopper switch (221) in the input impedance boosting chopper switch (22).

5. The integrated bio-signal chopper amplifier with improved input impedance according to claim 1, characterized in that The negative feedback unit (26) includes a chopper switch and two capacitors. Each input terminal of the chopper switch is connected to a capacitor, and the implementation manner of the chopper switch is the same as the implementation manner of the chopper switch (221) in the input impedance boosting chopper switch (22).

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