Differential signal receiver

Abstract

The application discloses a differential signal receiver, comprising a first differential difference amplifier, a second differential difference amplifier, a latch and a first inverter. The first differential difference amplifier and the second differential difference amplifier compare the voltage value of an input signal with a first threshold value and a second threshold value respectively to output a first difference signal and a second difference signal. The second threshold value is the opposite of the first threshold value. The latch has a set end for receiving the first difference signal and a reset end for receiving the second difference signal. The first inverter is used for receiving the first latch signal and outputting a first output signal. The first output signal has the same working period as the input signal.

Description

TECHNICAL FIELD

[0001] The present application relates to a differential signal receiver, and more particularly to a differential signal receiver using a differential difference amplifier (DDA) capable of improving duty cycle error of an output signal and an input signal. BACKGROUND

[0002] A differential difference amplifier is an amplifier having two differential inputs, and can be used in a differential signal receiver. The differential signal receiver can subtract a pair of differential signals to obtain an input signal. In addition, the differential difference amplifier is used to compare a voltage value of the input signal with a threshold value, and output a difference signal according to a comparison result. The input signal can be a sine wave signal having a duty cycle of 50%, but the differential difference amplifier can output a difference signal having a duty cycle other than 50% due to the threshold value and the amplitude of the input signal being close to each other. Therefore, in the case where the differential signal receiver outputs the difference signal as an output signal, the smaller the amplitude of the input signal, the greater the duty cycle error of the output signal and the input signal. SUMMARY

[0003] To overcome the drawbacks of the prior art, the present application provides a differential signal receiver including a first differential difference amplifier, a second differential difference amplifier, a latch, and a first inverter. The first differential difference amplifier is used to compare a voltage value of an input signal with a first threshold value, and output a first difference signal according to a comparison result. The second differential difference amplifier is used to compare the voltage value of the input signal with a second threshold value, and output a second difference signal according to a comparison result. The second threshold value is the opposite of the first threshold value. The latch has a set terminal for receiving the first difference signal and a reset terminal for receiving the second difference signal. When the first difference signal and the second difference signal are logic high and logic low, respectively, the latch starts to output a first latch signal having a logic low level, and when the first difference signal and the second difference signal are logic low and logic high, respectively, the latch starts to output the first latch signal having a logic high level. The first inverter is used to receive the first latch signal, and output a first output signal. The first output signal has the same duty cycle as the input signal.

[0004] For further understanding of the features and technical contents of the present application, please refer to the following detailed description of the present application and the attached drawings, however, the drawings provided are only for reference and illustration, and not intended to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 is a schematic diagram of a differential signal receiver according to an embodiment of the present application.

[0006] Figure 2 is Figure 1 a timing diagram of the differential signal receiver of DETAILED DESCRIPTION

[0007] The present application will now be described in greater detail by specific embodiments with reference to the attached drawings. The advantages and effects of the present application can be understood by those skilled in the art from the contents of the present specification. The present application can be implemented or applied by other different embodiments, and the details in the present specification can be modified and changed in various ways based on different views and applications without departing from the spirit of the present application. In addition, it is previously declared that the drawings of the present application are simple schematic illustrations and not actual size depictions. The following embodiments will further explain the related technical contents of the present application in detail, but the contents provided are not intended to limit the scope of protection of the present application.

[0008] It should be understood that although the terms "first", "second", "third" and the like can be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used herein can include any one or more combinations of the associated listed items as the case can be.

[0009] Please refer to Figure 1 and Figure 2 , Figure 1 is a schematic diagram of the differential signal receiver of the embodiment of the present application, Figure 2 is Figure 1 a timing diagram of the differential signal receiver of Figure 1 As shown in FIG. 1, the differential signal receiver 1 includes a differential difference amplifier 11, a differential difference amplifier 12, a latch 13, and an inverter 14. The differential difference amplifier 11 is configured to compare a voltage value of an input signal S1 with a first threshold TH1, and output a first difference signal D1 according to a comparison result.

[0010] Specifically, the input signal S1 is a result of subtraction of a pair of differential signals, and the pair of differential signals includes a first signal SP and a second signal SN, but the present application does not limit the specific form of the pair of differential signals. In addition, the size of the first threshold TH1 corresponds to a result of subtraction of the first signal SP from the second signal SN, but the present application also does not limit the specific value of the first threshold TH1. In the present embodiment, the first threshold TH1 is a result of subtraction of a first reference voltage V1 from a second reference voltage V2. The first reference voltage V1 can be a positive number, and the second reference voltage V2 is an opposite number of the first reference voltage V1, so the first threshold can also be a positive number, for example Figure 2 25mV (millivolt) of

[0011] In this configuration, the first differential input of the differential amplifier 11 includes a first non-inverting input terminal for receiving the first signal SP and a first inverting input terminal for receiving the second signal SN, and the second differential input of the differential amplifier 11 includes a second non-inverting input terminal for receiving the first reference voltage V1 and a second inverting input terminal for receiving the second reference voltage V2, such that the differential amplifier 11 uses the result of subtracting the second signal SN from the first signal SP as the input signal S1, and uses the result of subtracting the second reference voltage V2 from the first reference voltage V1 as the first threshold TH1.

[0012] like Figure 2 As shown, when the input signal S1 is greater than or equal to the first threshold TH1, the differential amplifier 11 outputs a first difference signal D1 with a logic high level; and when the input signal S1 is less than the first threshold TH1, the differential amplifier 11 outputs a first difference signal D1 with a logic low level. In this embodiment, Figure 2 The input signal S1 can be a sine wave signal with a duty cycle of 50%, but the differential amplifier 11 may output a first difference signal D1 with a duty cycle of less than 50% because the amplitude A of the first threshold TH1 and the input signal S1 are close. Therefore, when the differential signal receiver 1 uses the first difference signal D1 as the output signal, the smaller the amplitude A of the input signal S1, the greater the duty cycle error between the output signal and the input signal S1.

[0013] To address the aforementioned problem, the differential amplifier 12 compares the voltage value of the input signal S1 with a second threshold TH2, and outputs a second difference signal D2 based on the comparison result. In this embodiment, the second threshold TH2 is the inverse of the first threshold TH1, for example... Figure 2 The voltage is -25mV (millivolts). Therefore, the first differential input of the differential amplifier 12 includes a third non-inverting input terminal for receiving the second reference voltage V2 and a third inverting input terminal for receiving the first reference voltage V1, and the second differential input of the differential amplifier 12 includes a fourth non-inverting input terminal for receiving the first signal SP and a fourth inverting input terminal for receiving the second signal SN, such that the differential amplifier 12 uses the result of subtracting the second signal SN from the first signal SP as the input signal S1, and uses the result of subtracting the first reference voltage V1 from the second reference voltage V2 as the second threshold TH2.

[0014] like Figure 2As shown, when the input signal S1 is less than or equal to the second threshold TH2, the differential amplifier 12 outputs a second difference signal D2 at a logic high level; when the input signal S1 is greater than the second threshold TH2, the differential amplifier 12 outputs a second difference signal D2 at a logic low level. Furthermore, the latch 13 is coupled to the first differential amplifier 11 and the second differential amplifier 12, and has a setting terminal S for receiving the first difference signal D1 and a reset terminal R for receiving the second difference signal D2. Therefore, when the first difference signal D1 and the second difference signal D2 are at logic high and logic low levels respectively, the latch 13 starts outputting a first latch signal L1 at a logic low level, and when the first difference signal D1 and the second difference signal D2 are at logic low and logic high levels respectively, the latch 13 starts outputting a first latch signal L1 at a logic high level.

[0015] Therefore, latch 13 is an SR latch composed of a pair of interleaved NOR gates. That is, latch 13 may include a first NOR gate 131 and a second NOR gate 132. In this embodiment, the first NOR gate 131 has a first input terminal for receiving a first difference signal D1 and a second input terminal for receiving a second latch signal L2, and the first NOR gate 131 is used to output the first latch signal L1. Additionally, the second NOR gate 132 has a third input terminal for receiving the first latch signal L1 and a fourth input terminal for receiving the second difference signal D2, and the second NOR gate 132 is used to output the second latch signal L2.

[0016] Therefore, from Figure 1 It can be seen that the first input terminal of the first NOR gate 131 serves as the setting terminal (S) of the latch 13, and the fourth input terminal of the second NOR gate 132 serves as the reset terminal (R) of the latch 13. In this case, when the first difference signal D1 and the second difference signal D2 are at logic low and logic high levels respectively, the second NOR gate 132 starts outputting a logic low second latch signal L2, and when the first difference signal D1 and the second difference signal D2 are at logic high and logic low levels respectively, the second NOR gate 132 starts outputting a logic high second latch signal L2. Since the operating principle of the SR latch is well known to those skilled in the art, details regarding the latch 13 will not be elaborated further here.

[0017] On the other hand, the first inverter 14 is coupled to the latch 13 to receive the first latch signal L1 and output the first output signal O1. That is, the first output signal O1 is the inverted version of the first latch signal L1. Therefore, from... Figure 2It can be seen that even if the duty cycle of the first difference signal D1 and the duty cycle of the input signal S1 are quite different, by increasing the operations of the differential difference amplifier 12, the latch 13 and the first inverter 14, the present application can take the interval time between the rising edge of the first difference signal D1 and the rising edge of the second difference signal D2 as the pulse width of the new output signal (i.e. the first output signal O1). In this way, the first output signal O1 can have the same duty cycle as the input signal S1, so as to improve the duty cycle error of the output signal and the input signal S1.

[0018] Similarly, the duty cycle of the second difference signal D2 can also be quite different from the duty cycle of the input signal S1, so the differential signal receiver 1 can further include a second inverter 15. The second inverter 15 is coupled to the latch 13 to receive the second latch signal L2 and output a second output signal O2. That is, the second output signal O2 is the inverted second latch signal L2, and the present application further takes the interval time between the rising edge of the second difference signal D2 and the rising edge of the first difference signal D1 as the pulse width of another new output signal (i.e. the second output signal O2). Since the relevant details have been described as above, they will not be repeated here.

[0019] In summary, the differential signal receiver of the present application can have two differential difference amplifiers to compare the voltage value of the input signal with a first threshold value and a second threshold value respectively, so as to output a first difference signal and a second difference signal. The second threshold value is the opposite of the first threshold value. In addition, the differential signal receiver of the present application further has a latch and an inverter to take the interval time between the rising edges of the first difference signal and the second difference signal as the pulse width of the new output signal, so as to improve the duty cycle error of the output signal and the input signal.

[0020] The above provided content is only the preferred feasible embodiments of the present application, and does not limit the protection scope of the present application, so any equivalent technical changes made according to the content of the present application and the drawings are included in the protection scope of the present application.

Claims

1. A differential signal receiver, comprising: a first differential differential amplifier configured to compare a voltage value of an input signal to a first threshold value and output a first differential signal according to a comparison result; a second differential differential amplifier configured to compare the voltage value of the input signal to a second threshold value and output a second differential signal according to a comparison result, wherein the second threshold value is an opposite number of the first threshold value; a latch coupled to the first differential differential amplifier and the second differential differential amplifier, having a set terminal configured to receive the first differential signal and a reset terminal configured to receive the second differential signal, wherein the latch starts to output a first latch signal being a logic low level when the first differential signal and the second differential signal are a logic high level and a logic low level respectively, and the latch starts to output the first latch signal being a logic high level when the first differential signal and the second differential signal are the logic low level and the logic high level respectively; and a first inverter coupled to the latch, configured to receive the first latch signal and output a first output signal, wherein the first output signal has a same duty cycle as the input signal.

2. The differential signal receiver of claim 1, wherein, The input signal is a result of a subtraction of a pair of differential signals, and the pair of differential signals comprises a first signal and a second signal.

3. The differential signal receiver of claim 2, wherein, A magnitude of the first threshold value corresponds to a result of the first signal minus the second signal.

4. The differential signal receiver of claim 3, wherein, The first threshold value is a positive number.

5. The differential signal receiver of claim 2, wherein, A first differential input of the first differential differential amplifier comprises a first non-inverting input terminal configured to receive the first signal and a first inverting input terminal configured to receive the second signal, and a second differential input of the first differential differential amplifier comprises a second non-inverting input terminal configured to receive a first reference voltage and a second inverting input terminal configured to receive a second reference voltage, such that the first differential differential amplifier takes the result of the first signal minus the second signal as the input signal and takes a result of the first reference voltage minus the second reference voltage as the first threshold value.

6. The differential signal receiver of claim 5, wherein, A first differential input of the second differential differential amplifier comprises a third non-inverting input terminal configured to receive the second reference voltage and a third inverting input terminal configured to receive the first reference voltage, and a second differential input of the second differential differential amplifier comprises a fourth non-inverting input terminal configured to receive the first signal and a fourth inverting input terminal configured to receive the second signal, such that the second differential differential amplifier takes the result of the first signal minus the second signal as the input signal and takes a result of the second reference voltage minus the first reference voltage as the second threshold value.

7. The differential signal receiver of claim 1, wherein, The latch comprises: a first NAND gate having a first input terminal configured to receive the first differential signal and a second input terminal configured to receive a second latch signal, and the first NAND gate is configured to output the first latch signal; and a second NAND gate having a third input terminal configured to receive the first latch signal and a fourth input terminal configured to receive the second differential signal, and the second NAND gate is configured to output the second latch signal.

8. The differential signal receiver of claim 7, wherein, The first input terminal of the first NAND gate is the set terminal of the latch, and the fourth input terminal of the second NAND gate is the reset terminal of the latch.

9. The differential signal receiver of claim 8, wherein, The second NOR gate starts outputting the second latch signal as the logic low level when the first difference signal and the second difference signal are the logic low level and the logic high level respectively, and starts outputting the second latch signal as the logic high level when the first difference signal and the second difference signal are the logic high level and the logic low level respectively.

10. The differential signal receiver of claim 9, further comprising: a second inverter coupled to the latch for receiving the second latch signal and outputting a second output signal.

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