A polar pulse modulation and demodulation circuit applied to isolated communication

Abstract

The application belongs to the field of integrated circuits, and discloses a polarity pulse modulation and demodulation circuit applied to isolated communication, which comprises a first delay circuit, a second delay circuit, an AND gate, a NOT gate, a pulse driving circuit, a transformer, a pulse detection circuit and an SR flip-flop; the first input end of the AND gate is connected with the output end of the first delay circuit, the second input end is used for inputting a digital signal, and the output end is connected with the pulse driving circuit; the first input end of the NOT gate is connected with the output end of the second delay circuit, the second input end is used for inputting an input signal, and the output end is connected with the pulse driving circuit; the primary side of the transformer is connected with the pulse driving circuit, and the secondary side is connected with the pulse detection circuit and the SR flip-flop in sequence. The delay circuit has the characteristics of stable delay time, which guarantees the certainty of the pulse width of the transmitted pulse signal, and then the pulse amplitude of the pulse signal is controlled through the pulse driving circuit, so that the pulse signal can realize long communication distance in a typical twisted pair line.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of integrated circuits and relates to a polarity pulse modulation and demodulation circuit applied to isolated communication. BACKGROUND

[0002] With the continuous improvement of the precision of electronic products, the application range thereof is effectively promoted. Considering the uncertainty of the working conditions and environment of electronic products, the electronic products are often used under extreme working conditions such as high voltage and working environment, and therefore an isolator needs to be introduced to ensure the safety of the control circuit.

[0003] The isolator is widely applied to various occasions requiring isolation between a high-voltage domain and a low-voltage domain, such as industrial control, automobile electronics and medical electronics, and isolated communication refers to that there is no physical connection and no current flow between two points, but the data signal can still be transmitted between the two points. At present, the system is usually divided into several subsystems, the circuit safety is ensured through circuit isolation, mutual interference is avoided, and the reliability of the system is improved.

[0004] However, the existing isolation circuit has a simple internal structure, the width and amplitude of the transmitted pulse are unstable, the anti-interference performance is poor, the transmission is prone to error, and the long-distance transmission cannot be realized. SUMMARY

[0005] The application aims at overcoming the defects of the prior art and providing a polarity pulse modulation and demodulation circuit applied to isolated communication.

[0006] To achieve the above object, the application adopts the following technical scheme:

[0007] The application provides a polarity pulse modulation and demodulation circuit applied to isolated communication, which comprises a first delay circuit, a second delay circuit, an AND gate, a NOT gate, a pulse driving circuit, a transformer, a pulse detection circuit and an SR flip-flop.

[0008] The first input end of the AND gate is connected with the output end of the first delay circuit, the second input end is used for inputting a digital signal, and the output end is connected with the pulse driving circuit; the first input end of the NOT gate is connected with the output end of the second delay circuit, the second input end is used for inputting an input signal, and the output end is connected with the pulse driving circuit; the primary side of the transformer is connected with the pulse driving circuit, and the secondary side is connected with the pulse detection circuit and the SR flip-flop in sequence; the input ends of the first delay circuit and the second delay circuit are used for inputting the input signal.

[0009] The first delay circuit and the second delay circuit are used for modulating the digital signal into a pulse signal; the pulse driving circuit is used for adjusting the pulse amplitude of the pulse signal and sending the pulse signal to the pulse detection circuit through the transformer; and the pulse detection circuit is used for demodulating the pulse signal into a digital signal.

[0010] Optionally, the pulse driving circuit comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, a first resistor R1 and a second resistor R2.

[0011] The drain of the seventh MOS transistor M7 is connected with the gate of the seventh MOS transistor M7, the gate of the sixth MOS transistor M6 and the gate of the fifth MOS transistor M5; the drain of the sixth MOS transistor M6 is connected with the drain and the gate of the first MOS transistor M1; the drain of the second MOS transistor M2 is connected with the drain of the third MOS transistor M3 and the drain of the fourth MOS transistor M4; the source of the third MOS transistor M3 is connected with one end of the first resistor R1, and the gate is connected with the output end of the AND gate; the source of the fourth MOS transistor M4 is connected with one end of the second resistor R2, and the gate is connected with the output end of the NOT gate; the drain of the fifth MOS transistor M5 is connected with the other end of the first resistor R1 and the other end of the second resistor R2; the source of the third MOS transistor M3 and the source of the fourth MOS transistor M4 are connected with the primary side of the transformer.

[0012] Optionally, the drain of the seventh MOS transistor M7 is used for connecting a bias current source I bias , the source of the seventh MOS transistor M7 is grounded; the source of the sixth MOS transistor M6 is grounded; the source of the first MOS transistor M1 and the source of the second MOS transistor M2 are used for connecting a power supply VDD; the source of the fifth MOS transistor M5 is grounded.

[0013] Optionally, the pulse detection circuit comprises an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M 10 , an eleventh MOS transistor M 11 , a twelfth MOS transistor M 12 , a thirteenth MOS transistor M 13 , a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R 10 , a first comparator CMP1 and a second comparator CMP2.

[0014] The drain of the thirteenth MOS transistor M 13 is connected with the gate of the thirteenth MOS transistor M 13 , the gate of the twelfth MOS transistor M 12 , the gate of the eleventh MOS transistor M 11 and the gate of the tenth MOS transistor M 10 ; the drain of the twelfth MOS transistor M 12the drain of the eighth MOS transistor M8 and the gate of the eighth MOS transistor M8 are connected; the drain of the ninth MOS transistor M9 is connected with one end of the third resistor R3, one end of the fourth resistor R4, one end of the seventh resistor R7 and one end of the eighth resistor R8; the other end of the third resistor R3 is connected with one end of the fifth resistor R5 and the positive terminal of the first comparator CMP1; the other end of the fifth resistor R5 is connected with one end of the sixth resistor R6 and the drain of the eleventh MOS transistor M 11 ; the other end of the sixth resistor R6 is connected with the other end of the fourth resistor R4 and the negative terminal of the second comparator CMP2; the other end of the seventh resistor R7 is connected with one end of the ninth resistor R9 and the positive terminal of the second comparator CMP2; the other end of the ninth resistor R9 is connected with one end of the tenth resistor R 10 ; the drain of the tenth MOS transistor M 10 is connected with the other end of the tenth resistor R 10 ; the other end of the eighth resistor R8 is connected with the other end of the tenth resistor R 13 and the negative terminal of the first comparator CMP1; the output terminal of the first comparator CMP1 and the output terminal of the second comparator CMP2 are connected with the SR flip-flop; the other end of the fifth resistor R5 and the other end of the ninth resistor R9 are connected with the secondary side of the transformer.

[0015] Optionally, the drain of the thirteenth MOS transistor M 13 is used for connecting a bias current source I bias2 ; the source of the thirteenth MOS transistor M 13 , the source of the twelfth MOS transistor M 12 , the source of the eleventh MOS transistor M 11 and the source of the tenth MOS transistor M 10 are grounded; the source of the eighth MOS transistor M8 and the source of the ninth MOS transistor M9 are used for connecting a power supply VDD.

[0016] Optionally, the first comparator CMP1 and the second comparator CMP2 are both window comparators with differential voltage threshold voltage.

[0017] Optionally, the first delay circuit and the second delay circuit are of the same structure;

[0018] The first delay circuit comprises a fourteenth MOS transistor M 14 , a fifteenth MOS transistor M 15 , a sixteenth MOS transistor M 16 , a seventeenth MOS transistor M 17 , an eighteenth MOS transistor M 18 , a nineteenth MOS transistor M 19 , a twentieth MOS transistor M 20 , a twenty-first MOS transistor M 21 , a twenty-second MOS transistor M22 23rd MOSFET M 23 24th MOSFET M 24 25th MOSFET M 25 The components are: first inverter INV1, second inverter INV2, third inverter INV3, first capacitor CL1, and second capacitor CL2.

[0019] The fourteenth MOSFET M 14 The drain of the fourteenth MOSFET M 14 Gate, fifteenth MOSFET M 15 The gate of the eighteenth MOS transistor M 18 The drain of the 23rd MOSFET M 23 The gate, one end of the first capacitor CL1, and the fifteenth MOSFET M 15 The drains of all transistors are connected; the seventeenth MOSFET M 17 The drain of the seventeenth MOSFET M 17 Gate, nineteenth MOSFET M 19 The drain of the 24th MOSFET M 24 The gate of the sixteenth MOS transistor M 16 The drain of the first transistor and one end of the second capacitor CL2 are both connected; the eighteenth MOSFET M 18 The source of the twentieth MOSFET M 20 The drain of the nineteenth MOSFET M 19 The source of each transistor is connected, and the gate is connected to the output of the second inverter INV2; the nineteenth MOSFET M 19 The gate of the MOSFET is connected to the output of the first inverter INV1; the input of the first inverter INV1 is used to input the digital signal DIN; the twenty-third MOSFET M... 23 The source of the 25th MOSFET M 25 The drain of the 24th MOSFET M 24 The sources of the MOSFETs are all connected; the twenty-first MOSFET M 21 The drain of the 21st MOSFET M 21 The gate of the 22nd MOSFET M 22 The gates of all are connected; the twenty-second MOSFET M 22 The drain of the 24th MOSFET M 24 The drain of the first inverter and the input of the third inverter INV3 are both connected; the output of the third inverter INV3 is connected to the first input of the AND gate.

[0020] Optionally, the fourteenth MOS transistor M 14 The source of the seventeenth MOSFET M 17 The source of the fifteenth MOSFET M 15 The source of the sixteenth MOSFET M16 the source of the twenty-first MOS transistor M 21 the source of the twenty-second MOS transistor M 22 the source of the twentieth MOS transistor M 20 the gate of the twenty-fifth MOS transistor M 25 the gate of the twenty-fifth MOS transistor M 20 the source of the twenty-fifth MOS transistor M 25 the source of the twenty-fifth MOS transistor M

[0021] Optionally, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, the seventh MOS transistor M7, the tenth MOS transistor M 10 , the eleventh MOS transistor M 11 , the twelfth MOS transistor M 12 , the thirteenth MOS transistor M 13 , the fourteenth MOS transistor M 14 , the fifteenth MOS transistor M 15 , the sixteenth MOS transistor M 16 , the seventeenth MOS transistor M 17 , the twenty-first MOS transistor M 21 , and the twenty-second MOS transistor M 22 are N-type MOS transistors; the first MOS transistor M1, the second MOS transistor M2, the eighth MOS transistor M8, the ninth MOS transistor M9, the eighteenth MOS transistor M 18 , the nineteenth MOS transistor M 19 , the twentieth MOS transistor M 20 , the twenty-third MOS transistor M 23 , the twenty-fourth MOS transistor M 24 , and the twenty-fifth MOS transistor M 25 are P-type MOS transistors.

[0022] Compared with the prior art, the present application has the following beneficial effects:

[0023] The present application is applied to the polarity pulse modulation and demodulation circuit for isolated communication. Digital signals are modulated into pulse signals through the first delay circuit and the second delay circuit, then the pulse amplitude of the pulse signals is adjusted through the pulse driving circuit, and the pulse signals are sent to the pulse detection circuit through the transformer, then the pulse detection circuit is used to demodulate the pulse signals into digital signals and output through the SR flip-flop. The delay time of the delay circuit is stable, thereby ensuring the certainty of the pulse width of the transmitted pulse signals, and then the pulse amplitude of the pulse signals is controlled through the pulse driving circuit, so that the pulse signals can realize long communication distance in typical twisted pair, and the pulse detection circuit ensures that the pulse signals are correctly demodulated.

[0024] Further, the first comparator CMP1 and the second comparator CMP2 are both window comparators with differential voltage threshold voltages, which can eliminate pulse interference at the non-transmission end and ensure that the pulse signal is correctly demodulated. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A schematic diagram of a polarity pulse modulation and demodulation circuit for isolated communication according to an embodiment of the present application;

[0026] Figure 2 A topology diagram of a pulse driving circuit according to an embodiment of the present application;

[0027] Figure 3 A topology diagram of a pulse detection circuit according to an embodiment of the present application;

[0028] Figure 4 A topology diagram of a first delay circuit according to an embodiment of the present application;

[0029] Figure 5 A waveform diagram of a digital signal modulation process according to an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the personnel in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work should belong to the scope of protection of the present application.

[0031] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] The present application will be described in further detail below with reference to the drawings:

[0033] Reference is made to Figure 1The application provides a polarity pulse modulation and demodulation circuit applied to isolated communication.

[0034] The first input end of the AND gate is connected with the output end of the first delay circuit, the second input end is used for inputting a digital signal, and the output end is connected with the pulse driving circuit; the first input end of the NOT gate is connected with the output end of the second delay circuit, the second input end is used for inputting an input signal, and the output end is connected with the pulse driving circuit; the primary side of the transformer is connected with the pulse driving circuit, the secondary side is sequentially connected with the pulse detection circuit and the SR flip-flop; and the input ends of the first delay circuit and the second delay circuit are used for inputting the input signal.

[0035] Specifically, the first delay circuit and the second delay circuit are used for modulating the digital signal into a pulse signal; the pulse driving circuit is used for adjusting the pulse amplitude of the pulse signal and sending the pulse signal to the pulse detection circuit through the transformer; and the pulse detection circuit is used for demodulating the pulse signal into a digital signal.

[0036] The pulse polarity modulation is realized by using both terminals of the primary side of the transformer, and the positive and negative edges of the input digital signal are described by using positive and negative pulses.

[0037] The polarity pulse modulation and demodulation circuit applied to isolated communication has the characteristics of stable delay time of the delay circuit, thereby ensuring the determinacy of the pulse width of the transmitted pulse signal, then the pulse amplitude of the pulse signal is controlled by the pulse driving circuit, so that the pulse signal can realize long communication distance in a typical twisted pair, and the pulse signal is correctly demodulated by the pulse detection circuit.

[0038] Reference Figure 2 In a possible implementation, the pulse driving circuit comprises a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, a first resistor R1 and a second resistor R2.

[0039] The drain of the seventh MOS M7 is connected with the gate of the seventh MOS M7, the gate of the sixth MOS M6 and the gate of the fifth MOS M5; the drain of the sixth MOS M6 is connected with the drain and the gate of the first MOS M1; the drain of the second MOS M2 is connected with the drain of the third MOS M3 and the drain of the fourth MOS M4; the source of the third MOS M3 is connected with one end of the first resistor R1 and the output of the AND gate; the source of the fourth MOS M4 is connected with one end of the second resistor R2 and the output of the NOT gate; the drain of the fifth MOS M5 is connected with the other end of the first resistor R1 and the other end of the second resistor R2; the source of the third MOS M3 and the source of the fourth MOS M4 are connected with the primary side of the transformer.

[0040] In specific use, the drain of the seventh MOS M7 is used to connect a bias current source I bias , the source of the seventh MOS M7 is grounded; the source of the sixth MOS M6 is grounded; the source of the first MOS M1 and the source of the second MOS M2 are used to connect a power supply VDD; the source of the fifth MOS M5 is grounded.

[0041] Referring to Figure 3 In a possible implementation, the pulse detection circuit comprises an eighth MOS M8, a ninth MOS M9, a tenth MOS M 10 , an eleventh MOS M 11 , a twelfth MOS M 12 , a thirteenth MOS M 13 , a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R 10 , a first comparator CMP1 and a second comparator CMP2.

[0042] The drain of the thirteenth MOS M 13 is connected with the gate of the thirteenth MOS M 13 , the gate of the twelfth MOS M 12 , the gate of the eleventh MOS M 11 and the gate of the tenth MOS M 10 ; the drain of the twelfth MOS M 12The drain of the ninth MOSFET M9 is connected to both the drain and gate of the eighth MOSFET M8; the drain of the ninth MOSFET M9 is connected to one end of the third resistor R3, one end of the fourth resistor R4, one end of the seventh resistor R7, and one end of the eighth resistor R8; the other end of the third resistor R3 is connected to one end of the fifth resistor R5 and the positive terminal of the first comparator CMP1; the other end of the fifth resistor R5 is connected to one end of the sixth resistor R6 and the eleventh MOSFET M9. 11 The drains of all resistors are connected; the other end of the sixth resistor R6 is connected to the other end of the fourth resistor R4 and the negative terminal of the second comparator CMP2; the other end of the seventh resistor R7 is connected to one end of the ninth resistor R9 and the positive terminal of the second comparator CMP2; the other end of the ninth resistor R9 is connected to the tenth resistor R... 10 One end and the tenth MOSFET M 10 The drains of all resistors are connected; the other end of the eighth resistor R8 is connected to the tenth resistor R. 10 The other end of the resistor and the negative end of the first comparator CMP1 are both connected; the output of the first comparator CMP1 and the output of the second comparator CMP2 are connected to the SR flip-flop; the other end of the fifth resistor R5 and the other end of the ninth resistor R9 are both connected to the secondary side of the transformer.

[0043] In practical use, the thirteenth MOS transistor M 13 The drain is used to connect the bias current source I. bias2 The thirteenth MOSFET M 13 The source of the twelfth MOSFET M 12 The source of the eleventh MOSFET M 11 The source and the tenth MOSFET M 10 The sources of all transistors are grounded; the sources of the eighth MOSFET M8 and the ninth MOSFET M9 are both connected to the power supply VDD.

[0044] Optionally, both the first comparator CMP1 and the second comparator CMP2 are window comparators with differential voltage threshold voltage, which can eliminate pulse interference at the non-transmission end and ensure that the pulse signal is correctly demodulated.

[0045] In one possible implementation, the first delay circuit and the second delay circuit have the same structure; see [link to previous implementation]. Figure 4 The first delay circuit includes a fourteenth MOS transistor M 14 The fifteenth MOSFET M 15 The sixteenth MOSFET M 16 The seventeenth MOSFET M 17 The eighteenth MOSFET M 18 The nineteenth MOSFET M 19 20th MOSFET M 20 21st MOSFET M21 , the twenty-second MOS transistor M 22 , the twenty-third MOS transistor M 23 , the twenty-fourth MOS transistor M 24 , the twenty-fifth MOS transistor M 25 , the first inverter INV1, the second inverter INV2, the third inverter INV3, the first capacitor CL1 and the second capacitor CL2.

[0046] wherein the drain of the fourteenth MOS transistor M 14 is connected with the drain of the fourteenth MOS transistor M 14 , the gate of the fifteenth MOS transistor M 15 , the drain of the eighteenth MOS transistor M 18 , the gate of the twenty-third MOS transistor M 23 , one end of the first capacitor CL1 and the drain of the fifteenth MOS transistor M 15 are all connected; the drain of the seventeenth MOS transistor M 17 is connected with the gate of the seventeenth MOS transistor M 17 , the drain of the nineteenth MOS transistor M 19 , the gate of the twenty-fourth MOS transistor M 24 , the drain of the sixteenth MOS transistor M 16 and one end of the second capacitor CL2 are all connected; the source of the eighteenth MOS transistor M 18 is connected with the drain of the twentieth MOS transistor M 20 and the source of the nineteenth MOS transistor M 19 , and the gate is connected with the output end of the second inverter INV2; the gate of the nineteenth MOS transistor M 19 is connected with the output end of the first inverter INV1; the input end of the first inverter INV1 is used for inputting a digital signal DIN; the source of the twenty-third MOS transistor M 23 is connected with the drain of the twenty-fifth MOS transistor M 25 and the source of the twenty-fourth MOS transistor M 24 ; the drain of the twenty-first MOS transistor M 21 is connected with the gate of the twenty-first MOS transistor M 21 and the gate of the twenty-second MOS transistor M 22 ; the drain of the twenty-second MOS transistor M 22 is connected with the drain of the twenty-fourth MOS transistor M 24 and the input end of the third inverter INV3; the output end of the third inverter INV3 is connected with the first input end of the AND gate.

[0047] In specific use, the source of the fourteenth MOS transistor M 14 , the source of the seventeenth MOS transistor M 17 , the fifteenth MOS transistor M15 The source of the sixteenth MOSFET M 16 The source of the 21st MOSFET M 21 The source and the twenty-second MOSFET M 22 The sources of all transistors are grounded; the twentieth MOSFET M 20 The gate and the twenty-fifth MOSFET M 25 The gates of both transistors are used to connect to the bias voltage source VB, and the twentieth MOSFET M... 20 The source and the twenty-fifth MOSFET M 25 The source terminals are all used to connect to the power supply VDD.

[0048] Optionally, in the polar pulse modulation and demodulation circuit applied to isolated communication, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, the seventh MOS transistor M7, and the tenth MOS transistor M... 10 11th MOSFET M 11 12th MOSFET M 12 The thirteenth MOSFET M 13 The fourteenth MOSFET M 14 The fifteenth MOSFET M 15 The sixteenth MOSFET M 16 The seventeenth MOSFET M 17 21st MOSFET M 21 And the twenty-second MOSFET M 22 All are N-type MOSFETs; MOSFET M1, MOSFET M2, MOSFET M8, MOSFET M9, and MOSFET M18. 18 The nineteenth MOSFET M 19 20th MOSFET M 20 23rd MOSFET M 23 24th MOSFET M 24 And the 25th MOSFET M 25 All are P-type MOSFETs.

[0049] The working principle of the polar pulse modulation and demodulation circuit applied to isolated communication in this invention is as follows:

[0050] The pulse drive circuit is a current-regulated differential driver whose output drives the transformer. The voltage amplitude is determined by the drive current and the equivalent resistive load (cable characteristic impedance and terminating resistance). The pulse detection circuit and RS flip-flop constitute the signal demodulation module, which recovers the pulse signal into the corresponding rising or falling edge.

[0051] Two delay circuits and AND gate and NOT gate together constitute the encoding control logic module, for example, the first delay circuit can set the pulse width of the pulse signal, affect the circuit timing. Specifically, the input end is connected with bias voltage source V B , to provide reasonable bias current for the charging and discharging of the circuit. The input D IN of the first delay circuit is a digital signal, and the level value determines the conduction and turn-off of the eighteenth MOS transistor M 18 and the nineteenth MOS transistor M 19 . When D IN is a high level, the eighteenth MOS transistor M 18 is turned off, the nineteenth MOS transistor M 19 is turned on, the gate potential of the twenty-third MOS transistor M 23 is lower than that of the twenty-fourth MOS transistor M 24 , and the drain of the twenty-fourth MOS transistor M 24 outputs a low potential, which becomes a digital high level D OUT after shaping by the rear stage inverter. When D IN jumps to a low level, the eighteenth MOS transistor M 18 is turned on, the nineteenth MOS transistor M 19 is turned off, and the branch current of the eighteenth MOS transistor M 18 begins to charge the first capacitor CL1, until the fourteenth MOS transistor M 14 is turned on, the fifteenth MOS transistor M 15 is turned on, the drain of the seventeenth MOS transistor M 17 is pulled to a low level, and the gate potential of the twenty-third MOS transistor M 23 is higher than that of the twenty-fourth MOS transistor M 24 . At this time, the output D out of the first delay circuit becomes a digital low level. When D IN jumps to a high level, the eighteenth MOS transistor M 18 is turned off, the nineteenth MOS transistor M 19 is turned on, and the branch current of the nineteenth MOS transistor M 19 begins to charge the second capacitor CL2, until the seventeenth MOS transistor M 17 is turned on, the sixteenth MOS transistor M 16 is turned on, the drain of the fourteenth MOS transistor M 14 is pulled to a low level, and the gate potential of the twenty-third MOS transistor M 23 is lower than that of the twenty-fourth MOS transistor M 24 . At this time, the output D outThe input signal will become a digital high level. At this time, the delay function of the rising edge and the falling edge of the input signal is completed. The delay time is determined by the first capacitor CL1 and the second capacitor CL2 and the size of the charging current.

[0052] The input signal is encoded by the encoding control logic module and then acts on the third MOS transistor M3 and the fourth MOS transistor M4, controlling the conduction and shutdown of the branch. Among them, I bias1 is a constant current source generated by the circuit. The sixth MOS transistor M6 mirrors the bias current of the seventh MOS transistor M7, providing DC bias for the normal operation of the first MOS transistor M1 and the second MOS transistor M2. The fifth MOS transistor M5 mirrors the bias current of the seventh MOS transistor M7, providing operating current for the branch of the fifth MOS transistor M5. By adjusting the current size of the fifth MOS transistor M5 branch and the resistance values of the first resistor R1 and the second resistor R2, the pulse amplitude of the pulse signal output by the pulse driving circuit can be adjusted.

[0053] The pulse detection circuit includes two window comparators with differential voltage threshold voltage VTCMP. The drain of the thirteenth MOS transistor M 13 is connected to the bias current source I bias2 , the tenth MOS transistor M 10 and the eleventh MOS transistor M 11 mirror the bias current of the thirteenth MOS transistor M 13 , so that the sizes of the eleventh MOS transistor M 11 and the tenth MOS transistor M 10 are the same, and the currents in the branches of the two MOS transistors are equal. The input ends IPo and IMo are connected to the output of the secondary side of the transformer driver circuit. Different IPo and IMo signals form the positive and negative input voltage signals VIP and VIM in their branches through the third resistor R3 to the tenth resistor R 10 . When the voltage difference between the two input comparators is VIP-VIM greater than +VTCMP, the comparator outputs a logic +1, and an RS flip-flop outputs a rising edge. When VIP-VIM is less than -VTCMP, the comparator detects a logic -1, and an RS flip-flop outputs a falling edge.

[0054] Referring to Figure 5 , the polar pulse modulation and demodulation circuit for isolated communication is shown. In actual application, the waveform of each node is shown. Among them, IN is the digital signal input node, IP is the source output node of the third MOS transistor M3, and IM is the source output node of the fourth MOS transistor M4.

[0055] The above merely illustrates the technical idea of the present application, and cannot limit the protection scope of the present application. Any modification made according to the technical idea of the present application on the basis of the technical scheme falls within the protection scope of the present application.

Claims

1. A polar pulse modulation demodulation circuit applied to isolated communication, characterized by, The first delay circuit, the second delay circuit, the AND gate, the NOT gate, the pulse driving circuit, the transformer, the pulse detection circuit and the SR flip-flop are included. The first input end of the AND gate is connected with the output end of the first delay circuit, the second input end is used for inputting a digital signal, and the output end is connected with the pulse driving circuit; the first input end of the NOT gate is connected with the output end of the second delay circuit, the second input end is used for inputting an input signal, and the output end is connected with the pulse driving circuit; the primary side of the transformer is connected with the pulse driving circuit, and the secondary side is connected with the pulse detection circuit and the SR flip-flop in sequence; the input ends of the first delay circuit and the second delay circuit are used for inputting the input signal. The first delay circuit and the second delay circuit are used for modulating the digital signal into a pulse signal. The pulse driving circuit is used for adjusting the pulse amplitude of the pulse signal and sending the pulse signal to the pulse detection circuit through the transformer; and the pulse detection circuit is used for demodulating the pulse signal into a digital signal. The pulse driving circuit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, a first resistor R1 and a second resistor R2. The drain of the seventh MOS tube M7 is connected with the gate of the seventh MOS tube M7, the gate of the sixth MOS tube M6 and the gate of the fifth MOS tube M5; the drain of the sixth MOS tube M6 is connected with the drain and the gate of the first MOS tube M1; the drain of the second MOS tube M2 is connected with the drain of the third MOS tube M3 and the drain of the fourth MOS tube M4; the source of the third MOS tube M3 is connected with one end of the first resistor R1, and the gate is connected with the output end of the AND gate; the source of the fourth MOS tube M4 is connected with one end of the second resistor R2, and the gate is connected with the output end of the NOT gate; the drain of the fifth MOS tube M5 is connected with the other end of the first resistor R1 and the other end of the second resistor R2; the source of the third MOS tube M3 and the source of the fourth MOS tube M4 are connected with the primary side of the transformer.

2. The polar pulse modulation demodulation circuit for isolated communication according to claim 1, wherein, The drain of the seventh MOS transistor M7 is used to connect a bias current source I bias The source of the seventh MOS transistor M7 is grounded; the source of the sixth MOS transistor M6 is grounded; the source of the first MOS transistor M1 and the source of the second MOS transistor M2 are both used to connect a power supply VDD; and the source of the fifth MOS transistor M5 is grounded.

3. The polar pulse modulation demodulation circuit for isolated communication according to claim 1, wherein, The pulse detection circuit comprises an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M 10 , an eleventh MOS transistor M 11 , a twelfth MOS transistor M 12 , a thirteenth MOS transistor M 13 , a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R 10 , a first comparator CMP1 and a second comparator CMP2. the thirteenth MOS transistor M 13 the drain of the thirteenth MOS transistor M 13 the gate of the twelfth MOS transistor M 12 the gate of the eleventh MOS transistor M 11 the gate of the tenth MOS transistor M 10 the gate of the ninth MOS transistor M 12 the drain of the eighth MOS transistor M8 and the gate of the eighth MOS transistor M8; the drain of the ninth MOS transistor M9 is connected with one end of the third resistor R3, one end of the fourth resistor R4, one end of the seventh resistor R7 and one end of the eighth resistor R8; the other end of the third resistor R3 is connected with one end of the fifth resistor R5 and the positive end of the first comparator CMP1; the other end of the fifth resistor R5 is connected with one end of the sixth resistor R6 and the drain of the eleventh MOS transistor M 11 the other end of the sixth resistor R6 is connected with the other end of the fourth resistor R4 and the negative end of the second comparator CMP2; the other end of the seventh resistor R7 is connected with one end of the ninth resistor R9 and the positive end of the second comparator CMP2; the other end of the ninth resistor R9 is connected with one end of the tenth resistor R 10 the drain of the tenth MOS transistor M 10 the other end of the eighth resistor R8 is connected with the other end of the tenth resistor R 10 the negative end of the first comparator CMP1; the output end of the first comparator CMP1 and the output end of the second comparator CMP2 are connected with the SR flip-flop; the other end of the fifth resistor R5 and the other end of the ninth resistor R9 are connected with the secondary side of the transformer.

4. The polar pulse modulation demodulation circuit for isolated communication according to claim 3, wherein, the drain of the thirteenth MOS transistor M 13 is used for connecting a bias current source I bias2 , the source of the thirteenth MOS transistor M 13 , the source of the twelfth MOS transistor M 12 , the source of the eleventh MOS transistor M 11 , and the source of the tenth MOS transistor M 10 are all grounded; the source of the eighth MOS transistor M8 and the source of the ninth MOS transistor M9 are both used for connecting a power supply VDD.

5. The polar pulse modulation demodulation circuit for isolated communication according to claim 3, wherein, The first comparator CMP1 and the second comparator CMP2 are both window comparators with differential voltage threshold voltages.

6. The polar pulse modulation demodulation circuit for isolated communication according to claim 3, wherein, The first delay circuit and the second delay circuit have the same structure. The first delay circuit comprises a fourteenth MOS transistor M 14 , a fifteenth MOS transistor M 15 , a sixteenth MOS transistor M 16 , a seventeenth MOS transistor M 17 , an eighteenth MOS transistor M 18 , a nineteenth MOS transistor M 19 , a twentieth MOS transistor M 20 , a twenty-first MOS transistor M 21 , a twenty-second MOS transistor M 22 , a twenty-third MOS transistor M 23 , a twenty-fourth MOS transistor M 24 , a twenty-fifth MOS transistor M 25 , a first inverter INV1, a second inverter INV2, a third inverter INV3, a first capacitor CL1, and a second capacitor CL2. fourteenth MOS transistor M 14 drain of the fourteenth MOS transistor M 14 gate, fifteenth MOS transistor M 15 gate, eighteenth MOS transistor M 18 drain, twenty-third MOS transistor M 23 gate, one end of first capacitor CL1 and fifteenth MOS transistor M 15 drain of the fifteenth MOS transistor M 17 drain of the seventeenth MOS transistor M 17 gate, nineteenth MOS transistor M 19 drain, twenty-fourth MOS transistor M 24 gate, sixteenth MOS transistor M 16 drain of the sixteenth MOS transistor M and one end of second capacitor CL2; source of the eighteenth MOS transistor M 18 source of the twentieth MOS transistor M 20 drain of the nineteenth MOS transistor M 19 source of the nineteenth MOS transistor M and output end of the second inverter INV2; gate of the nineteenth MOS transistor M 19 gate of the nineteenth MOS transistor M and output end of the first inverter INV1; input end of the first inverter INV1 is used for inputting digital signal DIN; source of the twenty-third MOS transistor M 23 drain of the twenty-fifth MOS transistor M 25 source of the twenty-fourth MOS transistor M 24 source of the twenty-first MOS transistor M 21 drain of the twenty-first MOS transistor M 21 gate of the twenty-second MOS transistor M 22 gate of the twenty-second MOS transistor M 22 drain of the twenty-fourth MOS transistor M 24 drain of the twenty-fourth MOS transistor M and input end of the third inverter INV3; output end of the third inverter INV3 is connected with the first input end of the AND gate.

7. The polar pulse modulation demodulation circuit for isolated communication according to claim 6, wherein, the source of the fourteenth MOS transistor M 14 the source of the seventeenth MOS transistor M 17 the source of the fifteenth MOS transistor M 15 the source of the sixteenth MOS transistor M 16 the source of the twenty-first MOS transistor M 21 the source of the twenty-second MOS transistor M 22 the gate of the twentieth MOS transistor M 20 the gate of the twenty-fifth MOS transistor M 25 are used for connecting a bias voltage source VB, the source of the twentieth MOS transistor M 20 the source of the twenty-fifth MOS transistor M 25 are used for connecting a power source VDD.

8. The polar pulse modulation demodulation circuit for isolated communication according to claim 6, wherein, The third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, the seventh MOS transistor M7, the tenth MOS transistor M 10 , the eleventh MOS transistor M 11 , the twelfth MOS transistor M 12 , the thirteenth MOS transistor M 13 , the fourteenth MOS transistor M 14 , the fifteenth MOS transistor M 15 , the sixteenth MOS transistor M 16 , the seventeenth MOS transistor M 17 , the twenty-first MOS transistor M 21 , and the twenty-second MOS transistor M 22 are N-type MOS transistors; the first MOS transistor M1, the second MOS transistor M2, the eighth MOS transistor M8, the ninth MOS transistor M9, the eighteenth MOS transistor M 18 , the nineteenth MOS transistor M 19 , the twentieth MOS transistor M 20 , the twenty-third MOS transistor M 23 , the twenty-fourth MOS transistor M 24 , and the twenty-fifth MOS transistor M 25 are P-type MOS transistors.

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