A high-reliability and low-fan-out logic filtering system and method for eddy current small signals

Abstract

A logic filtering system and method for high reliability and low fan-out of eddy current small signals is proposed based on the traditional step-accumulation filtering method and the working characteristics of eddy current displacement sensors. The filtering results are updated in real time to reduce output delay and improve real-time performance. At the same time, modular split filtering operations are adopted to reduce the overall fan-out, and the filter submodule registers are updated in reverse order to ensure that the data in the overall filtering process is correct and reliable. Through the above method, the reliability and stability of eddy current displacement sensors for relative posture measurement can be accurately and intuitively improved.

Description

Technical Field

[0001] The invention relates to a high-reliability and low-fan-out logic filtering system and method for eddy current small signals, belonging to the field of non-contact displacement measurement. Background Art

[0002] Eddy current displacement sensor products require high precision and high stability, and they have the characteristics of fast mobility. Because the product itself has a narrow bandwidth, high sampling frequency, and fast sampling speed. Therefore, the product is highly sensitive to noise. Logical filtering processing to enhance the signal-to-noise ratio is the core technology and key technology in the above field. Traditional filtering methods cannot adapt to its special application limitations. At the same time, the realization of aerospace-grade engineering for satellites requires real-time performance and low fan-out. Therefore, a new real-time, reliable, and low fan-out filtering method is needed. Summary of the invention

[0003] The technical problem solved by the present invention is: in view of the problem that the traditional filtering method in the current existing technology cannot adapt to its special application limitations and cannot meet the aerospace-grade engineering requirements for satellites, a high-reliability and low-fan-out logic filtering system and method for eddy current small signals are proposed.

[0004] The present invention solves the above technical problems by the following technical solutions:

[0005] A logic filtering system for eddy current small signals with high reliability and low fan-out comprises an eddy current displacement sensor, an AD acquisition module, a first group accumulation module and a group sliding filter submodule. After the eddy current displacement sensor is started, the AD acquisition module performs initialization processing on the AD chip and performs self-calibration timing, detects the falling edge of the AD chip busy signal Busy, and outputs the AD chip data acquisition timing data; the first group accumulation module accumulates the output data according to the AD acquisition module and records the number of step accumulations at the same time; the group sliding filter submodule judges the number of step accumulations, and after reaching the step accumulation set value, the accumulated data is divided into a group, and a trigger signal is generated, and the trigger signal is monitored to judge whether to output the filter signal and update the signal, wherein the filter logic system composed of the eddy current displacement sensor, the AD acquisition module, the first group accumulation module and the group sliding filter submodule performs signal acquisition and data filtering processing on the AD chip.

[0006] In the group sliding filter submodule, it is determined whether the number of step accumulations has reached the step accumulation setting value. After reaching the step accumulation setting value, the data accumulated this time is divided into a group, a trigger signal Trig is generated, and the trigger signal Trig is judged. When the Trig signal is detected to be valid, a sliding group update signal Trig_r1 is generated. If the Trig signal is invalid, it continues to wait until the subsequent trigger signal Trig is valid.

[0007] The first group accumulation module performs accumulation of the next group of output data and records the number of step accumulations while the group sliding filter submodule is determining the number of step accumulations.

[0008] In the group sliding filter submodule, the sliding group update signal Trig_r1 is judged. When the sliding group update signal Trig_r1 is valid, the current accumulated output data is subjected to sliding filtering processing and retained, the next group of output data accumulated and processed by the first group accumulation module is grouped, and the sliding filter register group in the secondary group sliding filter submodule is updated using the retained current accumulated output data, and the current accumulated output data update completion flag Trig_r2 is generated. After all register groups are updated, the validity of the trigger signal Trig for the next group of output data is judged until all output data of the AD chip are traversed.

[0009] The AD acquisition module, the first group accumulation module, and the group sliding filter submodule can all be implemented through the FPGA architecture.

[0010] A high-reliability and low-fan-out logic filtering method for eddy current small signals, comprising:

[0011] (1) Monitor the busy signal Busy of the AD chip. When the falling edge of the busy signal Busy of the AD chip is detected, stop the self-calibration of the AD chip and output the data collection timing of the AD chip;

[0012] (2) Continuously collect the data output by the AD chip, accumulate the output data and record the number of step accumulations;

[0013] (3) judging the number of step accumulation times, and when reaching the step accumulation setting value, grouping the accumulated data into one group, generating a trigger signal Trig, and entering step (4) to judge the trigger signal Trig, and returning to step (2) to collect and step accumulate the next group of data;

[0014] (4) When the Trig signal is detected to be valid, a sliding filter process is performed and the accumulated data is retained to generate a dynamic group update signal Trig_r1, and then the process goes to step (5). If the Trig signal is invalid, the process continues to wait for the Trig signal until it is valid.

[0015] (5) When the Trig_r1 signal is detected to be valid, the accumulated first grouping data is input into the group sliding filter submodule, the next group of data is grouped, and the group update completion flag Trig_r2 of the current accumulated output data is generated. The sliding filter register group in the secondary group sliding filter submodule is updated using the retained current accumulated output data. After all register groups are updated, the validity of the trigger signal Trig for the next group of output data is judged until all output data of the AD chip are traversed.

[0016] In the step (1), before monitoring the busy signal Busy of the AD chip, the eddy current displacement sensor is started, the AD chip initialization process is started, and the AD chip self-calibration timing is output.

[0017] In the step (3), if the falling edge of the AD chip busy signal Busy is not detected, the AD chip self-calibration failure flag is set to be valid, and the AD chip self-calibration is performed again after the next instruction arrives.

[0018] In the step (2), after the trigger signal Trig is generated, the trigger signal Trig is monitored while the next set of data is collected and step-accumulated. If the number of step accumulations does not reach the step accumulation setting value, the output data is continuously accumulated.

[0019] In step (2), the output data is accumulated to complete the superposition amplification of the weak signal. The specific steps are as follows:

[0020] Assume that the step accumulation setting value is n, and the data output by the AD chip is Di;

[0021] The sum of every n data Di obtained by AD conversion is used to obtain the accumulated value N j ;

[0022] in,

[0023] N j Output to the group sliding filter submodule, and output Trig signal at the same time, marking a group of data N in the first grouping j The processing has been completed, and the data is subjected to sliding filtering;

[0024] Repeat the above operation until all the output data of the current group are processed to achieve real-time acquisition and amplification of AD chip data.

[0025] When sliding filtering is performed on the data, the values ​​of each register in the register group of the previous cycle retained by the group sliding filtering submodule are used to calculate the filtering results with the current data, specifically:

[0026]

[0027] In the formula, S k is the value of each register in the register group of the previous cycle, N j t The current accumulated amplified data is filtered and retained in the group sliding filter submodule after the calculation output is completed.

[0028] In the step (5), when updating each register of the group sliding filter submodule, each register data in the sliding filter register group of the current cycle is updated in reverse order according to the register index sequence to complete the decoupling of the filter data.

[0029] The advantages of the present invention compared with the prior art are:

[0030] The present invention provides a high-reliability and low-fan-out logic filtering system and method for eddy current small signals. Aiming at the unique characteristics of inertial sensitive eddy current small signal data, such as large step change gradient and discontinuous data, a high-precision step accumulation and logic filtering operation based on step accumulation and filtering is designed. Aiming at the real-time data processing requirement of eddy current displacement sensor, an atomic-level parallel pipeline operation is performed using FPGA working main frequency clock to reduce delay. Meanwhile, in view of the low fan-out requirement of on-board eddy current displacement sensor, pipeline calculation is grouped, and step accumulation and filtering operation with N filtering times is modularly split into five-level modules, so that the data fan-out of each level module is limited to the current effective register, and no coupling effect is generated on the signals of other modules, thereby ensuring that the step accumulation and filtering results are correct and reliable. The update order of sub-module registers is defined, and the values ​​of sub-module registers are updated in reverse order. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A flow chart of the implementation method provided for the invention;

[0032] Figure 2 Two loop control flow charts provided for the invention; DETAILED DESCRIPTION

[0033] A high-reliability and low-fan-out logic filtering system and method for eddy current small signals, based on the traditional step-accumulation filtering method and according to the working characteristics of the eddy current displacement sensor, reduces the output delay by updating the filtering results in real time to improve the real-time performance, and adopts modular split filtering operation to reduce the overall fan-out, and adopts the method of updating the filter submodule register in reverse order to ensure that the data in the overall filtering process is correct and reliable, which can intuitively improve the reliability and stability of the eddy current displacement sensor for relative posture measurement.

[0034] The logic filtering system specifically includes an eddy current displacement sensor, an AD acquisition module, a first group accumulation module, and a group sliding filter submodule. After the eddy current displacement sensor is started, the AD acquisition module initializes the AD chip and performs self-calibration timing, detects the falling edge of the AD chip busy signal Busy, and outputs the AD chip data acquisition timing data; the first group accumulation module accumulates the output data according to the AD acquisition module and records the number of step accumulations; the group sliding filter submodule judges the number of step accumulations, and after reaching the step accumulation set value, the accumulated data is divided into a group and a trigger signal is generated. The trigger signal is monitored to determine whether to output the filter signal and update the signal.

[0035] Among them, the first group accumulation module performs the accumulation of the next group of output data and records the number of step accumulations while the group sliding filter submodule performs the step accumulation number judgment process;

[0036] In the group sliding filter submodule, it is determined whether the number of step accumulations has reached the step accumulation setting value. After reaching the step accumulation setting value, the accumulated data is grouped into one group, a trigger signal Trig is generated, and the trigger signal Trig is judged. When the Trig signal is detected to be valid, a sliding group update signal Trig_r1 is generated. If the Trig signal is invalid, it continues to wait until the subsequent trigger signal Trig is valid.

[0037] At the same time, the sliding group update signal Trig_r1 is judged. When the sliding group update signal Trig_r1 is valid, the current accumulated output data is processed by sliding filtering and retained, the next group of output data accumulated by the first group accumulation module is grouped, and the sliding filter register group in the secondary group sliding filter submodule is updated using the retained current accumulated output data, and the current accumulated output data update completion flag Trig_r2 is generated. After all register groups are updated, the validity of the trigger signal Trig for the next group of output data is judged until all output data of the AD chip are traversed;

[0038] Specifically, the AD acquisition module, the first group accumulation module, and the group sliding filter submodule can all be implemented through the FPGA architecture.

[0039] According to the logic filtering system, a high-reliability and low-fan-out logic filtering method for eddy current small signals is proposed:

[0040] (1) Monitor the busy signal Busy of the AD chip. When the falling edge of the busy signal Busy of the AD chip is detected, stop the self-calibration of the AD chip and output the data collection timing of the AD chip;

[0041] Before monitoring the busy signal Busy of the AD chip, start the eddy current displacement sensor, start the AD chip initialization process, and output the AD chip self-calibration timing;

[0042] (2) Continuously collect the data output by the AD chip, accumulate the output data and record the number of step accumulations;

[0043] After the trigger signal Trig is generated, the next set of data is collected and step-accumulated while the trigger signal Trig is monitored. If the number of step accumulations does not reach the step accumulation setting value, the output data is continuously accumulated.

[0044] The output data is accumulated to complete the superposition and amplification of weak signals. The specific steps are as follows:

[0045] Assume that the step accumulation setting value is n, and the data output by the AD chip is Di;

[0046] The sum of every n data Di obtained by AD conversion is used to obtain the accumulated value N j ;

[0047] in,

[0048] N j Output to the group sliding filter submodule, and output Trig signal at the same time, marking a group of data N in the first grouping j The processing has been completed, and the data is subjected to sliding filtering;

[0049] Repeat the above operation until all the output data of the current group are processed to realize the real-time collection and amplification of the AD chip data;

[0050] (3) judging the number of step accumulation times, and when reaching the step accumulation setting value, grouping the accumulated data into one group, generating a trigger signal Trig, and entering step (4) to judge the trigger signal Trig, and returning to step (2) to collect and step accumulate the next group of data;

[0051] If the falling edge of the AD chip busy signal Busy is not detected, the AD chip self-calibration failure flag is set to be valid, and the AD chip self-calibration is performed again when the next instruction arrives;

[0052] (4) When the Trig signal is detected to be valid, a sliding filter process is performed and the accumulated data is retained to generate a dynamic group update signal Trig_r1, and then the process goes to step (5). If the Trig signal is invalid, the process continues to wait for the Trig signal until it is valid.

[0053] When sliding filtering is performed on the data, the values ​​of each register in the register group of the previous cycle retained by the group sliding filtering submodule are used to calculate the filtering results with the current data, specifically:

[0054]

[0055] In the formula, S k is the value of each register in the register group of the previous cycle, N j t The current accumulated amplified data is filtered and retained in the group sliding filter submodule after the calculation output is completed.

[0056] (5) When the Trig_r1 signal is detected to be valid, the accumulated first grouping data is input into the grouping sliding filter submodule, the next group of data is grouped, and the grouping update completion flag Trig_r2 of the current accumulated output data is generated. The sliding filter register group in the secondary grouping sliding filter submodule is updated using the retained current accumulated output data. After all register groups are updated, the validity of the trigger signal Trig of the next group of output data is judged until all output data of the AD chip are traversed;

[0057] In step (5), when updating each register of the group sliding filter submodule, each register data in the sliding filter register group of the current cycle is updated in reverse order according to the register index sequence to complete the decoupling of the filter data.

[0058] The following is further described based on specific embodiments:

[0059] In the current embodiment, FPGA is used to implement the flow chart as shown in the following figure: Figure 1 , 2 As shown in the figure, it is a logic filtering method with high reliability and low fan-out for eddy current small signals. The corresponding functional modules can be the AD acquisition module designed on FPGA, the first group accumulation module, and the group sliding filter submodule. The whole process is carried out under the control of the process control module. After the eddy current displacement sensor is started, the AD acquisition module initializes the AD chip and performs self-calibration timing, and detects the falling edge of the AD chip busy signal Busy, and outputs the AD chip data acquisition timing data; the first group accumulation module accumulates the output data according to the AD acquisition module and records the number of step accumulations; the group sliding filter submodule judges the number of step accumulations. After reaching the step accumulation set value, the accumulated data is divided into a group and a trigger signal is generated. The trigger signal is monitored to determine whether to output the filter signal and update the signal.

[0060] The specific process is as follows:

[0061] (1) After the eddy current displacement sensor is started, the AD chip initialization process starts by default, the AD chip self-calibration timing is output, and the falling edge of the AD chip busy signal Busy is monitored, and step (2) is performed;

[0062] (2) When the falling edge of the AD chip busy signal Busy is detected, the AD chip self-calibration is stopped and a judgment is made. If the self-calibration is completed, the AD chip data acquisition timing is output and step (3) is performed. Otherwise, the AD chip self-calibration failure flag is set to be valid and the AD chip self-calibration is performed again after the next instruction arrives.

[0063] (3) Start outputting the AD chip continuous acquisition timing, continuously acquire the data output by the AD chip, accumulate the output data and record the number of step accumulations, and proceed to step (4);

[0064] (4) judging the number of step accumulation times, and when reaching the step accumulation setting value, dividing the accumulated data into one group, and generating a trigger signal Trig to start step (5) and return to step (3) to collect and step accumulate the next group of data, otherwise, continue to accumulate the output data;

[0065] The first grouping is to accumulate the data collected by the AD chip for the first time to complete the superposition and amplification of weak signals. The specific steps are as follows:

[0066] Assume that the step accumulation setting value is 8, and the data output by the AD chip is Di;

[0067] First, sum each 8 data Di obtained by AD conversion to get the accumulated value N j ;

[0068] (Note: Di is a signed number);

[0069] Then N j Output to the sliding filter submodule, and output Trig signal at the same time, marking a group of data N in the first grouping j The processing has been completed and sliding filtering can be performed;

[0070] Finally, repeat the above operations to realize real-time acquisition and amplification of AD chip data.

[0071] (5) When the Trig signal is detected to be valid, the filtering result of the previous cycle is output and the sliding group update signal Trig_r1 is output, and step (6) is performed; otherwise, the Trig signal is continued to be valid;

[0072] When outputting the filtering result of the previous cycle, the filtering result is calculated using the values ​​of each register in the register group of the sliding filter submodule in the previous cycle and the data accumulated and amplified in the current first grouping.

[0073]

[0074] Among them, S k is the sliding filter result of the previous cycle, N j t The value obtained by current accumulation and amplification;

[0075] After the calculation output is completed, the current accumulated and amplified data is added to the sliding filter submodule register group to participate in the sliding filter operation. This is the first level of pipeline.

[0076] (6) When the Trig_r1 signal is detected to be valid, the accumulated first grouping data is input into the sliding filter submodule, and the sliding filter register group is updated in order after the second grouping. After each update, the current group update completion flag Trig_r2 is generated. When all register groups after the second grouping are updated, return to step (5) and continue to judge the signal validity until the data output by all AD chips are collected and accumulated. Otherwise, wait for the current group update completion flag Trig_r2 and repeat the current step;

[0077] When updating each register in the sliding filter register group, the "reverse order" group update operation is adopted. The specific operation steps are as follows:

[0078] Assume the sliding filter window is 16;

[0079] At time t,

[0080] …

[0081] At t+3,

[0082] The four-stage pipeline is used to update the register data in the current cycle's sliding filter register group in reverse order according to the register index sequence, ensuring that the data used in the calculation of the result in the next cycle are all from the same acquisition cycle, completing the decoupling of the filter data.

[0083] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

[0084] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A high-reliability and low-fan-out logic filtering system for eddy current small signals, characterized by: It includes an eddy current displacement sensor, an AD acquisition module, a first group accumulation module, and a group sliding filter submodule. After the eddy current displacement sensor is started, the AD acquisition module initializes the AD chip and performs self-calibration timing, detects the falling edge of the AD chip busy signal Busy, and outputs the AD chip data acquisition timing data; the first group accumulation module accumulates the output data according to the AD acquisition module and records the number of step accumulations; The group sliding filter submodule judges the number of step accumulations. When the step accumulation setting value is reached, the accumulated data is grouped into one group and a trigger signal is generated. The trigger signal is monitored to determine whether to output the filter signal and update the signal. The filter logic system composed of the eddy current displacement sensor, AD acquisition module, first group accumulation module and group sliding filter submodule performs signal acquisition and data filtering on the AD chip. The first group accumulation module performs the accumulation of the next group of output data and records the number of step accumulations while the group sliding filter submodule performs the step accumulation number judgment process; In the group sliding filter submodule, the sliding group update signal Trig_r1 is judged. When the sliding group update signal Trig_r1 is valid, the current accumulated output data is subjected to sliding filtering processing and retained, the next group of output data accumulated and processed by the first group accumulation module is grouped, and the sliding filter register group in the secondary group sliding filter submodule is updated using the retained current accumulated output data, and the current accumulated output data update completion flag Trig_r2 is generated. After all register groups are updated, the validity of the trigger signal Trig for the next group of output data is judged until all output data of the AD chip are traversed.

2. According to claim 1, a logic filtering system for eddy current small signals with high reliability and low fan-out, characterized in that: In the group sliding filter submodule, it is determined whether the number of step accumulations has reached the step accumulation setting value. After reaching the step accumulation setting value, the data accumulated this time is divided into a group, a trigger signal Trig is generated, and the trigger signal Trig is judged. When the Trig signal is detected to be valid, a sliding group update signal Trig_r1 is generated. If the Trig signal is invalid, it continues to wait until the subsequent trigger signal Trig is valid.

3. The high-reliability and low-fan-out logic filtering system for eddy current small signals according to claim 1 is characterized in that: The AD acquisition module, the first group accumulation module, and the group sliding filter submodule are all implemented through the FPGA architecture.

4. A filtering method implemented by the logic filtering system for eddy current small signal high reliability and low fan-out according to claim 3, characterized in that The following steps are involved: (1) Monitor the busy signal Busy of the AD chip. When the falling edge of the busy signal Busy of the AD chip is detected, stop the self-calibration of the AD chip and output the data acquisition timing of the AD chip; (2) Continuously collect the data output by the AD chip, accumulate the output data and record the number of step accumulations; (3) judging the number of step accumulation times, and when reaching the step accumulation setting value, grouping the accumulated data into one group, generating a trigger signal Trig, and entering step (4) to judge the trigger signal Trig, and returning to step (2) to collect and step accumulate the next group of data; (4) When the Trig signal is detected to be valid, a sliding filter process is performed and the accumulated data is retained to generate a dynamic group update signal Trig_r1, and then the process goes to step (5). If the Trig signal is invalid, the process continues to wait for the Trig signal until it is valid. (5) When the Trig_r1 signal is detected to be valid, the accumulated first grouping data is input into the group sliding filter submodule, the next group of data is grouped, and the group update completion flag Trig_r2 of the current accumulated output data is generated. The sliding filter register group in the secondary group sliding filter submodule is updated using the retained current accumulated output data. After all register groups are updated, the validity of the trigger signal Trig for the next group of output data is judged until all output data of the AD chip are traversed.

5. The filtering method according to claim 4, characterized in that: In the step (1), before monitoring the busy signal Busy of the AD chip, the eddy current displacement sensor is started, the AD chip initialization process is started, and the AD chip self-calibration timing is output.

6. The filtering method according to claim 5, characterized in that: In the step (3), if the falling edge of the AD chip busy signal Busy is not detected, the AD chip self-calibration failure flag is set to be valid, and the AD chip self-calibration is performed again after the next instruction arrives.

7. The filtering method according to claim 6, characterized in that: In the step (2), after the trigger signal Trig is generated, the trigger signal Trig is monitored while the next set of data is collected and step-accumulated. If the number of step accumulations does not reach the step accumulation setting value, the output data is continuously accumulated.

8. The filtering method according to claim 7, characterized in that: In step (2), the output data is accumulated to complete the superposition amplification of the weak signal. The specific steps are as follows: Assume that the step accumulation setting value is n, and the data output by the AD chip is Di; The sum of every n data Di obtained by AD conversion is used to obtain the accumulated value N j ; in, N j Output to the group sliding filter submodule, and output Trig signal at the same time, marking a group of data N in the first grouping j The processing has been completed, and the data is subjected to sliding filtering; Repeat the above operation until all the output data of the current group are processed to achieve real-time acquisition and amplification of AD chip data.

9. The filtering method according to claim 8, characterized in that: When sliding filtering is performed on the data, the values ​​of each register in the register group of the previous cycle retained by the group sliding filtering submodule are used to calculate the filtering results with the current data, specifically: In the formula, S k is the value of each register in the register group of the previous cycle, N j t The current accumulated amplified data is filtered and retained in the group sliding filter submodule after the calculation output is completed.

10. The filtering method according to claim 9, characterized in that: In the step (5), when updating each register of the group sliding filter submodule, each register data in the sliding filter register group of the current cycle is updated in reverse order according to the register index sequence to complete the decoupling of the filter data.

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