Serial input control driver chip and driving method thereof

Abstract

The present invention discloses a serial input control driver chip and a driving method thereof. The driving method of the serial input control driver chip comprises step S1: configuring the working mode of the chip according to the peripheral configuration pins of the serial input control driver chip; step S1.1: when the configuration pins are configured in cascade mode, the chip works in cascade mode, and the signal inputted by the input pins is a pulse signal or serial data, so that a preset number of output pins output in sequence according to the input pulse or output in series at the same time according to the input. The serial input control driver chip and the driving method thereof disclosed by the present invention make the peripheral circuit of the chip simple, have fewer input pins, can rely on the peripheral pins to configure the working mode of the chip, the input control signal can be serial data and pulse signal, the output can be output in sequence according to the input signal, and the chip can work in cascade mode, synchronous mode and single mode.

Description

Technical Field

[0001] The present invention belongs to the technical field of stepper motor drive chips, and in particular relates to a serial input control drive chip and a drive method of the serial input control drive chip. Background Art

[0002] At present, five-wire four-phase stepper motors, digital tubes and LEDs are mostly driven by Darlington integrated circuits. Darlington integrated circuits are simple to control, and the input control signals correspond to the output signals one by one. However, there are many input control signals, many microcontroller pins are required, and the output timing is completely controlled by the microcontroller. Proprietary motor driver chips have good motor control effects, but require complex peripheral circuits, complex control methods, and cannot drive digital tubes and LEDs.

[0003] Therefore, further improvements are made to the above problems. Summary of the invention

[0004] The main purpose of the present invention is to provide a serial input control driver chip and a driving method thereof, which makes the chip peripheral circuit simple, has fewer input pins, and can configure the working mode of the chip based on the peripheral pins. The input control signal can be serial data and pulse signal, and the output can be output in sequence according to the input signal. The chip can work in cascade mode, synchronous mode and single mode.

[0005] Another object of the present invention is to provide a serial input control driving chip and a driving method thereof, which can perform serial input control, parallel output and sequential output.

[0006] Another object of the present invention is to provide a serial input control driver chip and a driving method thereof, which improves the overcurrent capability, and the output pins output sequentially or simultaneously according to the input signal. The input signal is small, the peripheral circuit is simple, and it can be used for five-wire four-phase stepping motors, digital tubes and LED driving.

[0007] To achieve the above object, the present invention provides a driving method of a serial input control driving chip for driving a stepping motor, comprising the following steps:

[0008] Step S1: configuring the working mode of the chip (serial input control driver chip) according to the peripheral configuration pins of the serial input control driver chip;

[0009] Step S1.1: When the configuration pin is configured in cascade mode, the chip works in cascade mode, and according to the input signal of the input pin being a pulse signal or serial data, a preset number of output pins (several output pins corresponding to several Darlington transistors) output in sequence according to the input pulse or output simultaneously according to the input serial;

[0010] Step S1.2: When the pins are configured in synchronous mode, the chip works in synchronous mode, a preset number of output pins are divided into a first group of output pins and a second group of output pins, and according to different input signals of the input pins, the first group of output pins and the second group of output pins are simultaneously output in different orders;

[0011] Step S1.3: When the configuration pins are configured in separate mode, the chip works in separate mode, and a preset number of output pins are divided into a first group of output pins and a second group of output pins, and each group of output pins corresponds to an input pin, and based on whether the input signal of the input pin reaches a threshold, all output pins of the group of output pins corresponding to the input pin are output at the same time, so as to control each group of output pins individually.

[0012] As a further preferred technical solution of the above technical solution, step S1.1 is specifically implemented as follows:

[0013] Step S1.1.1: The input signal is a pulse signal, and the input signal is input from input pin IN1 (also In1), input pin DIR1 (also dir1) and input pin DIR2 (also dir2). Input pin IN1 inputs a pulse signal and input pins DIR1 and DIR2 input a high level or a low level. When input pins DIR1 and DIR2 input a high level, output pins out0-out7 (8) of the respective Darlington tubes are sequentially output according to the input pulse. When input pins DIR1 and DIR2 input a low level, output pins out7-out0 of the respective Darlington tubes are sequentially output according to the input pulse.

[0014] Step S1.1.2: The input signal is serial data. The input signal is input from input pin IN1 and input pin clk. Input pin IN1 inputs serial data and input pin clk inputs clock signal. The serial data corresponds to 8 Darlington tubes in sequence. When the serial data is full of 8 bits, output pins out0-out7 (8) output at the same time. When the serial data is less than 8 bits, output pins out0-out7 do not output.

[0015] As a further preferred technical solution of the above technical solution, step S1.2 is specifically implemented as the following steps, the first group of output pins includes output pin out0, output pin out1, output pin out2 and output pin out3, the second group of output pins includes output pin out4, output pin out5, output pin out6 and output pin out7, and each output pin corresponds to a Darlington tube:

[0016] Step S1.2.1: When the input pin IN1 inputs a pulse signal and the input pin DIR1 inputs a high level, the output pins out0 and out4 are output at the same time, the output pins out1 and out5 are output at the same time, the output pins out2 and out6 are output at the same time, the output pins out3 and out7 are output at the same time, and with the pulse input of the input pin IN1, the output pins out0-out3 and the output pins out4-out7 are output in sequence;

[0017] Step S1.2.2: When a pulse signal is input to input pin IN1 and a low level is input to input pin DIR1, output pin out3 and output pin out7 are output at the same time, output pin out2 and output pin out6 are output at the same time, output pin out1 and output pin out5 are output at the same time, output pin out0 and output pin out4 are output at the same time, and with the pulse input of input pin IN1, output pins out3-out0 and output pins out7-out4 are output in sequence.

[0018] As a further preferred technical solution of the above technical solution, step S1.3 is specifically implemented as the following steps, the first group of output pins includes output pin out0, output pin out1, output pin out2 and output pin out3, the second group of output pins includes output pin out4, output pin out5, output pin out6 and output pin out7, and each output pin corresponds to a Darlington tube:

[0019] Step S1.3.1: The serial data input by the input pin IN1 corresponds to the Darlington transistors corresponding to the first group of output pins in sequence, and when the serial data input by the input pin IN1 is full of 4 bits, the output pins out0-out3 are output at the same time. When the serial data input by the input pin IN1 is less than 4 bits, the output pins out0-out3 are not output, and the high and low levels of the input pin DIR1 are changed, thereby changing the corresponding relationship of the serial data input by the input pin IN1 (such as Figure 6 As shown, when the input pin DIR1 inputs a high level and the input pin IN1 inputs bit0, the output pin out0 corresponds to bit0. If the input pin DIR1 inputs a low level and the input pin IN1 inputs bit0, the output pin out3 corresponds to bit0. The corresponding order of the corresponding input and output is changed, and step S1.3.2 is the same);

[0020] Step S1.3.2: The serial data input by the input pin IN2 corresponds to the Darlington transistors corresponding to the second group of output pins in sequence, and when the serial data input by the input pin IN2 is full of 4 bits, the output pins out4-out7 are output at the same time. When the serial data input by the input pin IN2 is less than 4 bits, the output pins out4-out7 are not output, and the high and low levels of the input pin DIR2 are changed, thereby changing the corresponding relationship of the serial data input by the input pin IN1.

[0021] To achieve the above purpose, the present invention also provides a serial input control driver chip, which is applied to the driving method of the serial input control driver chip, including input pins, configuration pins, phase shifters, phase locks, mode decoding circuits and a plurality of Darlington transistors, wherein:

[0022] The input pins are electrically connected to the phase shifter, and the input pins include an input pin IN1, an input pin IN2, an input pin DIR1, an input pin DIR2, and an input pin CLK. The input pins IN1 and IN2 are used to input serial data and output the serial data in parallel to the Darlington tube or to input pulse signals and output the pulse signals sequentially to the Darlington tube. The input pins DIR1 and DIR2 are used to input a high level or a low level, and the input pin CLK is used to input a clock signal.

[0023] The configuration pins include configuration pin mode0, configuration pin mode1 and configuration pin mode2, the configuration pin mode0, configuration pin mode1 and configuration pin mode2 are electrically connected to the mode decoding circuit respectively, and the mode decoding circuit is used to configure the working mode of the chip according to the information of the configuration pins;

[0024] Each Darlington tube has an independent output pin.

[0025] As a further preferred technical solution of the above technical solution, the phase shifter includes a first phase shifter and a second phase shifter, the phase locker includes a first phase locker and a second phase locker, the first phase locker is electrically connected to the first phase shifter and the second phase locker is electrically connected to the second phase shifter.

[0026] As a further preferred technical solution of the above technical solution, the Darlington tube includes a first Darlington tube, a second Darlington tube, a third Darlington tube, a fourth Darlington tube, a fifth Darlington tube, a sixth Darlington tube, a seventh Darlington tube and an eighth Darlington tube, wherein:

[0027] The first phase shifter is electrically connected to the input pin IN1 and the input pin DIR1 respectively, and the first Darlington tube, the second Darlington tube, the third Darlington tube and the fourth Darlington tube are electrically connected to the first phase shifter respectively;

[0028] The second phase shifter is electrically connected to the input pin IN2 and the input pin DIR2 respectively, and the fifth Darlington transistor, the sixth Darlington transistor, the seventh Darlington transistor and the eighth Darlington transistor are electrically connected to the second phase shifter respectively.

[0029] As a further preferred technical solution of the above technical solution, each of the Darlington transistors includes a resistor R1, a resistor R2, a resistor R3, a transistor Q1, a transistor Q2, a diode D1, a diode D2 and a diode D3, wherein:

[0030] The resistor R1 is electrically connected to the phase shifter, and one end of the resistor R1 away from the phase shifter is electrically connected to the base of the transistor Q1. The base of the transistor Q1 is also connected to the output pin through the resistor R2, the resistor R3 and the diode D3 in sequence. The bases of the transistor Q1 and the transistor Q2 are electrically connected to the common end of the resistor R2 and the resistor R3, respectively. The emitter of the transistor Q2 is electrically connected to the common end of the resistor R3 and the diode D3.

[0031] The collectors of the transistor Q1 and the transistor Q2 are respectively connected to the power supply terminal VCC and the collector of the transistor Q2 is also connected to the output pin through the diode D2. One end of the resistor R1 close to the phase shifter is also grounded through the diode D1.

[0032] As a further preferred technical solution of the above technical solution, the serial input control driver chip further includes a power pin VCC and a ground pin GND. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is an internal structure diagram of the serial input control driving chip and the driving method thereof of the present invention.

[0034] Figure 2 It is a working mode diagram of the serial input control driving chip and the driving method thereof of the present invention.

[0035] Figure 3 It is a timing diagram of the serial input control driving chip and the driving method thereof of the present invention when they work in cascade mode and the input signal is serial data.

[0036] Figure 4It is a timing diagram of the serial input control driving chip and the driving method thereof of the present invention when they work in cascade mode and the input signal is a pulse signal.

[0037] Figure 5 It is a timing diagram of the serial input control driving chip and the driving method thereof of the present invention working in a synchronous mode.

[0038] Figure 6 It is a timing diagram of the serial input control driving chip and the driving method thereof of the present invention working in a single mode. DETAILED DESCRIPTION

[0039] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the present invention.

[0040] In the preferred embodiment of the present invention, those skilled in the art should note that the power supply and ground etc. involved in the present invention can be regarded as prior art.

[0041] Preferred embodiments.

[0042] The present invention discloses a driving method of a serial input control driving chip, which is used to drive a stepping motor, and comprises the following steps:

[0043] Step S1: configuring the working mode of the chip (serial input control driver chip) according to the peripheral configuration pins of the serial input control driver chip;

[0044] Step S1.1: When the configuration pin is configured in cascade mode, the chip works in cascade mode, and according to the input signal of the input pin being a pulse signal or serial data, a preset number of output pins (several output pins corresponding to several Darlington transistors) output in sequence according to the input pulse or output simultaneously according to the input serial;

[0045] Step S1.2: When the pins are configured in synchronous mode, the chip works in synchronous mode, a preset number of output pins are divided into a first group of output pins and a second group of output pins, and according to different input signals of the input pins, the first group of output pins and the second group of output pins are simultaneously output in different orders;

[0046] Step S1.3: When the configuration pins are configured in separate mode, the chip works in separate mode, and a preset number of output pins are divided into a first group of output pins and a second group of output pins, and each group of output pins corresponds to an input pin, and based on whether the input signal of the input pin reaches a threshold, all output pins of the group of output pins corresponding to the input pin are output at the same time, so as to control each group of output pins individually.

[0047] Specifically, step S1.1 is implemented as follows:

[0048] Step S1.1.1: The input signal is a pulse signal, and the input signal is input from input pin IN1 (also In1), input pin DIR1 (also dir1) and input pin DIR2 (also dir2). Input pin IN1 inputs a pulse signal and input pins DIR1 and DIR2 input a high level or a low level. When input pins DIR1 and DIR2 input a high level, output pins out0-out7 (8) of the respective Darlington tubes are sequentially output according to the input pulse. When input pins DIR1 and DIR2 input a low level, output pins out7-out0 of the respective Darlington tubes are sequentially output according to the input pulse.

[0049] Step S1.1.2: The input signal is serial data. The input signal is input from input pin IN1 and input pin clk. Input pin IN1 inputs serial data and input pin clk inputs clock signal. The serial data corresponds to 8 Darlington tubes in sequence. When the serial data is full of 8 bits, output pins out0-out7 (8) output at the same time. When the serial data is less than 8 bits, output pins out0-out7 do not output.

[0050] More specifically, step S1.2 is specifically implemented as the following steps, the first group of output pins includes output pin out0, output pin out1, output pin out2 and output pin out3, the second group of output pins includes output pin out4, output pin out5, output pin out6 and output pin out7, and each output pin corresponds to a Darlington transistor:

[0051] Step S1.2.1: When the input pin IN1 inputs a pulse signal and the input pin DIR1 inputs a high level, the output pins out0 and out4 are output at the same time, the output pins out1 and out5 are output at the same time, the output pins out2 and out6 are output at the same time, the output pins out3 and out7 are output at the same time, and with the pulse input of the input pin IN1, the output pins out0-out3 and the output pins out4-out7 are output in sequence;

[0052] Step S1.2.2: When a pulse signal is input to input pin IN1 and a low level is input to input pin DIR1, output pin out3 and output pin out7 are output at the same time, output pin out2 and output pin out6 are output at the same time, output pin out1 and output pin out5 are output at the same time, output pin out0 and output pin out4 are output at the same time, and with the pulse input of input pin IN1, output pins out3-out0 and output pins out7-out4 are output in sequence.

[0053] Furthermore, step S1.3 is specifically implemented as the following steps, the first group of output pins includes output pin out0, output pin out1, output pin out2 and output pin out3, the second group of output pins includes output pin out4, output pin out5, output pin out6 and output pin out7, and each output pin corresponds to a Darlington transistor:

[0054] Step S1.3.1: The serial data input by the input pin IN1 corresponds to the Darlington transistors corresponding to the first group of output pins in sequence, and when the serial data input by the input pin IN1 is full of 4 bits, the output pins out0-out3 are output at the same time. When the serial data input by the input pin IN1 is less than 4 bits, the output pins out0-out3 are not output, and the high and low levels of the input pin DIR1 are changed, thereby changing the corresponding relationship of the serial data input by the input pin IN1 (such as Figure 6 As shown, when the input pin DIR1 inputs a high level and the input pin IN1 inputs bit0, the output pin out0 corresponds to bit0. If the input pin DIR1 inputs a low level and the input pin IN1 inputs bit0, the output pin out3 corresponds to bit0. The corresponding order of the corresponding input and output is changed, and step S1.3.2 is the same);

[0055] Step S1.3.2: The serial data input by the input pin IN2 corresponds to the Darlington transistors corresponding to the second group of output pins in sequence, and when the serial data input by the input pin IN2 is full of 4 bits, the output pins out4-out7 are output at the same time. When the serial data input by the input pin IN2 is less than 4 bits, the output pins out4-out7 are not output, and the high and low levels of the input pin DIR2 are changed, thereby changing the corresponding relationship of the serial data input by the input pin IN1.

[0056] The present invention also discloses a serial input control driving chip, which is applied to a driving method of the serial input control driving chip, comprising an input pin, a configuration pin, a phase shifter, a phase lock, a mode decoding circuit and a plurality of Darlington transistors, wherein:

[0057] The input pins are electrically connected to the phase shifter, and the input pins include an input pin IN1 (equivalent to In1), an input pin IN2 (equivalent to In2), an input pin DIR1 (equivalent to dir1), an input pin DIR2 (equivalent to dir2), and an input pin CLK (equivalent to clk), the input pin IN1 and the input pin IN2 are used to input serial data and output the serial data in parallel to the Darlington tube or to input pulse signals and output the pulse signals to the Darlington tube in sequence, the input pins DIR1 and DIR2 are used to input a high level or a low level, and the input pin CLK is used to input a clock signal;

[0058] The configuration pins include configuration pin mode0, configuration pin mode1 and configuration pin mode2, the configuration pin mode0, configuration pin mode1 and configuration pin mode2 are electrically connected to the mode decoding circuit respectively, and the mode decoding circuit is used to configure the working mode of the chip according to the information of the configuration pins;

[0059] Each Darlington tube has an independent output pin.

[0060] Specifically, the phase shifter includes a first phase shifter and a second phase shifter, the phase locker includes a first phase locker and a second phase locker, the first phase locker is electrically connected to the first phase shifter, and the second phase locker is electrically connected to the second phase shifter.

[0061] More specifically, the Darlington tube includes a first Darlington tube, a second Darlington tube, a third Darlington tube, a fourth Darlington tube, a fifth Darlington tube, a sixth Darlington tube, a seventh Darlington tube and an eighth Darlington tube, wherein:

[0062] The first phase shifter is electrically connected to the input pin IN1 and the input pin DIR1 respectively, and the first Darlington tube, the second Darlington tube, the third Darlington tube and the fourth Darlington tube are electrically connected to the first phase shifter respectively;

[0063] The second phase shifter is electrically connected to the input pin IN2 and the input pin DIR2 respectively, and the fifth Darlington transistor, the sixth Darlington transistor, the seventh Darlington transistor and the eighth Darlington transistor are electrically connected to the second phase shifter respectively.

[0064] Furthermore, each of the Darlington transistors includes a resistor R1, a resistor R2, a resistor R3, a transistor Q1, a transistor Q2 (the transistor Q1 and the transistor Q2 are connected in the form of a Darlington transistor), a diode D1, a diode D2 and a diode D3, wherein:

[0065] The resistor R1 is electrically connected to the phase shifter, and one end of the resistor R1 away from the phase shifter is electrically connected to the base of the transistor Q1. The base of the transistor Q1 is also connected to an output pin (e.g., out0) through the resistor R2, the resistor R3, and the diode D3 in sequence. The bases of the transistor Q1 and the transistor Q2 are electrically connected to the common end of the resistor R2 and the resistor R3, respectively. The emitter (grounded) of the transistor Q2 is electrically connected to the common end of the resistor R3 and the diode D3.

[0066] The collectors of the transistor Q1 and the transistor Q2 are respectively connected to the power supply terminal VCC and the collector of the transistor Q2 is also connected to the output pin through the diode D2. One end of the resistor R1 close to the phase shifter is also grounded through the diode D1.

[0067] Furthermore, the serial input control driver chip also includes a power pin VCC and a ground pin GND.

[0068] Preferably, the two phase shifters of the present invention can be cascaded, and the data inputted through the input pin IN1 is sequentially shifted into the corresponding register (located in the phase lock);

[0069] Two phase shifters can be used separately, one phase shifter corresponds to IN1 and DIR1 inputs, corresponding to four Darlington tubes, and the other phase shifter corresponds to IN2 and DIR2 inputs, corresponding to the remaining four Darlington tubes;

[0070] The data in the phase shifter can be output to the Darlington tube at the same time;

[0071] 8-way Darlington tubes work in parallel;

[0072] Two phase lockers can be cascaded to latch the data in the phase shifter in real time;

[0073] Two phase lockers can correspond to phase shifters individually and lock the data in their respective phase shifters in real time;

[0074] The data in the phase lock can be read into the phase shifter at any time;

[0075] The mode decoding circuit can configure the present invention to work in cascade mode, synchronous mode and single mode according to the information of the configuration pins mode0, mode1 and mode2;

[0076] IN1 and IN2 can receive serial data or pulse signals. Serial signals are output to Darlington tubes in parallel, and pulse signals are output to Darlington tubes in sequence.

[0077] DIR1 and DIR2 can be high level or low level. When high level, when receiving IN1 receives a pulse signal, the Darlington tube outputs in sequence. In single mode, the four-way output sequence is out0, out1, out2 and out3, and the other four-way output sequence is out4, out5, out6 and out7. When low level, the Darlington tube outputs in sequence. In single mode, the four-way output sequence is out3, out2, out1 and out0, and the other four-way output sequence is out7, out6, out5 and out4.

[0078] clk receives the clock signal. When IN1 and IN2 receive serial signals, clk serves as the clock input. When IN1 and IN2 receive pulse signals, clk is left floating.

[0079] mode0, mode1 and mode2 can be high level, low level and floating.

[0080] Preferably, the present invention includes a power supply (power pin VCC), a ground (ground pin GND), a data input pin, a configuration pin, an output pin, a phase shifter, a latch (phase lock) and a Darlington tube. The power supply and the ground provide power to the chip. The data input pin controls the input signal. The input signal includes a pulse signal, serial data, a clock and a direction. The configuration pin configures the working mode of the chip, which is mainly a high and low level. The output pin is a power output. The phase shifter shifts the input serial data to the corresponding Darlington tube input terminal. The latch latches the data in the phase shifter. The Darlington tube is the power output part.

[0081] Preferably, the principle of the present invention is:

[0082] When the configuration pin is configured in cascade mode, the chip works in cascade mode. First, the signal is input from IN1 and DIR. IN1 input is a pulse signal. DIR is high or low. When DIR is high, the output pins out0~out7 are output in sequence according to the input pulse. When DIR is low, the output pins out7~out0 are output in sequence according to the input pulse. Second, the signal is input from IN1 and the clock. IN1 input is serial data. The serial data corresponds to 8 Darlington tubes in sequence. When the data is full of 8 bits, it is output from the output end at the same time. When the data is less than 8 bits, the output end does not output data.

[0083] When the pins are configured in synchronous mode, the chip works in synchronous mode, the signals are input from IN1 and DIR1, the IN1 input is a pulse signal, the DIR1 input is a high and low level, out0~out3 are a group, out4~out7 are a group, out0 and out4 are output at the same time, out1 and out5 are output at the same time, out2 and out6 are output at the same time, out3 and out7 are output at the same time, with the IN1 pulse input, out0~out3, out4~out7 are output in sequence.

[0084] When the configuration pin is configured in single mode, the chip works in single mode, and the signals are input from IN1 and DIR1, IN2 and DIR2, and clk. IN1 and IN2 input serial data, DIR1 and DIR2 input high and low levels, IN1 serial data corresponds to the first four Darlington tubes in sequence, IN2 serial data corresponds to the last four Darlington tubes in sequence, when the data is full of 4 bits, it is output from the output end at the same time, when the data is less than 4 bits, the output end does not output data, and the high and low levels of DIR1 and DIR2 are changed to change the corresponding relationship between the serial data inputted by IN1 and IN2.

[0085] It is worth mentioning that the technical features such as power supply and ground involved in the patent application of this invention should be regarded as prior art. The specific structure, working principle and possible control method and spatial layout method of these technical features can be selected according to the conventional selection in the field, and should not be regarded as the inventive point of this patent. This patent will not be further elaborated.

[0086] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A driving method of a serial input control driving chip for driving a stepping motor, characterized in that: The following steps are involved: Step S1: configuring the working mode of the chip according to the peripheral configuration pins of the serial input control driver chip; Step S1.1: When the configuration pin is configured in cascade mode, the chip works in cascade mode, and the signal input by the input pin is a pulse signal or serial data, so that a preset number of output pins output in sequence according to the input pulse or output simultaneously according to the input serial; Step S1.2: When the pins are configured in synchronous mode, the chip works in synchronous mode, a preset number of output pins are divided into a first group of output pins and a second group of output pins, and according to different input signals of the input pins, the first group of output pins and the second group of output pins are simultaneously output in different orders; Step S1.3: When the pins are configured in the separate mode, the chip works in the separate mode, and a preset number of output pins are divided into a first group of output pins and a second group of output pins, and each group of output pins corresponds to an input pin, and according to whether the input signal of the input pin reaches a threshold, all the output pins of the group of output pins corresponding to the input pin are output at the same time, so as to control each group of output pins separately; Step S1.3 is specifically implemented as the following steps, the first group of output pins includes output pin out0, output pin out1, output pin out2 and output pin out3, the second group of output pins includes output pin out4, output pin out5, output pin out6 and output pin out7, and each output pin corresponds to a Darlington transistor: Step S1.3.1: the serial data inputted by the input pin IN1 corresponds to the Darlington transistors corresponding to the first group of output pins in sequence, and when the serial data inputted by the input pin IN1 is full of 4 bits, the output pins out0-out3 output simultaneously, and when the serial data inputted by the input pin IN1 is less than 4 bits, the output pins out0-out3 do not output, and the high and low levels of the input pin DIR1 are changed, thereby changing the corresponding relationship of the serial data inputted by the input pin IN1; Step S1.3.2: The serial data input by the input pin IN2 corresponds to the Darlington transistors corresponding to the second group of output pins in sequence, and when the serial data input by the input pin IN2 is full of 4 bits, the output pins out4-out7 are output at the same time. When the serial data input by the input pin IN2 is less than 4 bits, the output pins out4-out7 are not output, and the high and low levels of the input pin DIR2 are changed, thereby changing the corresponding relationship of the serial data input by the input pin IN1.

2. The driving method of a serial input control driving chip according to claim 1, characterized in that: Step S1.1 is specifically implemented as follows: Step S1.1.1: The input signal is a pulse signal, and the input signal is input from input pin IN1, input pin DIR1 and input pin DIR2. The input pin IN1 inputs a pulse signal and the input pins DIR1 and DIR2 input a high level or a low level. When the input pins DIR1 and DIR2 input a high level, the output pins out0-out7 of the respective Darlington tubes are output in sequence according to the input pulse. When the input pins DIR1 and DIR2 input a low level, the output pins out7-out0 of the respective Darlington tubes are output in sequence according to the input pulse. Step S1.1.2: The input signal is serial data. The input signal is input from input pin IN1 and input pin clk. Input pin IN1 inputs serial data and input pin clk inputs clock signal. The serial data corresponds to 8 Darlington tubes in sequence. When the serial data is full of 8 bits, output pins out0-out7 output at the same time. When the serial data is less than 8 bits, output pins out0-out7 do not output.

3. The driving method of a serial input control driving chip according to claim 2, characterized in that: Step S1.2 is specifically implemented as the following steps, the first group of output pins includes output pin out0, output pin out1, output pin out2 and output pin out3, the second group of output pins includes output pin out4, output pin out5, output pin out6 and output pin out7, and each output pin corresponds to a Darlington transistor: Step S1.2.1: When a pulse signal is input to the input pin IN1 and a high level is input to the input pin DIR1, the output pins out0 and out4 are output at the same time, the output pins out1 and out5 are output at the same time, the output pins out2 and out6 are output at the same time, the output pins out3 and out7 are output at the same time, and with the pulse input of the input pin IN1, the output pins out0-out3 and the output pins out4-out7 are output in sequence; Step S1.2.2: When a pulse signal is input to input pin IN1 and a low level is input to input pin DIR1, output pin out3 and output pin out7 are output at the same time, output pin out2 and output pin out6 are output at the same time, output pin out1 and output pin out5 are output at the same time, output pin out0 and output pin out4 are output at the same time, and with the pulse input of input pin IN1, output pins out3-out0 and output pins out7-out4 are output in sequence.

4. A serial input control driver chip, characterized in that: A driving method for a serial input control driver chip as claimed in any one of claims 1 to 3, comprising an input pin, a configuration pin, a phase shifter, a phase lock, a mode decoding circuit and a plurality of Darlington transistors, wherein: The input pins are electrically connected to the phase shifter, and the input pins include an input pin IN1, an input pin IN2, an input pin DIR1, an input pin DIR2, and an input pin CLK. The input pins IN1 and IN2 are used to input serial data and output the serial data in parallel to the Darlington tube or to input pulse signals and output the pulse signals to the Darlington tube in sequence. The input pins DIR1 and DIR2 are used to input a high level or a low level, and the input pin CLK is used to input a clock signal. The configuration pins include configuration pin mode0, configuration pin mode1 and configuration pin mode2, the configuration pin mode0, configuration pin mode1 and configuration pin mode2 are electrically connected to the mode decoding circuit respectively, and the mode decoding circuit is used to configure the working mode of the chip according to the information of the configuration pins; Each Darlington tube has an independent output pin.

5. A serial input control driver chip according to claim 4, characterized in that: The phase shifter includes a first phase shifter and a second phase shifter, and the phase locker includes a first phase locker and a second phase locker, the first phase locker is electrically connected to the first phase shifter, and the second phase locker is electrically connected to the second phase shifter.

6. A serial input control driver chip according to claim 5, characterized in that: The Darlington tubes include a first Darlington tube, a second Darlington tube, a third Darlington tube, a fourth Darlington tube, a fifth Darlington tube, a sixth Darlington tube, a seventh Darlington tube and an eighth Darlington tube, wherein: The first phase shifter is electrically connected to the input pin IN1 and the input pin DIR1 respectively, and the first Darlington tube, the second Darlington tube, the third Darlington tube and the fourth Darlington tube are electrically connected to the first phase shifter respectively; The second phase shifter is electrically connected to the input pin IN2 and the input pin DIR2 respectively, and the fifth Darlington transistor, the sixth Darlington transistor, the seventh Darlington transistor and the eighth Darlington transistor are electrically connected to the second phase shifter respectively.

7. A serial input control driver chip according to claim 6, characterized in that: Each of the Darlington transistors includes a resistor R1, a resistor R2, a resistor R3, a transistor Q1, a transistor Q2, a diode D1, a diode D2 and a diode D3, wherein: The resistor R1 is electrically connected to the phase shifter, and one end of the resistor R1 away from the phase shifter is electrically connected to the base of the transistor Q1. The base of the transistor Q1 is also connected to the output pin through the resistor R2, the resistor R3 and the diode D3 in sequence. The bases of the transistor Q1 and the transistor Q2 are electrically connected to the common end of the resistor R2 and the resistor R3, respectively. The emitter of the transistor Q2 is electrically connected to the common end of the resistor R3 and the diode D3. The collector of the transistor Q1 and the collector of the transistor Q2 are respectively connected to the power supply terminal VCC and the collector of the transistor Q2 is also connected to the output pin through the diode D2. The end of the resistor R1 close to the phase shifter is also grounded through the diode D1.

8. A serial input control driver chip according to claim 7, characterized in that: The serial input control driver chip also includes a power pin VCC and a ground pin GND.

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