Register write suppression

Abstract

A technique for allocating registers to a processor is provided. The technique includes identifying a first instruction in an instruction dispatch set that satisfies all register allocation suppression criteria of a first set of register allocation suppression criteria, suppressing register allocation for the first instruction, identifying a second instruction in the instruction dispatch set that does not satisfy all register allocation suppression criteria of a second set of register allocation suppression criteria, and allocating registers for the second instruction.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of pending U.S. non-provisional patent application No. 16 / 697,147, entitled “Register Write Suppression,” filed November 26, 2019, the entire contents of which are hereby incorporated by reference. Background Technology

[0003] Register renaming is a technique that allows instructions with certain architectural register dependencies to still execute out of order in an out-of-order processor. More specifically, register renaming eliminates erroneous dependencies, thus preserving only true write-after-read data dependencies. Write-after-write and read-after-write are erroneous dependencies.

[0004] Register renaming allocates free physical registers in the register file used for writing instruction results to instructions. Furthermore, different physical registers are assigned to two instructions that write to registers in the same architecture. If these two instructions do not have a write-after-read data dependency, they may be dispatched out of order. While register renaming provides some benefits, the depth of speculative execution is limited by factors such as the number of physical registers available for allocation. Attached Figure Description

[0005] A more detailed understanding can be obtained from the following description, given by way of example in conjunction with the accompanying drawings:

[0006] Figure 1 It is a block diagram of an exemplary apparatus in which one or more of the disclosed embodiments may be implemented;

[0007] Figure 2 It is located in Figure 1 A block diagram of the instruction execution pipeline within the processor;

[0008] Figure 3 This illustrates an exemplary phase related to register renaming;

[0009] Figure 4 This illustrates techniques for physical register allocation to reduce register file pressure, based on examples; and

[0010] Figure 5 This is a flowchart illustrating a method for allocating physical registers in a register file to instructions, based on an example. Detailed Implementation

[0011] A technique for allocating registers to a processor is provided. The technique includes identifying a first instruction in an instruction dispatch set that satisfies all register allocation suppression criteria of a first set of register allocation suppression criteria, suppressing register allocation for the first instruction, identifying a second instruction in the instruction dispatch set that does not satisfy all register allocation suppression criteria of a second set of register allocation suppression criteria, and allocating registers for the second instruction.

[0012] Figure 1 This is a block diagram of an exemplary device 100 that implements aspects of the present disclosure. Device 100 includes, for example, a computer, gaming device, handheld device, set-top box, television, mobile phone, or tablet computer. Device 100 includes a processor 102, memory 104, storage device 106, one or more input devices 108, and one or more output devices 110. Device 100 may also optionally include an input driver 112 and an output driver 114. It should be understood that device 100 may include... Figure 1 Additional components not shown.

[0013] Processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and GPU located on the same die, or one or more processor cores, wherein each processor core is a CPU or a GPU. Memory 104 may be located on the same die as processor 102 or may be located separately from processor 102. Memory 104 includes volatile or non-volatile memory, such as random access memory (RAM), dynamic RAM, or cache.

[0014] Storage device 106 includes fixed or removable storage devices, such as hard disk drives, solid-state drives, optical disks, or flash drives. Input device 108 includes a keyboard, keypad, touchscreen, touchpad, detector, microphone, accelerometer, gyroscope, biometric scanner, or network connection (e.g., a wireless LAN card for transmitting and / or receiving wireless IEEE 802 signals). Output device 110 includes a display, speaker, printer, haptic feedback device, one or more lights, antenna, or network connection (e.g., a wireless LAN card for transmitting and / or receiving wireless IEEE 802 signals).

[0015] Input driver 112 communicates with processor 102 and input device 108, and allows processor 102 to receive input from input device 108. Output driver 114 communicates with processor 102 and output device 110, and allows processor 102 to send output to output device 110. It should be noted that input driver 112 and output driver 114 are optional components, and device 100 will operate in the same manner even without input driver 112 and output driver 114.

[0016] Figure 2 It is located in Figure 1 A block diagram of the instruction execution pipeline 200 within the processor 102 is provided. While a specific configuration for the instruction execution pipeline 200 is described, it should be understood that a wide variety of instruction execution pipelines fall within the scope of this disclosure. The instruction execution pipeline 200 retrieves instructions from memory and executes them, thereby outputting data to memory and modifying the state of elements associated with the instruction execution pipeline 200, such as registers in register file 218.

[0017] The instruction execution pipeline 200 includes an instruction fetching unit 204 that fetches instructions from system memory (e.g., memory 104) using an instruction cache 202, a decoder 208 that decodes the fetched instructions, a functional unit 216 that performs calculations to process the instructions, a load storage unit 214 that loads data from system memory or stores data into system memory via a data cache 220, and a register file 218 that includes registers for storing working data for the instructions.

[0018] Decoder 208 generates micro-operations and dispatches them to retirement queue 210. It should be noted that the term "instruction" used here, when referring to a decoded instruction, is sometimes used interchangeably with the term "micro-operation." In other words, it is sometimes indicated that a specific unit of decoder level 208 performs certain actions relative to an instruction, and in these cases, the word "instruction" refers to the micro-operation output by decoder level 208.

[0019] Register mapper 209 maps the schema registers specified by the instructions output by decoder 208 to the physical registers of register file 218. Register mapper 209 maps free registers in register file 218 to schema registers written by instructions. Register mapper 209 also maintains a table indicating which schema registers are mapped to which physical registers and uses this table to map the input registers of instructions to the correct physical registers. Register mapper 209 releases physical registers in response to instructions that allocate physical registers to it by: allocating a new physical register for the schema register mapped to the physical register to be released; and causing the instruction that allocated the new physical register to exit itself. In other words, physical registers are released in response to instructions that no longer require the value of the physical register. When a schema register is overwritten and the instruction that overwrites the schema register exits, this value is no longer needed.

[0020] The retirement queue 210 tracks currently in-progress instructions and ensures their in-order retirement, although out-of-order execution is permitted while in progress. The term "in-progress instruction" refers to an instruction that has been received by the retirement queue 210 but has not yet been retired. Retirement occurs when an instruction has completed (performing all operations in function unit 216 and / or load / store unit 214) and is no longer being executed speculatively. The reservation station 212 maintains in-progress instructions and tracks instruction operands. When all operands are ready to execute a specific instruction, the reservation station 212 sends the instruction to function unit 216 or load / store unit 214 for execution. Completed instructions are marked for retirement in the retirement queue 210 and retired at the front of the retirement queue 210. Retirement refers to the act of submitting the result of an instruction to the processor's architectural state. For example, an instruction might be executed out of order speculatively. If speculation fails, the instruction is not retired but is removed from the pipeline 200. At the retirement point, in most cases, it is assumed that the instruction is no longer executed speculatively, and therefore the result of the instruction is "submitted" to the state of pipeline 200.

[0021] Various components of the instruction execution pipeline 200 communicate via a common data bus 222. For example, functional unit 216 and load / store unit 214 write results to the common data bus 222, which can be read by the holding station 212 to execute related instructions and read by the decommissioning queue 210 as the final processing result of ongoing instructions that have been completed. Load / store unit 214 also reads data from the common data bus 222. For example, load / store unit 214 reads results from completed instructions from the common data bus 222 and writes the results to memory via data cache 220 to store instructions.

[0022] Figure 3 This illustrates exemplary stages related to register renaming. Stage 300 describes the instructions in program order, focusing on schema registers rather than physical registers. Four exemplary instructions are illustrated. Instruction 1 inputs values ​​at schema registers R1 and R2 and outputs the values ​​to schema register R3. Instruction 2 inputs values ​​at schema registers R3 and R4 and outputs the values ​​to schema register R1. Instruction 3 inputs values ​​at schema registers R5 and R7 and outputs the values ​​to schema register R3. Instruction 4 inputs values ​​at schema registers R3 and R2 and outputs the values ​​to schema register R4.

[0023] The register renaming for these instructions is illustrated in register renaming phase 310. In this phase, the architecture registers written to each instruction are allocated in the physical register file. For instruction 1, register mapper 209 allocates physical register PhysReg3 to architecture register R3. For instruction 2, register mapper 209 allocates physical register PhysReg10 to architecture register R1. For instruction 3, register mapper 209 allocates physical register PhysReg11 to architecture register R3. For instruction 4, register mapper 209 allocates physical register PhysReg12 to architecture register R4.

[0024] It should be noted that although instruction 3 writes to the same architecture register as instruction 1, the physical registers used are different. This difference allows instructions 1 and 3 to be executed out of program order relative to each other. For example, pipeline 200 can execute instruction 3 before instruction 1 or instruction 2. More specifically, the value written to architecture register R3 by instruction 1 will not be consumed after instruction 2 because instruction 3 will overwrite the architecture register. Therefore, instruction 3 and subsequent instructions refer to physical registers that are different from the physical registers mapped to architecture register R3 of instruction 1.

[0025] For register inputs, register mapper 209 maps the physical register holding the value to be read to the input architecture register. Because Figure 3 The example illustrates a small sample size of instructions, therefore the data source for architecture registers R1, R2, R4, R5, and R7 is not shown. However, in the example, it is assumed that the physical registers mapped to those architecture registers were generated in instructions not previously shown and placed into the physical registers mapped to those architecture registers, such as... Figure 3 As shown. Therefore, for example, the value of the schema register R1 is placed into the physical register PhysReg1, so R1 is mapped to the physical register PhysReg1. For similar reasons, schema registers R2, R4, R5, and R7 are mapped to the physical registers PhysReg2, PhysReg4, PhysReg5, and PhysReg7, respectively. Register mapper 209 can use default registers for schema registers that have not yet been written to.

[0026] In some cases, the input value of a newer described instruction is the same as the output value of an older described instruction. In these cases, the schema register holding the input value of the newer instruction is mapped to the physical register holding the output of the older instruction. In the example shown, instruction 2 reads from schema register R3, which holds the value generated by instruction 1. Therefore, in instruction 2, schema register R3 is mapped to physical register PhysReg3, which is the physical register allocated to instruction 1 and mapped to schema register R3 of instruction 1. Furthermore, instruction 4 reads from the value written to schema register R3 by instruction 3. In instruction 3, schema register R3 is mapped to physical register PhysReg11; therefore, in instruction 4, schema register R3 is mapped to PhysReg11.

[0027] After register mapping, reservation station 212 dispatches instructions to functional unit 216 and / or load / store unit 214. The first dispatch 320 includes instructions 1 and 3 because instructions 2 and 4 have data dependencies and therefore cannot begin execution until these dependencies are satisfied. It should be noted that instructions 1 and 3 are dispatched together even if they are written to the same architecture register. Register renaming allows these instructions to be dispatched together. After the data dependencies are satisfied, instructions 2 and 4 are dispatched in the second dispatch.

[0028] While register renaming is important for the proper functioning of out-of-order processors, it can put stress on register file 218 in certain situations. Here, "stress" refers to the large number of registers allocated due to a large number of instructions in progress. Furthermore, in some cases, certain allocations are unnecessary because the written values ​​will never be consumed. Therefore, reducing allocations in such cases increases register file utilization, which reduces pauses and thus improves performance. Reducing allocations also reduces register file power because there are fewer writes.

[0029] One aspect of instruction execution related to register pressure due to register renaming is writing flags to the flag register. Flags are values ​​that indicate the state between instructions. There are many examples of flags, but some include: a carry flag, which indicates whether there is a carry at the most significant arithmetic logic unit (ALU) bit position in the result of an operation; a parity flag, which indicates whether the last result is even or odd; a zero flag, which indicates whether the result of the last operation is zero; a sign flag, which indicates the sign of the last operation; and many other flags, such as those specified in the FLAGS register in the x86 instruction set architecture. Typically, most or all arithmetic logic unit (“ALU”) instructions, such as addition and subtraction, write to the flag register. Therefore, in architectures that allocate physical flag registers separately from data registers, a new flag register is allocated for each ALU instruction. In many cases, the writes to the flag register are never consumed, thus wasting such allocation.

[0030] Figure 4 This illustrates a technique for physical register allocation to reduce register file pressure, based on an example. Figure 4 In this implementation, decoder 208 generates and dispatches instruction dispatch set 402. Instruction dispatch set 402 includes multiple instructions 404. In some implementations, this instruction dispatch set 402 is generated in a single cycle. Therefore, in some cases, decoder 208 dispatches multiple instructions per cycle. In some implementations, instruction dispatch set 402 is generated across multiple cycles, so the operation performed by register mapper 209 is performed across multiple cycles. In some implementations, instruction dispatch set 402 includes instructions 404 consecutively in program order, without intervening instructions. In one example, instruction dispatch set 402 includes two consecutive instructions 404 in program order, which allows register mapper 209 to have the opportunity to suppress the dispatch of the older instruction of the two instructions 404.

[0031] To implement techniques for register allocation to reduce register file pressure, register mapper 209 detects that at least one instruction in instruction dispatch set 402 satisfies a set of allocation suppression criteria. The set of allocation suppression criteria includes the following: A first criterion is that instruction 404 is not the most recent instruction 404 in instruction dispatch set 402. A second criterion is that the instruction writes all flags overridden by a newer instruction 404 in instruction dispatch set 402. A third criterion is that a newer instruction 404 in instruction dispatch set 402 does not read any flags written by instruction 404. If instruction 404 satisfies all of the criteria in the set of allocation suppression criteria, register mapper 209 suppresses the allocation of a flag register for instruction 404. If instruction 404 does not satisfy at least one of the criteria in the set of allocation suppression criteria, register mapper 209 does not suppress the allocation of a flag register for instruction 404 and allocates a flag register for instruction 404.

[0032] To provide more detail for the above explanation, different instructions can write different flags. In one example, the addition instruction writes a set of flags, including the carry flag, the zero flag, and the parity flag. The subtraction instruction writes the same flags. In an example where instruction dispatch set 402 includes two consecutive instructions 404 (and no more than two instructions), the two consecutive instructions 404 write the same flags, and the newer instruction 404 does not read any flags written by the older instruction 404. In this example, the flag write of the first instruction 404 is suppressed because such a write will never be used. In another example of two consecutive instructions 404, the older instruction 404 writes a set of flags, while the newer instruction 404 writes a superset of flags that includes the set of flags written by the older instruction 404. Furthermore, the newer instruction 404 does not read any flags written by the older instruction 404. In this example, the flag writes of the older instruction are suppressed because these flag writes will never be used. In yet another example, the older instruction 404 writes a set of flags, and the newer instruction 404 does not write any flags written by the older instruction 404. In this example, flag writes are not suppressed for the older instruction 404. In yet another example, the newer instruction 404 and the older instruction 404 write the same flags, but the newer instruction reads at least one of the flags from the older instruction 404. In this example, flag writes by the older instruction 404 are not suppressed. In the above, the statement that flag writes are suppressed means that in some implementations, no register is allocated for the flag to be written. In other implementations, this statement means that flag writes are not performed.

[0033] As described above, register allocation for instruction 404 is suppressed if it meets a set of allocation suppression criteria. The effect of not allocating a flag register for any particular instruction 404 is that instruction 404 does not write any of its flags, and is similar to not using... Figure 4 Compared to the situation with the technology, register file pressure is reduced.

[0034] In some implementations, the flag register has a separate renamespace from the data register. A separate renamespace means that the register mapper 209 allocates physical registers to the architectural flag register independently of the physical registers mapped to the data registers. This contrasts with a configuration where space for flags is allocated every time a data register is allocated (the registers (“entries”) in register file 218 include space for both data registers and flag registers). In implementations where the flag register has a separate renamespace from the data register, the technique of not allocating the flag register, as described above, is applied when the flag is written along with instructions that perform tasks other than writing the flag (e.g., ALU instructions) and instructions that write the flag instead of the data register.

[0035] In other implementations, the flag register has the same renamespace as the data register. In this type of implementation, entries in the register file include space for both the data register and the flag register. Therefore, when an instruction that includes operations to write flags and write to the data register is executed, space in the register file is allocated for the data register and the flag register, which are treated as a single unit. In this type of implementation, register file pressure can sometimes be reduced by suppressing register allocations. However, in some cases, even for instructions that meet all register allocation suppression criteria, register file pressure cannot be reduced.

[0036] More specifically, in some cases, the older instruction 404 only writes flags and not data. Additionally, the older instruction 404 satisfies all register allocation suppression criteria for the newer instruction 404, which either only writes flags or writes both flags and data. In this case, allocation for the older instruction 404 is suppressed because the entire register file entry for that instruction 404 is not used. Specifically, instruction 404 does not write data, and the flags that instruction 404 will write will never be used.

[0037] However, in other cases, older instructions write both data and flags. Additionally, older instruction 404 satisfies all register allocation suppression criteria (for flags) for newer instruction 404, where the newer instruction only writes flags or writes both flags and data. In this case, allocation by older instruction 404 is not suppressed because the data in older instruction 404 requires entries in the register file. However, in this case, writing flags by older instruction 404 is suppressed because these flags are never used.

[0038] Register suppression techniques can be applied to registers other than the flag register. More specifically, instead of register mapper 209 determining whether one or more instructions 404 in instruction dispatch set 402 meet a register allocation suppression criterion regarding flags, register mapper 209 determines whether one or more instructions 404 in instruction dispatch set 402 meet a register allocation suppression criterion regarding data. For a second criterion listed elsewhere herein, this criterion is that an instruction writes to a data register overwritten by at least one newer instruction 404 of instruction dispatch set 402. For a third criterion listed elsewhere herein, this criterion is that a newer instruction 404 of instruction dispatch set 402 does not read the register under consideration. For instructions 404 that meet the register allocation suppression criterion, register allocation is suppressed.

[0039] Figure 5 This is a flowchart of method 500 for allocating physical registers in a register file to instructions, based on an example. Although regarding... Figures 1 to 4The system description method 500 is provided, but those skilled in the art will recognize that any system configured to perform the steps of method 500 in any technically feasible order falls within the scope of this disclosure.

[0040] Method 500 begins at step 502, where register mapper 209 identifies the first instruction in instruction dispatch set 402 that satisfies all register allocation suppression criteria of a set of register allocation suppression criteria. A set of register allocation criteria is described elsewhere in this document. Instruction dispatch set 402 is also described elsewhere in this document.

[0041] In step 504, because the first instruction satisfies all register allocation suppression criteria, register mapper 209 suppresses register allocation for the first instruction. As described elsewhere herein, in a separate register renamespace register file, suppressing register allocation for the flag register of the first instruction means that the flag register allocated for the first instruction is not assigned to said instruction, thus at least one additional register is available for use by a different instruction. As described elsewhere herein, in a non-separate namespace register file where flags and data share slots in the register file, suppressing register allocation means suppressing allocation for the entire register file slot or not writing to a portion of the register file slot, where another portion of the register file slot is still used for other purposes (e.g., data).

[0042] In step 506, register mapper 209 identifies a second instruction in the instruction dispatch set that does not meet any of the register allocation suppression criteria in the set of register allocation suppression criteria. In step 508, in response to step 506, register mapper 209 does not suppress register allocation for the second instruction.

[0043] In some implementations, method 500 is executed to determine whether to suppress flag register allocation. In other implementations, method 500 is executed to determine whether to suppress data register allocation.

[0044] In some implementations, register allocation is suppressed in certain situations, but the instruction pipeline 200 later determines that a register value that has already been written is needed. An example of this is when an instruction in instruction dispatch set 402 has a suppressed register allocation, but the instruction pipeline 200 detects an exception and therefore needs a value that has not yet been written. In this case, the instruction pipeline 200 flushes the instruction and replays it without suppressing the write.

[0045] In some implementations, an additional criterion for register allocation suppression is that the instruction being tested is not a branch instruction.

[0046] It should be understood that many variations are possible based on the disclosure herein. Although features and elements are described above in specific combinations, each feature or element can be used alone without other features and elements, or in various combinations with or without other features and elements.

[0047] The various functional units shown in the figures and / or described herein (including, where appropriate, processor 102, input driver 112, input device 108, output driver 114, output device 110, instruction cache 202, instruction fetch unit 204, decoder 208, register mapper 209, retirement queue 210, reservation station 212, data cache 220, load / store unit 214, functional unit 216, register file 218, and common data bus 222) can be implemented as hardware circuitry, software executing on a programmable processor, or a combination of hardware and software. The provided methods can be implemented in a general-purpose computer, processor, or processor core. Suitable processors include, for example, general-purpose processors, special-purpose processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application-specific integrated circuits (ASICs), field-programmable gate array (FPGA) circuitry, any other type of integrated circuit (IC), and / or state machine. Such processors can be manufactured by configuring the manufacturing process using the results of processed Hardware Description Language (HDL) instructions and other intermediate data, including netlists (such instructions can be stored on a computer-readable medium). The result of such processing can be a mask, which is then used in the semiconductor manufacturing process to manufacture processors that implement various aspects of the implementation scheme.

[0048] The methods or flowcharts provided herein can be implemented in a computer program, software, or firmware incorporated in a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media (e.g., internal hard disks and removable disks), magneto-optical media, and optical media (e.g., CD-ROMs and DVDs).

[0049] ***

Claims

1. A method of allocating registers for a processor, the method comprising: in response to a first instruction of an instruction dispatch set satisfying all of a set of register allocation suppression criteria, the set of register allocation suppression criteria including a requirement that the first instruction write a flag that is to be overwritten by one or more newer instructions of the instruction dispatch set, suppressing register allocation of a flag register of the first instruction; executing the first instruction to generate data stored in a data register; and in response to a second instruction of the instruction dispatch set not satisfying all of the set of register allocation suppression criteria, allocating a flag register for the second instruction.

2. The method of claim 1, wherein the set of register allocation suppression criteria further includes a requirement that the first instruction not be the most recent instruction of the instruction dispatch set.

3. The method of claim 1, wherein the set of register allocation suppression criteria further includes a requirement that the first instruction not be the most recent instruction of the instruction dispatch set and a requirement that no instruction of the instruction dispatch set newer than the first instruction is permitted to read any flag written by the first instruction.

4. The method of claim 1, wherein the set of register allocation suppression criteria includes a requirement that no instruction of the instruction dispatch set newer than the first instruction is permitted to read any of the flags written by the first instruction.

5. The method of claim 1, wherein: the register allocation suppression criteria includes a criterion regarding data registers.

6. The method of claim 1, wherein the instruction dispatch set includes instructions that are consecutive in program order, with no intervening instructions.

7. The method of claim 1, wherein suppressing register allocation of the flag register of the first instruction includes preventing allocation of a register written by the first instruction.

8. An instruction processing subsystem for allocating registers for a processor, the instruction processing subsystem comprising: a decode unit configured to dispatch an instruction dispatch set; and circuitry configured to: in response to a first instruction of the instruction dispatch set satisfying all of a set of register allocation suppression criteria, the set of register allocation suppression criteria including a requirement that the first instruction write a flag that is to be overwritten by one or more newer instructions of the instruction dispatch set, suppress register allocation of a flag register of the first instruction; execute the first instruction to generate data stored in a data register; and in response to a second instruction of the instruction dispatch set not satisfying all of the set of register allocation suppression criteria, allocate a flag register for the second instruction.

9. The instruction processing subsystem of claim 8, wherein the set of register allocation suppression criteria further includes a requirement that the first instruction not be the most recent instruction of the instruction dispatch set.

10. The instruction processing subsystem of claim 8, wherein the set of register allocation suppression criteria further includes a requirement that the first instruction not be the most recent instruction of the instruction dispatch set and a requirement that no instruction of the instruction dispatch set newer than the first instruction is permitted to read any flag written by the first instruction.

11. The instruction processing subsystem of claim 8, wherein the set of register allocation suppression criteria includes a requirement that any flags written by the first instruction not be read by a new instruction in the instruction dispatch set than the first instruction.

12. The instruction processing subsystem of claim 8, wherein the instruction dispatch set includes instructions that are consecutive in program order without intervening instructions.

13. The instruction processing subsystem of claim 8, wherein: the register allocation suppression criteria include criteria regarding data registers.

14. The instruction processing subsystem of claim 8, wherein the instruction dispatch set includes instructions that are consecutive in program order without intervening instructions.

15. The instruction processing subsystem of claim 8, wherein suppressing register allocation of the flag registers of the first instruction includes preventing allocation of registers written by the first instruction.

16. A processor to allocate registers for the processor, the processor comprising: a decode unit configured to dispatch an instruction dispatch set; circuitry configured to: suppress register allocation of flag registers of a first instruction in the instruction dispatch set in response to all of a set of register allocation suppression criteria being satisfied in the instruction dispatch set, the set of register allocation suppression criteria including a requirement that the first instruction write flags that are to be overwritten by one or more newer instructions in the instruction dispatch set; execute the first instruction to generate data stored in data registers; allocate flag registers for a second instruction in response to all of the register allocation suppression criteria not being satisfied in the instruction dispatch set; and one or more functional units configured to execute either or both of the first instruction and the second instruction.

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