Memory structure and manufacturing method thereof

Abstract

The present invention discloses a memory structure and a method for manufacturing the same. The memory structure includes a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductor layer. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first and second dielectric layers. The oxide layer is located at both ends of the charge storage layer and disposed between the first and second dielectric layers. The conductor layer is disposed on the second dielectric layer. The above-described memory structure can effectively prevent charge loss, thereby improving the data retention capacity and reliability of the memory element.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a memory structure and a manufacturing method thereof. Background Art

[0002] Memory devices used to store data can be categorized as volatile memory and non-volatile memory. Non-volatile memory has become widely used in personal computers and electronic devices because it allows for multiple data writes, reads, and erases, and offers advantages such as long-term data retention when power is interrupted, short data access times, and low power consumption. However, when the charge stored in non-volatile memory is lost, the memory device's data retention and reliability are reduced. Summary of the Invention

[0003] The present invention provides a memory structure and a manufacturing method thereof, which can effectively prevent charge loss and thereby improve the data retention capability and reliability of the memory element.

[0004] The present invention provides a memory structure comprising a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first and second dielectric layers. The oxide layer is located at both ends of the charge storage layer and disposed between the first and second dielectric layers. The conductive layer is disposed on the second dielectric layer.

[0005] According to an embodiment of the present invention, in the memory structure, the oxide layer may be connected between the bottom surface of the second dielectric layer and the top surface of the first dielectric layer.

[0006] According to an embodiment of the present invention, in the memory structure, the first dielectric layer, the second dielectric layer, and the oxide layer may surround the charge storage layer.

[0007] According to an embodiment of the present invention, in the memory structure, the conductive layer may cover the sidewalls of the oxide layer.

[0008] According to an embodiment of the present invention, in the above memory structure, the material of the first dielectric layer is, for example, oxide, the material of the second dielectric layer is, for example, oxide, and the material of the charge storage layer is, for example, nitride.

[0009] According to an embodiment of the present invention, the memory structure may further include an isolation structure located in the substrate.

[0010] According to an embodiment of the present invention, in the above memory structure, the oxide layer may be located above the isolation structure.

[0011] According to an embodiment of the present invention, in the memory structure, a portion of the first dielectric layer, a portion of the charge storage layer, and a portion of the second dielectric layer may be located above the isolation structure.

[0012] According to an embodiment of the present invention, in the above-mentioned memory structure, the upper surface of the isolation structure may have a recess, and the recess may be adjacent to the substrate.

[0013] According to an embodiment of the present invention, in the above memory structure, the upper surface of the isolation structure may be a flat surface.

[0014] The present invention provides a method for manufacturing a memory structure, comprising the following steps: providing a substrate; forming a first dielectric material layer on the substrate; forming a charge storage material layer on the first dielectric material layer; forming a second dielectric material layer on the charge storage material layer; performing a patterning process on the second dielectric material layer, the charge storage material layer, and the first dielectric material layer to form a second patterned dielectric material layer, a patterned charge storage material layer, and a first patterned dielectric material layer; performing an oxidation process on the patterned charge storage material layer to form an oxide material layer at the end of the patterned charge storage material layer; forming a conductor layer on the second patterned dielectric material layer; using the conductor layer as a mask, removing a portion of the second patterned dielectric material layer, a portion of the patterned charge storage material layer, a portion of the oxide material layer, and a portion of the first patterned dielectric material layer to form a second dielectric layer, a charge storage layer, an oxide layer, and a first dielectric layer, wherein the oxide layer is located at both ends of the charge storage layer.

[0015] According to an embodiment of the present invention, in the method for manufacturing the memory structure, the gas used in the oxidation process may include hydrogen (H 2 ), nitrous oxide (N 2 O), oxygen (O 2 ), or ozone (O 3 ).

[0016] According to an embodiment of the present invention, in the method for manufacturing the memory structure, the temperature range of the oxidation process is, for example, 800° C. to 900° C.

[0017] According to an embodiment of the present invention, in the method for manufacturing the memory structure, the oxidation process takes, for example, 10 seconds to 60 seconds.

[0018] According to an embodiment of the present invention, in the method for manufacturing the memory structure, the pressure range of the oxidation process is, for example, 2 Torr to 8 Torr.

[0019] According to an embodiment of the present invention, in the method for manufacturing the memory structure, the oxide material layer may be ring-shaped when viewed from above and may surround the patterned charge storage material layer.

[0020] According to one embodiment of the present invention, in the above-mentioned method for manufacturing a memory structure, the patterning process may include the following steps: forming a patterned photoresist layer on the second dielectric material layer; using the patterned photoresist layer as a mask to remove portions of the second dielectric material layer, portions of the charge storage material layer, and portions of the first dielectric material layer, thereby forming the second patterned dielectric material layer, the patterned charge storage material layer, and the first patterned dielectric material layer.

[0021] According to an embodiment of the present invention, the method for manufacturing the memory structure may further include the following steps: removing the patterned photoresist layer.

[0022] According to an embodiment of the present invention, in the method for manufacturing the memory structure, an oxidation process may be performed on the patterned charge storage material layer before removing the patterned photoresist layer.

[0023] According to an embodiment of the present invention, in the method for manufacturing the memory structure, after removing the patterned photoresist layer, an oxidation process may be performed on the patterned charge storage material layer.

[0024] Based on the above, in the memory structure and manufacturing method proposed in the present invention, since the oxide layer is located at both ends of the charge storage layer, the oxide layer can be used to seal the two ends of the charge storage layer to prevent charge from leaking from the two ends of the charge storage layer, thereby improving the data retention capability and reliability of the memory device. In addition, in the manufacturing method of the memory structure proposed in the present invention, although the etching process used to form the first patterned dielectric material layer, the patterned charge storage material layer, and the second patterned dielectric material layer may cause damage to the sidewalls of the first patterned dielectric material layer, the patterned charge storage material layer, and the second patterned dielectric material layer, the sidewall damage of the first patterned dielectric material layer, the patterned charge storage material layer, and the second patterned dielectric material layer can be repaired by the oxidation process.

[0025] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1A to 1F A top view of the manufacturing process of a memory structure according to an embodiment of the present invention;

[0027] Figures 2A to 2F To follow Figures 1A to 1F A sectional view along the section line I-I';

[0028] Figure 3 To follow Figure 1F A sectional view along section line II-II';

[0029] Figure 4 FIG. 4 is a cross-sectional view of a memory structure according to another embodiment of the present invention.

[0030] Explanation of symbols

[0031] 10,20: Memory structure

[0032] 100: Base

[0033] 102,202: Isolation structure

[0034] 104,108: Dielectric material layer

[0035] 104a, 108a: Patterned dielectric material layer

[0036] 104b, 108b: dielectric layer

[0037] 106: Charge storage material layer

[0038] 106a: Patterned charge storage material layer

[0039] 106b: Charge storage layer

[0040] 110: Patterned photoresist layer

[0041] 112,114: Oxide material layer

[0042] 112a, 114a: oxide layer

[0043] 116,118: Conductor layer

[0044] BS: bottom surface

[0045] D1: Direction

[0046] R: Depression

[0047] S1, S2: upper surface

[0048] TS: Top surface DETAILED DESCRIPTION

[0049] Figures 1A to 1F FIG. 1 is a top view of the manufacturing process of a memory structure according to an embodiment of the present invention. Figures 2A to 2F To follow Figures 1A to 1F Sectional view along section line I-I'. Figure 3 To follow Figure 1FSectional view along section line II-II'.

[0050] Please refer to Figure 1A and Figure 2A , providing a substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In addition, the substrate 100 may have an isolation structure 102. The isolation structure 102 may define an active area AA in the substrate 100. The upper surface S1 of the isolation structure 102 may have a recess R. The recess R may be adjacent to the substrate 100. In this embodiment, although the upper surface S1 of the isolation structure 102 is taken as having the recess R, the present invention is not limited thereto. In other embodiments, such as Figure 4 As shown, the upper surface S2 of the isolation structure 202 may be a flat surface. The isolation structure 102 may be, for example, a shallow trench isolation structure. The isolation structure 102 may be made of, for example, silicon oxide.

[0051] Please refer to Figure 1B and Figure 2B , a dielectric material layer 104 is formed on the substrate 100. The material of the dielectric material layer 104 is, for example, an oxide, such as silicon oxide. The dielectric material layer 104 is formed by, for example, thermal oxidation or chemical vapor deposition. In some embodiments, the dielectric material layer 104 may also be formed on the isolation structure 102. In some embodiments, although Figure 2B Although not shown, when the dielectric material layer 104 is formed using a thermal oxidation method, the thickness of the dielectric material layer 104 on the substrate 100 may be greater than the thickness of the dielectric material layer 104 on the isolation structure 102 .

[0052] Next, a charge storage material layer 106 is formed on the dielectric material layer 104. The charge storage material layer 106 may be made of a charge trapping material. In some embodiments, the charge storage material layer 106 may be made of a nitride, such as silicon nitride. The charge storage material layer 106 may be formed by chemical vapor deposition, for example.

[0053] Then, a dielectric material layer 108 is formed on the charge storage material layer 106. The material of the dielectric material layer 108 is, for example, an oxide, such as silicon oxide. The dielectric material layer 104 is formed by, for example, chemical vapor deposition.

[0054] Next, a patterned photoresist layer 110 may be formed on the dielectric material layer 108. The patterned photoresist layer 110 may expose a portion of the dielectric material layer 108. The patterned photoresist layer 110 may be formed by a photolithography process.

[0055] Please refer to Figure 1C and Figure 2CThe patterned photoresist layer 110 can be used as a mask to remove portions of the dielectric material layer 108, the charge storage material layer 106, and the dielectric material layer 104. Thus, the dielectric material layer 108, the charge storage material layer 106, and the dielectric material layer 104 can be patterned to form a patterned dielectric material layer 108a, a patterned charge storage material layer 106a, and a patterned dielectric material layer 104a. The removal of portions of the dielectric material layer 108, the charge storage material layer 106, and the dielectric material layer 104 can be performed by, for example, dry etching.

[0056] Please refer to Figure 1D and Figure 2D , the patterned charge storage material layer 106a is subjected to an oxidation process, and an oxide material layer 112 is formed at the end of the patterned charge storage material layer 106a. The top view shape of the oxide material layer 112 may be a ring ( Figure 1D ). In addition, the oxide material layer 112 may surround the patterned charge storage material layer 106a ( Figure 1D ). The material of the oxide material layer 112 is, for example, silicon oxide. In some embodiments, the above-mentioned oxidation process may simultaneously form an oxide material layer 114 on the substrate 100 that is not covered by the patterned dielectric material layer 104a. In some embodiments, the oxide material layer 114 may also be formed on the isolation structure 102. In some embodiments, when the oxide material layer 114 is formed using the oxidation process, the thickness of the oxide material layer 114 located on the substrate 100 may be greater than the thickness of the oxide material layer 114 located on the isolation structure 102. The material of the oxide material layer 114 is, for example, silicon oxide. The gas used in the oxidation process may include hydrogen, nitrous oxide, oxygen or ozone. The temperature range of the oxidation process is, for example, 800°C to 900°C. The time range of the oxidation process is, for example, 10 seconds to 60 seconds. The pressure range of the oxidation process is, for example, 2 Torr to 8 Torr.

[0057] Furthermore, although the etching process used to form the patterned dielectric material layer 104a, the patterned charge storage material layer 106a, and the patterned dielectric material layer 108a may cause damage to the sidewalls of the patterned dielectric material layer 104a, the sidewalls of the patterned charge storage material layer 106a, and the sidewalls of the patterned dielectric material layer 108a, the damage to the sidewalls of the patterned dielectric material layer 104a, the patterned charge storage material layer 106a, and the patterned dielectric material layer 108a can be repaired through an oxidation process.

[0058] Next, the patterned photoresist layer 110 can be removed. The patterned photoresist layer 110 can be removed by, for example, dry stripping or wet stripping. In this embodiment, an oxidation process is performed on the patterned charge storage material layer 106 a to form the oxide material layer 112 before removing the patterned photoresist layer 110, but the present invention is not limited thereto. In other embodiments, an oxidation process can be performed on the patterned charge storage material layer 106 a to form the oxide material layer 112 after removing the patterned photoresist layer 110.

[0059] Please refer to Figure 1E and Figure 2E , a conductor layer 116 is formed on the patterned dielectric material layer 108a. In some embodiments, a portion of the conductor layer 116 may be located on the oxide material layer 114. The conductor layer 116 may be used as a control gate. In addition, a conductor layer 118 ( Figure 1E ). Please refer to Figure 1E , the conductive layer 118 can be used as a select gate. The conductive layer 116 and the conductive layer 118 can extend along the direction D1. The material of the conductive layer 116 and the conductive layer 118 is, for example, doped polysilicon. The method for forming the conductive layer 116 and the conductive layer 118 may include the following steps, but the present invention is not limited thereto. First, a conductive material layer (not shown) can be formed to cover the patterned dielectric material layer 108a and the oxide material layer 114. Then, the conductive material layer can be patterned using photolithography and etching processes to form the conductive layer 116 and the conductive layer 118.

[0060] Please refer to Figure 1F 、 Figure 2F and Figure 3Using the conductive layer 116 as a mask, a portion of the patterned dielectric material layer 108a, a portion of the patterned charge storage material layer 106a, a portion of the oxide material layer 112, and a portion of the patterned dielectric material layer 104a are removed to form the dielectric layer 108b, the charge storage layer 106b, the oxide layer 112a, and the dielectric layer 104b. The oxide layer 112a is located at both ends of the charge storage layer 106b. Since the oxide layer 112a is located at both ends of the charge storage layer 106b, the ends of the charge storage layer 106b can be sealed by the oxide layer 112a to prevent charge from leaking from the ends of the charge storage layer 106b, thereby improving the data retention and reliability of the memory device. For example, the oxide layer 112a can be located at opposite ends of the charge storage layer 106b in the direction D1. The method for removing the portion of the patterned dielectric material layer 108 a , the portion of the patterned charge storage material layer 106 a , the portion of the oxide material layer 112 , and the portion of the patterned dielectric material layer 104 a is, for example, dry etching.

[0061] In addition, the conductive layer 116 and the conductive layer 118 can be used as a mask to remove part of the oxide material layer 114, thereby forming an oxide layer 114a located below the conductive layer 116 and an oxide layer 114b located below the conductive layer 118. The oxide layer 114b can be used as a gate dielectric layer below the conductive layer 118 (select gate). In this embodiment, although the gate dielectric layer below the conductive layer 118 (select gate) is taken as an example of the oxide layer 114b, the present invention is not limited thereto. In other embodiments, the oxide layer 114b can be removed first. Figure 1D A new dielectric layer is formed on the substrate 100 and patterned to form a gate dielectric layer below the conductive layer 118. The oxide material layer 114 is removed by dry etching, for example.

[0062] Furthermore, in subsequent manufacturing processes, required spacers, doping regions, and interconnect structures (not shown) may be formed according to product requirements. This is well known to those skilled in the art and will not be further described.

[0063] Below, through Figure 1F and Figure 2F In addition, although the method for forming the memory structure 10 is described using the above method as an example, the present invention is not limited thereto.

[0064] Please refer to Figure 1F and Figure 2FMemory structure 10 includes a substrate 100, a dielectric layer 104b, a dielectric layer 108b, a charge storage layer 106b, an oxide layer 112a, and a conductive layer 116. Memory structure 10 may be a non-volatile memory, such as a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory. Dielectric layer 104b is disposed on substrate 100. The material of dielectric layer 104b is, for example, an oxide, such as silicon oxide. Dielectric layer 108b is disposed on dielectric layer 104b. The material of dielectric layer 108b is, for example, an oxide, such as silicon oxide. Charge storage layer 106b is disposed between dielectric layer 104b and dielectric layer 108b. The material of charge storage layer 106b is, for example, a nitride, such as silicon nitride. Oxide layer 112a is located at both ends of charge storage layer 106b and disposed between dielectric layer 104b and dielectric layer 108b. For example, the oxide layer 112a may be connected between the bottom surface BS of the dielectric layer 108b and the top surface TS of the dielectric layer 104b. The material of the oxide layer 112a is, for example, silicon oxide. The dielectric layer 104b, the dielectric layer 108b and the oxide layer 112a may surround the charge storage layer 106b ( Figure 2F ). The conductor layer 116 is disposed on the dielectric layer 108b. In some embodiments, the conductor layer 116 may cover the sidewalls of the oxide layer 112a ( Figure 2F ).

[0065] Furthermore, the memory structure 10 may further include an isolation structure 102. The isolation structure 102 is located in the substrate 100. An oxide layer 112a may be located above the isolation structure 102. Furthermore, a portion of the dielectric layer 104b, a portion of the charge storage layer 106b, and a portion of the dielectric layer 108b may be located above the isolation structure 102. The top surface S1 of the isolation structure 102 may have a recess R. The recess R may be adjacent to the substrate 100.

[0066] In addition, the materials, configuration, formation methods, and functions of each component in the memory structure 10 have been described in detail in the above embodiments and will not be repeated here.

[0067] Based on the above embodiments, it can be seen that in the memory structure 10 and the manufacturing method thereof, since the oxide layer 112a is located at both ends of the charge storage layer 106b, the oxide layer 112a can seal the both ends of the charge storage layer 106b, thereby preventing charge from leaking from the both ends of the charge storage layer 106b, thereby improving the data retention capability and reliability of the memory device. In addition, in the manufacturing method of the memory structure 10, although the etching process used to form the patterned dielectric material layer 104a, the patterned charge storage material layer 106a, and the patterned dielectric material layer 108a may cause damage to the sidewalls of the patterned dielectric material layer 104a, the patterned charge storage material layer 106a, and the patterned dielectric material layer 108a, the damage to the sidewalls of the patterned dielectric material layer 104a, the patterned charge storage material layer 106a, and the patterned dielectric material layer 108a can be repaired by the oxidation process.

[0068] Figure 4 FIG. 4 is a cross-sectional view of a memory structure according to another embodiment of the present invention.

[0069] Please refer to Figure 2F and Figure 4 , Figure 4 The memory structure 20 and Figure 2F The differences between memory structure 10 and memory structure 20 are as follows. In memory structure 10, top surface S1 of isolation structure 102 may have a recess R. However, in memory structure 20, top surface S2 of isolation structure 202 may be a flat surface. Components identical to those in memory structure 10 and 20 are denoted by the same reference numerals and are not further described.

[0070] In summary, in the memory structure and manufacturing method of the above-described embodiment, since the oxide layer is located at both ends of the charge storage layer, the oxide layer can seal the ends of the charge storage layer, thereby preventing charge loss from the ends of the charge storage layer, thereby improving the data retention capability and reliability of the memory device. Furthermore, in the manufacturing method of the memory structure of the above-described embodiment, the oxidation process can repair sidewall damage caused by the etching process.

[0071] Although the present invention is disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the attached claims.

Claims

1. A memory structure, characterized in that: include: substrate; a first dielectric layer disposed on the substrate; a second dielectric layer disposed on the first dielectric layer; a charge storage layer, disposed between the first dielectric layer and the second dielectric layer; an oxide layer, located at both ends of the charge storage layer and disposed between the first dielectric layer and the second dielectric layer; a conductor layer, disposed on the second dielectric layer; as well as an isolation structure located in the substrate, The upper surface of the isolation structure has a recess, and the recess is adjacent to the base. 2 . The memory structure of claim 1 , wherein the oxide layer is connected between a bottom surface of the second dielectric layer and a top surface of the first dielectric layer. 3 . The memory structure of claim 1 , wherein the first dielectric layer, the second dielectric layer, and the oxide layer surround the charge storage layer. The memory structure of claim 1 , wherein the conductive layer covers sidewalls of the oxide layer. 5 . The memory structure of claim 1 , wherein a material of the first dielectric layer comprises oxide, a material of the second dielectric layer comprises oxide, and a material of the charge storage layer comprises nitride. The memory structure of claim 1 , wherein the oxide layer is located above the isolation structure. 7 . The memory structure of claim 1 , wherein a portion of the first dielectric layer, a portion of the charge storage layer, and a portion of the second dielectric layer are located above the isolation structure.

8. A method for manufacturing a memory structure, comprising: providing a substrate; forming a first dielectric material layer on the substrate; forming a charge storage material layer on the first dielectric material layer; forming a second dielectric material layer on the charge storage material layer; Performing a patterning process on the second dielectric material layer, the charge storage material layer, and the first dielectric material layer to form a second patterned dielectric material layer, a patterned charge storage material layer, and a first patterned dielectric material layer; performing an oxidation process on the patterned charge storage material layer to form an oxide material layer at an end of the patterned charge storage material layer; forming a conductor layer on the second patterned dielectric material layer; as well as Using the conductive layer as a mask, a portion of the second patterned dielectric material layer, a portion of the patterned charge storage material layer, a portion of the oxide material layer, and a portion of the first patterned dielectric material layer are removed to form a second dielectric layer, a charge storage layer, an oxide layer, and a first dielectric layer, wherein the oxide layer is located at both ends of the charge storage layer. 9 . The method for manufacturing a memory structure according to claim 8 , wherein the gas used in the oxidation process comprises hydrogen, nitrous oxide, oxygen or ozone. 10 . The method for manufacturing a memory structure according to claim 8 , wherein a temperature range of the oxidation process is 800° C. to 900° C. 11 . The method for manufacturing a memory structure according to claim 8 , wherein a time range of the oxidation process is 10 seconds to 60 seconds. 12 . The method for manufacturing a memory structure according to claim 8 , wherein a pressure range of the oxidation process is 2 Torr to 8 Torr. 13 . The method for manufacturing a memory structure according to claim 8 , wherein a top-view shape of the oxide material layer comprises a ring shape, and the oxide material layer surrounds the patterned charge storage material layer.

14. The method for manufacturing a memory structure according to claim 8, wherein the patterning process comprises: forming a patterned photoresist layer on the second dielectric material layer; as well as The patterned photoresist layer is used as a mask to remove a portion of the second dielectric material layer, a portion of the charge storage material layer and a portion of the first dielectric material layer to form the second patterned dielectric material layer, the patterned charge storage material layer and the first patterned dielectric material layer.

15. The method for manufacturing a memory structure according to claim 14, further comprising: The patterned photoresist layer is removed. 16 . The method for manufacturing a memory structure according to claim 15 , wherein the oxidation process is performed on the patterned charge storage material layer before removing the patterned photoresist layer. 17 . The method for manufacturing a memory structure according to claim 15 , wherein the oxidation process is performed on the patterned charge storage material layer after the patterned photoresist layer is removed.

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