Semiconductor Structure and Method for Forming the Same

Abstract

A semiconductor structure and a method for forming the same, wherein the structure includes: a substrate having an adjacent drift region and a body region, and the conductivity type of the drift region is opposite to that of the body region; a first gate structure located on the substrate, the first gate structure spanning the boundary between the drift region and the body region in a first direction, the first direction being perpendicular to the extending direction of the first gate structure; a source region located in the body region; a drain region and a first isolation structure located in the drift region, the source region and the drain region are respectively located on both sides of the first gate structure, the first isolation structure is located between the first gate structure and the drain region, and there is a spacing between the first gate structure and the first isolation structure in the first direction; a second gate structure located on the surface of the first isolation structure. Thereby, the performance of the LDMOS transistor is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and particularly relates to a semiconductor structure and a method for forming the same. Background Art

[0002] An LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor is a power device that forms a lateral current path on the surface of a semiconductor substrate through planar diffusion and is commonly used in radio frequency power circuits. In high-voltage power integrated circuits, high-voltage LDMOS is often used to meet requirements such as high-voltage resistance and power control. Compared with traditional MOS transistors, a lightly doped region is usually provided between the source region and the drain region in an LDMOS transistor, which is called a drift region. Therefore, when a high voltage is connected between the source region and the drain region of the LDMOS transistor, since the impurity concentration in the drift region is relatively low and presents a high-resistance state, the drift region can withstand a relatively high voltage drop, so the LDMOS transistor can have a relatively high breakdown voltage.

[0003] The LDMOS transistor can be compatible with the Complementary Metal Oxide Semiconductor (CMOS) process, so the LDMOS transistor is widely used in power devices. For an LDMOS transistor used as a power integrated circuit, the on-resistance (Rdson) and the breakdown voltage (BV) are two important indicators for measuring its device performance.

[0004] However, the performance of existing LDMOS transistors is still poor. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same to improve the performance of the LDMOS transistor.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate having an adjacent drift region and a body region, and the conductivity type of the drift region is opposite to that of the body region; a first gate structure located on the substrate, the first gate structure spanning the boundary between the drift region and the body region along a first direction, and the first direction is perpendicular to the extending direction of the first gate structure; a source region and a second isolation structure located in the body region; a drain region and a first isolation structure located in the drift region, the source region and the drain region are respectively located on both sides of the first gate structure, the first isolation structure is located between the first gate structure and the drain region, the first isolation structure and the second isolation structure are respectively located on both sides of the source region, and there is a spacing between the first gate structure and the first isolation structure along the first direction; a second gate structure located on the surface of the first isolation structure; a fourth gate structure located on the body region, the fourth gate structure is located between the second isolation structure and the source region, and the fourth gate structure also extends to a part of the surface of the second isolation structure; a fifth gate structure located on the body region, the fifth gate structure and the fourth gate structure are respectively located on both sides of the second isolation structure, and the fifth gate structure also extends to a part of the surface of the second isolation structure.

[0007] Optionally, the spacing between the first gate structure and the first isolation structure is greater than 0 micrometers and less than or equal to 0.3 micrometers.

[0008] Optionally, it further includes: a first gate conductive structure located on the first gate structure; a second gate conductive structure located on the second gate structure.

[0009] Optionally, the first gate conductive structure is electrically connected to the second gate conductive structure.

[0010] Optionally, there is a first heavily doped region in the drift region, the conductivity type of the first heavily doped region is the same as that of the drift region, and the first heavily doped region is located between the first gate structure and the first isolation structure.

[0011] Optionally, it further includes: a third gate structure located on the drift region, and the drain region and the first isolation structure are respectively located on both sides of the third gate structure.

[0012] Optionally, there is a spacing between the third gate structure and the first isolation structure along the first direction.

[0013] Optionally, the spacing between the third gate structure and the first isolation structure is greater than 0 micrometers and less than or equal to 0.2 micrometers.

[0014] Optionally, the first heavily doped region is also located between the third gate structure and the first isolation structure.

[0015] Correspondingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: forming a substrate having an adjacent drift region and a body region, and the conductivity types of the drift region and the body region are opposite; forming a first isolation structure in the drift region; after forming the first isolation structure, forming a first gate structure and a second gate structure on the substrate, the first gate structure straddles the boundary between the drift region and the body region along a first direction, the second gate structure is located on the surface of the first isolation structure, and there is a spacing between the first gate structure and the first isolation structure along the first direction, and the first direction is perpendicular to the extension direction of the first gate structure; forming a source region in the body region and a drain region in the drift region, the source region and the drain region are respectively located on both sides of the first gate structure, and the first isolation structure is located between the first gate structure and the drain region.

[0016] Optionally, it further includes: while forming the source region and the drain region, forming a first heavily doped region in the drift region, the conductivity type of the first heavily doped region is the same as that of the drift region, and the first heavily doped region is located between the first gate structure and the first isolation structure.

[0017] Optionally, it further includes: while forming the first gate structure, forming a third gate structure on the substrate, and the third gate structure is also located between the first isolation structure and the drain region.

[0018] Optionally, there is a spacing between the third gate structure and the first isolation structure along the first direction.

[0019] Optionally, the process of forming the first heavily doped region includes an epitaxial growth process.

[0020] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0021] In the semiconductor structure provided by the technical solution of the present invention, on the one hand, since there is a spacing between the first gate structure and the first isolation structure in the first direction (the direction perpendicular to the extension direction of the first gate structure), not only is the electric field strength generated between the first isolation structure and the boundary of the drift region and its vicinity not easily enhanced by the high voltage applied to the first gate structure. Thus, the hot carriers generated between the first isolation structure and the boundary of the drift region and its vicinity are reduced. At the same time, the path distance for the hot carriers generated between the first isolation structure and the boundary of the drift region and its vicinity to move to the first gate structure is increased. Therefore, the difficulty of injecting the hot carriers into the first gate structure is increased. Thus, under the combined action of the above two aspects, the hot carriers injected into the first gate structure are preferably reduced, the influence on the electrical characteristics of the semiconductor structure is reduced, and further, the performance of the semiconductor structure is improved. On the other hand, since the semiconductor structure further includes a second gate structure located on the surface of the first isolation structure, by applying a relatively high voltage to the second gate structure, the control ability of the carriers in the drift region around the first isolation structure can be enhanced to improve the voltage division ability of the drift region, so that the semiconductor structure has better withstand voltage ability, and further, the performance of the semiconductor structure is improved.

[0022] Furthermore, since there is a first heavily doped region in the drift region, the conductivity type of the first heavily doped region is the same as that of the drift region, and the first heavily doped region is located between the first gate structure and the first isolation structure. Therefore, the contact resistance on the surface of the drift region between the first gate structure and the first isolation structure is reduced through the first heavily doped region. Thus, while enabling the semiconductor structure to have better withstand voltage ability, the resistance of the semiconductor structure is reduced, and the performance of the semiconductor structure is improved.

[0023] Furthermore, since there is a spacing between the third gate structure and the first isolation structure in the first direction, that is, the spacing between the first isolation structure and the drain region is relatively large. Therefore, the size of the moving region of the carriers between the third gate structure and the first isolation structure and its vicinity is increased. Thus, the situation of carrier congestion is reduced, the heating problem caused by carrier congestion is improved, the performance of the semiconductor structure is improved, and the service life of the semiconductor structure is prolonged. Description of the Drawings

[0024] Figure 1 is a schematic cross-sectional structure diagram of an LDMOS transistor;

[0025] Figures 2 to 8 is a schematic cross-sectional structure diagram of each step of the method for forming the semiconductor structure in an embodiment of the present invention. Detailed Embodiments

[0026] As described in the background art, the performance of existing LDMOS transistors is still poor. The following will be specifically described with reference to the accompanying drawings.

[0027] Figure 1 It is a schematic cross-sectional structure diagram of an LDMOS transistor.

[0028] Please refer to Figure 1 , the LDMOS transistor includes: a substrate 100, in which a doped drift region 101 and a doped body region 102 are provided, and the conductivity types of the drift region 101 and the body region 102 are opposite; a source region 103 located in the body region 102; a drain region 104 and an isolation structure 110 located in the drift region 101, and the source region 103 and the drain region 104 are respectively located on both sides of the isolation structure 110; a gate structure 120 located on the substrate 100, the gate structure 120 straddles the boundary between the drift region 101 and the body region 102, and along the vertical direction of the extending direction of the gate structure 120, the gate structure 120 extends onto the isolation structure 110; a first conductive plug 131 located on the surface of the source region 103.

[0029] In the above embodiment, by extending the gate structure 120 onto the isolation structure 110, the control ability of the gate structure 120 for the carriers in the offset region 101 is increased, thereby improving the voltage division ability of the LDMOS transistor and the breakdown voltage ability of the LDMOS transistor.

[0030] However, due to applying a relatively high voltage to the drain region 104 and the gate structure 120, a strong electric field is generated in region A (as Figure 1 shown). Therefore, affected by the strong electric field, hot carriers are easily generated in region A, resulting in the injection of hot carriers into the gate structure 120, affecting the electrical characteristics of the LDMOS transistor, and thus causing poor performance of the LDMOS transistor.

[0031] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure and a method for forming the same. In the semiconductor structure, since there is a spacing between the first gate structure and the first isolation structure in a first direction, and the semiconductor structure further includes a second gate structure located on the surface of the first isolation structure, the performance of the LDMOS transistor is improved.

[0032] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following specifically describes the specific embodiments of the present invention with reference to the accompanying drawings.

[0033] It should be noted that the "surface" in this specification is used to describe the relative positional relationship in space and does not limit whether it is in direct contact.

[0034] Figures 2 to 8 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention.

[0035] Please refer to Figure 2 , a substrate 200 is formed, the substrate 200 has an adjacent drift region 201 and a body region 202, and the conductivity type of the drift region 201 is opposite to the conductivity type of the body region 202.

[0036] The material of the substrate 200 includes silicon, germanium, silicon germanium or silicon carbide; it may also include silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as group III-V compounds such as gallium arsenide.

[0037] In this embodiment, the material of the substrate 200 is silicon.

[0038] In this embodiment, the method for forming the substrate 200 includes: providing an initial substrate (not shown); using an ion implantation process to form a doped drift region 201 in the initial substrate; forming a doped body region 202 in the initial substrate to form the substrate 200, the conductivity type of the drift region 201 is opposite to the conductivity type of the body region 202, and the drift region 201 and the body region 202 are adjacent.

[0039] The drift region 201 is used to separate the subsequently formed drain region and channel region, thereby extending the current channel of the semiconductor structure and increasing the breakdown voltage.

[0040] The drift region 201 is doped with a first ion.

[0041] In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the first ion is an N-type ion, including: one or more of phosphorus ions, arsenic ions or antimony ions, that is, the conductivity type of the drift region 201 is N-type.

[0042] In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the first ion may also be a P-type ion, including: one or more of boron ions, indium ions or gallium ions.

[0043] The method for forming the drift region 201 includes: forming a drift region mask layer (not shown) on the surface of the initial substrate, and the drift region mask layer is used to define the position and size of the drift region; using the drift region mask layer as a mask, performing an ion implantation process on the initial substrate to form the drift region 201 in the initial substrate.

[0044] In this embodiment, after forming the drift region 201, the method for forming the semiconductor structure further includes: removing the drift region mask layer.

[0045] In this embodiment, the material of the drift region mask layer is photoresist, and the drift region mask layer is removed by an ashing process.

[0046] The body region 202 is used to separate the subsequently formed source region and channel region.

[0047] The body region 202 is doped with a second ion.

[0048] The forming method of the body region 202 includes: forming a body region mask layer (not shown) on the surface of the initial substrate, where the body region mask layer is used to define the position and size of the body region; using the body region mask layer as a mask, performing an ion implantation process on the initial substrate to form the body region 202 in the initial substrate.

[0049] In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the second ion is a P-type ion, including: one or more of boron ions, indium ions, or gallium ions. That is to say, the conductivity type of the body region 202 is P-type.

[0050] Since the conductivity types of the first ion and the second ion are opposite, the conductivity types of the drift region 201 and the body region 202 are opposite.

[0051] In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the second ion can also be an N-type ion, including: one or more of phosphorus ions, arsenic ions, or antimony ions.

[0052] In this embodiment, after forming the body region 202, the forming method of the semiconductor structure further includes: removing the body region mask layer.

[0053] In this embodiment, the material of the body region mask layer is photoresist, and the body region mask layer is removed by an ashing process.

[0054] In this embodiment, the substrate includes: a substrate (not shown), and a plurality of fin structures (not shown) located on the surface of the substrate and separated from each other.

[0055] In other embodiments, the substrate is a planar substrate.

[0056] Please refer to Figure 3 , and a first isolation structure 211 is formed in the drift region 201.

[0057] In this embodiment, while forming the first isolation structure 211, a second isolation structure 212 is formed in the body region 202.

[0058] Specifically, in this embodiment, the method for forming the first isolation structure 211 and the second isolation structure 212 includes: forming an isolation structure mask layer (not shown) on the surface of the substrate 200, where the isolation structure mask layer exposes a part of the drift region 201 and a part of the body region 202; using the isolation structure mask layer as a mask to etch the substrate 200, forming a first isolation opening (not shown) in the drift region 201, and forming a second isolation opening (not shown) in the body region 202; forming an isolation structure material layer in the first isolation opening, the second isolation opening, and on the surface of the substrate 200, where the isolation structure material layer fills the first isolation opening and the second isolation opening; planarizing the isolation structure material layer until the surface of the substrate 200 is exposed. Thus, the first isolation structure 211 is formed in the first isolation opening in the drift region 201, and the second isolation structure 212 is formed in the second isolation opening in the body region 202.

[0059] In this embodiment, the material of the isolation structure mask layer is photoresist. After forming the first isolation opening and the second isolation opening and before forming the isolation structure material layer, the isolation structure mask layer is removed by an ashing process.

[0060] Please refer to Figure 4 , after forming the first isolation structure 211, a first gate structure 221 and a second gate structure 222 are formed on the substrate 200.

[0061] The first gate structure 221 extends across the boundary between the drift region 201 and the body region 202 in the first direction X, and there is a spacing W1 between the first gate structure 221 and the first isolation structure 211 in the first direction X, where the first direction X is perpendicular to the extending direction of the first gate structure 221.

[0062] In this embodiment, the first gate structure 221 includes: a first gate (not shown) located on the substrate 200, a first gate dielectric layer (not shown) located between the first gate and the substrate 200, and a first gate sidewall (not shown) located on the sidewall surface of the first gate.

[0063] The function of the first gate sidewall is, on the one hand, to protect the sidewall surfaces of the first gate dielectric layer and the first gate, avoiding being affected by subsequent processes, thereby maintaining the morphology and improving the stability of electrical performance; on the other hand, it is used to define the position of the source region subsequently.

[0064] In this embodiment, the first gate structure 221 is a dummy gate. Through the first gate sidewall, the position of the first gate opening can also be defined subsequently, so as to form a first metal gate in the first gate opening.

[0065] In this embodiment, through the first gate sidewall and the first isolation structure 211, the position of the first heavily doped region between the first gate sidewall and the first isolation structure 211 can also be defined subsequently.

[0066] The second gate structure 222 is located on the surface of the first isolation structure 211.

[0067] In this embodiment, the second gate structure 222 includes: a second gate (not shown) located on the substrate 200, a second gate dielectric layer (not shown) located between the second gate and the substrate 200, and a second gate sidewall (not shown) located on the sidewall surface of the second gate.

[0068] The function of the second gate sidewall is to protect the sidewall surfaces of the second gate dielectric layer and the second gate, avoid the sidewall surfaces of the second gate dielectric layer and the second gate from being affected by subsequent processes, thereby maintaining the morphology and improving the stability of electrical performance.

[0069] In this embodiment, the second gate structure 222 is a dummy gate. Through the second gate sidewall, the position of the second gate opening can also be defined subsequently, so as to form a second metal gate in the second gate opening.

[0070] In this embodiment, while forming the first gate structure 221 and the second gate structure 222, a third gate structure 223 is also formed on the substrate 200.

[0071] The third gate structure 223 is located on the drift region 201, and the first gate structure 221 and the third gate structure 223 are respectively located on both sides of the first isolation structure 211.

[0072] In this embodiment, there is a spacing W2 in the first direction X between the third gate structure 223 and the first isolation structure 211.

[0073] In this embodiment, the third gate structure 223 includes: a third gate (not shown) located on the substrate 200, a third gate dielectric layer (not shown) located between the third gate and the substrate 200, and a third gate sidewall (not shown) located on the sidewall surface of the third gate.

[0074] The function of the third gate sidewall is, on the one hand, to protect the sidewall surfaces of the third gate dielectric layer and the third gate, avoid being affected by subsequent processes, thereby maintaining the morphology and improving the stability of electrical performance; on the other hand, to define the position of the drain region subsequently.

[0075] In this embodiment, through the third gate sidewall and the first isolation structure 211, the position of the first heavily doped region between the third gate sidewall and the first isolation structure 211 can also be defined subsequently.

[0076] In this embodiment, the third gate structure 223 is a dummy gate. Through the third gate sidewall, the position of the third gate opening can also be defined subsequently, so as to facilitate the formation of a third metal gate within the third gate opening.

[0077] In this embodiment, while forming the first gate structure 221 and the second gate structure 222, a fourth gate structure 224 and a fifth gate structure 225 are also formed on the substrate 200.

[0078] Specifically, the fourth gate structure 224 is located on the body region 202. The fourth gate structure 224 is located between the second isolation structure 212 and the source region 232, and the fourth gate structure 224 also extends to the surface of a part of the second isolation structure 212.

[0079] The fifth gate structure 225 is located on the body region 202. Moreover, the fourth gate structure 224 and the fifth gate structure 225 are respectively located on both sides of the second isolation structure 212 along the first direction X, and the fifth gate structure 225 also extends to the surface of a part of the second isolation structure 212.

[0080] In this embodiment, the fourth gate structure 224 includes: a fourth gate (not shown) located on the substrate 200, a fourth gate dielectric layer (not shown) located between the fourth gate and the substrate 200, and a fourth gate sidewall (not shown) located on the sidewall surface of the fourth gate.

[0081] The function of the fourth gate sidewall is, on the one hand, to protect the sidewall surfaces of the fourth gate dielectric layer and the fourth gate, avoiding being affected by subsequent processes, thereby maintaining the morphology and improving the stability of electrical performance; on the other hand, it jointly defines the position of the source region with the first gate structure 221 in the subsequent process.

[0082] In this embodiment, the fourth gate structure 224 is a dummy gate. Through the fourth gate sidewall, the position of the fourth gate opening can also be defined subsequently, so as to facilitate the formation of a fourth metal gate within the fourth gate opening.

[0083] In this embodiment, the fifth gate structure 225 includes: a fifth gate (not shown) located on the substrate 200, a fifth gate dielectric layer (not shown) located between the fifth gate and the substrate 200, and a fifth gate sidewall (not shown) located on the sidewall surface of the fifth gate.

[0084] The function of the fifth gate sidewall is, on the one hand, to protect the sidewall surfaces of the fifth gate dielectric layer and the fifth gate, avoiding being affected by subsequent processes, thereby maintaining the morphology and improving the stability of electrical performance; on the other hand, to define the position of the second heavily doped region subsequently.

[0085] In this embodiment, the fifth gate structure 225 is a dummy gate. Through the fifth gate sidewall, the position of the fifth gate opening can also be defined subsequently, so as to form the fifth metal gate within the fifth gate opening.

[0086] Specifically, in this embodiment, the method for forming the first gate structure 221, the second gate structure 222, the third gate structure 223, the fourth gate structure 224, and the fifth gate structure 225 includes: forming a gate material layer (not shown) on the substrate 200; forming a gate structure mask layer (not shown) on the surface of the gate material layer, the gate structure mask layer covering the gate material layer on a part of the drift region 201 and a part of the body region 202; using the gate structure mask layer as a mask to etch the gate material layer until the surface of the substrate 200 is exposed, so as to form the first gate, the second gate, the third gate, the fourth gate, and the fifth gate on the substrate 200; forming a sidewall material film on the surface of the substrate 200, the surface of the first gate, the surface of the second gate, the surface of the third gate, the surface of the fourth gate, and the surface of the fifth gate; using an anisotropic etching process to etch the sidewall material film until the surface of the substrate 200, the top surfaces of the first gate, the second gate, the third gate, the fourth gate, and the fifth gate are exposed, forming a first gate sidewall on the sidewall of the first gate, a second gate sidewall on the sidewall of the second gate, a third gate sidewall on the sidewall of the third gate, a fourth gate sidewall on the sidewall of the fourth gate, and a fifth gate sidewall on the sidewall of the fifth gate.

[0087] In this embodiment, the materials of the first gate, the second gate, the third gate, the fourth gate, and the fifth gate include polysilicon.

[0088] In this embodiment, the method for forming the first gate structure 221, the second gate structure 222, the third gate structure 223, the fourth gate structure 224, and the fifth gate structure 225 further includes: forming a gate dielectric material layer (not shown) on the substrate 200 before forming the gate material layer; forming the gate material layer on the surface of the gate dielectric material layer; using the gate structure mask layer as a mask, and during the process of etching the gate material layer, also etching the gate dielectric material layer until the surface of the substrate 200 is exposed, so as to form the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer, the fourth gate dielectric layer, and the fifth gate dielectric layer.

[0089] In this embodiment, the material of the gate structure mask layer is photoresist. After etching the gate material layer and before forming the spacer material layer, the gate structure mask layer is removed by an ashing process.

[0090] In this embodiment, in the extending direction of the first gate structure 221, the first gate structure 221, the second gate structure 222, the third gate structure 223, the fourth gate structure 224, and the fifth gate structure 225 respectively straddle the fin structure.

[0091] Please refer to Figure 5 , a source region 232 is formed in the body region 202, and a drain region 231 is formed in the drift region 201. The source region 232 and the drain region 231 are respectively located on both sides of the first gate structure 221, and the first isolation structure 211 is located between the first gate structure 221 and the drain region 231.

[0092] The first isolation structure 211 and the second isolation structure 212 are respectively located on both sides of the source region 232.

[0093] In this embodiment, the third gate structure 223 is also located between the first isolation structure 211 and the drain region 231.

[0094] Specifically, in this embodiment, the method for forming the source region 232 and the drain region 231 includes: etching the substrate of the drift region 201 to form a drain opening (not shown) in the drift region 201, and the position of the drain opening is defined by the third gate spacer; etching the substrate of the body region 202 to form a source opening (not shown) in the body region 202, and the position of the source opening is defined by the first gate spacer and the fourth gate spacer; using an epitaxial growth process to form a doped drain material in the drain opening to form the drain region 231, and forming a doped source material in the source opening to form the source region 232.

[0095] The drain region 231 is doped with a third ion, the source region 232 is doped with a fourth ion, and the third ion and the fourth ion have the same conduction type.

[0096] In this embodiment, the semiconductor structure to be formed is an N-type LDMOS, and the third ion and the fourth ion are N-type ions, including: one or more of phosphorus ions, arsenic ions, or antimony ions. Correspondingly, the conduction types of both the drain region 231 and the source region 232 are N-type.

[0097] In other embodiments, the semiconductor structure to be formed is a P-type LDMOS, and the third ion and the fourth ion can also be P-type ions, including: one or more of boron ions, indium ions, or gallium ions.

[0098] In this embodiment, while forming the source region 232 and the drain region 231, a first heavily doped region 241 is formed in the drift region 201. The conductivity type of the first heavily doped region 241 is the same as that of the drift region 201, and the first heavily doped region 241 is located between the first gate structure 221 and the first isolation structure 211.

[0099] In this embodiment, the first heavily doped region 241 is also located between the third gate structure 223 and the first isolation structure 211.

[0100] In this embodiment, the method of forming the first heavily doped region 241 includes: during the etching process of forming the source region opening and the drain region opening, the surface of the substrate 200 exposed between the first isolation structure 211 and the first gate structure 221 and between the first isolation structure 211 and the third gate structure 223 in the drift region 201 is also etched, and a first heavily doped opening (not shown) is formed between the first isolation structure 211 and the first gate structure 221 and between the first isolation structure 211 and the third gate structure 223. The position of the first heavily doped opening is defined by the first isolation structure 211, the first gate sidewall, and the third gate sidewall; while forming the doped source material and drain material, the first heavily doped opening is filled with material through the epitaxial growth process to form the first heavily doped region 241.

[0101] The first heavily doped region 241 is doped with a fifth ion, and the conductivity type of the fifth ion is the same as that of the third ion.

[0102] Specifically, in this embodiment, the fifth ion is an N-type ion, including one or more of phosphorus ions, arsenic ions, or antimony ions.

[0103] Please refer to Figure 6 , a second heavily doped region 242 is formed in the body region 202, and the conductivity type of the second heavily doped region 242 is the same as that of the body region 202.

[0104] Specifically, the second heavily doped region 242 and the source region 232 are respectively located on both sides of the second isolation structure 212.

[0105] In this embodiment, the method of forming the second heavily doped region 242 includes: etching the substrate 200 of the body region 202 to form a second heavily doped opening (not shown) in the body region 202. The position of the second heavily doped opening is defined by the fifth gate sidewall; the epitaxial growth process is used to fill the second heavily doped opening with material to form the second heavily doped region 242.

[0106] The second doping region 242 is doped with a sixth ion, and the sixth ion and the second ion have the same conduction type.

[0107] Specifically, in this embodiment, the sixth ion is a P-type ion, including: one or more of boron ions, indium ions, or gallium ions.

[0108] Please refer to Figure 7 , after forming the source region 232, the drain region 231, the first doping region 241, and the second doping region 242, the first gate is removed to form a first gate opening; a metal gate material is filled in the first gate opening to form a first metal gate, so as to form a first gate structure 321.

[0109] In this embodiment, when removing the first gate, the second gate, the third gate, the fourth gate, and the fifth gate are also removed to form a second gate opening, a third gate opening, a fourth gate opening, and a fifth gate opening respectively; when filling the metal gate material in the first gate opening, the metal gate material is also filled in the second gate opening, the third gate opening, the fourth gate opening, and the fifth gate opening to form a second gate structure 322, a third gate structure 323, a fourth gate structure 324, and a fifth gate structure 325.

[0110] Specifically, the method for forming the first gate structure 321, the second gate structure 322, the third gate structure 323, the fourth gate structure 324, and the fifth gate structure 325 includes: after forming the source region 232, the drain region 231, the first heavily doped region 241, and the second heavily doped region 242, forming a first dielectric layer 250 on the surfaces of the source region 232, the drain region 231, the first heavily doped region 241, the second heavily doped region 242, the surface of the first isolation structure 211, the surface of the second isolation structure 212, the surface of the substrate 200, the sidewall surfaces of the first gate structure 221, the sidewall surfaces of the second gate structure 222, the sidewall surfaces of the third gate structure 223, the sidewall surfaces of the fourth gate structure 224, and the sidewall surfaces of the fifth gate structure 225, wherein the first dielectric layer 250 exposes the top surfaces of the first gate, the second gate, the third gate, the fourth gate, and the fifth gate; after forming the dielectric layer, etching the exposed first gate, second gate, third gate, fourth gate, and fifth gate until the first gate, second gate, third gate, fourth gate, and fifth gate are removed, so as to form a first gate opening between the first gate sidewalls, a second gate opening between the second gate sidewalls, a third gate opening between the third gate sidewalls, a fourth gate opening between the fourth gate sidewalls, and a fifth gate opening between the fifth gate sidewalls; filling a metal gate material in the first gate opening, the second gate opening, the third gate opening, the fourth gate opening, and the fifth gate opening to form the first gate structure 321, the second gate structure 322, the third gate structure 323, the fourth gate structure 324, and the fifth gate structure 325.

[0111] Please refer to Figure 8 , after forming the first gate structure 321, the second gate structure 322, the third gate structure 323, the fourth gate structure 324, and the fifth gate structure 325, etching the first dielectric layer 250 until the surfaces of the drain region 231, the source region 232, and the second heavily doped region 242 are exposed, and forming a first conductive opening (not shown), a second conductive opening (not shown), and a third conductive opening (not shown) in the first dielectric layer 250, wherein the first conductive opening exposes the surface of the drain region 231, the second conductive opening exposes the surface of the source region 232, and the third conductive opening exposes the surface of the second heavily doped region 242; filling a conductive material in the first conductive opening, the second conductive opening, and the third conductive opening to form a first conductive structure 261 in the first conductive opening, a second conductive structure 262 in the second conductive opening, and a third conductive structure 263 in the third conductive opening.

[0112] The first conductive structure 261 is located on the drain region 231, the second conductive structure 262 is located on the source region 232, and the third conductive structure 263 is located on the second heavily doped region 242.

[0113] In this embodiment, the method for forming the semiconductor structure further includes: after forming the first conductive structure 261, the second conductive structure 262, and the third conductive structure 263, a second dielectric layer is further formed on the first dielectric layer 250, and the second dielectric layer covers the body region 202 and the drift region 201; the second dielectric layer is etched to form a first gate conductive opening and a second gate conductive opening in the second dielectric layer, the first gate conductive opening exposes the surface of the first gate structure 321, and the second gate conductive opening exposes the surface of the second gate structure 322; a conductive material is filled in the first gate conductive opening and the second gate conductive opening to form a first gate conductive structure (not shown) and a second gate conductive structure.

[0114] In this embodiment, the first gate conductive structure and the second gate conductive structure are electrically connected.

[0115] In other embodiments, the first gate conductive structure and the second gate conductive structure are not electrically connected.

[0116] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method. Please continue to refer to Figure 8 , including: a substrate 200 having adjacent drift region 201 and body region 202, and the conductivity type of the drift region 201 is opposite to that of the body region 202; a first gate structure 321 located on the substrate 200, the first gate structure 321 straddles the boundary between the drift region 201 and the body region 202 in a first direction X, and the first direction X is perpendicular to the extending direction of the first gate structure 321; a source region 232 and a second isolation structure 212 located in the body region 202; a drain region 231 and a first isolation structure 211 located in the drift region 201, the source region 232 and the drain region 231 are respectively located on both sides of the first gate structure 321, the first isolation structure 211 is located between the first gate structure 321 and the drain region 231, the first isolation structure 211 and the second isolation structure 212 are respectively located on both sides of the source region 232, and there is a spacing W1 between the first gate structure 231 and the first isolation structure 211 in the first direction X (such as Figure 4as shown); a second gate structure 322 located on the surface of the first isolation structure 211; a fourth gate structure 324 located on the body region 202, the fourth gate structure 324 being located between the second isolation structure 212 and the source region 232, and the fourth gate structure 324 further extending to a part of the surface of the second isolation structure 212; a fifth gate structure 325 located on the body region 202, the fifth gate structure 325 and the fourth gate structure 324 being respectively located on both sides of the second isolation structure 212, and the fifth gate structure 325 further extending to a part of the surface of the second isolation structure 212.

[0117] On the one hand, since there is a spacing W1 between the first gate structure 321 and the first isolation structure 211 in the first direction X, not only is the electric field strength generated at the boundary between the first isolation structure 211 and the drift region 201 and its vicinity not easily enhanced by the high voltage applied to the first gate structure 321, thus reducing the hot carriers generated at the boundary between the first isolation structure 211 and the drift region 201 and its vicinity. At the same time, the path distance for the hot carriers generated at the boundary between the first isolation structure 211 and the drift region 201 and its vicinity to move to the first gate structure 321 is increased. Therefore, the difficulty of the hot carriers injecting into the first gate structure 321 is increased. Thus, under the combined action of the above two aspects, the hot carriers injected into the first gate structure 321 are preferably reduced, the influence on the electrical characteristics of the semiconductor structure is reduced, and further, the performance of the semiconductor structure is improved. On the other hand, since the semiconductor structure further includes a second gate structure 322 located on the surface of the first isolation structure 211, by applying a higher voltage to the second gate structure 322, the control ability of the carriers in the drift region 201 around the first isolation structure 211 can be enhanced to improve the voltage division ability of the drift region 201, so that the semiconductor structure has better breakdown voltage ability, and further, the performance of the semiconductor structure is improved.

[0118] Specifically, the fourth gate structure 324 and the fifth gate structure 325 are respectively located on both sides of the second isolation structure 212 in the first direction X.

[0119] In this embodiment, the substrate includes: a substrate (not shown), and a plurality of fin structures (not shown) located on the surface of the substrate and separated from each other.

[0120] In other embodiments, the substrate is a planar substrate.

[0121] The material of the substrate 200 includes silicon, germanium, silicon germanium or silicon carbide; it may also include silicon on insulator (SOI), germanium on insulator (GOI); or it may also be other materials, such as group III-V compounds such as gallium arsenide.

[0122] In this embodiment, the material of the substrate 200 is silicon.

[0123] The drift region 201 is doped with a first ion, and the body region 202 is doped with a second ion.

[0124] In this embodiment, the semiconductor structure is an N-type LDMOS. The first ion is an N-type ion, including: one or more of phosphorus ions, arsenic ions or antimony ions. That is to say, the conductivity type of the drift region 201 is N-type. The second ion is a P-type ion, including: one or more of boron ions, indium ions or gallium ions. That is to say, the conductivity type of the body region 202 is P-type. Since the conductivity types of the first ion and the second ion are opposite, the conductivity types of the drift region 201 and the body region 202 are opposite.

[0125] In other embodiments, the semiconductor structure is a P-type LDMOS, and the first ion can also be a P-type ion, including: one or more of boron ions, indium ions or gallium ions. The second ion can also be an N-type ion, including: one or more of phosphorus ions, arsenic ions or antimony ions.

[0126] The drain region 231 is doped with a third ion, and the source region 232 is doped with a fourth ion, and the conductivity types of the third ion and the fourth ion are the same.

[0127] In this embodiment, the third ion and the fourth ion are N-type ions, including: one or more of phosphorus ions, arsenic ions or antimony ions. Correspondingly, the conductivity types of the drain region 231 and the source region 232 are both N-type.

[0128] In other embodiments, the semiconductor structure is a P-type LDMOS. The third ion and the fourth ion can also be P-type ions, including: one or more of boron ions, indium ions or gallium ions.

[0129] In this embodiment, the first gate structure 321 includes: a first metal gate (not shown) located on the substrate 200, a first gate dielectric layer (not shown) located between the first metal gate and the substrate 200, and a first gate sidewall (not shown) located on the sidewall surface of the first metal gate.

[0130] In other embodiments, the first gate structure includes: a first gate located on the substrate, a first gate dielectric layer located between the first gate and the substrate, and a first gate sidewall located on the sidewall surface of the first gate. Among them, the material of the first gate includes polysilicon.

[0131] In this embodiment, the second gate structure 322 includes: a second metal gate (not shown) on the substrate 200, a second gate dielectric layer (not shown) between the second metal gate and the substrate 200, and a second gate sidewall (not shown) on the sidewall of the second metal gate.

[0132] In this embodiment, the second gate structure includes: a second gate on the substrate, a second gate dielectric layer between the second gate and the substrate, and a second gate sidewall on the sidewall of the second gate. Among them, the material of the second gate includes polysilicon.

[0133] In this embodiment, the distance W1 between the first gate structure 321 and the first isolation structure 211 is greater than 0 micrometers and less than or equal to 0.3 micrometers.

[0134] If the distance W1 is too large, the control ability of the carriers in the drift region 201 near the middle between the first gate structure 321 and the first isolation structure 211 is poor, resulting in poor performance of the semiconductor structure. If the distance W1 is too small, the effect of reducing hot carrier injection is poor, which is not conducive to reducing the influence on the electrical characteristics of the semiconductor structure. Therefore, when selecting a suitable range of the distance W1, that is, when the distance W1 is greater than 0 micrometers and less than or equal to 0.3 micrometers, on the one hand, the control ability of the carriers in all the drift regions 201 between the first gate structure 321 and the first isolation structure 211 is good, and on the other hand, it is also beneficial to better reduce the influence on the electrical characteristics of the semiconductor structure, thereby better improving the performance of the semiconductor structure.

[0135] In this embodiment, the semiconductor structure further includes: a first gate conductive structure (not shown) on the first gate structure 321; a second gate conductive structure (not shown) on the second gate structure 322.

[0136] In this embodiment, the first gate conductive structure is electrically connected to the second gate conductive structure. Therefore, a high voltage can be applied to the first gate structure 321 and the second gate conductive structure 322 simultaneously, so as to realize the control of the carriers in the drift region 201 around the first isolation structure 211 through the second gate conductive structure 322.

[0137] In other embodiments, the first gate conductive structure and the second gate conductive structure are not electrically connected. That is, voltages are applied to the first gate structure and the second gate structure respectively.

[0138] In this embodiment, a first heavily doped region 241 is provided in the drift region 201. The conduction type of the first heavily doped region 241 is the same as that of the drift region 201, and the first heavily doped region 241 is located between the first gate structure 321 and the first isolation structure 211.

[0139] Since there is a first heavily doped region 241 in the drift region 201, the conductivity type of the first heavily doped region 241 is the same as that of the drift region 201, and the first heavily doped region 241 is located between the first gate structure 321 and the first isolation structure 211. Therefore, the contact resistance of the surface of the drift region 201 between the first gate structure 321 and the first isolation structure 211 is reduced through the first heavily doped region 241. Thus, while enabling the semiconductor structure to have better breakdown voltage capability, the resistance of the semiconductor structure is reduced, and the performance of the semiconductor structure is improved.

[0140] The first heavily doped region 241 is doped with a fifth ion, and the conductivity type of the fifth ion is the same as that of the third ion.

[0141] Specifically, in this embodiment, the fifth ion is an N-type ion, including: one or more of phosphorus ions, arsenic ions, or antimony ions.

[0142] In this embodiment, the depth of the first heavily doped region 241 is respectively less than the depths of the drain region 231 and the source region 232.

[0143] In this embodiment, the depth range of the first heavily doped region 241 is 200 angstroms to 500 angstroms. Thus, while reducing the contact resistance, the influence of the first heavily doped region 241 on other electrical characteristics of the semiconductor structure is avoided.

[0144] In this embodiment, the semiconductor structure further includes: a third gate structure 323 located on the substrate 200.

[0145] Specifically, the third gate structure 323 is located on the drift region 201, and the drain region 231 and the first isolation structure 211 are respectively located on both sides of the third gate structure 323.

[0146] In this embodiment, the third gate structure 323 includes: a third metal gate (not shown) located on the substrate 200, a third gate dielectric layer (not shown) located between the third metal gate and the substrate 200, and a third gate sidewall (not shown) located on the sidewall surface of the third gate.

[0147] In other embodiments, the third gate structure includes: a third gate located on the substrate, a third gate dielectric layer located between the third gate and the substrate, and a third gate sidewall located on the sidewall surface of the third gate. Among them, the material of the third gate includes polysilicon.

[0148] In this embodiment, there is a spacing W2 between the third gate structure 323 and the first isolation structure 211 along the first direction X (asFigure 4 as shown

[0149] Since there is a spacing W2 between the third gate structure 323 and the first isolation structure 211 in the first direction X, that is, the spacing between the first isolation structure 211 and the drain region 231 is relatively large. Therefore, the size of the moving region of carriers between and near the third gate structure 323 and the first isolation structure 211 is increased. Thus, the situation of carrier congestion is reduced, the heating problem caused by carrier congestion is improved, the performance of the semiconductor structure is enhanced, and the service life of the semiconductor structure is prolonged.

[0150] In this embodiment, the spacing W2 between the third gate structure 323 and the first isolation structure 211 is greater than 0 micrometer and not more than 0.2 micrometer.

[0151] If the spacing W2 is too large, it is not conducive to controlling the carriers in the drift region 201 near the middle between the first isolation structure 211 and the third gate structure 323 through the second gate structure 322 and the third gate structure 323, resulting in poor performance of the semiconductor structure. If the spacing W2 is too small, the effect of improving the carrier congestion situation is poor, which is not conducive to improving the heating problem caused by carrier congestion. Therefore, when selecting an appropriate range of the spacing W2, that is, when the spacing W2 is greater than 0 micrometer and not more than 0.2 micrometer, on the one hand, the control ability of the carriers in the drift region 201 between the first isolation structure 211 and the third gate structure 323 is better, and on the other hand, it is also conducive to better improving the heating problem caused by carrier congestion. Thus, the performance of the semiconductor structure is better improved, and the service life of the semiconductor structure is prolonged.

[0152] In this embodiment, the first heavily doped region 241 is also located between the third gate structure 323 and the first isolation structure 211.

[0153] Therefore, the contact resistance on the surface of the drift region 201 between the third gate structure 323 and the first isolation structure 211 can also be reduced by the first heavily doped region 241. Thus, the resistance of the semiconductor structure is further reduced, and the performance of the semiconductor structure is improved.

[0154] In this embodiment, the fourth gate structure 324 includes: a fourth metal gate (not shown) located on the substrate 200, a fourth gate dielectric layer (not shown) located between the fourth metal gate and the substrate 200, and a fourth gate sidewall (not shown) located on the sidewall surface of the fourth gate.

[0155] In other embodiments, the fourth gate structure includes: a fourth gate located on a substrate, a fourth gate dielectric layer located between the fourth gate and the substrate, and a fourth gate sidewall located on a sidewall surface of the fourth gate. The material of the fourth gate includes polysilicon.

[0156] In this embodiment, the fifth gate structure 325 includes: a fifth metal gate (not shown) located on the substrate 200, a fifth gate dielectric layer (not shown) located between the fifth metal gate and the substrate 200, and a fifth gate sidewall (not shown) located on a sidewall surface of the fifth gate.

[0157] In other embodiments, the fifth gate structure includes: a fifth gate located on a substrate, a fifth gate dielectric layer located between the fifth gate and the substrate, and a fifth gate sidewall located on a sidewall surface of the fifth gate. The material of the fifth gate includes polysilicon.

[0158] In this embodiment, in an extending direction of the first gate structure 321, the first gate structure 321, the second gate structure 322, the third gate structure 323, the fourth gate structure 324, and the fifth gate structure 325 respectively straddle the fin structure.

[0159] In this embodiment, the semiconductor structure further includes: a second heavily doped region 242 located in the body region 202, and a conductivity type of the second heavily doped region 242 is the same as that of the body region 202.

[0160] Specifically, the second heavily doped region 242 and the source region 232 are respectively located on two sides of the second isolation structure 212, and the fifth gate structure 325 is located between the second heavily doped region 242 and the second isolation structure 212.

[0161] The second heavily doped region 242 is doped with a sixth ion, and a conductivity type of the sixth ion is the same as that of the second ion.

[0162] Specifically, in this embodiment, the sixth ion is a P-type ion, including: one or more of boron ions, indium ions, or gallium ions.

[0163] In this embodiment, the semiconductor structure further includes: a first conductive structure 261 located on the drain region 231; a second conductive structure 262 located on the source region 232; a third conductive structure 263 located on the second heavily doped region 242.

[0164] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate having an adjacent drift region and a body region, and the conductivity type of the drift region is opposite to that of the body region; A first gate structure located on the substrate, the first gate structure spanning the boundary between the drift region and the body region in a first direction, and the first direction is perpendicular to the extending direction of the first gate structure; A source region and a second isolation structure located in the body region; A drain region and a first isolation structure located in the drift region, the source region and the drain region are respectively located on both sides of the first gate structure, the first isolation structure is located between the first gate structure and the drain region, and the first isolation structure and the second isolation structure are respectively located on both sides of the source region, and there is a spacing between the first gate structure and the first isolation structure in the first direction; A second gate structure located on the surface of the first isolation structure; A fourth gate structure located on the body region, the fourth gate structure is located between the second isolation structure and the source region, and the fourth gate structure also extends to a part of the surface of the second isolation structure; A fifth gate structure located on the body region, the fifth gate structure and the fourth gate structure are respectively located on both sides of the second isolation structure, and the fifth gate structure also extends to a part of the surface of the second isolation structure.

2. The semiconductor structure according to claim 1, wherein The spacing between the first gate structure and the first isolation structure is greater than 0 micrometers and less than or equal to 0.3 micrometers.

3. The semiconductor structure according to claim 1, characterized in that, Further comprising: A first gate conductive structure located on the first gate structure; A second gate conductive structure located on the second gate structure.

4. The semiconductor structure according to claim 3, wherein The first gate conductive structure is electrically connected to the second gate conductive structure.

5. The semiconductor structure according to claim 1, wherein, A first heavily doped region is formed in the drift region, the conductivity type of the first heavily doped region is the same as that of the drift region, and the first heavily doped region is located between the first gate structure and the first isolation structure.

6. The semiconductor structure according to claim 5, wherein, Further comprising: A third gate structure located on the drift region, and the drain region and the first isolation structure are respectively located on both sides of the third gate structure.

7. The semiconductor structure according to claim 6, wherein There is a spacing between the third gate structure and the first isolation structure in the first direction.

8. The semiconductor structure according to claim 7, wherein, The spacing between the third gate structure and the first isolation structure is greater than 0 micrometers and less than or equal to 0.2 micrometers.

9. The semiconductor structure according to claim 7, wherein, The first heavily doped region is also located between the third gate structure and the first isolation structure.

10. A method for forming a semiconductor structure, characterized in that, Comprising: Forming a substrate having an adjacent drift region and a body region, and the conductivity type of the drift region is opposite to that of the body region; Forming a first isolation structure in the drift region; After forming the first isolation structure, forming a first gate structure and a second gate structure on the substrate, the first gate structure spanning the boundary between the drift region and the body region in a first direction, the second gate structure is located on the surface of the first isolation structure, and there is a spacing between the first gate structure and the first isolation structure in the first direction, and the first direction is perpendicular to the extending direction of the first gate structure; A source region is formed in the body region, and a drain region is formed in the drift region. The source region and the drain region are respectively located on two sides of the first gate structure, and the first isolation structure is located between the first gate structure and the drain region; While forming the first gate structure, a third gate structure is formed on the substrate. The third gate structure is also located between the first isolation structure and the drain region; there is a spacing between the third gate structure and the first isolation structure along the first direction.

11. The method for forming a semiconductor structure according to claim 10, wherein It further includes: While forming the source region and the drain region, a first heavily doped region is formed in the drift region. The conduction type of the first heavily doped region is the same as that of the drift region, and the first heavily doped region is located between the first gate structure and the first isolation structure.

12. The method for forming a semiconductor structure according to claim 11, wherein The process of forming the first heavily doped region includes an epitaxial growth process.

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