A cache management method, system, device and medium

Abstract

The present invention provides a cache management method, including: counting the behaviors of each core with respect to the cache, and setting corresponding states for each core based on the impact of the behaviors on the cache; judging the cores with abnormal states according to a preset management strategy based on the states of the cores, and restricting the operations of the cores with abnormal states to access the cache. In view of the demand for shared cache in multi-core parallel computing in deep learning, the present invention adds automatic recognition of the access frequency and pattern of a single core on the basis of the LRU replacement strategy, and uses this as a basis to separately restrict the cache replacement initiated by the shared cache for different cores, so as to realize the dynamic allocation of the shared cache.

Description

Technical Field

[0001] The present invention belongs to the field of computers, and particularly relates to a cache management method, system, device and medium. Background Art

[0002] Due to the development of the big data industry, the amount of data has shown an explosive growth trend. With the failure of Moore's Law, large-scale applications, especially AI applications, have adopted multi-core and even many-core parallel computing solutions at the chip level. Chip cache refers to a storage device such as SRAM integrated on the chip, which is different from the off-chip storage device of the chip. The most well-known cache concept is the CPU cache. The space available for placing caches on the chip and the power consumption that can be supported are limited. Therefore, compared with off-chip storage devices, the capacity of chip caches is very small, but the speed is much faster. Under the existing architecture, CPUs and other computing core controllers all adopt a multi-level storage architecture. Taking the CPU as an example, the cache is at the top. The CPU communicates with the off-chip memory through the cache. That is, when the CPU wants to read a piece of data, it first looks for it in the CPU cache. If found, it is immediately read and sent to the CPU for processing; if not found, it is read from the relatively slow memory and sent to the CPU for processing, and at the same time, the data block where this data is located is transferred into the cache, so that subsequent reads of the entire data block can be performed from the cache without having to call the memory again. Since the size of the cache is necessarily much smaller than off-chip storage, when the on-chip core accesses data not in the cache, it must read it from off-chip storage into the cache. If the cache is full at this time, some data in the cache needs to be cleared (data not modified) or written back to off-chip storage (data modified), and this is cache replacement. Because the on-chip cache resources are limited, when multiple cores on the chip work together, there are usually two types of caches. One is the cache resources private to each core and only accessible to itself, which is usually relatively small. The other is the cache shared globally or among some cores. The sharing method can improve the utilization efficiency of cache resources on the one hand,

[0003] On the other hand, different cores can also improve the cooperation efficiency by operating on the same data in the shared cache. Since the bottleneck of modern computing is often data access, adopting a suitable cache size and cache replacement strategy has also become the key to improving system performance. Different from the highly customizable configuration of private caches, shared caches, especially many-core shared caches containing various different types of cores, usually can only adopt the simplest LRU (Least Recently Used) replacement strategy, that is, when replacement is needed, the data that has not been accessed for the longest time is selected for replacement. However, this simple implementation is difficult to meet the efficient scheduling problem of caches in multiple parallel computations of AI. Summary of the Invention

[0004] To solve the above problems, the present invention proposes a cache management method, including:

[0005] Statistically analyze the behavior of each core with respect to the cache, and set a corresponding state for each core based on the impact of the behavior on the cache;

[0006] Based on the state of the core, determine the core with an abnormal state according to a preset management strategy, and restrict the operation of the core with the abnormal state to access the cache.

[0007] In some embodiments of the present invention, statistically analyzing the behavior of each core with respect to the cache, and setting a corresponding state for each core based on the impact of the behavior on the cache includes:

[0008] Periodically statistically analyze the number of cache accesses and the number of initiated cache replacements of each core;

[0009] In response to the number of accesses reaching a first predetermined number and the number of initiated cache replacements being equal to the number of accesses, set the state of the corresponding core to abnormal.

[0010] In some embodiments of the present invention, based on the state of the core, determine the core with an abnormal state according to a preset management strategy, and restrict the operation of the core with the abnormal state to access the cache includes:

[0011] In response to the state of the corresponding core being abnormal, restrict the cache replacement initiated by the core for a new cache.

[0012] In some embodiments of the present invention, statistically analyzing the behavior of each core with respect to the cache, and setting a corresponding state for each core based on the impact of the behavior on the cache further includes:

[0013] Statistically analyze the cache that has not been released after each core initiates a cache replacement, and calculate the access number occupancy ratio of the unreleased cache and the access number based on the access number;

[0014] Determine whether the access number occupancy ratio is higher than a first predetermined ratio. In response to the access number occupancy ratio being higher than the first predetermined ratio, set the state of the corresponding core to abnormal.

[0015] In some embodiments of the present invention, statistically analyzing the behavior of each core with respect to the cache, and setting a corresponding state for each core based on the impact of the behavior on the cache further includes:

[0016] Statistically analyze the cache space occupied after each core initiates a cache replacement, and calculate the ratio of the cache space occupied by each core to the total cache space. In response to the ratio being higher than a second predetermined ratio, set the state of the corresponding core to abnormal.

[0017] In some embodiments of the present invention, the method further includes:

[0018] Count the number of times each core accesses the cache and initiates cache replacement. In response to the number of times each core accesses the cache and initiates cache replacement being higher than a second predetermined number, set the status of the core with the largest number of cache replacement initiations to abnormal.

[0019] In some embodiments of the present invention, based on the status of the core, determine the core with abnormal status according to a preset management strategy, and restrict the operation of the core with abnormal status accessing the cache, including:

[0020] In response to all the caches occupied by the core being released, set the status of the core to normal.

[0021] Another aspect of the present invention also proposes a cache management system, including:

[0022] A calculation and analysis module configured to count the behavior of each core with respect to the cache and set a corresponding status for each core based on the impact of the behavior on the cache;

[0023] A core cache management module configured to

[0024] Based on the status of the core, determine the core with abnormal status according to a preset management strategy, and restrict the operation of the core with abnormal status accessing the cache.

[0025] Another aspect of the present invention also proposes a computer device, including:

[0026] At least one processor; and

[0027] A memory storing computer instructions executable on the processor, and when the instructions are executed by the processor, the steps of the method according to any one of the above embodiments are implemented.

[0028] Another aspect of the present invention is a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the steps of the method according to any one of the above embodiments are implemented.

[0029] In view of the demand for shared caches in multi-core parallel computing in deep learning, based on the LRU replacement strategy, the present invention adds automatic recognition of the access frequency and pattern of a single core, and uses this as a basis to separately restrict the cache replacement initiated by the shared cache for different cores, thereby realizing the dynamic allocation of the shared cache. Description of the Drawings

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0031] Figure 1 Flowchart of a cache management method provided by an embodiment of the present invention;

[0032] Figure 2 Structural schematic diagram of a cache management system provided by an embodiment of the present invention;

[0033] Figure 3 Structural schematic diagram of a computer device provided by an embodiment of the present invention;

[0034] Figure 4 Structural schematic diagram of a computer-readable storage medium provided by an embodiment of the present invention. Detailed implementation manners

[0035] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the following further elaborates on the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0036] It should be noted that all the expressions using "first" and "second" in the embodiments of the present invention are used to distinguish two entities or parameters with the same name but different, and it can be seen that "first" and "second" are only for the convenience of expression and should not be construed as a limitation on the embodiments of the present invention. This will not be elaborated one by one in the subsequent embodiments.

[0037] In the field of AI parallel computing in the field of artificial intelligence, in the design of AI processors, the LRU replacement strategy is adopted for shared caches, and there is room for optimization in AI computing represented by deep learning.

[0038] First, in the AI multi-core parallel computing for deep learning, during the same period, there will be clear divisions among the cores, and each core will perform calculations at different levels. The data requirements vary greatly, and often the same set of data is operated on successively. During most of the calculation time, if each core has the right to use the entire shared cache, it is easy to have a situation where a set of data is repeatedly read in and then replaced, reducing the cache usage efficiency.

[0039] Secondly, the model data used in AI computing is often extremely large, and a single set of model data is much larger than the shared cache size. That is to say, when a certain core needs to read model data, it will continuously read new data, causing cache replacement. In this case, its frequent access will not only occupy a large amount of shared cache resources, but such occupation will not bring an improvement in efficiency. Instead, it will affect the use of the cache by other cores, thus affecting the overall performance.

[0040] As Figure 1 shown, to solve the above problems, the present invention proposes a cache management method, including:

[0041] Step S1, statistically analyze the behavior of each core towards the cache, and set a corresponding state for each core based on the impact of the behavior on the cache;

[0042] Step S2, based on the state of the core, judge the core with abnormal state according to a preset management strategy, and restrict the operation of the core with abnormal state accessing the cache.

[0043] In an embodiment of the invention, a core refers to a processing unit of a processor such as a CPU, a GPU, or an AI chip. The behavior of a core towards the cache can be a read / write request initiated by the core to the cache, that is, it includes reading data and writing data. Reading data also includes the process of writing data from memory or other external storage media to the cache when the corresponding data does not exist in the cache. It can be understood as operations such as adding, deleting, modifying, and querying the cache by the core, and there are different definitions according to different CPUs.

[0044] Specifically, in step S1, first, multiple counters for recording the behavior of each core towards the cache need to be set in the shared cache controller, and each counter corresponds to one behavior. The behavior of the core towards the cache is statistically analyzed through the corresponding counter, and at the same time, the impact of the core on the cache is represented by the values of multiple behavior counters corresponding to each core. The impact on the cache caused by the cumulative behavior of the core towards the cache refers to the visible or foreseeable impact caused by the cumulative behavior of the core towards the cache. For example, if a certain core frequently writes data to the cache, occupying a large amount of cache space, it will cause the data service ability of the cache for other cores to decrease. When other cores need data, it will frequently trigger the replacement of cache data, resulting in a decrease in the effective utilization rate of the cache. That is to say, the so-called behavior of the core towards the cache does not refer to a single behavior of the core towards the cache, because a single behavior has little impact on the cache unless it triggers a cache failure. Therefore, in this embodiment, the impact of the so-called behavior of the core towards the cache on the cache refers to the impact after a certain measurement of the behavior of the core towards the cache, that is, the impact on the cache according to the common operation behaviors of the core and the cache, and is represented in the way of adding the values of the corresponding counters.

[0045] Further, multiple counters set for each core by the shared cache controller are used to count the cache behavior corresponding to each core. When the value of one counter or multiple counters reaches a certain value, it is compared with a preset threshold. If it exceeds the set threshold, it is considered that the state of the core is abnormal. If it does not exceed the set threshold, it is considered that the core is within the normal range of the scheduling mechanism.

[0046] In step S2, the behavior of the core accessing the cache is managed based on the state of the core determined in the above steps. Specifically, if the state of the corresponding core is determined to be abnormal, the use of the cache by the abnormal core is restricted, including: prohibiting the corresponding core from performing cache replacement operations to prevent the abnormal core from overusing the cache. In some embodiments of the present invention, the behavior of each core accessing the cache is counted, and the corresponding state is set for each core based on the impact of the behavior on the cache, including:

[0047] Periodically count the number of cache accesses and the number of initiated cache replacements for each core;

[0048] In response to the number of accesses reaching a first predetermined number and the number of initiated cache replacements being equal to the number of accesses, set the state of the corresponding core to abnormal.

[0049] In this embodiment, the number of cache accesses by the core refers to the number of times the core reads data from a certain address space in the cache, that is, the number of times the core obtains data from the cache. The number of initiated cache replacements refers to when the data required by the core does not exist in the cache, reading new data from other memories and storing the new data in the idle space in the cache, or erasing the data in the storage space with data in the cache according to the LRU algorithm and saving the new data to the space after erasure.

[0050] Further, the shared cache controller periodically counts the number of cache accesses and the number of initiated cache replacements for each core. At the same time, the number of cache accesses of each core is compared with a preset predetermined number. If the number of accesses of a certain core exceeds the predetermined number, at this time, it is judged and compared whether the number of accesses of the core is the same as the number of initiated cache replacements. If they are the same, the state of the core is set to abnormal.

[0051] In some embodiments of the present invention, based on the state of the core, the core with abnormal state is judged according to a preset management strategy, and the operation of the core with abnormal state accessing the cache is restricted, including:

[0052] In response to the state of the corresponding core being abnormal, restrict the cache replacement initiated by the core for a new cache.

[0053] In this embodiment, if the state of the corresponding core is set to abnormal, the cache replacement requests initiated by the shared cache controller for this core again are blocked, and the core is refused to use new cache space. In addition, other data in the cache can be normally accessed by the cache, and the core is also allowed to change the data in a certain storage space in the cache, that is, the abnormal core is allowed to rewrite the data in the cache, but the core is not allowed to occupy new storage space again.

[0054] In some embodiments of the present invention, counting the behavior of each core with respect to the cache and setting a corresponding state for each core based on the impact of the behavior on the cache further includes:

[0055] Counting the cache that has not been released after each core initiates cache replacement, and calculating the access times occupancy ratio of the unreleased cache and the access times according to the access times;

[0056] Judging whether the access times occupancy ratio is higher than a first predetermined ratio, and in response to the access times occupancy ratio being higher than the first predetermined ratio, setting the state of the corresponding core to abnormal.

[0057] In this embodiment, the operations of each core on the corresponding address space in the cache are associated by the shared cache controller. Specifically, if core 1 initiates a cache replacement request to the cache and reads a certain amount of data from the memory and saves it to storage space 1, then the cache replacement initiated for storage space 1 is associated and bound with this core as a cache replacement behavior (regardless of the size of storage space 1). If the data in cache space 1 is not released in the current cycle (that is, not released by the LRU algorithm), then the number of behavior times corresponding to the unreleased cache of this core is 1. Specifically, if in one cycle, a certain core initiates 10 cache replacement requests to the cache, and the data corresponding to its cache replacement requests is not released, and the access times of this core counted at the same time is 12, that is, 2 cache data are hit, but 10 need to be obtained from the memory, then its access times occupancy ratio is 10 / 12, approximately 0.83, which means that a large amount of the data obtained by this core does not exist in the cache. If it is allowed to continue to obtain, more cache space data will be replaced, which will seriously affect the efficiency of the cache in providing cache functions for other cores, that is, the cache data of other cores will be pushed out by a large number of cache replacement requests of this core, resulting in the programs executed by other cores being unable to obtain the corresponding data in time, and then initiating cache replacement again, leading to a vicious cycle and reducing the effectiveness of the cache.

[0058] Further, set the core with a relatively high access frequency occupancy as an abnormal core, and further prohibit this core from initiating new cache replacement requests. Additionally, since the statistics are performed periodically, for a core with a large demand for cache data, after the cache replacement requests initiated by it in the current cycle are rejected, to ensure its cache data requirements, the cache corresponding to the data it initiates for cache replacement will be satisfied in the next statistical cycle, or after the data in its cache is read and released by this core or replaced by the data of other cores and released, it is still allowed to initiate cache replacement in the current cycle. This can effectively prevent a certain core from crazily initiating cache replacement requests and affecting the cache usage efficiency of other cores. In some embodiments of the present invention, the method of statistically analyzing the behavior of each core with respect to the cache and setting corresponding states for each core based on the impact of the behavior on the cache further includes:

[0059] Statistically analyze the cache space occupied after each core initiates a cache replacement, and calculate the ratio of the cache space occupied by each core to the total cache space. In response to the ratio being higher than a second predetermined ratio, set the state of the corresponding core as abnormal.

[0060] In this embodiment, since the data sizes written to the cache when a core initiates a cache replacement may not be the same, it is necessary to determine the state of the core based on the data space size occupied by each core in the cache. Specifically, the shared cache controller statistically analyzes the size of the data saved in the cache by each core, and further calculates (dynamically calculates) the ratio of the data cached by each core in the cache to the total space. If the ratio of the data cached by a certain core in the cache to the total space size exceeds a preset value, then set the state of this core as abnormal.

[0061] Further, in some embodiments, the second ratio can evenly allocate the cache space according to the number of cores.

[0062] In some embodiments of the present invention, the second ratio used to determine the core state can be dynamically set according to the size of the cache occupied by each core within a certain period of time, that is, when the use of the cache by other cores (mainly based on the ratio of cache replacement requests initiated by the corresponding other cores within a certain period of time) is low, it indicates that the use of the cache by other cores is low, then the second ratio of the total cache occupied by each core can be dynamically increased.

[0063] In some embodiments of the present invention, the method further includes:

[0064] Statistically analyze the number of times each core accesses the cache and initiates a cache replacement. In response to the number of times each core accesses the cache and initiates a cache replacement being higher than a second predetermined number of times, set the state of the core with the largest number of cache replacement initiations as abnormal.

[0065] In this embodiment, the number of times each core accesses the cache and initiates cache replacement is periodically counted, and the number of cache replacement initiated is used as a judgment condition. When the number of cache replacement initiated by the corresponding core is higher than the second number, the state of the core with the largest number of cache replacement initiated is set to abnormal. That is, a single number of cache replacement initiated is used as the judgment condition for the core state.

[0066] In some embodiments of the present invention, determining a core with an abnormal state according to a preset management policy based on the state of the core, and restricting the operation of the core with the abnormal state accessing the cache includes:

[0067] In response to all the caches occupied by the core being released, the state of the core is set to normal.

[0068] In this embodiment, for a core whose status is set to abnormal, its status is set to normal only when the cache replacement request initiated by it and the corresponding data written into the cache successfully are all released.

[0069] In some embodiments of the present invention, when the resolution of cache anomalies is conditional on the complete release of caches corresponding to the core, the time range of determination may span a statistical cycle, or may be re-determined in each statistical cycle.

[0070] Aiming at the demand for shared cache in multi-core parallel computing in deep learning, the present invention adds automatic recognition of the access frequency and mode of a single core on the basis of the LRU replacement strategy, and uses this as a basis to separately limit the cache replacement initiated by different cores in the shared cache, thereby realizing dynamic allocation of the shared cache.

[0071] Another aspect of the present invention further provides a cache management system, comprising:

[0072] A calculation and analysis module 1, wherein the calculation and analysis module 1 is configured to count the behavior of each core on the cache and set a corresponding state for each core based on the impact of the behavior on the cache;

[0073] The core cache management module 2 is configured to determine the core with abnormal status according to a preset management policy based on the status of the core, and restrict the operation of the core with abnormal status accessing the cache.

[0074] Another aspect of the present invention further provides a computer device, comprising:

[0075] at least one processor 21; and

[0076] A memory 22 stores computer instructions 23 that can run on the processor 21. When the instructions 23 are executed by the processor 21, a cache management method is implemented, including:

[0077] Statistically analyze the behavior of each core with respect to the cache, and set a corresponding status for each core based on the impact of the behavior on the cache.

[0078] Based on the status of the core, determine the core with an abnormal status according to a preset management strategy, and restrict the operation of the core with the abnormal status to access the cache.

[0079] In some embodiments of the present invention, statistically analyzing the behavior of each core with respect to the cache, and setting a corresponding status for each core based on the impact of the behavior on the cache includes:

[0080] Periodically statistically analyze the number of cache accesses and the number of cache replacement initiations of each core.

[0081] In response to the number of accesses reaching a first predetermined number and the number of cache replacement initiations being equal to the number of accesses, set the status of the corresponding core as abnormal.

[0082] In some embodiments of the present invention, based on the status of the core, determine the core with an abnormal status according to a preset management strategy, and restrict the operation of the core with the abnormal status to access the cache includes:

[0083] In response to the status of the corresponding core being abnormal, restrict the cache replacement initiated by the core for a new cache.

[0084] In some embodiments of the present invention, statistically analyzing the behavior of each core with respect to the cache, and setting a corresponding status for each core based on the impact of the behavior on the cache further includes:

[0085] Statistically analyze the cache that has not been released after each core initiates a cache replacement, and calculate the access ratio of the unreleased cache and the number of accesses based on the number of accesses.

[0086] Determine whether the access ratio is higher than a first predetermined ratio. In response to the access ratio being higher than the first predetermined ratio, set the status of the corresponding core as abnormal.

[0087] In some embodiments of the present invention, statistically analyzing the behavior of each core with respect to the cache, and setting a corresponding status for each core based on the impact of the behavior on the cache further includes:

[0088] Statistically analyze the cache space occupied after each core initiates a cache replacement, and calculate the ratio of the cache space occupied by each core to the total cache space. In response to the ratio being higher than a second predetermined ratio, set the status of the corresponding core as abnormal.

[0089] In some embodiments of the present invention, the method further includes:

[0090] Count the number of times each core accesses the cache and initiates cache replacement, and in response to the number of times each core accesses the cache and initiates cache replacement being higher than a second predetermined number, set the status of the core with the maximum number of cache replacement initiations to abnormal.

[0091] In some embodiments of the present invention, judging the core with abnormal status based on the status of the core according to a preset management strategy, and restricting the operation of the core with abnormal status accessing the cache includes:

[0092] In response to all the caches occupied by the core being released, set the status of the core to normal.

[0093] Another aspect of the present invention is a computer-readable storage medium 401, the computer-readable storage medium 401 stores a computer program 402, and when the computer program is executed by a processor, a cache management method is implemented, including:

[0094] Count the behavior of each core on the cache, and set a corresponding status for each core based on the impact of the behavior on the cache;

[0095] Judge the core with abnormal status based on the status of the core according to a preset management strategy, and restrict the operation of the core with abnormal status accessing the cache.

[0096] In some embodiments of the present invention, counting the behavior of each core on the cache, and setting a corresponding status for each core based on the impact of the behavior on the cache includes:

[0097] Periodically count the number of cache accesses and the number of cache replacement initiations of each core;

[0098] In response to the number of accesses reaching a first predetermined number and the number of cache replacement initiations being equal to the number of accesses, set the status of the corresponding core to abnormal.

[0099] In some embodiments of the present invention, judging the core with abnormal status based on the status of the core according to a preset management strategy, and restricting the operation of the core with abnormal status accessing the cache includes:

[0100] In response to the status of the corresponding core being abnormal, restrict the cache replacement initiated by the core for a new cache.

[0101] In some embodiments of the present invention, counting the behavior of each core on the cache, and setting a corresponding status for each core based on the impact of the behavior on the cache further includes:

[0102] Count the caches that are not released after each core initiates cache replacement, and calculate the occupancy ratio of the unreleased caches and the access times based on the access times;

[0103] Determine whether the access times occupancy ratio is higher than a first predetermined ratio. In response to the access times occupancy ratio being higher than the first predetermined ratio, set the status of the corresponding core to abnormal.

[0104] In some embodiments of the present invention, counting the behaviors of each core on the cache and setting corresponding statuses for each core based on the impact of the behaviors on the cache further includes:

[0105] Count the cache space occupied after each core initiates cache replacement, and calculate the ratio of the cache space occupied by each core to the total cache space. In response to the ratio being higher than a second predetermined ratio, set the status of the corresponding core to abnormal.

[0106] In some embodiments of the present invention, the method further includes:

[0107] Count the number of times each core accesses the cache and initiates cache replacement. In response to the number of times each core accesses the cache and initiates cache replacement being higher than a second predetermined number of times, set the status of the core with the largest number of cache replacement initiations to abnormal.

[0108] In some embodiments of the present invention, based on the status of the core, judging the core with abnormal status according to a preset management strategy, and restricting the operation of the core with abnormal status accessing the cache includes:

[0109] In response to all the caches occupied by the core being released, set the status of the core to normal.

[0110] The above are exemplary embodiments disclosed by the present invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present invention defined by the claims. The functions, steps, and / or actions of the method claims according to the disclosed embodiments herein do not need to be executed in any specific order. In addition, although the elements disclosed by the embodiments of the present invention can be described or claimed in an individual form, they can also be understood as multiple unless explicitly limited to the singular.

[0111] It should be understood that, as used herein, unless the context clearly supports an exception, the singular form "a" is also intended to include the plural form. It should also be understood that "and / or" as used herein refers to any and all possible combinations including one or more of the associated listed items.

[0112] The steps of the methods or algorithms described in connection with the disclosure herein may be directly included in hardware, in software modules executed by a processor, or in a combination of both. The software modules may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, or write information to, the storage medium. In an alternative, the storage medium may be integrated with the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative, the processor and the storage medium may reside in the user terminal as discrete components.

[0113] The serial numbers of the above disclosed embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0114] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above embodiments can be completed by hardware or by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disk, or the like.

[0115] Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is exemplary only and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other variations in different aspects of the embodiments of the present invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention shall be included in the protection scope of the embodiments of the present invention.

Claims

1. A cache management method, characterized in that, Including: Statistically analyze the behavior of each core with respect to the cache, and set a corresponding status for each core based on the impact of the behavior on the cache; wherein, statistically analyzing the behavior of each core with respect to the cache and setting a corresponding status for each core based on the impact of the behavior on the cache includes: statistically analyzing the number of behavior times corresponding to the cache that has not been released after each core initiates cache replacement, and calculating the access times occupancy ratio of the number of behavior times and access times corresponding to the unreleased cache based on the access times; determining whether the access times occupancy ratio is higher than a first predetermined ratio, and in response to the access times occupancy ratio being higher than the first predetermined ratio, setting the status of the corresponding core as abnormal; Based on the status of the core, determine the core with abnormal status according to a preset management policy, and restrict the operation of the core with abnormal status accessing the cache.

2. The method according to claim 1, characterized in that, The statistically analyzing the behavior of each core with respect to the cache and setting a corresponding status for each core based on the impact of the behavior on the cache includes: Periodically statistically analyze the number of cache access times and the number of cache replacement initiations of each core; In response to the number of cache access times reaching a first predetermined number and the number of cache replacement initiations being equal to the number of cache access times, set the status of the corresponding core as abnormal.

3. The method according to claim 1, characterized in that, The based on the status of the core, determine the core with abnormal status according to a preset management policy, and restrict the operation of the core with abnormal status accessing the cache includes: In response to the status of the corresponding core being abnormal, restrict the cache replacement initiated by the core for new cache.

4. The method according to claim 1, characterized in that, The statistically analyzing the behavior of each core with respect to the cache and setting a corresponding status for each core based on the impact of the behavior on the cache further includes: Statistically analyze the cache space occupied after each core initiates cache replacement, and calculate the ratio of the cache space occupied by each core to the total cache space. In response to the ratio being higher than a second predetermined ratio, set the status of the corresponding core as abnormal.

5. The method according to claim 1, wherein Also including: Statistically analyze the number of times each core accesses the cache and initiates cache replacement. In response to the number of times each core accesses the cache and initiates cache replacement being higher than a second predetermined number, set the status of the core with the largest number of cache replacement initiations as abnormal.

6. The method according to claim 1, characterized in that, The based on the status of the core, determine the core with abnormal status according to a preset management policy, and restrict the operation of the core with abnormal status accessing the cache includes: In response to all the cache occupied by the core being released, set the status of the core as normal.

7. A cache management system, characterized in that, Including: A calculation and analysis module, the calculation and analysis module is configured to statistically analyze the behavior of each core with respect to the cache, and set a corresponding status for each core based on the impact of the behavior on the cache; wherein, statistically analyzing the behavior of each core with respect to the cache and setting a corresponding status for each core based on the impact of the behavior on the cache includes: statistically analyzing the number of behavior times corresponding to the cache that has not been released after each core initiates cache replacement, and calculating the access times occupancy ratio of the number of behavior times and access times corresponding to the unreleased cache based on the access times; determining whether the access times occupancy ratio is higher than a first predetermined ratio, and in response to the access times occupancy ratio being higher than the first predetermined ratio, setting the status of the corresponding core as abnormal; A core cache management module, which is configured to determine a core with an abnormal state based on the state of the core according to a preset management policy, and restrict the operation of accessing the cache by the core with the abnormal state.

8. A computer device, characterized in that, Comprising: At least one processor; And A memory storing computer instructions executable on the processor, and when the instructions are executed by the processor, the steps of the method according to any one of claims 1-6 are implemented.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, the steps of the method according to any one of claims 1-6 are implemented.

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