Exception testing method and system based on virtual instruction set platform and storage medium

Abstract

The application discloses a kind of based on virtual instruction set platform's exception test method, system and storage medium, wherein method includes: S1: according to the hardware information to be measured, builds virtual target system on virtual instruction set platform;S2: according to selected VCPU and test plan, select exception test component from exception test component library, and generate dynamic link library file according to selected exception test component;S3: load bin file of control software on virtual target system, start virtual target system and enter normal operation mode, confirm that each monitoring variable meets expected value;S4: engine simulation model host computer triggers exception test component dynamically by dynamic link library file, executes automation test, and stores the output result of component.The above-mentioned exception test method is tested by setting up virtual target system on virtual instruction set platform, not limited to hardware resource, test is convenient and simultaneously avoids the test failure caused by test environment influence.

Description

Technical Field

[0001] This invention pertains to software testing technology in the field of safety-critical areas, and specifically relates to an anomaly testing method, system, and storage medium based on a virtual instruction set platform. Background Technology

[0002] FADEC control software is a crucial technology in safety-critical fields. When an anomaly occurs in the control software, the CPU chip must be able to respond promptly and execute exception handling to prevent code crashes or the execution of erroneous instructions. Therefore, anomaly testing is an essential part of control software testing. Traditional testing methods rely on hardware controller instrumentation and serial port printing of test results. This method is limited by the serial port protocol, cannot accurately display changes in registers and memory, and can only show partial variable test results. It is difficult to capture and analyze CPU anomalies from a microscopic perspective, significantly reducing reliability and accuracy. Furthermore, hardware testing requires coordination with the controller, test bench, and adapter boxes, making unified coordination difficult. When manually instrumenting tests on the hardware controller, the testing methods for each test case are different, and the reset and flashing process needs to be repeated, resulting in low efficiency and a high risk of errors. Summary of the Invention

[0003] Purpose of the invention: The purpose of this invention is to propose an anomaly testing method based on a virtual instruction set platform, which has high testing efficiency and is not limited by hardware resources, thereby improving the testing efficiency of testers.

[0004] Another objective of this invention is to provide a testing system capable of implementing the above-described anomaly testing method and a storage medium storing a computer program instantiated with the above-described anomaly testing method.

[0005] Technical solution: The anomaly testing method based on a virtual instruction set platform described in this invention includes the following steps:

[0006] S1: Based on the hardware information under test, build a virtual target system on the virtual instruction set platform;

[0007] S2: Based on the selected VCPU and test plan, select an exception test component from the exception test component library, and generate a dynamic link library file based on the selected exception test component;

[0008] S3: Load the control software's bin file onto the virtual target system, start the virtual target system into normal operating mode, and confirm that each monitored variable meets the expected value;

[0009] S4: The host computer of the engine simulation model dynamically triggers abnormal test components through dynamic link library files, executes automated tests, and stores the output results of the components.

[0010] Furthermore, the abnormal test component in step S2 is generated from the abnormal component model, which includes the following items:

[0011] Input interface, used to configure the input parameters of the component;

[0012] Access address, used to configure the address space in which the component runs;

[0013] Permission configuration is used to configure the access permissions of components;

[0014] Command operations are used to set the specific actions of components;

[0015] Output interface, used to configure the output parameters of the component.

[0016] Furthermore, the dynamic link library files in step S2 follow the following principles: all abnormal test components must be triggered when no other high-priority interrupts are triggered, and an interrupt handling process is performed after triggering.

[0017] Furthermore, in step S3, each triggered exception test component is executed starting at the header address of the virtual target system.

[0018] The anomaly testing system based on a virtual instruction set platform according to the present invention includes a virtual target system, an anomaly test component library, an anomaly test case generation module, and an engine simulation model host computer. The virtual target system is built on the virtual instruction set platform according to the hardware under test information. The anomaly test case generation module is used to generate dynamic link library files based on anomaly test components selected from the anomaly test component library. The engine simulation model host computer dynamically triggers the anomaly test components on the virtual target system according to the dynamic link library files.

[0019] The storage medium of the present invention stores a computer program, which is designed to implement the above-described anomaly testing method based on a virtual instruction set platform when run.

[0020] Beneficial effects: Compared with existing technologies, this invention has the following advantages: By building a virtual target system on a virtual instruction set platform for testing, it is not limited by hardware resources, making testing convenient and avoiding test errors caused by the test environment. By constructing abnormal test components and dynamically triggering them through the host computer of the engine simulation model, testing efficiency is improved, and abnormal test components are easy to migrate, making the testing process uniform and less prone to errors. Attached Figure Description

[0021] Figure 1 This is a structural diagram of the virtual target system according to an embodiment of the present invention;

[0022] Figure 2This is an interface diagram of the abnormal test case generation module in an embodiment of the present invention;

[0023] Figure 3 This is a diagram of the abnormal test case running interface in an embodiment of the present invention. Detailed Implementation

[0024] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0025] An anomaly testing method based on a virtual instruction set platform according to an embodiment of the present invention includes the following steps:

[0026] S1: Based on the hardware information under test, build a virtual target system on the virtual instruction set platform;

[0027] S2: Based on the selected VCPU and test plan, select an exception test component from the exception test component library, and generate a dynamic link library file based on the selected exception test component;

[0028] S3: Load the control software's bin file onto the virtual target system, start the virtual target system into normal operating mode, and confirm that each monitored variable meets the expected value;

[0029] S4: The host computer of the engine simulation model dynamically triggers abnormal test components through dynamic link library files, executes automated tests, and stores the output results of the components.

[0030] The aforementioned testing method utilizes control software running on a virtual target system based on the hardware under test. A fully digital engine simulation model is used as the host computer to dynamically trigger pre-established anomaly test components. This automates the testing process, improving efficiency. It is not limited by serial port protocols, accurately displays register and memory changes, and enhances test reliability and accuracy, avoiding test errors caused by environmental factors. Furthermore, the testing process is not limited by hardware resources, and the established anomaly test components are easily portable and reusable, ensuring a consistent testing process and reducing the likelihood of errors.

[0031] Reference Figure 1 The components of the virtual target system are shown in the figure. The virtual target system is constructed by selecting the instruction set on the virtual instruction set platform based on the CPU, FPGA, and storage peripheral information of the hardware under test, and configuring the resources of the virtual CPU and storage peripherals. In this embodiment, the virtual instruction set platform is developed based on the QEMU virtual machine and supports instruction sets for three types of chips: MPC5554, MPC5674, and P2020. It can also add peripheral module functionality according to testing requirements.

[0032] The exception testing components in the exception testing component library have a unified component template, which includes the following information:

[0033] Input interface, used to configure the input parameters of the component;

[0034] Access address, used to configure the address space in which the component runs;

[0035] Permission configuration is used to configure the access permissions of components;

[0036] Command operations are used to set the specific actions of components;

[0037] Output interface, used to configure the output parameters of the component.

[0038] Based on the above template, different types of anomaly test components can be obtained by configuring them according to actual testing requirements. Common anomalies in FADEC control software include check anomalies, data read / write access anomalies, instruction access anomalies, watchdog anomalies, data TLB error anomalies, data misalignment access anomalies, floating-point division by zero anomalies, data cache miss anomalies, instruction cache miss anomalies, subtractor interrupt anomalies, and fixed timer interrupt anomalies. The basic settings for the anomaly test components for the above anomalies are as follows:

[0039] 1) Machine check error: [Access Address] is configured as unavailable address space, [Permission Configuration] is configured as accessible, [Command Operation] is configured as jump command, and the rest are configured as default.

[0040] 2) Data read / write access error: [Access address] is configured to virtual memory address space, [Permission configuration] is configured to unreadable permission, [Command operation] is configured to data read command, and the rest are configured to default.

[0041] 3) Instruction access exception: [Access address] is configured to virtual memory address space, [Permission configuration] is configured to prohibit execution permission, [Instruction operation] is configured to jump instruction, and the rest are configured as default.

[0042] 4) Watchdog exception: [Instruction Operation] Configure the watchdog register enable instruction and set the watchdog timer length; the rest are default configurations.

[0043] 5) Data TLB error exception: [Access Address] is configured to virtual FLASH address space, [Permission Configuration] is configured to disable TLB permissions, [Command Operation] is configured to data read command, and the rest are configured to default.

[0044] 6) Instruction TLB error exception: [Access address] is configured to virtual FLASH address space, [Permission configuration] is configured to disable TLB permissions, [Instruction operation] is configured to jump instruction, and the rest are configured as default.

[0045] 7) Data unaligned access exception: [Access address] is configured to virtual memory address space (not 4-byte aligned), [Permission configuration] is configured to be accessible, [Instruction operation] is configured to data read instruction, and the rest are configured to default.

[0046] 8) Floating-point division by zero exception: [Access address] is configured to a certain virtual memory address space, [Permission configuration] is configured to be accessible, [Instruction operation] is configured to the instruction corresponding to the division by zero code, and the rest are default configurations;

[0047] 9) Data cache miss exception: [Access address] is configured to the data address space not configured by the MMU, [Permission configuration] is configured to be accessible, [Command operation] is configured to be a data write command, and the rest are configured to default.

[0048] 10) Instruction cache miss exception: [Access address] is configured to the instruction address space not configured by the MMU, [Permission configuration] is configured to be accessible, [Instruction operation] is configured to jump instruction, and the rest are configured as default.

[0049] 11) Subtractor Interrupt: [Instruction Operation] is configured as the subtractor timer interrupt enable instruction, the rest are default settings;

[0050] 12) Fixed timer interrupt: [Instruction operation] is configured as a fixed timer interrupt enable instruction, the rest are default settings.

[0051] In step S2, the dynamic triggering of abnormal test components must follow these rules: 1. All abnormal test components can only be triggered when there are no other high-priority interrupts, and after triggering, the abnormal test component is processed according to the interrupt handling procedure. 2. Each triggered abnormal test component starts execution at the header address of the virtual target system. The engine simulation model's host computer triggers the abnormal test component's runtime interface based on the DLL file generated by the selected abnormal test component, as shown in the example. Figure 3 As shown. Rule 1 effectively avoids multiple nested interrupt triggers, facilitating terminal type identification and location, thus simplifying anomaly localization. Rule 2, because the code executes from the starting address after a CPU reset, unifies virtual and real testing, improving test accuracy.

[0052] An anomaly testing system based on a virtual instruction set platform according to an embodiment of the present invention includes a virtual target system built on the virtual instruction set platform according to the hardware configuration information under test, an anomaly test component library containing multiple anomaly test components generated according to a unified template, an anomaly test case generation module that generates DLL files based on selected anomaly test components, and an engine simulation model host computer for simulating an engine. The interface of the anomaly test case generation module is shown below. Figure 2As shown, the left window displays abnormal test components from the abnormal test component library. Exception test components in the left window can be selected and added to the right window of the selected component using the "Add" virtual button. Alternatively, components in the right window can be selected and deleted using the "Delete" virtual button. After selecting the required abnormal test components, clicking the "Generate Code" virtual button will generate a DLL file for triggering the engine simulation model's host computer, based on the selected abnormal test components and the aforementioned dynamic triggering rules. The storage medium according to this embodiment stores a computer program instantiated from the above-described abnormal test method.

Claims

1. A method of testing exceptions based on a virtual instruction set platform, characterized by, The method comprises the following steps: S1: according to the hardware information to be tested, a virtual target system is built on a virtual instruction set platform; S2: according to the selected VCPU and test plan, an abnormal test component is selected from an abnormal test component library, and a dynamic link library file is generated according to the selected abnormal test component; the dynamic link library file follows the following principles: all abnormal test components need to be triggered when no other high-priority interrupt is triggered, and the interrupt processing process is performed after the triggering; The abnormal test component is generated by an abnormal component model, and the abnormal component model comprises the following items: an input interface for configuring the input parameters of the component; an access address for configuring the address space for running the component; permission configuration for configuring the access permission of the component; instruction operation for setting the specific action of the component; an output interface for configuring the output parameters of the component; S3: the bin file of the control software is loaded on the virtual target system, the virtual target system is started to enter a normal operation mode, and it is confirmed that each monitoring variable meets the expected value; S4: the engine simulation model host computer dynamically triggers the abnormal test component through the dynamic link library file, performs automatic testing, and stores the output result of the component; each triggered abnormal test component is executed from the head address of the virtual target system.

2. A virtual instruction set platform based exception test system using the virtual instruction set platform based exception test method according to claim 1, characterized by, The system comprises a virtual target system, an abnormal test component library, an abnormal test case generation module and an engine simulation model host computer, the virtual target system is built on a virtual instruction set platform according to the hardware information to be tested, the abnormal test case generation module is used for generating a dynamic link library file according to the selected abnormal test component from the abnormal test component library, and the engine simulation model host computer dynamically triggers the abnormal test component on the virtual target system according to the dynamic link library file.

3. A storage medium storing a computer program, characterized by The computer program is designed to realize the abnormal test method based on the virtual instruction set platform according to claim 1 when running.

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