MPU-based memory access methods, devices, electronic devices, and storage media

Abstract

This invention provides a memory access method, apparatus, electronic device, and storage medium based on an MPU. The memory access method includes: establishing a flexible page table based on the memory segment actually needed by a thread, wherein the flexible page table includes several flexible pages, each flexible page corresponding to a memory block in a memory pool group, and the memory segment needed by the thread consists of one or more memory blocks; retrieving one or more flexible pages corresponding to the memory segment actually needed by the thread from the flexible page table and placing them into the thread's address space; establishing a linked list of flexible pages used by the thread; and the thread accessing the memory segment by retrieving one or more flexible pages from its address space and mapping the corresponding memory segment in the memory pool using the linked list. This invention, by using flexible pages to allocate matching memory space to threads, can minimize the triggering of memory management errors, thereby improving the security and reliability of embedded system software.

Description

Technical Field

[0001] This invention relates to the field of embedded operating system technology, and in particular to a memory access method, apparatus, electronic device, and storage medium based on an MPU. Background Technology

[0002] Current operating systems primarily employ two memory management mechanisms: virtual memory management and non-virtual memory management. Some embedded processors have an MMU (Memory Management Unit), which the operating system uses to translate virtual addresses into physical addresses. Applications only need to use virtual addresses for data addressing. This method of addressing using virtual addresses is called virtual memory. Virtual memory management allows the system to meet program speed requirements while saving physical memory space.

[0003] However, virtual memory mechanisms can lead to unpredictable I / O blocking times, making program execution unpredictable. Furthermore, due to cost and design complexity considerations for embedded processors, many lack a memory management unit (MMU). Therefore, most embedded real-time operating systems employ non-virtual memory management strategies, where memory access is direct, and all addresses accessed in the program are actual physical addresses. Most embedded real-time operating systems do not protect memory space; all processes effectively share a single runtime environment. This can improve system response time, but program memory access violations or improper operations can easily cause system crashes.

[0004] In embedded multi-process systems, it is crucial to ensure that operations between different processes do not interfere with each other. Mechanisms that prevent unauthorized access to system resources or other process resources are called protection strategies. There are two methods for controlling access to system resources: hardware-supported protection and software protection. Hardware-supported protection refers to the processor itself being designed with a corresponding functional unit (MPU, memory protection unit), with software drivers jointly performing system resource protection. Software protection relies solely on software to protect system resources. In systems without an MPU, there is no dedicated hardware to protect peripheral devices and memory. To avoid interference between different processes, a software coordination mechanism must be used. If a process fails to comply with access restrictions, memory access violations can easily occur, causing the coordination mechanism to fail. In systems with an MPU, there is a dedicated hardware MPU that checks and restricts access to system resources, ensuring resource ownership. Processes must adhere to a set of rules defined by the operating system, which are implemented and maintained by hardware. Special permissions for monitoring and controlling resources are granted through the hardware registry. A protected system can effectively prevent one process from using the resources of other processes. Hardware-supported protection is more reliable and effective than purely software protection.

[0005] The size of the MPU field supported by ARM Cortex-M7 must be a power of 2. If a thread needs to request a 192-byte field, it can theoretically request a 256-byte MPU field directly. However, the thread cannot use a 256-byte MPU field, so the thread occupies too much space. Furthermore, the maximum number of MPU fields supported by the ARM Cortex-M7 processor is 8 or 16. When multiple threads access it, it is easy to cause a MemManage Fault. Summary of the Invention

[0006] This invention provides a memory access method, apparatus, electronic device, and storage medium based on an MPU, which achieves isolation between different processes through the MPU.

[0007] In a first aspect, embodiments of the present invention provide a memory access method based on an MPU, wherein multiple MPU domains correspond one-to-one with multiple memory pools, and the memory access method includes:

[0008] A flexible page table is established based on the memory segment that the thread actually needs to access. The flexible page table includes several flexible pages, each of which corresponds to a memory block in the memory pool group. The memory segment that the thread needs to access consists of one or more memory blocks.

[0009] Based on the memory segment that the thread actually needs to access, one or more corresponding flexible pages are obtained from the flexible page table and placed into the address space of the thread;

[0010] A flexible page list is established for the thread to establish the mapping relationship between the thread's address space and memory pool;

[0011] The thread accesses the memory segment by obtaining one or more flexible pages in the address space and then using the flexible page linked list mapping to obtain the corresponding memory segment in the memory pool.

[0012] Optionally, the step of establishing a flexible page table based on the memory segment actually needed by the thread includes:

[0013] Allocate a corresponding MPU field for each thread and set the corresponding attributes;

[0014] For each memory pool corresponding to each MPU domain, determine the memory segment that each thread needs to access;

[0015] The memory segment that each thread needs to access is mapped into several flexible pages, each flexible page corresponds to a memory block, and multiple memory blocks just make up a memory segment;

[0016] Create flexible page tables to map each memory block in the memory pool group.

[0017] Optionally, the flexible page includes the base address of the corresponding memory block and the length of the corresponding memory block. The step of retrieving one or more flexible pages from the flexible page table and placing them into the thread's address space based on the memory segment actually needed by the thread includes:

[0018] The address range corresponding to the memory segment is calculated by using the base address and length of the memory segment actually accessed by a certain thread;

[0019] Traverse the base address and length of each flexible page in the flexible page table, and store the base address and length of the flexible pages located within the address range in the address space of the thread.

[0020] Optionally, the memory access method further includes:

[0021] After a thread finishes its work, the flexible pages in the address space are cleared, so that new threads can use the memory blocks used by the thread.

[0022] Optionally, if a high-priority thread is switched to work while a low-priority thread is accessing the memory pool, the memory access method further includes:

[0023] Prevent low-priority threads from continuing to access memory segment A, and save the information of the low-priority threads accessing the corresponding memory segment A in the memory pool through flexible paging;

[0024] High-priority threads access memory segment B in the memory pool by acquiring flexible pages in the address space and using a flexible page linked list mapping.

[0025] If memory segment A and memory segment B are in the same memory pool, then accessing memory segment B by a high-priority thread will not affect subsequent access to memory segment A by a low-priority thread.

[0026] Optionally, the memory access method further includes:

[0027] Based on the multiple memory pools corresponding to all MPU domains of the thread, obtain all flexible pages corresponding to the multiple memory pools from the flexible page table, and establish a total flexible page linked list to map the memory pools corresponding to all domains;

[0028] Based on the memory pool corresponding to the MPU domain used by the thread, all flexible pages corresponding to the memory pool are retrieved from the flexible page table, and a domain flexible page linked list is established to map the memory pool.

[0029] Optionally, if the processor generates a MemManageFault due to the memory segment B accessed by the thread exceeding the MPU domain of the thread, the memory access method further includes:

[0030] If the address of memory segment B exists in the total flexible page list of the thread, then the corresponding flexible page is found and the flexible page is updated in the domain flexible page list corresponding to the thread to clear the fault.

[0031] Secondly, embodiments of the present invention provide an MPU-based memory access device, the memory access device comprising:

[0032] The flexible page creation module establishes a flexible page table based on the memory segment that the thread actually needs to access. The flexible page table includes several flexible pages, each of which corresponds to a memory block in the memory pool group. The memory segment that the thread needs to access consists of one or more memory blocks.

[0033] The flexible page allocation module retrieves one or more flexible pages from the flexible page table and places them into the address space of the thread based on the memory segment that the thread actually needs to access; it also establishes a linked list of flexible pages used by the thread to establish the mapping relationship between the thread's address space and the memory pool.

[0034] The thread access module allows the thread to access the memory segment by obtaining one or more flexible pages in the address space and then using the flexible page linked list mapping to obtain the corresponding memory segment in the memory pool.

[0035] Thirdly, embodiments of the present invention provide an electronic device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to implement the method as described in any of the first aspects.

[0036] Fourthly, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method as described in any of the first aspects.

[0037] Beneficial effects

[0038] This invention provides a memory access method, apparatus, electronic device, and storage medium based on an MPU. The memory access method is implemented based on an MPU, and the memory includes multiple memory pools. In this invention, the multiple memory pools are described as memory pool groups. Access to relevant memory pools by threads is managed through a one-to-one correspondence between multiple MPU domains and multiple memory pools, and by setting the attributes and permissions of each thread's MPU domain. This ensures that multiple threads do not interfere with each other when accessing memory pools, thereby protecting the memory. Based on the MPU, this invention establishes a flexible page table according to the memory segments actually accessed by the threads. The flexible page table includes several flexible pages, each corresponding to a memory block in the memory pool group. The memory segment accessed by a thread consists of one or more memory blocks. In other words, a flexible page table is established to map flexible pages to memory blocks in the memory pool. A thread retrieves one or more flexible pages from the flexible page table and places them into its address space based on the memory segment it actually needs to access. A linked list of flexible pages used by the thread is established to map the thread's address space to the memory pool. All flexible pages in the linked list correspond to the memory blocks the thread actually needs to access in the memory pool. All memory blocks mapped by the linked list together form the memory segment the thread actually needs to access. When a thread needs to access a memory segment in the memory pool, it only needs to find the corresponding flexible page in its address space and map it to the corresponding memory block using the linked list. All flexible pages in the linked list map to the memory segment the thread needs to access, thus ensuring that only that memory segment is authorized to the thread, while memory segments in the memory pool that the thread does not actually need are not authorized. This invention, by using flexible pages to grant threads matching memory space, can minimize the triggering of memory management errors, thereby improving the security and reliability of embedded system software.

[0039] It should be understood that the description in the Summary of the Invention is not intended to limit the key or essential features of the embodiments of the present invention, nor is it intended to restrict the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0040] The above and other features, advantages, and aspects of the various embodiments of the present invention will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements.

[0041] Figure 1 A flowchart illustrating an MPU-based memory access method according to an embodiment of the present invention is shown;

[0042] Figure 2 A flowchart illustrating the clearing of the MemMangeFault fault according to an embodiment of the present invention is shown;

[0043] Figure 3 A schematic diagram of the structure of an MPU-based memory access device according to an embodiment of the present invention is shown;

[0044] Figure 4 A structural diagram of an electronic device according to an embodiment of the present invention is shown. Detailed Implementation

[0045] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this document.

[0046] It should be noted that the embodiments of the present invention are described only to more clearly illustrate the technical solutions of the embodiments of the present invention, and do not constitute a limitation on the technical solutions provided by the embodiments of the present invention.

[0047] This embodiment Figure 1 A flowchart illustrating an MPU-based memory access method according to an embodiment of the present invention is shown; see also Figure 1 The memory access method includes:

[0048] S1. A flexible page table is established based on the memory segment that the thread actually needs to access. The flexible page table includes several flexible pages, each of which corresponds to a memory block in the memory pool group. The memory segment that the thread needs to access consists of one or more memory blocks. That is, the flexible page table is calculated based on the existing threads to establish a correspondence between the flexible pages and each memory block in the memory pool group. Regardless of which thread it is, it can find the corresponding memory block by finding the corresponding flexible page. For any given thread, one or more memory segments exactly constitute the memory segment that the thread actually needs to access.

[0049] S2. Based on the memory segment that the thread actually needs to access, retrieve one or more corresponding flexible pages from the flexible page table and place them in the address space of the thread; wherein, the memory segment that a certain thread actually needs to access is set when the thread is created, and based on setting the memory address of a known memory segment, retrieve all flexible pages corresponding to the memory segment from the flexible page table and place them in the address space; the thread can be bound to the flexible pages of the memory segment it actually needs to access;

[0050] S3. Establish a flexible page linked list for the thread to establish the mapping relationship between the thread's address space and the memory pool; the flexible page linked list can be used to establish the mapping relationship between the flexible pages placed in the thread's address space and the memory blocks in the memory pool; so that the thread can directly find the corresponding memory block by finding the flexible page in its own address space;

[0051] S4. The thread accesses the memory segment by acquiring one or more flexible pages in the address space and obtaining the corresponding memory segment in the memory pool through the flexible page linked list mapping. For example, if the memory segment the thread actually needs to access is 192 bytes, and the memory pool where this memory segment is located is managed by the MPU domain, then the size of the memory pool can only be a power of 2 bytes corresponding to the MPU domain. If the size of the memory pool is 256 bytes, in this embodiment, to ensure reasonable allocation and utilization of memory, the thread acquires the corresponding flexible page in the address space. If two corresponding flexible pages are found in the address space, and the sizes of the memory blocks corresponding to the two flexible pages are 128 bytes and 64 bytes respectively, these two memory blocks exactly form a 192-byte memory segment. That is, only 192 bytes of memory space are actually allocated to the thread, rather than the entire memory pool size corresponding to the domain, which greatly reduces the system's operating load and can minimize the triggering of memory management errors.

[0052] This embodiment provides a memory access method based on an MPU. The memory access method is implemented using an MPU, and the memory includes multiple memory pools. In this embodiment, the multiple memory pools are described as memory pool groups. Access to relevant memory pools by threads is managed through a one-to-one correspondence between multiple MPU domains and multiple memory pools, and by setting the attributes and permissions of each thread's MPU domain. This ensures that multiple threads do not interfere with each other when accessing memory pools, thereby protecting memory. Based on the MPU, this invention establishes a flexible page table according to the memory segments actually accessed by the threads. The flexible page table includes several flexible pages, each corresponding to a memory block in the memory pool group. The memory segment accessed by a thread consists of one or more memory blocks. In other words, a flexible page table is established to map flexible pages to memory blocks in the memory pool. A thread retrieves one or more flexible pages from the flexible page table and places them into its address space based on the memory segment it actually needs to access. A linked list of flexible pages used by the thread is established to map the thread's address space to the memory pool. All flexible pages in the linked list correspond to the memory blocks the thread actually needs to access in the memory pool. All memory blocks mapped by the linked list together form the memory segment the thread actually needs to access. When a thread needs to access a memory segment in the memory pool, it only needs to find the corresponding flexible page in its address space and map it to the corresponding memory block according to the linked list. All flexible pages in the linked list map to the memory segment the thread needs to access, thus ensuring that only that memory segment is authorized to the thread, while memory segments in the memory pool that the thread does not actually need are not authorized. This embodiment, by using flexible pages to grant threads matching memory space, can minimize the triggering of memory management errors, thereby improving the security and reliability of the embedded system software.

[0053] Specifically, the step of establishing a flexible page table based on the memory segments actually needed by the thread includes:

[0054] S11. Allocate a corresponding MPU field for each thread and set the corresponding attributes;

[0055] The maximum number of MPU domains supported by the operating system depends on the processor's processing power. The ARM Cortex-M7 processor's MPU divides memory mapping into 8 or 16 domains, each corresponding to a memory pool. The location and size of each domain are defined, and access permissions and memory attributes are defined for the corresponding domain when a thread binds to an MPU domain. Instruction and data access share the same region settings. During operating system context switching, the access permissions and memory attributes corresponding to the current thread's MPU domains are reset. Each thread accesses the memory segment mapped to its own MPU domain.

[0056] S12. For each memory pool corresponding to an MPU domain, determine the memory segment that each thread needs to access; the memory segment that the thread needs to access is directly specified, but for systems managed by MPUs, the thread will generally directly access the entire memory pool mapped by the corresponding MPU.

[0057] S13. The memory segment that each thread needs to access is mapped into several flexible pages, each flexible page corresponds to a memory block, and multiple memory blocks form a memory segment; so that the thread can directly access the specific memory segment it needs through flexible page mapping, instead of the entire memory pool;

[0058] S14. Establish a flexible page table to map each memory block in the memory pool group, thereby implementing the mapping relationship between flexible pages and the memory pool. At this point, the flexible page table corresponds to all memory blocks in the memory pool group, making it convenient for subsequent threads to directly obtain the flexible pages they need from the flexible page table to access the corresponding memory segments.

[0059] Specifically, the flexible page includes the base address of the corresponding memory block and the length of the corresponding memory block. The step of retrieving one or more flexible pages from the flexible page table and placing them into the thread's address space based on the memory segment actually needed by the thread includes:

[0060] S21. Calculate the address range corresponding to the memory segment by using the base address and length of the memory segment actually accessed by a certain thread; specifically, the base address is the starting address of the memory segment, and the base address + length = the ending address of the memory segment. The address range is represented by [starting address, ending address), which includes the starting address but does not include the ending address to avoid access errors.

[0061] S22. Traverse the base address and length of each flexible page in the flexible page table, and store the base address and length of the flexible pages located within the address range in the thread's address space. During access, the base address recorded in the flexible page can be directly used to determine whether the base address of the flexible page is within the address range. Since the memory blocks corresponding to one or more flexible pages form a memory segment, the terminating address of a flexible page whose base address is in the address space must also be within that address range.

[0062] Specifically, the memory access method further includes:

[0063] After a thread finishes its work, the flexible pages in the address space are cleared, allowing new threads to use the memory blocks previously used by the original thread. This is only required if the new thread also has a memory pool corresponding to the same MPU domain as the original thread.

[0064] In addition, threads have different priorities, specifically implemented through bound MPU fields. Each thread has its own MPU configuration, which achieves the following: ensuring that a thread can only access its own allocated stack space, preventing stack leaks from corrupting other stacks; ensuring that a thread can only access limited peripherals; and ensuring that a thread can only access its own data or its own program data. From the perspective of thread execution, two threads cannot work simultaneously, but due to priority, a higher-priority thread will interrupt the work of a lower-priority thread, and the higher-priority thread will have priority in performing its work.

[0065] Specifically, if a high-priority thread is switched to work while a low-priority thread is accessing the memory pool, the memory access method further includes:

[0066] Suspend low-priority threads from accessing memory segment A and save the information of the low-priority threads accessing the corresponding memory segment A in the memory pool through flexible pages; specifically, this is achieved through a special exception PendSV in ARM Cortex-M7. To trigger PendSV, simply set the PENDSVSET bit in the Interrupt Control Status Register (ICSR) to 1 to switch the PendSV state to the pending state.

[0067] High-priority threads access memory segment B in the memory pool by acquiring flexible pages in the address space and using a flexible page linked list mapping.

[0068] If memory segment A and memory segment B are in the same memory pool, then accessing memory segment B by a high-priority thread will not affect subsequent access to memory segment A by a low-priority thread.

[0069] Specifically, the memory access method further includes:

[0070] Based on the multiple memory pools corresponding to all MPU domains of the thread, obtain all flexible pages corresponding to the multiple memory pools from the flexible page table, and establish a total flexible page linked list to map the memory pools corresponding to all domains;

[0071] Based on the memory pool corresponding to the MPU domain used by the thread, all flexible pages corresponding to the memory pool are retrieved from the flexible page table, and a domain flexible page linked list is established to map the memory pool.

[0072] Specifically, if the processor generates a MemManageFault due to the memory segment B accessed by the thread exceeding the MPU domain of the thread, the memory access method further includes:

[0073] If the address of memory segment B exists in the total flexible page list of the thread, then the corresponding flexible page is found and the flexible page is updated in the domain flexible page list corresponding to the thread to clear the fault.

[0074] Specifically, this is achieved through memory management exception handling functions. Figure 2 A flowchart illustrating the clearing of the MemMangeFault according to an embodiment of the present invention is shown; as follows: Figure 2 As shown, in the memory management exception handling function, the cause of the error is determined based on the corresponding flag in the Memory Management Fault Status Register (MMFSR), and appropriate processing is performed. If MMARVALID in the Memory Management Fault Status Register is 1, then the fault address stored in the Memory Management Fault Address Register (MMFAR) is valid. During MemMangeFault handling, it first checks if the fault address validity bit in the Memory Management Fault Status Register is 1. If it is, it checks if the fault address exists in the current thread's total flexible page list, finds the corresponding flexible page, and updates the flexible page to the thread's corresponding domain flexible page list. If the fault address validity bit in the Memory Management Fault Status Register is not 1, it checks if the stack error validity bit in the Memory Management Fault Status Register is 1. If it is, it manually checks if the program access error address exists in the current thread's total flexible page list. In the table, the corresponding flexible page is searched and updated to the flexible page linked list of the domain corresponding to the thread. If the valid bit of the stack error in the memory fault status register is not 1, it is determined whether the instruction access conflict flag in the memory fault status register is 1. If the instruction access conflict flag in the memory fault status register is 1, it is manually confirmed whether the program access error address exists in the full flexible page linked list of the current thread, the corresponding flexible page is searched and updated to the flexible page linked list of the domain corresponding to the thread, and then the memory fault status register is cleared. If the instruction access conflict flag in the memory fault status register is not 1, the memory fault status register is cleared directly.

[0075] Specifically, the memory access method further includes:

[0076] By dividing a domain into subdomains and disabling these subdomains, unused memory segments in thread X's domain can be allocated to thread Y, thus achieving efficient memory utilization. Specifically, a domain of 256 bytes or more can be divided into eight equal-sized subdomains. The corresponding bit in the SRD field of the MPU Domain Attributes and Size Register (MPU_RASR) is set to disable the subdomain. Disabling a subdomain means that another domain can overlap with the disabled range. If no other enabled domain overlaps with the disabled subdomain, and access permissions are unrestricted or the background domain is disabled, the MPU will issue a fault. For example, user thread domain A and kernel thread domain B have the same base address in the system. Domain A is 1MB, and domain B is 128KB. Domain B is the kernel-mode kernel running area and cannot be used by user threads. Domain A can be divided into eight subdomains, each 128KB in size; domain B, running on kernel threads, occupies the initial 128KB. Because the priority of kernel thread domain B is higher than that of user thread domain A, the domain number of domain A is set to 1, and the domain number of domain B is set to 2. To ensure that the attributes of domain B apply to the first 128 KB region of domain A, the SRD field of domain A should be set to 0b00000001 to disable the first subdomain. This allows kernel threads to use the memory corresponding to the first subdomain in domain A, which originally also belonged to user threads.

[0077] Figure 3 A schematic diagram of the structure of an MPU-based memory access device according to an embodiment of the present invention is shown; as follows: Figure 3 As shown, the memory access device includes:

[0078] The flexible page creation module 10 establishes a flexible page table based on the memory segment that the thread actually needs to access. The flexible page table includes several flexible pages, each of which corresponds to a memory block in the memory pool group. The memory segment that the thread needs to access consists of one or more memory blocks.

[0079] The flexible page allocation module 20 retrieves one or more flexible pages from the flexible page table and places them into the address space of the thread according to the memory segment that the thread actually needs to access; it also establishes a linked list of flexible pages used by the thread to establish the mapping relationship between the thread's address space and the memory pool.

[0080] The thread access module 30 allows the thread to access the memory segment by obtaining one or more flexible pages in the address space and then obtaining the corresponding memory segment in the memory pool through the flexible page linked list mapping.

[0081] This embodiment provides a memory access device based on an MPU. The flexible page creation module of the memory access device establishes a flexible page table based on the memory segments actually needed by the thread. The flexible page table includes several flexible pages, each corresponding to a memory block in a memory pool group. The memory segment needed by the thread consists of one or more memory blocks. In the flexible page allocation module, based on the memory segment actually needed by the thread, one or more corresponding flexible pages are retrieved from the flexible page table and placed into the thread's address space. A linked list of used flexible pages for the thread is established to map the thread's address space to the memory pool. In the thread access module, the thread accesses the memory segment by retrieving one or more flexible pages from its address space and mapping them to the corresponding memory segment in the memory pool through the linked list. This embodiment, by using flexible pages to allocate matching memory space to threads, can minimize the triggering of memory management errors, thereby improving the security and reliability of the embedded system software.

[0082] This invention also provides a computer electronic device. Figure 4 A schematic diagram of the structure of an electronic device to which embodiments of the present invention can be applied is shown, such as... Figure 4 As shown, the computer electronic device includes a central processing unit (CPU) 401, which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 402 or programs loaded from storage section 408 into random access memory (RAM) 403. The RAM 403 also stores various programs and data required for system operation. The CPU 401, ROM 402, and RAM 403 are interconnected via bus 404. An input / output (I / O) interface 405 is also connected to bus 404.

[0083] The following components are connected to I / O interface 405: an input section 406 including a keyboard, mouse, etc.; an output section 407 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 408 including a hard disk, etc.; and a communication section 409 including a network interface card such as a LAN card, modem, etc. The communication section 409 performs communication processing via a network such as the Internet. A drive 410 is also connected to I / O interface 405 as needed. A removable medium 411, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 410 as needed so that computer programs read from it can be installed into storage section 408 as needed.

[0084] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0085] The units or modules described in the embodiments of the present invention can be implemented in software or hardware. The described units or modules can also be located in a processor. For example, a processor can be described as including a flexible page creation module 10, a flexible page allocation module 20, and a thread access module 30. The names of these modules do not necessarily limit the module itself. For example, the flexible page creation module 10 can also be described as "a flexible page creation module 10 that creates flexible page tables based on the memory segments actually accessed by the threads."

[0086] In another aspect, the present invention also provides a computer-readable storage medium, which may be the computer-readable storage medium included in the MPU-based memory access device described in the above embodiments; or it may be a standalone computer-readable storage medium not assembled into an electronic device. The computer-readable storage medium stores one or more programs, which are used by one or more processors to execute the MPU-based memory access method described in the present invention.

[0087] The above description is merely a preferred embodiment of the present invention and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention is not limited to the specific combination of the above-described technical features, but also includes other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this invention.

Claims

1. A memory access method based on an MPU, wherein multiple MPU domains correspond one-to-one with multiple memory pools, characterized in that, The memory access method includes: A flexible page table is established based on the memory segment that the thread actually needs to access. The flexible page table includes several flexible pages, each of which corresponds to a memory block in the memory pool group. The memory segment that the thread needs to access consists of one or more memory blocks. Based on the memory segment that the thread actually needs to access, one or more corresponding flexible pages are obtained from the flexible page table and placed into the address space of the thread; A flexible page list is established for the thread to establish the mapping relationship between the thread's address space and memory pool; The thread accesses the memory segment by obtaining one or more flexible pages in the address space and then using the flexible page linked list mapping to obtain the corresponding memory segment in the memory pool.

2. The memory access method based on MPU according to claim 1, characterized in that, The process of establishing a flexible page table based on the memory segments actually accessed by the thread includes: Allocate a corresponding MPU field for each thread and set the corresponding attributes; For each memory pool corresponding to each MPU domain, determine the memory segment that each thread needs to access; The memory segment that each thread needs to access is mapped into several flexible pages, each flexible page corresponds to a memory block, and multiple memory blocks just make up a memory segment; Create flexible page tables to map each memory block in the memory pool group.

3. The memory access method based on MPU according to claim 1, wherein the flexible page includes the base address of the corresponding memory block and the length of the corresponding memory block, characterized in that, The step of retrieving one or more flexible pages from the flexible page table and placing them into the thread's address space based on the memory segment actually needed by the thread includes: The address range corresponding to the memory segment is calculated by using the base address and length of the memory segment actually accessed by a certain thread; Traverse the base address and length of each flexible page in the flexible page table, and store the base address and length of the flexible pages located within the address range in the address space of the thread.

4. The memory access method based on MPU according to claim 1, characterized in that, The memory access method further includes: After a thread finishes its work, the flexible pages in the address space are cleared, so that new threads can use the memory blocks used by the thread.

5. The memory access method based on MPU according to claim 1, characterized in that, If a high-priority thread is switched to work while a low-priority thread is accessing the memory pool, the memory access method further includes: Pause low-priority threads from accessing memory segment A, and save the information about the low-priority threads accessing the corresponding memory segment A in the memory pool through flexible paging; High-priority threads access memory segment B in the memory pool by acquiring flexible pages in the address space and using a flexible page linked list mapping. If memory segment A and memory segment B are in the same memory pool, then accessing memory segment B by a high-priority thread will not affect subsequent access to memory segment A by a low-priority thread.

6. The memory access method based on MPU according to claim 1, characterized in that, The memory access method further includes: Based on the multiple memory pools corresponding to all MPU domains of the thread, obtain all flexible pages corresponding to the multiple memory pools from the flexible page table, and establish a total flexible page linked list to map the memory pools corresponding to all domains; Based on the memory pool corresponding to the MPU domain used by the thread, all flexible pages corresponding to the memory pool are retrieved from the flexible page table, and a domain flexible page linked list is established to map the memory pool.

7. The memory access method based on MPU according to claim 6, characterized in that, If the processor generates a MemManageFault due to the memory segment B accessed by the thread exceeding the MPU domain of the thread, the memory access method further includes: If the address of memory segment B exists in the total flexible page list of the thread, then the corresponding flexible page is found and the flexible page is updated in the domain flexible page list corresponding to the thread to clear the fault.

8. A memory access device based on an MPU, characterized in that, The memory access device includes: The flexible page creation module establishes a flexible page table based on the memory segment that the thread actually needs to access. The flexible page table includes several flexible pages, each of which corresponds to a memory block in the memory pool group. The memory segment that the thread needs to access consists of one or more memory blocks. The flexible page allocation module retrieves one or more flexible pages from the flexible page table and places them into the address space of the thread based on the memory segment that the thread actually needs to access; it also establishes a linked list of flexible pages used by the thread to establish the mapping relationship between the thread's address space and the memory pool. The thread access module allows the thread to access the memory segment by obtaining one or more flexible pages in the address space and then using the flexible page linked list mapping to obtain the corresponding memory segment in the memory pool.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 7.

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