Atomic manipulation control circuits, systems and electronic devices

Abstract

The embodiment of the present application provides an atomic operation control circuit, system and electronic device, which relates to the field of chip technology. The atomic operation control circuit is applied to a multi-core system including multiple processors, including: a control module, which is respectively connected to multiple processor signals, and the control module is used to receive data read and write signals for target resources sent by each processor; an atomic operation module, which is connected to the control module signal, and the atomic operation module is used to generate a resource status signal for the target resource according to the data read and write signal sent by the control module, and send the resource status signal to the control module; wherein the resource status signal is used to indicate whether the target resource is currently occupied; the control module is also used to control multiple processors to perform atomic operations on the target resource according to the resource occupation status signal, so as to improve the stability and reliability of atomic operations in the multi-core system.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular, to an atomic operation control circuit, system and electronic device. Background Art

[0002] Nowadays, as the integration of chips becomes higher and higher, the computing power of chips has become one of the most important indicators for measuring a SoC (System on Chip) system. The CPU (Central Processing Unit) has also officially entered the multi-core era from the traditional single-core operation. With the application of multi-cores, the resources inside SoC chips are becoming more and more abundant. Generally speaking, in slightly complex application scenarios, how to efficiently occupy and release hardware resources (for example, bus, memory, interrupts, etc.) or software resources (for example, processes) between multiple cores has become a problem that must be solved in high-performance SoC design. Summary of the invention

[0003] In order to solve the above technical problems, an atomic operation control circuit, system and electronic device are provided in the embodiments of the present application to improve the stability and reliability of atomic operations in a multi-core system.

[0004] According to a first aspect of an embodiment of the present application, an atomic operation control circuit is provided, which is applied to a multi-core system including multiple processors, including:

[0005] A control module, the control modules are respectively connected to the plurality of processor signals, and the control module is used to receive data read and write signals for target resources sent by each processor;

[0006] The atomic operation module is connected to the control module signal, and the atomic operation module is used to generate a resource status signal for the target resource according to the data read and write signal sent by the control module, and send the resource status signal to the control module; wherein the resource status signal is used to indicate whether the target resource is currently occupied;

[0007] The control module is also used to control multiple processors to perform atomic operations on target resources according to the resource occupancy status signal.

[0008] In an optional embodiment of the present application, the atomic operation module includes:

[0009] A judgment unit, wherein a first input terminal of the judgment unit is connected to a data read-write interface signal of the control module;

[0010] A register unit, a switch end of the register unit is connected to the output end signal of the judgment unit, an input end of the register unit is connected to the data read and write interface signal of the control module, and an output end of the register unit is respectively connected to the second input end of the judgment unit and the feedback interface signal of the control module.

[0011] In an optional embodiment of the present application, the judging unit includes:

[0012] A comparator component, wherein a first input terminal of the comparator component is connected to a data read / write interface signal of the control module, and a second input terminal of the comparator component is connected to an output terminal signal of the register unit;

[0013] The gate circuit has an input end connected to the output end of the comparator component and the data read-write interface signal of the control module, and an output end of the gate circuit is connected to the switch end signal of the register unit.

[0014] In an optional embodiment of the present application, the comparator component includes:

[0015] A first comparator, wherein an input end of the first comparator is connected to a data read / write interface signal of the control module, and an output end of the first comparator is connected to a first input end signal of the gate circuit;

[0016] The second comparator has an input terminal connected to the output terminal of the register unit by signal, and an output terminal of the second comparator connected to the second input terminal of the gate circuit by signal.

[0017] In an optional embodiment of the present application, the gate circuit includes:

[0018] An OR gate subcircuit, wherein a first input terminal of the OR gate subcircuit is signal-connected to an output terminal of the first comparator, and a second input terminal of the OR gate subcircuit is signal-connected to an output terminal of the second comparator;

[0019] The AND gate subcircuit has a first input terminal connected to an output terminal signal of the OR gate subcircuit, a second input terminal connected to a data read / write interface signal of the control module, and an output terminal of the AND gate subcircuit connected to a switch terminal signal of the register unit.

[0020] In an optional embodiment of the present application, the atomic operation control circuit further includes:

[0021] An address selector, wherein the input end of the address selector is respectively connected to the input end of the second comparator and the output end signal of the register unit, and the output end of the address selector is connected to the feedback interface signal of the control module. The address selector is used to determine the processor identifier of the target processor currently occupied by the target resource according to the resource status signal.

[0022] In an optional embodiment of the present application, the control module includes at least a data bus, which is respectively connected to multiple processor signals and atomic operation module signals. The data bus is used to receive data read and write signals for target resources sent by each processor, and to control multiple processors to perform atomic operations on the target resources according to resource occupancy status signals.

[0023] In an optional embodiment of the present application, the target resource includes at least one of a protocol resource and a memory resource.

[0024] In a second aspect, an embodiment of the present application provides an atomic operation control system, including:

[0025] An atomic operation control circuit as in any one of the above items;

[0026] Multiple processors are connected to the control module signal in the atomic control circuit.

[0027] In a third aspect, an embodiment of the present application provides an electronic device, comprising the atomic operation control system of any of the above items.

[0028] The above-mentioned atomic operation control circuit is provided with a control module and an atomic operation module. After receiving the data read and write signal, the control module triggers the atomic operation module to determine the current resource status of the target resource, generates a resource status signal for characterizing whether the target resource is currently occupied, and feeds back the resource status signal to the control module. On the one hand, the control module determines whether the target resource is currently occupied based on the resource status signal, and controls whether other processors can access the target resource based on the determined result, so that the current loading or writing operation of the target resource is not interfered with, that is, the atomic operation mechanism for the target resource is realized, thereby solving the technical problem of poor reliability of atomic operations in the current multi-core system, and achieving the technical effect of improving the stability and reliability of atomic operations. On the other hand, regardless of whether there are atomic operation instructions in each processor in the multi-core system, the atomic operation control circuit provided in the embodiment of the present application can realize atomic operations for each resource, thereby greatly improving the applicability of atomic operations and the stability and reliability of the multi-core system. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0030] 10. Atomic operation control circuit; 100. Control module; 200. Atomic operation module; 310. Judgment unit; 211. Comparator component; U0. First comparator; U1. Second comparator; 212. Gate circuit; B0. OR gate subcircuit; A0. AND gate subcircuit; D0. Register unit; M0. Address selector; 20. Multi-core system; 210. Processor.

[0031] Figure 1 A schematic diagram of an atomic operation control circuit and an application environment provided in an embodiment of the present application;

[0032] Figure 2 A schematic diagram of an atomic operation control circuit provided in an embodiment of the present application;

[0033] Figure 3 A partial schematic diagram of an atomic operation control circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] In the process of implementing the present application, the applicant discovered that in a multi-core system, it is easy for some cores (i.e., CPUs) to not have atomic operation instructions for performing atomic operations. Once some cores do not have atomic operation instructions, they cannot perform atomic operations, which results in the entire multi-core system being unable to achieve exclusive access to certain resources. Therefore, the reliability of atomic operations in current multi-core systems is relatively poor.

[0035] In response to the above problems, an atomic operation control circuit, system and electronic device are provided in the embodiments of the present application to improve the stability and reliability of atomic operations in multi-core systems. In order to make the purpose, technical solutions and advantages of the present application clearer, an atomic operation control circuit, system and electronic device of the present application are further described in detail through embodiments and in combination with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0036] The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings). In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0037] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0038] See also Figure 1 , the atomic operation control circuit 10 provided in the embodiment of the present application is applied to a multi-core system 20, and the multi-core system 20 includes a plurality of processors 210, each processor 210 being a core that together constitutes the multi-core system 20, and the multi-core system 20 can be any other system such as a Soc system, which is not specifically limited in this embodiment. When applied, the atomic operation control circuit 10 provided in the embodiment of the present application is connected to the signal of each processor 210 in the multi-core system 20, and is used to control each processor 210 to exclusively load or exclusively write hardware resources (such as IP resources, memory resources) or software resources (such as processes), that is, to perform atomic operations on target resources. It should be explained that the atomic operation in the embodiment of the present application refers to an operation that will not be interrupted by the thread scheduling mechanism. Once this operation starts, it will run until it ends, and there will be no thread interference in the middle.

[0039] See also Figure 2 The embodiment of the present application provides an atomic operation control circuit 10, comprising: a control module 100 and an atomic operation module 200, wherein:

[0040] The control module 100 is respectively connected to the multiple processors 210 by signal. The control module 100 is used to receive the data read and write signals for the target resources sent by each processor 210. For example, the first processor CPU1 needs to access the target resource I2C interface among the three IP resources of I2C interface, UART interface and SPI interface, such as data reading or data writing, and the first processor CPU1 generates a data read and write request for the target resource I2C interface, that is, generates a data read and write signal, and sends it to the control module 100. The control module 100 is also used to control the multiple processors 210 to perform atomic operations on the target resources according to the resource occupancy status signal, that is, to start the exclusive mechanism for the target resources to perform exclusive access to the target resources, and avoid interference from other processors in the multi-core system 20, such as CPU2 and CPU3. It should be explained that the processor 210 is each core in the multi-core system 20, and the control module 100 is the central medium for controlling each processor 210 in the multi-core system 20 to access each resource, such as loading or writing operations. The control module 100 exists in different forms in different multi-core systems 20. For example, in a Soc system, the control module 100 is a data bus, and exists in other forms in other multi-core systems.

[0041] The atomic operation module 200 is connected to the control module 100 by signal, and the atomic operation module 200 is used to generate a resource status signal for the target resource according to the data read and write signal sent by the control module 100, and send the resource status signal to the control module 100. Among them, the resource status signal is used to characterize whether the target resource is currently occupied. The atomic operation module 200 can be configured based on registers, address memories, address control chips, etc., and the embodiments of the present application are not specifically limited. It only needs to be able to realize the function of determining whether the target resource is currently occupied and generating the corresponding resource status signal.

[0042] The following is a brief description of the working principle of the atomic operation control circuit 10 provided in the embodiment of the present application:

[0043] The current multi-core system 20 includes multiple processors 210, and the atomic operation control circuit 10 of the embodiment of the present application includes a control module 100 and an atomic operation module 200. When working, each processor 210 sends a data read and write request for the target resource to the control module 100, that is, the above-mentioned data read and write signal. After receiving the data read and write signal, the control module 100 triggers the atomic operation module 200 to determine the current resource status of the target resource, generates a resource status signal for characterizing whether the target resource is currently occupied, and feeds back the resource status signal to the control module 100. The control module 100 determines whether the target resource is currently occupied based on the resource status signal, and controls whether other processors 210 can access the target resource based on the determined result, so as to achieve that the current loading or writing operation of the target resource is not interfered with. For example, the first processor CPU1 wants to read the target resource I2C, but at the current moment the target resource I2C is occupied by the second processor CPU2. The atomic operation module 200 generates a resource status signal indicating that the target resource I2C is occupied or that the target resource I2C is occupied by the second processor CPU2 and feeds it back to the control module 100. The control module 100 prohibits the first processor CPU1 from accessing the target resource I2C based on the resource status signal obtained, so as to maintain the second processor CPU2's exclusive loading or exclusive writing of the target resource I2C to prevent interference by CPU1, that is, to perform atomic operations on the target resource I2C.

[0044] The atomic operation control circuit 10 provided in the embodiment of the present application is provided with a control module 100 and an atomic operation module 200. After receiving the data read and write signal, the control module 100 triggers the atomic operation module 200 to determine the current resource state of the target resource, generates a resource state signal for characterizing whether the target resource is currently occupied, and feeds back the resource state signal to the control module 100. On the one hand, the control module 100 determines whether the target resource is currently occupied based on the resource state signal, and controls whether other processors 210 can access the target resource based on the determined result, so that the current loading or writing operation of the target resource is not interfered, that is, the atomic operation mechanism for the target resource is realized, thereby solving the technical problem of poor reliability of atomic operations in the current multi-core system 20, and achieving the technical effect of improving the stability and reliability of atomic operations. On the other hand, regardless of whether each processor 210 in the multi-core system 20 has an atomic operation instruction, the atomic operation control circuit 10 provided in the embodiment of the present application can realize atomic operations for each resource, thereby greatly improving the applicability of atomic operations and the stability and reliability of the multi-core system 20.

[0045] Please also see Figure 2 In an optional embodiment of the present application, the atomic operation module 200 includes: a judgment unit 310 and a register unit D0, wherein:

[0046] The first input end of the judgment unit 310 is connected to the data read and write interface signal of the control module 100, and the output end of the judgment unit 310 is connected to the switch end signal of the register unit D0. The judgment unit 310 is used to determine the current occupation state of the target resource according to the data read and write signal sent by the control module 100 from the data read and write interface, and the resource state signal of the target resource generated inside the register unit D0. The resource state signal can be a level signal, which only indicates whether the target resource is currently occupied through high level and low level, and the circuit is simple, and the target resource occupation state determination efficiency is high; the resource state signal can also be a digital signal, which indicates whether the target resource is currently occupied and the processor identification of the occupied processor 210 through a specific digital signal carrying information, so that the control module 100 and other processors 210 know which processor 210 is currently occupying the target resource. Of course, the form of the resource state signal includes but is not limited to the above two types, which are not limited in this embodiment and can be specifically set according to actual conditions.

[0047] The switch end EN of the register unit D0 is connected to the output end signal of the judgment unit 310, the input end D[2:0] of the register unit D0 is connected to the data read and write interface signal of the control module 100, and the output end Q[2:0] of the register unit D0 is respectively connected to the second input end of the judgment unit 310 and the feedback interface signal of the control module 100. The resource identifier or resource address of each hardware resource and software resource in the multi-core system 20 is stored in the register unit D0. The register unit D0 determines the occupation status of each resource according to the update status of the current resource identifier or resource address, and generates a resource status signal for indicating whether the target resource is currently occupied, and feeds the resource status signal back to the control module 100.

[0048] The embodiment of the present application is provided with a judgment unit 310 and a register unit D0, the input terminal D[2:0] of the register unit D0 is connected to the data read and write interface signal of the control module 100, and the output terminal Q[2:0] of the register unit D0 is respectively connected to the second input terminal of the judgment unit 310 and the feedback interface signal of the control module 100. When working, the register unit D0 updates the resource identification or resource address of each hardware resource or software resource in real time, generates a corresponding resource occupancy signal and feeds it back to the control module 100, and the control module 100 can determine the current occupancy status of the target resource to be accessed through the resource status signal sent by the register unit D0, thereby avoiding interference of the access operation of other processors when the target resource is accessed by one of the processors, and further improving the stability and reliability of the atomic operation on the target resource.

[0049] Please continue to see Figure 3In an optional embodiment of the present application, the above-mentioned judgment unit 310 includes: a comparator component 211 and a gate circuit 212.

[0050] The first input terminal of the comparator component 211 is connected to the data read / write interface signal of the control module 100, and the second input terminal of the comparator component 211 is connected to the output terminal Q[2:0] signal of the register unit D0. A preset duty signal is pre-stored in the comparator component 211. After receiving the data read / write signal based on the data read / write interface, the comparator component 211 compares the received data read / write signal with the preset duty signal. If the two match, a high level signal "1" is generated and output. If the two do not match, a low level signal "0" is generated and output. Correspondingly, if the resource status signal output by the register unit D0 matches the preset duty signal, a high level signal "1" is output. If the two do not match, a low level signal "0" is generated and output.

[0051] The input end of the gate circuit 212 is respectively connected to the output end of the comparator component 211 and the data read and write interface signal of the control module 100, and the output end of the gate circuit 212 is connected to the switch end EN signal of the register unit D0. The gate circuit 212 is used to control the opening and closing of the switch end EN of the register unit D0 according to the input signal, so as to control the access of the control module 100 and other processors 210 to the register unit D0. For example, the two signals output by the comparator component 211 are both high level "1", that is, the target resource is in an occupied state, and there is a processor 210 that needs to access the target resource, or has just initiated an access request but has not yet formally accessed it. At this time, the gate circuit 212 performs a logic AND process on the two high-level "1s", and the gate circuit 212 opens and outputs a high-level "1" to open the switch end EN of the register unit D0. Otherwise, as long as one of the two signals output by the comparator component 211 is a low-level signal, the signal output by the gate circuit 212 is also a low-level "0", and the switch end EN of the register unit D0 cannot be opened. The control module 100 cannot update or rewrite the status of each resource in the register unit D0, that is, it cannot update or rewrite the generated resource status signal.

[0052] The embodiment of the present application is provided with a comparator component 211 and a gate circuit 212. The comparator component 211 compares the data read and write signals received from the data read and write interface of the control module 100 and the resource status signal output by the register unit D0 based on the internal pre-stored preset occupancy signal, so as to determine whether the target resource is currently occupied. The determination method is simple and fast, and does not require complex logical processing, thereby greatly improving the execution efficiency of atomic operations.

[0053] Please also see Figure 2and Figure 3 In an optional embodiment of the present application, the comparator component 211 includes a first comparator U0 and a second comparator U1:

[0054] The input terminal B of the first comparator U0 is connected to the data read / write interface signal of the control module 100, and the output terminal Y of the first comparator U0 is connected to the first input terminal signal of the gate circuit 212. The first comparator U0 compares the data read / write signal output by the control module 100 with the preset duty signal (for example, 3b'111) preset internally. If the data read signal icb-wdata[2:0] in the data read / write signal is also 3b'111, then the output terminal Y of the first comparator U0 outputs a high level "1"; if the data read signal icb-wdata[2:0] is not 3b'111, for example, 3b'101, then the output terminal Y of the first comparator U0 outputs a low level "0".

[0055] The input terminal Y of the second comparator U1 is connected to the output terminal Q[2:0] signal of the register unit D0, and the output terminal Y of the second comparator U1 is connected to the second input terminal signal of the gate circuit 212. For example, a high level "1" is used to represent that the target resource is occupied by a certain processor 210, and "0" represents that it is not occupied. If the multi-core system 20 includes three processors: CPU1, CPU2 and CPU3, and the target resource in the register unit D0 is not accessed or occupied by any processor 210, then the output resource status signal is 3b'111; if the target resource in the register unit D0 is occupied by the second processor CPU2, then the output resource status signal is 3b'101, and if the target resource is occupied by the third processor CPU3, then the output resource status signal is 3b'110.

[0056] The comparator component 211 in the atomic operation control circuit 10 provided in the embodiment of the present application includes a first comparator U0 and a second comparator U1. The first comparator U0 compares the data read and write signal input by the control module 100 with the preset duty signal to determine whether there is a processor 210 that needs to access the target resource at present. The second comparator U1 compares the resource occupancy signal output by the register unit D0 with the preset duty signal to determine whether the target resource is occupied and which processor 210 is occupying it. The occupancy status of each resource can be determined more accurately, further improving the reliability of atomic operations on the target resource.

[0057] In an optional embodiment of the present application, the gate circuit 212 includes an OR gate subcircuit B0 and an AND gate subcircuit A0:

[0058] The first input terminal of the OR gate sub-circuit B0 is connected to the output terminal Y signal of the first comparator U0 , and the second input terminal of the OR gate sub-circuit B0 is connected to the output terminal Y signal of the second comparator U1 .

[0059] If the first comparator U0 outputs a high level "1", it means that there is currently a processor 210 that needs to access the target resource. If the second comparator U1 outputs a high level "1", that is, the resource status signal output by the register unit D0 matches the preset duty signal, both are 3b'111, that is, the target resource is not currently occupied by any processor 210. Therefore, as long as the target resource in the register unit D0 is not occupied (the resource occupation signal output by the output terminal Y of the second comparator U1 is all high level "1"), or there is a processor 210 that needs to access the target resource (the output terminal Y of the first comparator U0 is high level "1"), then the OR gate sub-circuit B0 will be turned on and output a high level "1"; if the target resource in the register unit D0 is occupied (the resource occupation signal output by the output terminal Y of the second comparator U1 is not all high level "1"), and there is no processor 210 that needs to access the target resource (the output terminal Y of the first comparator U0 is low level "0"), then the OR gate sub-circuit B0 will output a low level "0".

[0060] The first input terminal of the AND gate subcircuit A0 is connected to the output terminal signal of the OR gate subcircuit B0, the second input terminal of the AND gate subcircuit A0 is connected to the data read and write interface signal of the control module 100, and the output terminal of the AND gate subcircuit A0 is connected to the switch terminal signal of the register unit D0. For example, the data read and write signal output by the control module 100 includes a data write signal, and the data write signal icb-semaphore-sel-ena is a high level "1", indicating that there is a processor 210 that needs to access the target resource at present. At the same time, the output terminal Y of the OR gate subcircuit B0 outputs a high level "1", then the first output terminal of the AND gate subcircuit A0 will generate a high level "1", and the high level turns on the switch terminal EN of the register unit D0. The controller identifies the processor 210 that needs to access the target resource based on the data read signal icb-wdata[2:0], for example, the processor ID is written into the input terminal D[2:0] of the register unit D0. During the high level of CLK, the state of the Q terminal of the register unit D0 changes with the change of the state of the D terminal; after CLK becomes low level, the Q terminal will maintain the state of the D terminal at the moment when CLK becomes low level. Therefore, after the next clock cycle or the preset clock cycle, the processor ID will be written into the output terminal Q[2:0] of the register unit D0, and the register unit D0 can update the resource occupation signal according to the processor 210 identification. For example, if the first processor CPU1 needs to access the target resource, then its counting signal quantity is modified to 3b'011 to feedback to the control module 100, and the first processor CPU1 is currently accessing the target resource exclusively, and so on, which will not be exhaustively listed here.

[0061] By setting an OR gate subcircuit B0 and an AND gate subcircuit A0 in the gate circuit 212, the embodiment of the present application can update or rewrite the resource occupancy signal in the register unit D0 through the received data read and write signal, so as to facilitate the determination of which processor 210 specifically occupies the target resource, and the atomic operation execution efficiency and reliability are higher.

[0062] In an optional embodiment of the present application, the atomic operation control circuit 10 further includes an address selector M0:

[0063] The input end of the address selector M0 is respectively connected to the input end of the second comparator U1 and the output end signal of the register unit D0, and the output end of the address selector M0 is connected to the feedback interface signal of the control module 100. The address selector M0 is used to determine the processor 210 identifier of the target processor 210 currently occupied by the target resource according to the resource status signal, and return the processor identifier of the first processor 210 to the control module 100, so that the control module 100 can feedback to the processor 210 that currently needs to access the target resource which specific processor is currently occupying the target resource.

[0064] In an optional embodiment of the present application, the control module 100 at least includes a data bus, which is respectively connected to the multiple processors 210 and the atomic operation module 200, and the data bus is used to receive data read and write signals for target resources sent by each processor 210, and control the multiple processors 210 to perform atomic operations on the target resources according to the resource occupancy status signal. The embodiment of the present application does not need to configure other central media, and directly uses the data bus as the central media between each processor 210 and the atomic operation module 200 in the multi-core system 20, which has high reliability and greatly reduces the cost of executing atomic operations.

[0065] In an optional embodiment of the present application, the above-mentioned target resources include at least one of protocol resources and memory resources. Among them, the protocol resources are IP resources, different protocol interfaces, such as I2C interface, UART interface, SPI interface, etc., and the memory resources can be physical memory or virtual memory. This embodiment is not specifically limited and can be specifically selected according to actual conditions. Of course, the atomic operation control circuit 10 provided in the embodiment of the present application can control the atomic operations corresponding to the hardware resources of the above-mentioned protocol resources and memory resources, and can also control the atomic operations corresponding to software resources such as processes, which are not limited here.

[0066] Another embodiment of the present application provides an atomic operation control system, including: an atomic operation control circuit 10 as described in any of the above embodiments, and multiple processors 210, and the multiple processors 210 are all signal-connected to the control module 100 in the atomic control circuit.

[0067] The beneficial effects of the atomic operation control circuit 10 have been described in detail in the above embodiments and will not be repeated here.

[0068] Another embodiment of the present application provides an electronic device, including the atomic operation control system as described above.

[0069] The electronic device may be a chip, a mobile phone, a server, etc., which is not specifically limited in this embodiment.

[0070] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. An atomic operation control circuit, characterized in that: Applications include: A control module, the control modules are respectively connected to the plurality of processors by signal, and the control module is used to receive a data read and write signal for a target resource sent by each of the processors; an atomic operation module, connected to the control module signal, the atomic operation module is used to generate a resource status signal for the target resource according to the data read and write signal sent by the control module, and send the resource status signal to the control module; wherein the resource status signal is used to indicate whether the target resource is currently occupied; the atomic operation module comprises: a judgment unit, the first input end of the judgment unit is connected to the data read and write interface signal of the control module; a register unit, the switch end of the register unit is connected to the output end signal of the judgment unit, the input end of the register unit is connected to the data read and write interface signal of the control module, and the output end of the register unit is respectively connected to the second input end of the judgment unit and the feedback interface signal of the control module; wherein the judgment unit comprises: a comparator component, the first input end of the comparator component is connected to the data read and write interface signal of the control module, and the second input end of the comparator component is connected to the output end signal of the register unit; a gate circuit, the input end of the gate circuit is respectively connected to the output end of the comparator component and the data read and write interface signal of the control module, and the output end of the gate circuit is connected to the switch end signal of the register unit; The control module is further used to control the plurality of processors to perform atomic operations on the target resource according to the resource status signal.

2. The atomic operation control circuit according to claim 1, characterized in that: The comparator component comprises: A first comparator, wherein an input end of the first comparator is signal-connected to a data read / write interface of the control module, and an output end of the first comparator is signal-connected to a first input end of the gate circuit; A second comparator, wherein an input terminal of the second comparator is signal-connected to an output terminal of the register unit, and an output terminal of the second comparator is signal-connected to a second input terminal of the gate circuit.

3. The atomic operation control circuit according to claim 2, characterized in that: The gate circuit comprises: An OR gate subcircuit, wherein a first input terminal of the OR gate subcircuit is signal-connected to an output terminal of the first comparator, and a second input terminal of the OR gate subcircuit is signal-connected to an output terminal of the second comparator; An AND gate subcircuit, wherein the first input end of the AND gate subcircuit is signal-connected to the output end of the OR gate subcircuit, the second input end of the AND gate subcircuit is signal-connected to the data read and write interface of the control module, and the output end of the AND gate subcircuit is signal-connected to the switch end of the register unit.

4. The atomic operation control circuit according to claim 2, characterized in that: Also includes: An address selector, wherein the input end of the address selector is respectively connected to the input end of the second comparator and the output end signal of the register unit, the output end of the address selector is connected to the feedback interface signal of the control module, and the address selector is used to determine the processor identifier of the target processor currently occupied by the target resource according to the resource status signal.

5. The atomic operation control circuit according to claim 1, characterized in that: The control module at least includes a data bus, which is respectively connected to the multiple processor signals and the atomic operation module signal. The data bus is used to receive data read and write signals for target resources sent by each of the processors, and control the multiple processors to perform atomic operations on the target resources according to the resource status signal.

6. The atomic operation control circuit according to claim 1, characterized in that: The target resource includes at least one of a protocol resource and a memory resource.

7. An atomic operation control system, characterized in that: include: The atomic operation control circuit according to any one of claims 1 to 6; A plurality of processors are each connected to the control module signal in the atomic operation control circuit.

8. An electronic device, characterized in that: Includes the atomic operation control system as described in claim 7.

Images