Method for electrical testing of semiconductor devices and testing structure

CN114783500BActive Publication Date: 2026-08-28CHANGXIN MEMORY TECH INC
View PDF 2 Cites 0 Cited by

Patent Information

Application Number
CN202210398929.9
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-04-15
Publication Date
2026-08-28
Estimated Expiration
2042-04-15

AI Technical Summary

Technical Problem

然而,现有测试方法测试结果偏差较大,准确率较低

Benefits of technology

[0041]在本公开的一种示例性实施例中,各所述字线之间均等间距分布,所述第二导电结构与所述第三导电结构的间距大于相邻分布的两个所述字线的间距。

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN114783500B_ABST
    Figure CN114783500B_ABST
Patent Text Reader

Abstract

The present disclosure relates to the technical field of semiconductor, and discloses a method for testing electrical property of semiconductor device and a testing structure. The method comprises: providing a semiconductor structure, wherein the semiconductor structure comprises an array region and a bulk lead-out region, the array region comprises a plurality of spaced-apart word lines, and each word line is provided with a conductive contact plug and a bit line on both sides thereof; forming conductive structures of the lead-out bit line, the conductive contact plug, the bulk lead-out region, any word line and the word line adjacent to the both sides of the word line, respectively; and applying voltages to the conductive structures, respectively, to complete the electrical property test. The method can reduce the deviation of test results and improve the test accuracy.
Need to check novelty before this filing date? Find Prior Art

Citation Information

Patent Citations

  • Detection of word-line leakage in memory arrays: current based approach

    CN103069498A

  • Semiconductor device and method for testing the same

    US20060236172A1