A frequency-band phase-locked loop based on programmable capacitor array

Abstract

The present invention discloses a frequency band phase locked loop based on a programmable capacitor array, wherein a frequency detector circuit is sequentially connected to a charge pump circuit, a switch loop filter and a multi-band voltage controlled oscillator circuit, the multi-band voltage controlled oscillator circuit is connected to the frequency detector circuit via a programmable frequency divider circuit, the frequency detector circuit is connected to the switch loop filter via a switch control circuit; the reference clock signals clk_ref and clk_div generate control signals UP and DN via the frequency detector, the charge pump converts the received pulse difference signal into a current signal, and then converts it into a voltage signal via a loop filter for controlling the frequency change of the voltage controlled oscillator, discrete frequency modulation is achieved by changing the load capacitance, the frequency output range is obtained by using a programmable capacitor array structure, the output is fed back to the frequency detector via a frequency divider, and loop locking is achieved. The present invention achieves a lower phase noise of the voltage controlled oscillator while reducing the gain of the voltage controlled oscillator, and simultaneously obtains a wider output frequency range.

Description

Technical Field

[0001] The invention belongs to the technical field of frequency synthesizers designed for low power consumption integrated circuits, and in particular relates to a frequency band phase locked loop based on a programmable capacitor array. Background Art

[0002] With the development of the times and the continuous changes in science and technology, traditional image sensors can no longer meet daily needs. In recent years, LiDAR has played an increasingly important role in the fields of smart phones, machine vision, and autonomous driving. The current mainstream time-of-flight (ToF) LiDAR solution obtains distance information by calculating the round-trip time from the emitted laser pulse to the object being measured. Therefore, the requirements for the noise, power consumption, and resistance to process voltage and temperature (PVT) changes of the phase-locked loop (PLL) circuit are much higher than other applications.

[0003] As a closed-loop automatic control system that enables the phase of the feedback signal to track the phase of the input signal, PLL can realize functions such as signal synchronization, frequency multiplication, and frequency synthesis. The traditional analog phase-locked loop has a simple structure and high linearity, but a narrow frequency locking range; the digital-analog hybrid phase-locked loop has good phase noise performance and a high operating frequency; the fully digital phase-locked loop has high integration, small footprint, but a low operating frequency. At present, analog phase-locked loops are rarely used, and the output frequency of fully digital phase-locked loops needs to be improved. Therefore, digital-analog hybrid phase-locked loops are still widely used in wireless communication transceivers, data clock recovery, and clock generation. In addition, the bandwidth design directly determines the quality of the noise transmission characteristics of the loop. The larger the bandwidth, the faster the locking speed, but the more conducive to noise transmission. Conversely, the smaller the bandwidth, the slower the loop locking speed, but the less conducive to noise transmission, and the better the output noise performance. Therefore, how to balance the compromise between the two to achieve the optimal solution has always been the focus of research. At present, there are many literatures on digital-analog hybrid phase-locked loops that are mainly devoted to the research of low noise and low power consumption, and various improved structures have also appeared.

[0004] In the field of ToF LiDAR detection, the low power consumption, low noise and PVT resistance of PLL circuits are always the focus of attention. As an important part of the entire radar system, the smaller the clock signal noise, the better the ranging accuracy of the radar system; the more stable the clock signal, the less pressure on system calibration; the wider the tuning range that the clock signal can provide, the more convenient it is for more complex on-chip digital processing and function realization.

[0005] Most traditional phase-locked loops can only operate at a single frequency, such as Figure 1 As shown, the requirement of the laser radar system for a multi-frequency clock source cannot be met. Meanwhile, the ability to resist PVT changes based on the ring oscillator structure cannot meet the requirement of ToF laser radar.

[0006] Existing solution 1 uses dynamic high threshold voltage and switch coupling technology to provide high drive current. Due to the low power design, the loop bandwidth of the overall structure of the phase-locked loop is limited to only 150KHz.

[0007] Existing solution 2 uses a new charge pump structure, with an rms jitter of 16.9ps at an output frequency of 500MHz and a phase noise of -94dBC / Hz at a frequency offset of 1MHz. The rms jitter of the loop output of this structure is relatively large.

[0008] Existing Solution 3 introduces a power supply noise compensation feedforward ring voltage-controlled oscillator, which compensates for the oscillation frequency fluctuation caused by power supply noise by adjusting the drive strength in the feedforward path and the direct path; however, due to structural limitations, the optimal loop bandwidth is only 200KHz, resulting in a long loop locking time.

[0009] Existing solution 4 uses a fast phase error correction technology to better suppress the frequency jitter of the VCO. This technology simulates the phase realignment mechanism of the injection-locked phase-locked loop, so that the accumulated jitter of the VCO can be removed in a short time, and selective frequency tuning technology is used to further suppress the reference spurious level. This implementation method has high static power consumption and poor resistance to PVT changes.

[0010] The existing solution 5 adopts a small-area charge pump current injection technology, uses an embedded startup circuit and a fast self-bias locking method, and the loop bandwidth needs to be re-optimized. Summary of the invention

[0011] The technical problem to be solved by the present invention is to provide a frequency band phase-locked loop based on a programmable capacitor array in view of the deficiencies in the above-mentioned prior art. By utilizing the programmable capacitor array structure, a lower phase noise of the voltage-controlled oscillator is achieved while reducing the gain of the voltage-controlled oscillator, while obtaining a wider output frequency range.

[0012] The present invention adopts the following technical solutions:

[0013] A frequency band phase-locked loop based on a programmable capacitor array comprises a frequency detector circuit, the frequency detector circuit is connected to a charge pump circuit CP, a switch loop filter SLPF and a multi-band voltage-controlled oscillator circuit VCO in sequence, the multi-band voltage-controlled oscillator circuit VCO is connected to the frequency detector circuit via a programmable frequency divider circuit, and the frequency detector circuit is connected to the switch loop filter via a switch control circuit;

[0014] The reference clock signals clk_ref and clk_div generate control signals UP and DN through the phase frequency detector PFD. The charge pump converts the received pulse difference signal into a current signal, which is then converted into a voltage signal through a loop filter to control the frequency change of the voltage-controlled oscillator. Discrete frequency modulation is achieved by changing the load capacitance, and the frequency output range is obtained using a programmable capacitor array structure. The output is fed back to the phase frequency detector through a divider to achieve loop locking.

[0015] Specifically, the switching loop filter SLPF includes a power switch SW, a source S of the power switch SW is divided into two paths, one path is connected to the charge pump circuit CP, and the other path is grounded via a capacitor C1; the gate of the power switch SW is connected to the switch control circuit; the drain of the power switch SW is divided into four paths, the first path is grounded via a resistor R and a capacitor C2, the second path is connected to a common ground with the capacitor C2 via a capacitor C3, the third path is connected to a multi-band voltage-controlled oscillator circuit VCO, and the fourth path is connected to the multi-band voltage-controlled oscillator circuit VCO via a band switching circuit.

[0016] Further, the switch of the switching loop filter operates when the phase-locked loop is in a locked state, and the switching loop filter is turned on after it is detected that the phase-locked loop is locked or substantially locked.

[0017] Furthermore, the power switch SW is a MOS tube.

[0018] Specifically, the multi-band voltage-controlled oscillator circuit includes a bias circuit and a ring oscillator circuit, the bias circuit includes M1, the power supply VDD is connected to the source of M1, the gate of M1 is connected to the bias potential Vb, the drain of M1 is divided into three paths, the first path is connected to the source of M2, the second path is grounded through the capacitor C, the third path is connected to the control voltage Vcont of the ring oscillator, the gate of M2 is connected to the control voltage Vc, the drain of M2 is connected to GND, the ring oscillator circuit includes a three-stage differential inverter module, the control voltage Vcout is connected to the substrate potential of M3 and M4, the power supply voltage VDD is connected to the source of M3, the source of M4, the source of M7, and the source of M8, and the gate of M7 is connected to M3. The gate of M8 is connected to the gate of M4 and the gate of M6. The drain of M8 is divided into five paths, the first path is connected to the drain of M3, the second path is connected to the source of M1, the third path is connected to the drain of M5, the fourth path is connected to the load capacitor array, and the other end of the load capacitor is grounded via switch S. The fifth path is connected to the gate of M2, the gate of M8 is connected to the gate of M4 and the gate of M6, the drain of M8 is divided into five paths, the first path is connected to the drain of M4, the second path is connected to the source of M2, the third path is connected to the drain of M6, the fourth path is connected to the load capacitor array, and the other end of the load capacitor is grounded via switch S. The fifth path is connected to the gate of M1, and the drain of M1, the drain of M2, the source of M5, and the source of M6 are connected to GND.

[0019] Furthermore, the delay unit of the ring oscillator changes the charging current of the delay unit by changing the N-well bias voltage Vsb of the PMOS tube, thereby changing the oscillation frequency.

[0020] Furthermore, the multi-band voltage controlled oscillator VCO adopts a ring oscillator structure.

[0021] Specifically, the control voltage of the multi-band voltage-controlled oscillator circuit VCO is 0.3-0.8V, and the voltage-controlled gain is 50-120MHz / V.

[0022] Specifically, the multi-band voltage controlled oscillator circuit VCO is connected to an LDO with a high power supply rejection ratio to provide a low-noise power supply voltage VDD.

[0023] Specifically, the frequency band phase-locked loop also includes a lock detection circuit and a frequency band switching circuit. One end of the lock detection circuit is connected to the reference clock signal and the feedback clock signal, and the other end is connected to the switch control circuit. One end of the frequency band switching circuit is connected to the loop filter circuit, and the other end is connected to the voltage-controlled oscillator circuit.

[0024] Compared with the prior art, the present invention has at least the following beneficial effects:

[0025] A frequency band phase-locked loop based on a programmable capacitor array includes a phase detector circuit, which is connected to a charge pump circuit CP and transmits the phase difference between a reference clock signal and a feedback clock signal to the charge pump. The charge pump circuit is connected to the input end of a switch loop filter and converts the phase difference signal into a current pulse signal and connects it to the loop filter. The output end of the loop filter is connected to a voltage-controlled oscillator. The loop filter filters out high-frequency components in the signal and converts the pulse current signal into a voltage signal and connects it to a voltage control point of the ring oscillator. The output end of the voltage-controlled oscillator circuit is connected to a frequency divider, and the frequency divider connects the feedback signal to the input end of the phase detector, thereby forming a loop lock. The phase detector circuit is connected to the switch loop filter via a switch control circuit and is used to reduce the disturbance of the loop electrical signal.

[0026] Furthermore, the switching loop filter SLPF includes a power switch SW, a source S of the power switch SW is divided into two paths, one path is connected to the charge pump circuit CP, and the other path is grounded via the capacitor C1, the gate of the power switch SW is connected to the switch control circuit, and the drain of the power switch SW is divided into four paths, the first path is grounded via the resistor R and the capacitor C2, the second path is connected to the capacitor C3 and the capacitor C2, the third path is connected to the multi-band voltage-controlled oscillator circuit VCO, and the fourth path is connected to the multi-band voltage-controlled oscillator circuit VCO via the band switching circuit.

[0027] Furthermore, the switch of the switching loop filter works only when the phase-locked loop is in a locked state. The locking detection circuit turns on the switching loop filter after detecting that the phase-locked loop is locked or substantially locked, which can reduce the voltage disturbance of the voltage-controlled potential.

[0028] Furthermore, since the switch SW is also implemented by a MOS tube, there is also a clock feedthrough effect, but the size of the SW is smaller, the impact of charge injection and clock feedthrough is much smaller, and there is no current mismatch and time mismatch problem, so the control voltage Vcont of the VCO after the SW fluctuates much less than that of V0.

[0029] Furthermore, the oscillator circuit is mainly composed of two categories, among which the phase noise of the LC oscillator is better than that of the ring oscillator, and is mostly used in the communication field with relatively high requirements, but it requires capacitors and inductors, occupies a large area and has a narrow tuning range. The ring oscillator itself has the advantages of wide output frequency range, simple structure, small area, etc., and is widely used in digital clock generators, short-distance wired data transmission and other circuits with looser phase noise requirements. In addition, in order to better match the oscillator in the time-to-digital converter, the ring oscillator itself can obtain a signal output with a fixed phase difference, so a ring voltage-controlled oscillator is used.

[0030] Furthermore, the multi-band voltage-controlled oscillator circuit includes a bias circuit and a ring oscillator circuit, wherein the bias circuit includes M1 and M2. In order to provide a larger tuning voltage range for the ring oscillator, M1 and M2 both use PMOS tubes with low threshold voltage to obtain a lower turn-on level.

[0031] Furthermore, the delay unit of the ring oscillator changes the charging current of the delay unit by changing the N-well bias voltage Vsb of the PMOS tube, thereby changing the oscillation frequency. The advantage of this method is that the control tube will not be in the on state all the time, avoiding a certain amount of DC power consumption. In addition, the oscillation frequency range of the oscillator can be changed by changing the load capacitance, and the change of capacitance will only cause the voltage control curve to shift up and down, and will not cause K VCO changes.

[0032] Furthermore, the control voltage of the multi-band voltage-controlled oscillator circuit VCO is set to 0.3-0.8V, so as to select a relatively linear tuning region of the ring oscillator. Meanwhile, by reducing the voltage-controlled gain, the influence of voltage disturbance on the output frequency can be reduced, thereby reducing jitter.

[0033] Furthermore, the phase-locked loop is a power-sensitive module circuit, especially the voltage-controlled oscillator in the phase-locked loop is very sensitive to changes in power supply voltage and noise. Using an LDO with a high power supply rejection ratio to power the VCO can reduce the impact of the power supply voltage on the ring oscillator and reduce output jitter.

[0034] Furthermore, one end of the lock detection circuit is connected to the reference clock signal and the feedback clock signal, and the other end is connected to the switch control circuit for detecting the stable state of the phase-locked loop, and the frequency band switching circuit is used to control the switch of the load capacitor of the voltage-controlled oscillator circuit.

[0035] In summary, the present invention applies low-power and low-noise technologies to a phase-locked loop architecture to improve the stability and energy efficiency of the clock circuit, and is suitable for applications such as laser ranging radars and image sensors that require a stable clock.

[0036] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of the structure of a traditional ring oscillator;

[0038] Figure 2 This is a schematic diagram of the overall structure of the frequency configurable phase-locked loop of the present invention;

[0039] Figure 3 Schematic diagram of a switching loop filter, wherein (a) is the switching loop filter, and (b) is the operating waveform of the filter;

[0040] Figure 4 Schematic diagram of the structure of a multi-band voltage-controlled oscillator, where (a) is the structure of the voltage-controlled oscillator, and (b) is the internal delay unit circuit of the voltage-controlled oscillator;

[0041] Figure 5 Schematic diagram of frequency tuning curves of a multi-band voltage-controlled oscillator, where (a) is the tuning curve of frequency bands 1 to 5, and (b) is the tuning curve of frequency bands 44 to 48;

[0042] Figure 6 Schematic diagram of the phase noise of the voltage controlled oscillator under different process angles;

[0043] Figure 7 The figure shows the simulation results of the phase-locked loop RMS jitter at different output frequencies. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0047] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0048] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0049] Various structural schematic diagrams of the embodiments disclosed in the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0050] The present invention provides a frequency band phase-locked loop based on a programmable capacitor array, which reduces the reference spurious of the phase-locked loop through a switching loop filter, and reduces the voltage spikes of the voltage-controlled oscillator control voltage. In addition, a multi-band voltage-controlled oscillator is used to reduce the voltage-controlled gain while expanding the output frequency range, which can reduce the reference spurious on the one hand, and reduce the phase noise of the voltage-controlled oscillator itself on the other hand. The programmable frequency divider of the phase-locked loop is used to change the loop frequency division ratio to obtain different output frequencies of integer multiples of the reference frequency.

[0051] See also Figure 2The present invention discloses a frequency band phase-locked loop based on a programmable capacitor array, comprising a phase frequency detector circuit PFD, a charge pump circuit CP, a switch loop filter SLPF, a multi-band voltage-controlled oscillator circuit VCO, a programmable frequency divider circuit 1 / N and other auxiliary circuits.

[0052] The phase frequency detector circuit PFD is connected in sequence to the charge pump circuit CP, the switching loop filter SLPF and the multi-band voltage controlled oscillator circuit VCO to output the frequency f out , output frequency f out The phase frequency detector circuit PFD is connected via the programmable divider circuit 1 / N, the switch loop filter SLPF is connected to the multi-band voltage-controlled oscillator VCO via the frequency band switching circuit, and the phase frequency detector circuit PFD is connected to the switch loop filter SLPF via the switch control circuit. The reference clock signals clk_ref and clk_div generate control signals UP and DN via the phase frequency detector PFD, the charge pump converts the received pulse difference signal into a current signal, and then converts it into a voltage signal through the loop filter to control the frequency change of the voltage-controlled oscillator. In order to reduce the influence of phase noise on the loop, a lower voltage control gain Kvco is used, and discrete frequency modulation is realized by changing the load capacitance, and a programmable capacitor array structure is used to obtain a wider frequency output range, and finally the divider feeds the output back to the phase frequency detector to achieve loop locking. Other auxiliary circuits include a lock detection circuit and a frequency band switching circuit. One end of the lock detection circuit is connected to the reference clock signal and the feedback clock signal, and the other end is connected to the switch control circuit for detecting the stable state of the phase-locked loop. One end of the frequency band switching circuit is connected to the loop filter circuit, and the other end is connected to the voltage-controlled oscillator circuit for controlling the switch of the load capacitor of the voltage-controlled oscillator circuit.

[0053] The reference clock signals clk_ref and clk_div are passed through the phase frequency detector PFD to generate control signals UP and DN. Since the switch of the switching loop filter works only when the phase-locked loop is in a locked state, a locking detection circuit needs to be designed. After detecting that the phase-locked loop is locked or basically locked, the control signals up0 and dn0 are connected to the switch control circuit to control the opening and closing of the switching loop filter. In addition, after the control signals UP and DN are boosted by the charge pump circuit CP, they are divided into two paths, one of which is connected to the ground through the capacitor C1, and the other is connected to the source S of the power switch SW. The gate of the power switch SW and the drain of the power switch SW are divided into four paths, the first of which is connected to the ground through the resistor R and the capacitor C2, the second of which is connected to the capacitor C2 through the capacitor C3, the third of which is connected to the multi-band voltage-controlled oscillator VCO, and the fourth of which is connected to the multi-band voltage-controlled oscillator VCO through the band switching circuit.

[0054] Among them, the multi-band voltage-controlled oscillator VCO adopts a ring oscillator structure, and the phase noise performance of the ring oscillator is poor. It is necessary to increase the loop bandwidth of the phase-locked loop to suppress the noise of the voltage-controlled oscillator. However, too wide a bandwidth will cause the reference spurious of the phase-locked loop to be large. Therefore, a switching loop filter SLPF is used to reduce the reference spurious of the phase-locked loop. At the same time, a low current mismatch charge pump structure is also used to reduce the jitter performance of the overall loop.

[0055] See also Figure 3 , Figure 3 (a) shows the connection between the charge pump and the switching loop filter. The output control signals UP and DN of the phase frequency detector PFD respectively control the direction of the charge and discharge current of the charge pump CP and connect the output current to the loop filter. When the rising edge of the control signals UP and DN arrives, due to non-ideal effects such as time mismatch, current mismatch, and clock feedthrough, a relatively large current is injected into the capacitor C1, causing a positive voltage spike to appear on the capacitor C1. When the falling edge of the control signals UP and DN arrives, a negative voltage spike is generated. After the pulse signals of the control signals UP and DN, a small amount of average charge exists on the capacitor C1 to adjust the output frequency of the phase-locked loop.

[0056] The existence of the power switch SW can isolate the voltage spikes. The power switch SW is disconnected during the high level period of the pulse signal of the control signal UP and DN. At this time, Vcont is in a floating state, and the voltage spike of V0 will not affect the control voltage of the voltage-controlled oscillator. After the short pulse signal of the control signal UP and DN has passed, the power switch SW is closed, and the charge on the capacitor C1 is shared with the loop filter to fine-tune the phase-locked loop.

[0057] Since the power switch SW is also implemented by a MOS tube, there is also a clock feedthrough effect, but the size of the power switch SW is smaller, the impact of charge injection and clock feedthrough is much smaller, and there is no current mismatch and time mismatch problem, so the control voltage Vcont of the multi-band voltage-controlled oscillator VCO after the power switch SW has much smaller fluctuation than V0.

[0058] See also Figure 4 , Figure 4 (a) shows a multi-band voltage-controlled oscillator circuit structure, which includes a bias circuit and a ring oscillator circuit. The bias circuit includes M1, the source of M1 is connected to the power supply VDD, the gate of M1 is connected to the bias potential Vb, the drain of M1 is divided into three paths, the first path is connected to the source of M2, the second path is grounded via a capacitor C, and the third path is connected to the control voltage Vcont of the ring oscillator. The gate of M2 is connected to the control voltage Vc, and the drain of M2 is connected to GND. The ring oscillator circuit includes a three-stage differential inverter module. Figure 4(b) shows the circuit structure of the delay unit in the voltage-controlled oscillator, in which the control voltage Vcout is connected to the substrate potential of M3 and M4, the power supply voltage VDD is connected to the source of M3, the source of M4, the source of M7, and the source of M8, the gate of M7 is connected to the gate of M3 and the gate of M5, and the drain of M7 is divided into five paths, the first path is connected to the drain of M3, the second path is connected to the source of M1, the third path is connected to the drain of M5, and the fourth path is connected to the load capacitor array. The other end of the capacitor is grounded via switch S, the fifth path is connected to the gate of M2, the gate of M8 is connected to the gate of M4 and the gate of M6, the drain of M8 is divided into five paths, the first path is connected to the drain of M4, the second path is connected to the source of M2, the third path is connected to the drain of M6, and the fourth path is connected to the load capacitor array. The other end of the load capacitor is also grounded via switch S, the fifth path is connected to the gate of M1, and the drain of M1, the drain of M2, the source of M5, and the source of M6 are connected to GND.

[0059] The phase noise of the multi-band voltage controlled oscillator (VCO) is reduced by widening the frequency band and reducing the size of Kvco, while the jitter of the overall phase-locked loop is reduced. Figure 4 (a) shows the schematic diagram of the multi-band voltage-controlled oscillator structure, which mainly adopts the three-stage inverter cascade method. Figure 1 The traditional voltage-controlled oscillator structure shown in FIG. 1 can reduce the disturbance of the output frequency when the phase-locked loop frequency is stable by reducing the gain Kvco of the voltage-controlled oscillator. In addition, the programmable capacitor array can not only widen the output frequency band of the phase-locked loop, but also achieve stable output of different frequencies through external control. The internal structure diagram of the delay unit is shown in FIG. Figure 4 As shown in (b), by changing the N-well bias voltage V of the PMOS tube sb The charging current of the delay unit is changed, and then the oscillation frequency is changed. The advantage is that the control tube will not be in the on state all the time, avoiding DC power consumption. The change of Vcont causes the change of the threshold voltage, and the threshold voltage changes the charging current of the delay unit, thereby changing the oscillator frequency.

[0060] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention described and shown in the drawings here can usually be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0061] See also Figure 5 , is the simulation result of the oscillator's frequency modulation curve. The frequency band is represented by a discrete voltage-frequency tuning curve. There are 48 discrete frequency modulation curves, i.e., 48 frequency bands, among which, Figure 5 (a) The figure shows the frequency bands 1 to 5. Figure 5 (b) is a frequency band of 44 to 48. To achieve continuous frequency modulation, there is a certain frequency overlap between each frequency band. The control voltage of the oscillator varies between 0.3 and 0.8 V, and the voltage-controlled gain varies between 50 and 120 MHz / V, which can meet the overall design requirements of the phase-locked loop.

[0062] See also Figure 6 , which represents the phase noise curves at different process angles and different temperatures. This simulation only considers the worst cases, namely the slowest case of the ss process angle at minus 40 degrees Celsius, the fastest case of the ff process angle at 100 degrees Celsius, and the typical case of the tt process angle at room temperature of 25 degrees Celsius. Figure 6 It can be seen that under three different PVT conditions, the phase noise at 1MHz frequency offset is basically maintained at -100dBC / Hz. It can be seen that the structure has a certain robustness to PVT changes.

[0063] The present invention proposes to use a multi-band voltage-controlled oscillator to realize a frequency-configurable phase-locked loop, and use a switch capacitor array to widen the output frequency band, thereby alleviating the error jitter caused by high Kvco. Since a programmable loop oscillator and a frequency divider are used, the interference change caused by PVT is also reduced to a certain extent. The present invention also uses a high power supply rejection ratio LDO to power the phase-locked loop, reducing the influence of power supply noise on the phase noise of the phase-locked loop. The frequency-allocatable phase-locked loop proposed by the present invention is designed and simulated under a standard CMOS process. When the frequency division ratio N=32, the output frequency of the phase-locked loop is 800MHz, at which time the phase noise at 10kHz is -96dBc / Hz, the phase noise at 1MHz is -100dBc / Hz, and the phase noise at 10MHz is -118dBc / Hz. The RMS jitter value is 4.5ps in the integration range of 1kHz to 100MHz.

[0064] See also Figure 7 , which is the RMS jitter simulation result of the structure proposed in the present invention at different output frequencies. The RMS jitter is inversely proportional to the output frequency. The overall phase-locked loop tuning range accounts for 49.2% of the highest output frequency, and the power consumption is 9.2mW. Compared with similar literature, while sacrificing part of the power consumption, the output frequency range is greatly widened, so that a single frequency is no longer output, which is convenient for responding to multiple needs. At the same time, the phase noise at 1MHz frequency deviation is reduced by 6-10dBc / Hz and the RMS jitter is reduced by 18.2%-62%.

[0065] In summary, the present invention is a frequency band phase-locked loop based on a programmable capacitor array, which utilizes a programmable capacitor array structure to improve the performance of the phase-locked loop circuit in resisting PVT changes and widens the output frequency range. It can be used in laser radar systems with various clock requirements and has better phase noise and RMS jitter.

[0066] The above contents are only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A frequency band phase-locked loop based on a programmable capacitor array, characterized in that: The invention comprises a phase detector circuit, which is connected to a charge pump circuit CP, a switch loop filter SLPF and a multi-band voltage-controlled oscillator circuit VCO in sequence, the multi-band voltage-controlled oscillator circuit VCO is connected to the phase detector circuit via a programmable frequency divider circuit, and the phase detector circuit is connected to the switch loop filter via a switch control circuit; The reference clock signals clk_ref and clk_div generate control signals UP and DN through the phase frequency detector PFD. The charge pump converts the received pulse difference signal into a current signal, which is then converted into a voltage signal through a loop filter to control the frequency change of the voltage-controlled oscillator. Discrete frequency modulation is achieved by changing the load capacitance, and the frequency output range is obtained by using a programmable capacitor array structure. The output is fed back to the phase frequency detector through a frequency divider to achieve loop locking. The switch loop filter SLPF includes a power switch SW, a source S of the power switch SW is divided into two paths, one path is connected to the charge pump circuit CP, and the other path is grounded via a capacitor C1; the gate of the power switch SW is connected to the switch control circuit; the drain of the power switch SW is divided into four paths, the first path is grounded via a resistor R and a capacitor C2, the second path is connected to the capacitor C2 via a capacitor C3, the third path is connected to a multi-band voltage-controlled oscillator circuit VCO, and the fourth path is connected to the multi-band voltage-controlled oscillator circuit VCO via a band switching circuit; The multi-band voltage-controlled oscillator circuit includes a bias circuit and a ring oscillator circuit. The bias circuit includes M1. The power supply VDD is connected to the source of M1. The gate of M1 is connected to the bias potential Vb. The drain of M1 is divided into three paths. The first path is connected to the source of M2. The second path is grounded through a capacitor C. The third path is connected to the control voltage Vcont of the ring oscillator. The gate of M2 is connected to the control voltage Vc. The drain of M2 is connected to GND. The ring oscillator circuit includes a three-stage differential inverter module. The control voltage Vcout is connected to the substrate potential of M3 and M4. The power supply voltage VDD is connected to the source of M3, the source of M4, the source of M7, and the source of M8. The gate of M7 is connected to the gate of M3. The gate of M8 is connected to the gate of M4 and the gate of M6. The drain of M8 is divided into five paths, the first path is connected to the drain of M3, the second path is connected to the source of M1, the third path is connected to the drain of M5, the fourth path is connected to the load capacitor array, and the other end of the load capacitor is grounded via switch S. The fifth path is connected to the gate of M2, and the gate of M8 is connected to the gate of M4 and the gate of M6. The drain of M8 is divided into five paths, the first path is connected to the drain of M4, the second path is connected to the source of M2, the third path is connected to the drain of M6, and the fourth path is connected to the load capacitor array. The other end of the load capacitor is grounded via switch S. The fifth path is connected to the gate of M1, and the drain of M1, the drain of M2, the source of M5, and the source of M6 are connected to GND.

2. The frequency band phase-locked loop based on a programmable capacitor array according to claim 1, characterized in that: The switch of the switching loop filter works when the phase-locked loop is in a locked state, and the switching loop filter is turned on after it is detected that the phase-locked loop is locked or substantially locked.

3. The frequency band phase locked loop based on programmable capacitor array according to claim 1, characterized in that: The power switch SW is a MOS tube.

4. The frequency band phase locked loop based on programmable capacitor array according to claim 1, characterized in that: The delay unit of the ring oscillator changes the charging current of the delay unit by changing the N-well bias voltage Vsb of the PMOS tube, thereby changing the oscillation frequency.

5. The frequency band phase-locked loop based on a programmable capacitor array according to claim 1 or 4, characterized in that: The multi-band voltage controlled oscillator VCO adopts a ring oscillator structure.

6. The frequency band phase locked loop based on programmable capacitor array according to claim 1, characterized in that: The control voltage of the multi-band voltage-controlled oscillator circuit VCO is 0.3~0.8V, and the voltage-controlled gain is 50~120MHz / V.

7. The frequency band phase locked loop based on programmable capacitor array according to claim 1, characterized in that: The multi-band voltage controlled oscillator circuit VCO is connected to an LDO with a high power supply rejection ratio to provide a low-noise power supply voltage VDD.

8. The frequency band phase locked loop based on programmable capacitor array according to claim 1, characterized in that: The frequency band phase-locked loop also includes a lock detection circuit and a frequency band switching circuit. One end of the lock detection circuit is connected to the reference clock signal and the feedback clock signal, and the other end is connected to the switch control circuit. One end of the frequency band switching circuit is connected to the loop filter circuit, and the other end is connected to the voltage-controlled oscillator circuit.

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