Method and apparatus for synchronizing time stamp counters

Abstract

A method and apparatus for synchronizing a timestamp counter (TSC) associated with a processor core in a computer system includes initializing a TSC associated with the processor core by synchronizing the TSC associated with the processor core with at least one other TSC in a TSC hierarchy. One or more processor cores are powered down. Upon power up of the one or more processor cores, the TSC associated with the processor core is synchronized with the at least one other TSC in the TSC hierarchy.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. nonprovisional patent application number 16 / 721,886, filed December 19, 2019, the contents of which are incorporated herein by reference. Background Technology

[0003] A major challenge in multi-core processor systems is keeping the timestamp counters (TSCs) synchronized across all the different cores that may be operating at different frequencies. This becomes increasingly difficult as the distance between cores and even sockets increases. Another challenge is maintaining TSC synchronization during power management events such as CC1, CC6, or other sleep states. In traditional designs, each core logic must be reprogrammed with a new TSC value when it wakes up from a clock stop or sleep state. Attached Figure Description

[0004] A more detailed understanding can be obtained from the following description, given by way of example in conjunction with the accompanying drawings:

[0005] Figure 1 It is a block diagram of an exemplary apparatus in which one or more features of this disclosure may be implemented;

[0006] Figure 2 It is a schematic diagram of an exemplary processor including multiple cores; and

[0007] Figure 3 This is a flowchart of an exemplary method for synchronizing a timestamp counter. Detailed Implementation

[0008] While the methods and apparatus will be developed in greater detail below, a brief description of the use of time stamp counters (TSCs) and synchronization as an important aspect of computer systems is included here. In computer systems, it is sometimes useful to use the concept of a global time stamp (GT). The GT is a continuously incrementing value that is common to all processor threads and can be used to indicate the order in which global events completed. This GT can be used by individual processor threads to coordinate activities and indicate the correct order. This mechanism is often used in distributed database systems to determine whether to continue processing a multi-step transaction or whether a multi-step transaction needs to be rescheduled due to a change in a dependent transaction that was scheduled using a GT that was newer than the GT of the transaction that is trying to complete. There are software mechanisms that can be used to implement a global time stamp counter (GTC), but these mechanisms typically involve semaphore transactions on shared variables and tend to be very slow due to the communication overhead and conflict resolution of many processes trying to update a single shared location. Instead, processors implement a time stamp counter (TSC) that is local to each physical processor in order to quickly access and synchronize with all other TSCs so that globally all processes will see the same value at approximately the same time period, avoiding the overhead of maintaining a software GTC. In order to use this mechanism, all local TSCs must always be synchronized with each other regardless of power management events.

[0009] A method for synchronizing a time stamp counter (TSC) associated with a processor core in a computer system includes initializing the TSC associated with the processor core by synchronizing the TSC associated with the processor core with at least one other TSC in a TSC hierarchy. One or more processor cores are powered down. Upon power up of the one or more processor cores, the TSC associated with the processor core is synchronized with the at least one other TSC in the TSC hierarchy.

[0010] An apparatus for synchronizing a time stamp counter (TSC) in a computer system includes a processor die including a plurality of processor cores, a first TSC associated with a processor core of the plurality of processor cores, and a second TSC in a TSC hierarchy in communication with the first TSC. The first TSC is initialized by synchronizing the first TSC with the second TSC. Upon power up of one or more processor cores after a power down, the first TSC associated with the processor core is synchronized with the second TSC in the TSC hierarchy.

[0011] A non-transitory computer-readable medium for synchronizing a timestamp counter (TSC) associated with a processor core in a computer system has instructions recorded thereon that, when executed by a processor, cause the processor to perform operations. The operations include initializing a TSC associated with a processor core by synchronizing the TSC associated with the processor core with at least one other TSC in a TSC hierarchy, powering down one or more processor cores, and synchronizing the TSC associated with the processor core with the at least one other TSC in the TSC hierarchy upon powering up the one or more processor cores.

[0012] Figure 1 is a block diagram of an example device 100 in which one or more features of the present disclosure can be implemented. The device 100 can include, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. The device 100 includes a processor 102, a memory 104, a storage 106, one or more input devices 108, and one or more output devices 110. The device 100 can also optionally include an input driver 112 and an output driver 114. In addition, the device 100 includes a memory controller 115 that is in communication with the processor 102 and the memory 104, and can also be in communication with external memory 116. It is understood that the device 100 can include additional components not shown in FIG. 1 that serve the same or a similar purpose as the components described herein. Figure 1 In various alternatives, the processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and GPU located on the same die, or one or more processor cores, where each processor core can be a CPU or GPU. In various alternatives, the memory 104 is located on the same die as the processor 102, or is located separately from the processor 102. The memory 104 includes volatile or non-volatile memory, such as random access memory (RAM), dynamic RAM, or a cache.

[0013] In various alternatives, the processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and GPU located on the same die, or one or more processor cores, where each processor core can be a CPU or GPU. In various alternatives, the memory 104 is located on the same die as the processor 102, or is located separately from the processor 102. The memory 104 includes volatile or non-volatile memory, such as random access memory (RAM), dynamic RAM, or a cache.

[0014] The storage 106 includes a fixed or removable storage, such as a hard disk drive, a solid state drive, an optical disk, or a flash drive. The input devices 108 include, without limitation, a keyboard, a keypad, a touchscreen, a touchpad, a detector, a microphone, an accelerometer, a gyroscope, a biometric scanner, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals). The output devices 110 include, without limitation, a display, a speaker, a printer, a haptic feedback device, one or more lights, an antenna, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals).

[0015] Input driver 112 is in communication with processor 102 and input device 108, and allows processor 102 to receive input from input device 108. Output driver 114 is in communication with processor 102 and output device 110, and allows processor 102 to send output to output device 110. Note that input driver 112 and output driver 114 are optional components, and that device 100 will operate in the same manner if input driver 112 and output driver 114 are absent.

[0016] External memory 116 can be similar to memory 104, and can exist in the form of off-chip memory. Additionally, external memory can be memory resident in a server, where memory controller 115 communicates over a network interface to access memory 116.

[0017] Figure 2 is a schematic diagram of an exemplary processor that includes multiple cores. In Figure 2 In the example shown, processor 102 of device 100 is depicted as having multiple cores 122 (labeled 1221, 1222, 1223, 1224, 1225, and 1226). Processor 102 includes TSC 1230, which is part of the hierarchy of TSCs 123 and is in communication with master TSC 123 T In addition, each core 122 includes a TSC 123 (labeled 1231, 1232, 1233, 1234, 1235, and 1236), respectively. As described above, each TSC 123 is synchronized with all other TSCs.

[0018] The "allow TSC update" and "add TSC offset" steps described herein are depicted as occurring in sequence; however, these steps can be completed in any order. Both need to be completed before indicating that the TSCs have synchronized. In some embodiments, one order is used, while in other embodiments, a different order is used. The choice of order can depend on the logic of communicating the "TSC offset." When the physical distance that the "TSC offset" needs to be transmitted is small, it is transmitted on a dedicated line, so the offset is added after the TSC update starts. When the physical distance that the "TSC offset" needs to be transmitted is large, the "TSC offset" can piggyback on the "TSC update" signal and be transmitted serially to the TSCs. In this case, the TSC update is delayed by a sufficient number of TSC cycles to allow the "TSC offset" to be transmitted before the first TSC update pulse is sent.

[0019] Figure 3 is a flowchart of an exemplary method 300 of synchronizing timestamp counters, such as TSCs 123.

[0020] At step 310, the TSC is reset (initialized). At this point, TSC updates are disabled and a TSC offset value is stored for the next TSC update (step 320). Thus, during a power management event, the TSC 123 associated with the core 122 is in a power-on-synchronized state.

[0021] Once the power-on cycle begins, TSC updates are again enabled for the TSC 123 (step 330). At this point, the stored offset value is added to the counter (step 340), thereby synchronizing the TSC 123 (step 350).

[0022] To perform the above-described method 300, there is a hierarchy of TSC counters that perform this sequence. At the top level, there is a master TSC counter (TSC T ) that is always on and always incremented with the TSC clock (not shown). The next level (e.g., a die-level TSC - TSC 1230 on the processor 102) is synchronized with the master TSC T to get a reference for each die. From there, each TSC 123 associated with a core 122 is synchronized with the die-level TSC to get its offset from the TSC to the die-level counter. Thus, each branch of the tree (e.g., a core 122) can be powered off individually, and the method repeated as needed to resynchronize all TSCs on that branch, starting with the highest TSC and working down.

[0023] The provided methods can be implemented in a general purpose computer, a processor, or a processor core. Suitable processors include, by way of example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a plurality of microprocessors, one or more microprocessors in association with a DSP core, a controller, a microcontroller, Application Specific Integrated Circuits (ASICs), Field Programmable Gate Array (FPGAs) circuits, any other type of integrated circuit (IC), and / or a state machine. Such processors can be made of a processed hardware description language (HDL) instructions and other intermediate data including netlists (which can be stored on a computer readable medium) can be used to configure a manufacturing process to fabricate the processors. The results of the processing can be a mask work product, and then used in the semiconductor fabrication process to manufacture the processors that implement the various features of the present disclosure. Furthermore, although the above methods and apparatus are described in the context of controlling and configuring PCIe links and ports, these methods and apparatus can be used in any interconnect protocol that negotiates link width.

[0024] The methods or flow charts provided herein can be implemented in computer programs, software, or firmware incorporated in non-transitory computer readable storage media for execution by a general purpose computer or a processor. Examples of non-transitory computer-readable storage media include a read-only memory (ROM), a random access memory (RAM), a register, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks, and digital versatile disks (DVDs). For example, the methods described above can be implemented in the processor 102 or on any other processor in the computer system 100.

[0025] ***

Claims

1. A method for synchronizing a timestamp counter (TSC) associated with a first processor core in a computer system, comprising: initializing a first TSC associated with the first processor core by synchronizing the first TSC associated with the first processor core with at least a second TSC associated with a second processor core in a TSC hierarchy, wherein the hierarchy of TSCs comprises a die-level TSC coupled to at least the second TSC and a master TSC coupled to the die-level TSC; powering down one or more processor cores including the first processor core; and synchronizing the first TSC associated with the first processor core with at least the second TSC in the TSC hierarchy upon powering up the one or more processor cores including the first processor core.

2. The method of claim 1, further comprising disabling updates to the first TSC upon powering down the first processor core.

3. The method of claim 2, further comprising storing a TSC offset value upon powering down the first processor core.

4. The method of claim 3, further comprising enabling updates to the first TSC upon powering up the first processor core.

5. The method of claim 4, further comprising adding the TSC offset value to the first TSC associated with the first processor core to synchronize the first TSC with at least the second TSC in the TSC hierarchy upon powering up the first processor core.

6. The method of claim 5, further comprising delaying updates to the first TSC until the TSC offset value is added.

7. The method of claim 1, wherein at least the second TSC in the TSC hierarchy is the die-level TSC in communication with a plurality of TSCs each associated with a plurality of processor cores.

8. The method of claim 7, wherein the die-level TSC is in communication with the master TSC that is always powered up.

9. The method of claim 8, wherein the die-level TSC receives a TSC offset value from the master TSC and communicates the TSC offset value to the TSCs associated with the plurality of processor cores.

10. An apparatus for synchronizing a timestamp counter (TSC) in a computer system, comprising: a processor die including a plurality of processor cores; a first TSC associated with a first processor core of the plurality of processor cores; and a second TSC in a TSC hierarchy in communication with the first TSC and associated with a second processor core, wherein the hierarchy of TSCs comprises a die-level TSC coupled to at least the second TSC and a master TSC coupled to the die-level TSC, wherein the first TSC is initialized by synchronizing the first TSC with the second TSC. ​ synchronizing the first TSC associated with the first processor core with at least the second TSC in the TSC hierarchy when one or more processor cores, including the first processor core, of the plurality of processor cores are powered up after a power down.

11. The apparatus of claim 10, wherein updates to the first TSC associated with the first processor core are disabled at power down.

12. The apparatus of claim 11, wherein a TSC offset value is stored when the first processor core is powered down.

13. The apparatus of claim 12, wherein updates to the first TSC are enabled at power up.

14. The apparatus of claim 13, wherein the TSC offset value is added to the first TSC associated with the first processor core at power up to synchronize the first TSC with at least the second TSC in the TSC hierarchy.

15. The apparatus of claim 14, wherein updates to the first TSC are delayed until the TSC offset value is added.

16. The apparatus of claim 15, wherein the second TSC in the TSC hierarchy is the die-level TSC in communication with the first TSC and a plurality of TSCs each associated with the plurality of processor cores.

17. The apparatus of claim 16, further comprising the master TSC in communication with the die-level TSC.

18. The apparatus of claim 17, wherein the master TSC is always powered up.

19. The apparatus of claim 18, wherein the die-level TSC receives the TSC offset value from the master TSC and communicates the TSC offset value to the first TSC and the TSCs associated with the plurality of processor cores.

20. A non-transitory computer-readable medium for synchronizing a timestamp counter (TSC) associated with a first processor core in a computer system, the non-transitory computer-readable medium having instructions recorded thereon, which when executed by a processor, cause the processor to perform operations comprising: initializing a first TSC associated with the first processor core by synchronizing the first TSC associated with the first processor core with at least a second TSC associated with a second processor core in a TSC hierarchy, wherein the hierarchy of TSCs includes a die-level TSC coupled to at least the second TSC and a master TSC coupled to the die-level TSC; powering down one or more processor cores, including the first processor core; and synchronizing the first TSC associated with the first processor core with at least the second TSC in the TSC hierarchy when the one or more processor cores, including the first processor core, are powered up.

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