Three-dimensional NAND gate stack reinforcement

Abstract

An example method of forming a semiconductor structure can include forming a first silicon oxide layer covering a semiconductor substrate. The method can include forming a first silicon layer covering the first silicon oxide layer. The method can include forming a silicon nitride layer covering the first silicon layer. The method can include forming a second silicon layer covering the silicon nitride layer. The method can include forming a second silicon oxide layer covering the second silicon layer. The method can include removing the silicon nitride layer. The method can include removing the first silicon layer and the second silicon layer. The method can include forming a metal layer between and contacting each of the first silicon oxide layer and the second silicon oxide layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority to U.S. Patent Application No. 62 / 932,861, filed November 8, 2019, the contents of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] This technology relates to semiconductor processes and materials. More specifically, this technology relates to methods for forming enhanced semiconductor structures. Background Technology

[0004] Integrated circuits are fabricated by creating complex patterned material layers on a substrate surface. Creating patterned material on a substrate requires controlled methods for exposing and removing the material. Stacked memories, such as vertical or 3D NAND, may comprise the formation of a series of alternating layers of dielectric material, with several memory vias or apertures etched through these alternating layers. The material properties of the layers, as well as the process conditions and materials used for etching, can affect the consistency and integrity of the resulting structure. As devices continue to shrink, conventional techniques are no longer adequate.

[0005] Therefore, there is a need for improved systems and methods to produce high-quality devices and structures. This technology addresses these and other needs. Summary of the Invention

[0006] Exemplary methods for forming a semiconductor structure may include forming a first silicon oxide layer covering a semiconductor substrate. This method may include forming a first silicon layer covering the first silicon oxide layer. This method may include forming a silicon nitride layer covering the first silicon layer. This method may include forming a second silicon layer covering the silicon nitride layer. This method may include forming a second silicon oxide layer covering the second silicon layer. This method may include removing the silicon nitride layer. This method may include removing the first and second silicon layers. This method may include a metal layer formed between and in contact with each of the first and second silicon oxide layers.

[0007] In some embodiments, the silicon nitride layer can be removed by a wet etching process. The first and second silicon layers can be removed by a dry etching process. The second silicon layer and the second silicon oxide layer can form a composite film characterized by a Young's modulus greater than 90 GPa or about 90 GPa. The metal layer can be tungsten or include tungsten. This method may include forming a pad layer along the first and second silicon oxide layers after removing the first and second silicon layers. The formation of the first silicon oxide layer may occur in a first processing chamber, while the removal of the first and second silicon layers may occur in a second processing chamber. This method may include transferring the semiconductor substrate from the first processing chamber to the second processing chamber while maintaining a vacuum. The first and second silicon oxide layers may be characterized by a thickness of less than 50 nm or about 50 nm.

[0008] Some embodiments of this technology may cover methods for forming semiconductor structures. This method may include forming a first silicon oxide layer covering a semiconductor substrate. This method may include forming a first amorphous silicon layer covering the first silicon oxide layer. This method may include forming a silicon nitride layer covering the first amorphous silicon layer. This method may include forming a second amorphous silicon layer covering the silicon nitride layer. This method may include forming a second silicon oxide layer covering the second amorphous silicon layer. This method may include removing the silicon nitride layer. This method may also include converting the first and second amorphous silicon layers into metallic materials that are in contact with the first and second silicon oxide layers, respectively.

[0009] In some embodiments, this conversion may include flowing a metal-containing precursor to contact the first and second amorphous silicon layers. This method may include forming volatile silicon-containing byproducts simultaneously with the formation of the metal material layer. This method may include forming a metal material layer extending between the first and second silicon oxide layers. The silicon nitride layer may be removed by a wet etching process. The first and second amorphous silicon layers may be characterized by a thickness of less than about 5 nm or about 5 nm.

[0010] Some embodiments of this technology may cover methods for forming semiconductor structures. This method may include forming a first silicon oxide layer covering a semiconductor substrate. The first silicon oxide layer may include a nitrogen dopant or be silicon-rich stoichiometry. This method may include forming a silicon nitride layer covering the first silicon oxide layer. This method may include forming a second silicon oxide layer covering the silicon nitride layer. The second silicon oxide layer may include a nitrogen dopant or be silicon-rich stoichiometry. This method may include removing the silicon nitride layer. This method may include processing the first silicon oxide layer and the second silicon oxide layer.

[0011] In some embodiments, this process may include performing vapor annealing. The first silicon oxide layer may include a nitrogen dopant incorporated at a nitrogen concentration of less than 5% or about 5%. The first silicon oxide layer may be characterized by a Young's modulus greater than or about 110 GPa. The first silicon oxide layer may be characterized by an oxygen-to-silicon stoichiometry ratio of less than or about 1.8:1. The first silicon oxide layer may be characterized by a Young's modulus greater than or about 130 GPa. After this process, the first and second silicon oxide layers may be characterized by a breakdown voltage greater than or about 9 MV / cm.

[0012] This technology offers numerous benefits compared to conventional systems and techniques. For example, this process can produce a film with improved resistance to deformation during removal operations. Furthermore, embodiments of this technology can produce a film protected from thinning during removal operations. These and other embodiments, along with their many advantages and features, are described in more detail below in conjunction with the description and accompanying drawings. Attached Figure Description

[0013] A further understanding of the nature and advantages of the disclosed technology can be achieved by referring to the remainder of this specification and the accompanying drawings.

[0014] Figure 1 A top plan view of one embodiment of an exemplary processing system according to some embodiments of the present technology is shown.

[0015] Figure 2A A schematic cross-sectional view of an exemplary processing chamber according to some embodiments of the present technology is shown.

[0016] Figure 2B A schematic cross-sectional view of an exemplary processing chamber according to some embodiments of the present technology is shown.

[0017] Figure 3 Exemplary operations in a method for forming a semiconductor structure according to some embodiments of the present technology are shown.

[0018] Figures 4A to 4D A schematic cross-sectional view of a substrate during a forming operation is shown, according to some embodiments of the present technology.

[0019] Figure 5 Exemplary operations in a method for forming a semiconductor structure according to some embodiments of the present technology are shown.

[0020] Figures 6A to 6D A schematic cross-sectional view of a substrate during a forming operation is shown, according to some embodiments of the present technology.

[0021] Figure 7 Exemplary operations in a method for forming a semiconductor structure according to some embodiments of the present technology are shown.

[0022] Figures 8A to 8D A schematic cross-sectional view of a substrate during a forming operation is shown, according to some embodiments of the present technology.

[0023] Several figures in the accompanying drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and are not to be construed as being to scale unless expressly stated otherwise. Furthermore, as schematic diagrams, the drawings are provided to aid understanding and may not include all aspects or information compared to actual representations, and may include exaggerated material for illustrative purposes.

[0024] In the accompanying drawings, similar parts and / or features may have the same reference numerals. Furthermore, various parts of the same type may be distinguished by text following the reference numerals to differentiate them. If only primary reference numerals are used in the specification, this description applies to any of the similar parts that have the same primary reference numerals, regardless of the text. Detailed Implementation

[0025] In the transition from 2D NAND to 3D NAND, many process operations have been modified from vertical to horizontal. During 3D NAND processing, the stacking of placeholder layers and dielectric materials can form inter-electrode dielectric layers or inter-poly dielectric (“IPD”) layers. These placeholder layers can perform various operations to place structures before completely removing and replacing the material with metal. As memory devices continue to shrink in size and more cells develop on each stack, the dielectric and placeholder layers continue to shrink in thickness. When memory vias are formed, the vias can extend through all the alternating layers of material before reaching the underlying substrate. Subsequent processing can form stepped structures for contacts and can also laterally excavate the placeholder material and form conductive material within the recesses.

[0026] Many techniques utilize wet etching to move in and out of each of the cell occupant materials to perform lateral etch of the occupants. For example, in many oxide-nitride stacks, nitrides can be removed by wet etching, which may include a thermal phosphoric acid treatment that is selective for nitrides compared to oxides. However, wet etching of small shape factor structures can cause pattern collapse or deformation due to the surface tension of the etchant, such as in subsequent drying processes. The oxide layer may be characterized by reduced rigidity or resistance to surface tension effects, which can cause the dielectric material to deform during the etching process. Depending on the required structural aspects and removal, thinning of the dielectric material layer may also occur during occupant removal.

[0027] This technology overcomes these problems by creating a structure-reinforced dielectric layer that better withstands the effects of wet etching processes. Furthermore, aspects of this technology can advantageously improve metal filling. Following the description of an example system that can be configured to implement aspects of this technology, several example methods and materials will be described.

[0028] While the remainder of the disclosure will routinely specify the specific deposition and removal processes used to produce particular structures (such as those for memory), it will be readily understood that the systems and methods are equally applicable to several other processes and semiconductor structures. Therefore, this technology should not be construed as being so limited to the described deposition and etching processes or chambers alone. Furthermore, while exemplary chambers and systems are described herein to provide the basis for this technology, it will be understood that the present invention is applicable to any semiconductor processing chamber or system that can actually accommodate the processing operations described herein.

[0029] Figure 1 A top plan view of one embodiment of a processing system 100 comprising deposition, etching, annealing, or other processing chambers according to an embodiment is shown. In the figures, a pair of front-opening standard chambers 102 provide substrates of various sizes, which are received by a robotic arm 104 and placed into a low-pressure holding region 106 before being placed into one of the substrate processing chambers 108a-f located in tandem segments 109a-109c. A second robotic arm 110 is available to transfer substrate wafers from the holding region 106 to and from the substrate processing chambers 108a-f. Each of the substrate processing chambers 108a-f can be equipped to perform several substrate processing operations, including the deposition processes described herein, as well as dry etching processes, removal processes, atomic layer deposition, chemical vapor deposition, physical vapor deposition, general etching, pre-cleaning, degassing, orientation, and other substrate processes.

[0030] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching dielectric films on a substrate wafer. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be specifically configured to deposit dielectric material on the substrate as described later, and a third pair of processing chambers (e.g., 108a-b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to deposit dielectric films on the substrate. Any or more of these processes may be performed in one or more chambers separate from the processing systems shown in the different embodiments. It will be understood that additional configurations of the chambers for the deposition, etching, annealing, and curing of dielectric films are taken into account through system 100.

[0031] Figure 2 shows a cross-sectional view of an example processing chamber 200 according to some embodiments of the present technology. This figure may illustrate an overview of a system incorporating one or more aspects of the present technology, and / or the system may also be specifically configured to perform one or more operations according to embodiments of the present technology. Additional details of the chamber 200 or the methods performed in this specifically configured chamber will be described later. The chamber 200 may be used to form a film layer according to some embodiments of the present technology; however, it will be understood that this method can be similarly performed in any chamber in which film formation may occur. The processing chamber 200 may include a chamber body 202, a substrate support 204 disposed within the chamber body 202, and a cover assembly 206 coupled to the chamber body 202 and surrounding the substrate support 204 in a processing volume 220. A substrate 203 may be provided to the processing volume 220 through an opening 226, which may be conventionally sealed for processing using a slit valve or door. The substrate 203 may rest on the surface 205 of the substrate support during processing. The substrate support 204 is rotatable along axis 247, as indicated by arrow 245, and the shaft 244 of the substrate support 204 may be located on axis 247. Alternatively, if necessary, the substrate support 204 may be lifted for rotation during the deposition process.

[0032] Plasma profile modulator 211 may be disposed in processing chamber 200 to control plasma distribution across substrate 203 disposed on substrate support 204. Plasma profile modulator 211 may include a first electrode 208 disposed adjacent to chamber body 202 and separating chamber body 202 from other components of cover assembly 206. First electrode 208 may be part of cover assembly 206 or may be a separate sidewall electrode. First electrode 208 may be annular or ring-like member and may be a ring electrode. First electrode 208 may be a continuous member surrounding the processing chamber 200 surrounding processing volume 220, or may be discontinuous at selected locations if desired. First electrode 208 may also be a perforated electrode, such as a perforated ring or grid electrode, or may be a plate electrode, such as an auxiliary gas distributor.

[0033] One or more isolators 210a, 210b (which may be dielectric materials such as ceramics or metal oxides, e.g., alumina and / or aluminum nitride)) may contact the first electrode 208 and electrically and thermally isolate the first electrode 208 from the gas distributor 212 and from the chamber body 202. The gas distributor 212 may define an orifice 218 for distributing the processing precursor into the processing volume 220. The gas distributor 212 may be coupled to a first source of electrical power 242, such as an RF generator, RF power source, DC power source, pulsed DC power source, pulsed RF power source, or any other power source that may be coupled to the processing chamber. In some embodiments, the first source of electrical power 242 may be an RF power source. In some embodiments, the first source of electrical power 242 may also be an inductively coupled plasma coil extending around the inlet 214, which may be used to generate or deliver plasma effluent into the processing volume 220.

[0034] The gas distributor 212 can be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 212 can also be formed from conductive and non-conductive components. For example, the body of the gas distributor 212 can be conductive, while the panel of the gas distributor 212 can be non-conductive. The gas distributor 212 can be powered by a first power source 242, such as the one shown in FIG. 2, or in some embodiments, the gas distributor 212 can be grounded.

[0035] The first electrode 208 may be coupled to a first tuning circuit 228, which controls the grounding path of the processing chamber 200. The first tuning circuit 228 may include a first electronic sensor 230 and a first electronic controller 234. The first electronic controller 234 may be or include a variable capacitor or other circuit elements. The first tuning circuit 228 may be or include one or more inductors 232. The first tuning circuit 228 may be any circuit that allows for a variable or controllable impedance under plasma conditions present in the processing volume 220 during processing. In some embodiments as shown, the first tuning circuit 228 may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 230. The first circuit leg may include a first inductor 232a. The second circuit leg may include a second inductor 232b coupled in series with the first electronic controller 234. The second inductor 232b may be disposed between the first electronic controller 234 and the node connecting both the first circuit branch and the second circuit branch to the first electronic sensor 230. The first electronic sensor 230 may be a voltage sensor or a current sensor and may be coupled to the first electronic controller 234, which may provide a degree of closed-loop control over the plasma conditions within the processing volume 220.

[0036] The second electrode 222 may be coupled to the substrate support 204. The second electrode 222 may be embedded within the substrate support 204 or coupled to the surface of the substrate support 204. The second electrode 222 may be a plate, perforated plate, mesh, wire screen, or any other arrangement of conductive material. The second electrode 222 may be a tuning electrode and may be coupled to the second tuning circuit 236 via a conduit 246, for example, a cable having a selected resistance such as 50 ohms disposed in a shaft 244 of the substrate support 204. The second tuning circuit 236 may have a second electronic sensor 238 and a second electronic controller 240, the second electronic controller 240 being a second variable capacitor. The second electronic sensor 238 may be a voltage sensor or a current sensor and may be coupled to the second electronic controller 240 to provide further control over the plasma conditions in the processing volume 220.

[0037] A third electrode 224, which may be a bias electrode and / or an electrostatic clamping electrode, may be coupled to a substrate support 204. The third electrode may be coupled to a second source of electrical power 250 via a filter 248, which may be an impedance matching circuit. The second source of electrical power 250 may be DC power, pulsed DC power, RF bias power, a pulsed RF source, or bias power, or a combination of these or other power sources. In some embodiments, the second source of electrical power 250 may be RF bias power.

[0038] Figure 1 The cover assembly 206 and substrate support assembly 204 can be used in any processing chamber for plasma or thermal processing. In operation, the processing chamber 200 can provide real-time control of the plasma conditions within the processing volume 220. A substrate 203 can be disposed on the substrate support 204, and process gases can flow through the cover assembly 206 via inlet 214 according to any desired flow pattern. Gases exit the processing chamber 200 via outlet 252, which can be coupled to a pump, such as any exhaust pump, including, in some embodiments, a turbomolecular pump. Electrical power can be coupled to a gas distributor 212 to establish plasma in the processing volume 220. In some embodiments, a third electrode 224 can be used to subject the substrate to an electrical bias.

[0039] When the plasma is energized in processing volume 220, a potential difference can be established between the plasma and the first electrode 208. A potential difference can also be established between the plasma and the second electrode 222. Electronic controllers 234 and 240 can then be used to adjust the flow properties of the ground path represented by two tuning circuits 228 and 236. Setpoints can be delivered to the first tuning circuit 228 and the second tuning circuit 236 to provide independent control over the deposition rate and plasma density consistency from center to edge. In embodiments where the electronic controllers are both variable capacitors, electronic sensors can adjust the variable capacitors to independently maximize the deposition rate and minimize thickness inconsistencies.

[0040] Each of the tuning circuits 228 and 236 may have a variable impedance, which can be adjusted using separate electronic controllers 234 and 240. When the electronic controllers 234 and 240 are variable capacitors, the capacitance range of each of the variable capacitors, and the inductance of the first inductor 232a and the second inductor 232b, can be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, and may have a minimum value within the capacitance range of each variable capacitor. Therefore, when the capacitance of the first electronic controller 234 is at its minimum or maximum value, the impedance of the first tuning circuit 228 will be high, resulting in a plasma shape with minimal air coverage or lateral coverage over the substrate support. When the capacitance of the first electronic controller 234 approaches the value that minimizes the impedance of the first tuning circuit 228, the air coverage of the plasma grows to its maximum value, effectively covering the entire working area of ​​the substrate support 204. When the capacitance of the first electronic controller 234 deviates from the minimum impedance setting, the plasma shape shrinks from the chamber wall and the air coverage of the substrate support decreases. The second electronic controller 240 can have a similar effect, as the capacitance of the second electronic controller 240 can be changed to increase or decrease the air coverage of the plasma above the substrate support.

[0041] Electronic sensors 230 and 238 can be used to tune individual circuits 228 and 236 in a closed loop. Setpoints for current or voltage, depending on the type of sensor used, can be installed in each sensor, and the sensors can be provided with software that determines the adjustment of each individual electronic controller 234 and 240 to minimize deviations from the setpoint. Therefore, the plasma shape can be selected and dynamically controlled during processing. It will be understood that although the foregoing discussion is based on electronic controllers 234 and 240 that can be variable capacitors, any electronic component with adjustable characteristics can be used to provide tuning circuits 228 and 236 with adjustable impedance.

[0042] Figure 2BThis is a schematic cross-sectional view of a plasma chamber 260 according to some embodiments of the present technology. The figures may illustrate an overview of a system incorporating one or more aspects of the present technology, and / or a system that may be specifically configured to perform one or more operations according to embodiments of the present technology, such as utilizing an inductively coupled plasma source. However, when utilizing a chamber incorporating an inductively coupled plasma, additional plasma parameters can be controlled, which may affect the resulting membrane. For example, the chamber may be supplied with a lower processing pressure, which may affect membrane formation and properties. The plasma chamber 260 may include a chamber body 262 and a cover assembly 264 that may be coupled to the chamber body. The cover assembly 264 may include a precursor delivery assembly 266 and a cover 268. The cover 268 may define an orifice or opening 270 that may provide entry and exit of one or more processing precursor gases within the processing chamber.

[0043] A precursor delivery assembly 266 may be disposed on a cover 268 and extend through an opening 270. The precursor delivery assembly 266 may be coupled to a precursor source 272, which may provide precursor through the opening 274 to supply one or more processing precursors into a substrate processing region 275. A substrate 276 may be disposed on a substrate support 278, which is positioned within or extends into the substrate processing region 275 and coupled to a bias power source or other materials or electronic components. One or more processing precursor gases may exit the substrate processing region 275 via an exhaust ring 280, which may be coupled to an exhaust pump 282. In some embodiments, pump 282 may be a turbomolecular pump that can tolerate operating pressures below 1 tor or about 1 tor, below 500 mtor or about 500 mtor, below 100 mtor or about 100 mtor, below 50 mtor or about 50 mtor, below 20 mtor or about 20 mtor, below 5 mtor or about 5 mtor, or lower.

[0044] One or more coils may be coupled to the cover assembly 264 for energizing the precursor to generate a plasma effluent. The coils may include several coil groups, such as an inner coil 284, a middle coil 286, and an outer coil 288, all of which may be disposed adjacent to the cover 268 and extend around the opening 270. The inner coil 284 and the outer coil 288 may be electrically coupled to an RF power source 290 via a matching circuit 292. Power applied from the RF power source 290 to the outer coil 446 may be inductively coupled through the cover 268 to generate plasma from the processed precursor provided by the precursor source 272 within the substrate processing region 275. The RF power source 290 may provide several currents of different frequencies to control the plasma density, such as the number of ions per unit volume in the plasma, which may define the density of the ion flux corresponding to the plasma density over time. A bias power source may control the voltage between the substrate 276 and the generated plasma, and may thus control the energy and directionality of the ions, such as directing them toward the substrate. Therefore, the plasma chamber 260 can independently control both the ion flux and the ion energy.

[0045] Heater assembly 294 may be positioned adjacent to cover 268, and in some embodiments may be positioned between cover and coil as illustrated. Heater assembly 294 may be secured to cover 408 using clamping member 296. The surface of the substrate may be maintained in a temperature range that may extend between about 100°C and about 500°C or greater. Plasma chamber 260 may be used in any number of embodiments to produce the film described further later.

[0046] Figure 3 Exemplary operations in a processing method 300 according to some embodiments of the present technology are illustrated. This method can be performed in various processing chambers, including, for example, the processing chamber 200 described above, which can be incorporated into system 100. Method 300 may include several optional operations, which may or may not be specific to some embodiments of the method according to the present technology. For example, many operations are described to provide a broader range of structure formation, but are not critical to the present technology, or may be performed by alternative methods that would be readily understood. Method 300 may be illustrated schematically as shown in the illustration. Figures 4A to 4D The operation in the middle, Figures 4A to 4D The illustrations will be explained in conjunction with the operation of method 300. It will be understood that the figures show only partial schematic views, and the substrate may contain any number of structural sections having aspects shown in the figures as well as alternative structural aspects that may still benefit from the operation of this technology.

[0047] Prior to the commencement of the listed operations, method 300 may include additional operations. For example, additional processing operations may include forming a structure on a semiconductor substrate, which may include both forming and removing material. The prior processing operations may be performed in the chamber in which method 300 is performed, or may be performed in one or more other processing chambers prior to delivering the substrate into the chamber in which method 300 is performed. In any case, method 300 may optionally include a processing area for delivering the semiconductor substrate to a semiconductor processing chamber (such as processing chamber 200 described above or other chambers that may include the aforementioned components). The substrate may be positioned on a substrate support (such as substrate support 204), which may be a stage, and may be seated within a processing area of ​​the chamber (such as processing volume 220 described above). An exemplary substrate 405 is shown in… Figure 4A In, and may be an aspect of a substrate on which operations according to the present technology can be performed.

[0048] The substrate 405 may be any number of materials on which material can be deposited. The substrate may be or include silicon, germanium, dielectric materials including silicon oxide or silicon nitride, metallic materials, or any combination of these materials, which may be the substrate 405 or materials formed on the substrate 405. In some embodiments, optional processing operations such as pretreatment may be performed to prepare the surface of the substrate 405 for deposition. Additionally, material removal, such as reducing native oxide or etching material, or any other operations may be performed to prepare one or more exposed surfaces of the substrate 405 for deposition.

[0049] Method 300 may include forming a first silicon oxide layer covering the substrate in operation 305, such as Figure 4A Layer 407 is shown in the diagram. This formation can be performed using silicon-containing precursors and / or oxygen-containing precursors. While some conventional techniques may include forming a nitride layer covering the oxide, in some embodiments, during operation 310, a first silicon layer may be formed covering a first silicon oxide layer. Figure 4A As shown, layer 409 may be formed over the oxide layer. The silicon layer may include any number of silicon or silicon-containing materials, and in some embodiments may be or include amorphous silicon. The silicon layer may be formed from a silicon precursor. This method may include forming a silicon nitride layer over the silicon layer in operation 315. This formation may be performed using both silicon-containing and nitrogen-containing precursors. The nitride layer 411 may extend across the silicon layer and may be separated from the oxide layer by silicon layer 409. Each of the oxide layer, silicon layer, and nitride layer may be formed in the same chamber or in different chambers on the same tool. In some embodiments, each of the layers may be formed in a plasma-enhanced chemical vapor deposition process. Between each deposition operation, a cleanup process may be performed to create a stable transition between layers, which may limit surface roughness during the layer operation.

[0050] The second silicon layer can be formed to cover the silicon nitride layer during operation 320. In some embodiments, the second silicon layer may be similar to the first silicon layer and can be formed by a process similar to that of the first silicon layer. Figure 4A As shown, silicon layer 413 may be similar to or the same as silicon layer 409. A nitride layer 411 may be present between these two layers. A second silicon oxide layer may be formed in operation 325 to cover the second silicon layer. As shown in the figures, layer 415 may be formed over silicon layer 413. In some embodiments, the second silicon oxide layer may be similar to the first silicon oxide layer and may be formed using a similar process.

[0051] The second silicon oxide layer 415 may be the starting point for a second segment of the material forming the cover substrate. The specified operation may be repeated any number of times until a predetermined number of material pairs that can form a stack of materials can be formed. For example, any number of layers may be generated within the structure, such as from less than or about 10 layers to up to 200 layers or more of material. Figure 4A The structure 400 covered by this technology is illustrated as a developed stack comprising alternating layers, which may contain the desired alternating structure. It will be understood that any layer may be the first or last layer formed in some embodiments of this technology. Between each layer of silicon oxide and silicon nitride may be an intercalation layer of silicon, such as amorphous silicon. The overall stack may include any number of groups of layers, including more than or about 2 groups, more than or about 10 groups, more than or about 50 groups, more than or about 100 groups, or more groups of layers. Therefore, in some embodiments, operations 305 to 320 may be repeated any number of times to produce a stack of any size. Operations may be stopped and the stack ended with any number of layers before continuing further processing. Any particular number of groups covered by any of these descriptions is understood to be explicitly stated herein and the figures are included only to illustrate exemplary structures.

[0052] Regarding the deposition precursors used during any formation operation, any number of precursors may be used in this technology. Silicon-containing precursors that may be used during any of the silicon oxide formation, silicon formation, or silicon nitride formation may include, but are not limited to, silanes (SiH4), disilanes (Si2H6), or other organosilanes, silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilanes (SiH2Cl2), tetraethoxysilanes (TEOS), and any other silicon-containing precursors that may be used in silicon-containing film formation. Oxygen-containing precursors used in any operation described in this technology may include O2, N2O, NO2, O3, H2O, and any other oxygen-containing precursors that may be used in silicon oxide film formation or other film formation. Nitrogen-containing precursors used in any operation may include N2, N2O, NO2, NH3, N2H2, and any other nitrogen-containing precursors that may be used in silicon nitride film formation. One or more additional precursors may be included in any formation operation, such as inert precursors, which may include Ar, He, Xe, Kr, nitrogen, hydrogen, or other precursors.

[0053] The film thickness can be any range to create memory or other semiconductor structures. For example, in some embodiments, the oxide or nitride layer can be less than or about 100 nm, and can be less than or about 90 nm, less than or about 80 nm, less than or about 70 nm, less than or about 60 nm, less than or about 50 nm, less than or about 45 nm, less than or about 40 nm, less than or about 35 nm, less than or about 30 nm, less than or about 25 nm, less than or about 20 nm, less than or about 15 nm, less than or about 10 nm, or smaller. In some embodiments, the oxide or nitride layer can be thinner than other dielectric or placeholder material layers to accommodate the silicon layer while maintaining the overall stack thickness. In some embodiments, silicon increases the overall stack thickness. In some embodiments, an oxide thickness sufficient to limit crosstalk or leakage between developed cells can be maintained, and the nitride layer can be of reduced thickness to accommodate the incorporated silicon layer. The silicon layer may be characterized by a thickness less than that of the oxide or nitride layer, and may be characterized by the following thicknesses: less than or about 10 nm, less than or about 9 nm, less than or about 8 nm, less than or about 7 nm, less than or about 6 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, or smaller.

[0054] Temperature and pressure during any formation or removal operation may be controlled depending on the operation performed. Typically, the pressure within the processing chamber may be less than or about 30 Torr, and may be less than or about 20 Torr, less than or about 15 Torr, less than or about 12 Torr, less than or about 10 Torr, less than or about 8 Torr, less than or about 6 Torr, less than or about 5 Torr, less than or about 4 Torr, less than or about 3 Torr, less than or about 2 Torr, less than or about 1 Torr, or less. For some embodiments, such as processing chambers including an inductively coupled plasma source and / or a turbomolecular pump, the processing pressure may be further reduced to less than or about 100 mTorr, less than or about 90 mTorr, less than or about 80 mTorr, less than or about 70 mTorr, less than or about 60 mTorr, less than or about 50 mTorr, less than or about 40 mTorr, less than or about 30 mTorr, less than or about 20 mTorr, less than or about 10 mTorr, less than or about 5 mTorr, less than or about 2 mTorr, or less.

[0055] Any of the formation or removal operations can be performed at one or more process temperatures, which may be greater than or about 200°C, and may be greater than or about 250°C, greater than or about 300°C, greater than or about 350°C, greater than or about 400°C, greater than or about 450°C, greater than or about 500°C, or higher. Various plasma powers, precursor flow rates, and other chamber conditions can be similarly adjusted during any formation or other processing operation. Additional processing operations can be performed after the material stack has been prepared. For example, in some embodiments, annealing operations can be performed, such as at temperatures greater than or about 700°C, and may be greater than or about 750°C, greater than or about 800°C, greater than or about 850°C, greater than or about 900°C, or higher. Annealing can be performed with heated precursors, such as inert precursors including, for example, nitrogen. Reactive ion etching processes can be performed to create one or more pores through the layer stack, such as memory vias. Furthermore, stepped structures can be formed in the outer regions of the stack, as well as additional processing to create aspects of memory or other semiconductor structures. To begin production of memory cells, placeholder materials such as silicon nitride layers can be removed from the structure.

[0056] During operation 330, one or more silicon nitride layers can be removed from the layer stack, such as Figure 4B As shown. Several removal operations can be performed, and in some embodiments, a wet etching process, such as using hot phosphoric acid, can be performed to remove the nitride film. After etching has been performed, the wet etchant is typically dried from the structure. The surface tension of the etchant can affect the oxide layer. The conventionally formed unit with alternating oxide and nitride layers can cause deformation of the oxide, which can be characterized by reduced thickness and / or rigidity. For example, the Young's modulus of silicon oxide can be less than or about 85 GPa, and can be less than or about 80 GPa, which can increase the likelihood of deformation during the etchant drying process. Although the Young's modulus of silicon oxide can be slightly increased by tuned deposition, the Young's modulus can still remain stably less than about 90 GPa, or about 88 GPa. Therefore, the surface tension generated by the wet etchant can overcome the film strength and cause the film to twist.

[0057] Some embodiments of this technology, incorporating a silicon layer between nitride and oxide layers, can create oxide reinforcement, which can promote resistance to surface tension associated with dry etchant materials. For example, silicon such as amorphous silicon can be characterized by a high Young's modulus. When incorporated with an oxide layer, the silicon layer or multiple silicon layers adjacent to the silicon oxide layer can produce a composite material with oxide, which can be characterized by a Young's modulus greater than or about 90 GPa, and can be characterized by the following Young's moduli: greater than or about 92 GPa, greater than or about 94 GPa, greater than or about 96 GPa, greater than or about 98 GPa, greater than or about 100 GPa, greater than or about 102 GPa, or higher. Similarly, the amorphous silicon layer can also improve film hardness. However, silicon oxide can be characterized by a hardness of less than 12 GPa, and can be characterized by the following hardnesses: less than or about 11.7 GPa, less than or about 11.6 GPa, or less. Incorporating a silicon layer can improve the hardness to greater than or about 12.0 GPa, and can improve the hardness of the composite layer to greater than or about 12.2 GPa, greater than or about 12.4 GPa, greater than or about 12.5 GPa, greater than or about 12.6 GPa, greater than or about 12.7 GPa, greater than or about 12.8 GPa, greater than or about 12.9 GPa, greater than or about 13.0 GPa, or greater. Therefore, the composite film can withstand the surface tension effect of dry etchant materials.

[0058] Furthermore, amorphous silicon is more resistant to wet etching, and nitride removal is characterized by its higher selectivity for silicon compared to oxides. For example, wet etchants can extend across a larger area of ​​the structure, maintaining contact with the edge regions of the oxide layer during extension, and can cause thinning of the oxide layer in certain areas. The amorphous silicon layer can protect multiple regions across the oxide layer and can extend completely across the formed structure. Amorphous silicon can cover the edge regions of the oxide layer, limiting the extended interaction with the wet etchant. Therefore, the oxide layer can be further protected from thinning by the wet etchant.

[0059] In some embodiments, the silicon layer can be removed after the removal of silicon nitride. Although metal filling can occur within open inlets and outlets, the reduced volume from the silicon layer can increase the line resistance of the metal. Therefore, a second removal process can be performed in operation 335 to selectively remove the first and second silicon layers from the remaining oxide layers, as... Figure 4C As shown. Selective removal of silicon relative to silicon oxide can be performed in various processes, and in some embodiments may involve dry etching processes, including plasma-enhanced dry etching processes.

[0060] In some embodiments, the substrate may be transferred from a first processing chamber or processing system to a second processing chamber on the same system, or to a separate system in which a dry etching chamber may be disposed. In some embodiments, the dry etching chamber and the deposition chamber may be on the same chamber system, which allows the substrate to be transferred from the first processing system to the second processing chamber while maintaining a vacuum. In some embodiments, the wet etching process may occur on similar or different processing systems, which may include transferring the substrate between chambers and / or systems during operation of this method.

[0061] When delivered to a dry etching chamber, the substrate allows for the removal of a nitride layer, while also including exposed areas or layers of silicon (such as amorphous silicon) and oxide layers, which may be at least partially disposed between the silicon layers or areas. The silicon removal operation can be performed using one or more precursors including fluorine-containing precursors, and may also include hydrogen-containing precursors, as well as one or more additional precursors, which may include inert or rare gases, such as helium, argon, or other materials that facilitate the etching process. In some embodiments, one or both of the fluorine-containing or hydrogen-containing precursors may flow into a distal plasma region of the dry etching chamber. For example, the distal plasma region may be fluidly coupled to a processing region housing the substrate, although this region may be physically separated, such as by a nozzle operable as an electrode within the distal plasma region. The distal plasma system may also be externally coupled to the chamber and provide plasma effluent into the chamber.

[0062] The plasma effluent of the precursor can be delivered into the processing region to contact the silicon layer and selectively remove the silicon layer from the oxide layer. The processing conditions can be configured in one or more ways to provide selective etching of silicon relative to the oxide, characterized by a selectivity greater than or about 100:1. For example, the processing chamber, stage, or substrate can be maintained at a temperature between about 40°C and about 150°C during etching or removal operations, while the pressure within the processing chamber can be maintained, for example, below or about 12 Torr. Furthermore, in some embodiments, the flow rates of the fluorine-containing precursor and / or the hydrogen-containing precursor can be adjusted, such as maintaining a flow rate ratio between the precursors.

[0063] For example, in some embodiments, removal can be performed while maintaining a hydrogen to fluorine atomic flow rate ratio greater than or about 10:1. Such a process maintains a hydrogen-capped surface that allows fluorine to selectively remove silicon relative to oxides. Exemplary hydrogen-containing precursors may include one or more precursors comprising hydrogen, such as diatomic hydrogen, ammonia, hydrocarbons, or other precursors comprising hydrogen. Exemplary fluorine-containing precursors may include one or more precursors, including atomic fluorine, diatomic fluorine, bromine trifluoride, chlorine trifluoride, nitrogen trifluoride, hydrogen fluoride, fluorinated hydrocarbons, sulfur hexafluoride, or xenon difluoride, as non-limiting examples. Further processing, including metallization, may be performed after the removal of the silicon layer.

[0064] In some embodiments, additional operations may be performed to improve the nucleation and formation of metal within trenches contoured by the oxide material. For example, in some embodiments, in optional operation 340, a pad or other material may be formed along the exposed surface of the oxide, as... Figure 4D Material 420 is shown in the diagram. The liner material may include several barrier or liner materials, such as metal nitrides including titanium nitride, which may include any number of transition metals or other materials. The liner material may be conformally formed along the oxide layer and may protect the oxide surface from the diffusion or exposure of effluents containing metal precursors, which may include halogen materials or other materials that react with the oxide.

[0065] In operation 345, if a liner material is incorporated, a metal layer may be formed between the oxide and / or liner material layers, such as... Figure 4D Material 425 is shown. One or more metal-containing or deposition precursors can be used to deposit metallic materials within open trench regions to form conductive unit materials between oxide material layers. For example, tungsten, cobalt, or other conductive metals or materials can be used as unit formation in embodiments of this technology.

[0066] As described above, padding materials can be incorporated into the trenches to promote the nucleation of metallic materials, such as tungsten in one non-limiting embodiment. Tungsten and other metallic materials do not readily deposit on silicon oxide and therefore often include an additional layer of material to facilitate deposition. Furthermore, because oxide materials can be manipulated to separate cells, such as in memory applications, limiting metal diffusion or removal from metal deposition byproducts can limit crosstalk and prevent short circuits or device failure. However, even at thicknesses of a few nanometers or less, incorporating padding materials further limits the volume that can be occupied by the metal. As stack sizes continue to shrink, thinner amounts of metal drastically increase the material's resistance.

[0067] As described above, the silicon layer improves the resistance of oxides to deformation or breakage during wet etching removal of the silicon nitride layer. In some embodiments of this technology, the formed silicon layer can also be used to facilitate the formation of tungsten or other metals. [Go to...] Figure 5 This illustrates exemplary operation of a method 500 for forming a semiconductor structure according to some embodiments of the present technology. This method may include aspects of forming a stacked structure and a transition structure for metal bonding. Method 500 may include any number of similar operations of the above-described method 300, and may include any operations, materials, or properties of any of the aforementioned aspects. Furthermore, this method can be performed in various processing chambers, including the aforementioned processing chamber 200, which may, for example, be incorporated into system 100. Method 500 may be illustrated schematically in… Figures 6A to 6D The operation in the middle, Figures 6A to 6DThe illustrations will be explained in conjunction with the operation of method 500. It will be understood that the figures show only partial schematic views, and the substrate may contain any number of structural segments having the aspects shown in the figures, and alternative structural aspects may still benefit from the operation of embodiments of the present technology.

[0068] Similar to method 300 described above, method 500 may include forming a first oxide layer over a substrate in operation 505. A first amorphous silicon layer may form a covering silicon oxide layer in operation 510. A silicon nitride layer may form a covering amorphous silicon layer in operation 515. A second amorphous silicon layer may form a covering silicon oxide layer in operation 520. A second silicon oxide layer may form a covering second amorphous silicon layer in operation 525. Any of these operations may be performed using any of the aforementioned precursors, any of the aforementioned processing conditions, or considerations, and may include any aspect or characteristic of the aforementioned processes, materials, or properties.

[0069] The stack can extend in any number of the aforementioned layers and may include any number of material component layers. For example, the specified operation may be repeated any number of times until a predetermined number of layer pairs constituting the layer stack can be formed. For example, any number of layers may be generated within the structure, such as from less than or about 10 layers to up to 200 layers of material or more. The stack may begin or end at any of the layers, and only one enclosing configuration is shown. Figure 6A In this structure, silicon layers 609 and 613 surround a nitride layer 611, and all three layers are situated between oxide layers 607 and 615, forming a cover substrate 605. As described above, additional operations, such as memory via formation or other stacking aspects, may optionally be performed. Figure 6B As shown, in subsequent stacking and any additional optional operations, the silicon nitride layer can be removed in operation 530. As mentioned above, removal can be performed using a wet etchant; however, additional techniques can be similarly incorporated into this technique.

[0070] The method 300 described above includes embodiments in which the silicon layer is subsequently removed, such as using a dry etching process. This technology also includes processes in which the silicon layer may alternatively be used in a conversion reaction. For example, in operation 535, the silicon layer may be converted into a metal-containing layer 620, such as... Figure 6C As shown. Certain metallic materials can be used to perform the conversion reaction of amorphous silicon, providing an exchange of silicon for the metallic material. By performing the exchange reaction, the metallic material can form along the silicon oxide surface while maintaining a relatively stable transition between layers. This allows for metal formation without the additional formation of the aforementioned pads and / or nucleation layers. By removing the pad layers, a larger thickness and bulk volume of metallic material can be generated between the oxide layers, which can improve the resistance through the metal.

[0071] The conversion reaction may include introducing a metal-containing precursor into a processing region to contact the amorphous silicon layer and causing a reaction between the materials. The reaction may be at least partially based on a thermal activation reaction, and this conversion may be performed at temperatures greater than or about 300°C, and may be performed at temperatures greater than or about 350°C, greater than or about 400°C, greater than or about 450°C, greater than or about 500°C, greater than or about 550°C, greater than or about 600°C, greater than or about 650°C, greater than or about 700°C, greater than or about 750°C, or higher. For example, the exchange of tungsten and silicon may occur according to the following reaction:

[0072]

[0073] X can be, for example, 1 or 2, while Y can be, for example, 2 or 4, and other integers or decimals.

[0074] Therefore, this reaction can form volatile silicon byproducts while leaving solid metal to form a metallic material layer. Because an exchange reaction can occur, the thickness of the silicon layer affects the material. For example, if the silicon layer extends beyond a certain threshold, a complete transformation may not occur, and the remaining silicon may become trapped between the oxide layer and the metal formation layer. Therefore, in some embodiments, the silicon layer may be maintained at a thickness of less than or about 5 nm, and may be maintained at less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, or even smaller.

[0075] By performing the conversion reaction, the formation of the edge region can be maintained while the metal-containing precursor extends within the trench. Therefore, in some embodiments, pinch-off and void formation can be reduced. After the silicon material is converted to metal, additional processing can be performed to complete the metal-containing material layer. For example... Figure 6D As shown, the metal material 625 may extend to connect the converted portions of the metal material to create a substantially or completely continuous metal material extending between the oxide layers. Therefore, in some embodiments, the volume of the metal material may be increased in structures where the nucleation and / or barrier layers may not be incorporated along the silicon oxide material.

[0076] Embodiments of this technology may also include additional modifications to strengthen the oxide layer to limit or prevent deformation or breakage during wet process removal of the nitride material. In some embodiments of this technology, the formed silicon oxide layer may be modified by doping to enhance resistance to deformation due to surface tension effects. [Go to...] Figure 7This illustrates exemplary operations in a method 700 for forming a semiconductor structure according to some embodiments of the present technology. This method may include forming a stacked structure utilizing a modified silicon oxide material as a dielectric layer. Method 700 may include any number of the similar operations described above with respect to method 300 or method 500, and may include any operations, materials, or properties of any aspect described above. Furthermore, this method can be performed in various processing chambers, including the aforementioned processing chamber 200, which may, for example, be incorporated into system 100. Method 700 may illustrate... Figures 8A to 8D The operation is illustrated schematically in the diagram. Figures 8A to 8D The illustrations will be explained in conjunction with the operation of method 700. It will be understood that the figures show only partial schematic views, and the substrate may contain any number of structural segments having the aspects shown in the figures, as well as alternative structural aspects that may still benefit from the operation of embodiments of the present technology.

[0077] In some embodiments, method 700 may include forming a modified oxide layer overlay on the substrate in operation 705, and as shown in... Figure 8A Layer 807 covers substrate 805. The modified layer may include one or more dopants or stoichiometric modifiers. In operation 710, the silicon nitride layer may form a cover amorphous silicon layer, and may be shown as... Figure 8A Layer 809 in the middle. In operation 715, a second modified silicon oxide layer can be formed to cover the silicon nitride layer, and it can be shown as in... Figure 8A Layer 811 in the middle. The second modified layer may also include one or more dopants or stoichiometric modifiers, and in embodiments of the present technology may be similar to or different from the first silicon oxide layer. In some embodiments of the present technology, additional processes, such as memory hole or step formation, may be performed. In operation 720, the silicon nitride layer may be removed, such as Figure 8B As shown, it can be performed using any removal technique, including the aforementioned wet etching removal.

[0078] The modified silicon oxide layer can be modified to enhance resistance to deformation caused by the surface tension of the etchant used in nitride removal, resulting from wet etching effects. In some embodiments, one or more dopants can be incorporated to increase the Young's modulus of silicon oxide, and they can also increase the hardness of the material. For example, in some embodiments, a nitrogen dopant can be incorporated during formation to provide a certain amount of nitrogen incorporated into the oxide film. During layer formation, nitrogen or a nitrogen-containing precursor can flow with a silicon-containing precursor and / or an oxygen-containing precursor. The nitrogen-containing precursor may include any of the nitrogen-containing precursors described above and any combination of the aforementioned precursors.

[0079] Nitrogen incorporation can be performed to enhance film properties and structural integrity. Through nitrogen doping, the Young's modulus of the modified oxide can be increased to greater than or about 90 GPa, and can be increased to greater than or about 95 GPa, greater than or about 100 GPa, greater than or about 105 GPa, greater than or about 110 GPa, greater than or about 115 GPa, greater than or about 120 GPa, greater than or about 125 GPa, or higher. Furthermore, the film hardness can be increased to greater than or about 12 GPa, and can be increased to greater than or about 13 GPa, greater than or about 14 GPa, greater than or about 15 GPa, greater than or about 16 GPa, greater than or about 17 GPa, or higher.

[0080] Because nitride removal is operable selectively for oxide materials, increasing nitrogen doping within the oxide film can enhance the etching characteristics of the oxide material. Therefore, in some embodiments, to maintain selectivity during nitride removal, nitrogen incorporation can be maintained at less than or about 10 atomic percent, and can be maintained at less than or about 8 atomic percent, less than or about 7 atomic percent, less than or about 6 atomic percent, less than or about 5 atomic percent, less than or about 4.5 atomic percent, less than or about 4.0 atomic percent, less than or about 3.5 atomic percent, less than or about 3 atomic percent, less than or about 2.5 atomic percent, less than or about 2 atomic percent, less than or about 1.5 atomic percent, less than or about 1 atomic percent, less than or about 0.5 atomic percent, or less. To ensure increased structural integrity, nitrogen incorporation can be maintained at greater than or about 0.5 atomic percent or greater.

[0081] Furthermore, in some embodiments, the stoichiometry of the silicon oxide film can be adjusted to increase film properties. By increasing the silicon-like properties of the film, structural integrity relative to the silicon oxide film can be increased. To increase the stoichiometric ratio of the formed film, in some embodiments, precursor delivery can be adjusted from standard silicon oxide deposition conditions. For example, during certain processes, the silicon-to-oxide atomic ratio can be as high as 1:7 in some embodiments. During the formation method according to some embodiments of the present technology, the silicon-to-oxide ratio can be adjusted to less than or about 1:7, and can be adjusted to less than or about 1:6, less than or about 1:5, less than or about 1:4, less than or about 1:3, less than or about 1:2, less than or about 1:1, or smaller. By providing a formation process that is relatively oxygen-dependent compared to other formations, the oxygen-to-silicon ratio in the resulting film can be less than or about 2.0:1, and can be less than or about 1.9:1, less than or about 1.8:1, less than or about 1.7:1, less than or about 1.6:1, less than or about 1.5:1, or smaller.

[0082] By increasing the incorporation of silicon within the film, the Young's modulus of the modified oxide can be increased to greater than or about 100 GPa, and can be increased to greater than or about 110 GPa, greater than or about 120 GPa, greater than or about 125 GPa, greater than or about 130 GPa, greater than or about 135 GPa, greater than or about 140 GPa, greater than or about 145 GPa, greater than or about 150 GPa, greater than or about 155 GPa, greater than or about 160 GPa, or higher. Furthermore, the film hardness can be increased to greater than or about 12 GPa, and can be increased to greater than or about 13 GPa, greater than or about 14 GPa, greater than or about 15 GPa, greater than or about 16 GPa, greater than or about 17 GPa, or higher. Any of the foregoing additional treatments can also be incorporated into optional operations of one or more aspects of method 700, including nitrogen or other high-temperature annealing after film formation.

[0083] Stacked dielectric materials can separate cells, such as memory cells, generated through subsequent processing. Nitrogen doping, silicon-rich films, or other doping or modification can affect the leakage current of the resulting film, which can affect device performance. Therefore, in some embodiments, method 700 may include processing a modified oxide material in operation 725 after etching or removing the nitride layer. This processing may in embodiments involve removing the dopant concentration or adjusting the film properties to more closely resemble silicon oxide, and it is in Figure 8C The layer shown is a silicon oxide layer 815. For example, processing the modified oxide may include performing an oxygen treatment, which in some covered embodiments may include vapor annealing or other oxygen treatments. This annealing may be performed to extract nitrogen or other dopants and / or increase oxygen incorporation within the film, and it may be performed at any of the temperatures described above, including temperatures greater than or about 500°C, or higher temperatures described above. Additional operations may optionally be performed to form a layer such as... Figure 8D The metal layer 820 shown may include any material, including the optional pads described above.

[0084] Following vapor annealing, tests showed that nitrogen incorporation could be reduced to a nominal level, allowing for inclusion in standard oxide films. Furthermore, the stoichiometry of the treated film could be characterized by a substantially or essentially 2:1 oxygen-to-silicon ratio. The leakage current density within the treated film could be maintained at less than or approximately 1 x 10⁻⁶. -6 A / cm 2 And can be maintained at less than or about 8x10 -7 A / cm 2 Less than or approximately 5x10 -7 A / cm 2 Less than or about 2x10 -7 A / cm 2 Less than or about 1x10 -7 A / cm2 Less than or approximately 9x10 -8 A / cm 2 Less than or approximately 8x10 -8 A / cm 2 Less than or approximately 7x10 -8 A / cm 2 Less than or approximately 6x10 -8 A / cm 2 Less than or approximately 5x10 -8 A / cm 2 Less than or approximately 4x10 -8 A / cm 2 Less than or about 3x10 -8 A / cm 2 Less than or about 2x10 -8 A / cm 2 Less than or approximately 1.5 x 10 -8 A / cm 2 Less than or about 1.2 x 10 -8 A / cm 2 Less than or about 1x10 -8 A / cm 2 or smaller.

[0085] Furthermore, the treated oxide layer can be characterized by a breakdown voltage greater than or about 6.0 MV / cm, and can be characterized by a breakdown voltage greater than or about 7.0 MV / cm, greater than or about 7.5 MV / cm, greater than or about 8.0 MV / cm, greater than or about 8.5 MV / cm, greater than or about 9.0 MV / cm, greater than or about 9.5 MV / cm, greater than or about 10.0 MV / cm, greater than or about 10.5 MV / cm, greater than or about 11.0 MV / cm, greater than or about 11.5 MV / cm, greater than or about 12.0 MV / cm, greater than or about 12.5 MV / cm, or higher. Therefore, this technology can produce oxide films that can be strengthened into composite layers and produce modified oxide layers, any of which can resist deformation and breakdown during wet etching or other removal processes, and can be substantially maintained or treated to improve electrical properties.

[0086] In the foregoing description, various details have been described for illustrative purposes, in order to provide an understanding of the various embodiments of the present technology. However, it will be apparent to those skilled in the art that some embodiments may be practiced without certain of these details or with additional details.

[0087] Several embodiments have been disclosed, and those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, several well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be construed as limiting the scope of the present technology. Additionally, methods or processes may be described as sequential or step-by-step, but it will be understood that operations may be performed simultaneously or in a sequence other than that listed.

[0088] Unless the context clearly indicates otherwise, where a range of values ​​is provided, the smallest segment of the unit to the lower limit of each intermediate value between the upper and lower limits of this range is also explicitly disclosed. Any narrower range between any specified values ​​or unspecified intermediate values ​​within a specified range, and any other specified or intermediate value within the specified range, is covered. The upper and lower limits of these narrower ranges may be independently included or excluded from this range, and each range including both limits, either non-limit values, or any limit values ​​within a narrower range is also covered in this technique, depending on any explicitly excluded limit values ​​within the specified range. Where a specified range includes one or both limit values, the range excluding either or both of these included limit values ​​is also included.

[0089] As used herein and in the appended claims, the singular forms “a,” “an,” and “the” include the plural references unless the context clearly states otherwise. Thus, for example, reference to “a precursor” includes a plurality of such precursors, and reference to “the layer” includes reference to one or more layers and their equivalents known to those skilled in the art, and so on.

[0090] Furthermore, the terms “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including”, when used in this specification and the appended claims, are intended to specify the presence of the indicated feature, integral, component, or operation, but do not exclude the presence or addition of one or more other features, integrals, components, operations, actions, or groups.

Claims

1. A method for forming a semiconductor structure, the method comprising: A first silicon oxide layer is formed, and the first silicon oxide layer covers the semiconductor substrate; A first silicon layer is formed, which covers the first silicon oxide layer; A silicon nitride layer is formed, wherein the silicon nitride layer covers the first silicon layer; A second silicon layer is formed, which covers the silicon nitride layer; A second silicon oxide layer is formed, and the second silicon oxide layer covers the second silicon layer; Remove the silicon nitride layer; Remove the first silicon layer and the second silicon layer; as well as A metal layer is formed between each of the first silicon oxide layer and the second silicon oxide layer.

2. The method of forming a semiconductor structure as claimed in claim 1, wherein the silicon nitride layer is removed by a wet etching process.

3. The method for forming a semiconductor structure as claimed in claim 1, wherein the first silicon layer and the second silicon layer are removed by a dry etching process.

4. The method for forming a semiconductor structure as claimed in claim 1, wherein the second silicon layer and the second silicon oxide layer form a composite film, the composite film being characterized by a Young's modulus greater than or equal to 90 GPa.

5. The method of forming a semiconductor structure as claimed in claim 1, wherein the metal layer comprises tungsten.

6. The method for forming a semiconductor structure as described in claim 1, further comprising: After removing the first silicon layer and the second silicon layer, a pad layer is formed along the first silicon oxide layer and the second silicon oxide layer.

7. The method of forming a semiconductor structure as claimed in claim 1, wherein the formation of the first silicon oxide layer occurs in a first processing chamber, and the removal of the first silicon layer and the second silicon layer occurs in a second processing chamber, the method further comprising: The semiconductor substrate is transferred from the first processing chamber to the second processing chamber while maintaining a vacuum state.

8. The method of forming a semiconductor structure as claimed in claim 1, wherein the first silicon oxide layer and the second silicon oxide layer are characterized by a thickness of less than 50 nm or equal to 50 nm.

9. A method for forming a semiconductor structure, the method comprising: A first silicon oxide layer is formed, and the first silicon oxide layer covers the semiconductor substrate; A first amorphous silicon layer is formed, and the first amorphous silicon layer covers the first silicon oxide layer; A silicon nitride layer is formed, which covers the first amorphous silicon layer; A second amorphous silicon layer is formed, which covers the silicon nitride layer; A second silicon oxide layer is formed, which covers the second amorphous silicon layer; Remove the silicon nitride layer; as well as The first amorphous silicon layer and the second amorphous silicon layer are converted into metallic materials that are in contact with the first silicon oxide layer and the second silicon oxide layer, respectively.

10. The method of forming a semiconductor structure as claimed in claim 9, wherein the conversion comprises: The metal-containing precursor is allowed to flow to contact the first amorphous silicon layer and the second amorphous silicon layer; as well as Volatile silicon-containing byproducts are formed, and a layer of the metal material is formed simultaneously.

11. The method for forming a semiconductor structure as described in claim 9, further comprising: A layer of metallic material is formed extending between the first silicon oxide layer and the second silicon oxide layer.

12. The method of forming a semiconductor structure as claimed in claim 9, wherein the silicon nitride layer is removed by a wet etching process.

13. The method of forming a semiconductor structure as claimed in claim 9, wherein the first amorphous silicon layer and the second amorphous silicon layer are characterized by a thickness of less than 5 nm or equal to 5 nm.

14. A method for forming a semiconductor structure, the method comprising: A first silicon oxide layer is formed, the first silicon oxide layer covering a semiconductor substrate, wherein the first silicon oxide layer includes a nitrogen dopant or is rich in silicon stoichiometry, and the first silicon oxide layer is characterized by a Young's modulus greater than or equal to 110 GPa; A silicon nitride layer is formed, wherein the silicon nitride layer covers the first silicon oxide layer; A second silicon oxide layer is formed, which covers the silicon nitride layer, wherein the second silicon oxide layer includes a nitrogen dopant or is rich in silicon stoichiometry; Remove the silicon nitride layer; as well as The first silicon oxide layer and the second silicon oxide layer are processed.

15. The method of forming a semiconductor structure as claimed in claim 14, wherein the process includes performing vapor annealing.

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