Microelectronic devices including passivation materials, related electronic devices, and related methods

Abstract

A microelectronic device includes a conductive line and a transistor adjacent the conductive line. The transistor includes a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions; a dielectric material adjacent the channel material; a conductive material adjacent the dielectric material; and a passivation material adjacent the channel material. The microelectronic device additionally includes a conductive contact adjacent the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.

Description

[0001] Cross-citation of related applications

[0002] This application claims the benefit of U.S. Patent Application No. 16 / 682,617, filed November 13, 2019, entitled “Microelectronic Device, Related Electronic Device, and Related Method Including Passivating Material”. Technical Field

[0003] The embodiments disclosed herein relate to microelectronic devices, related electronic devices, and related methods that include transistors having passivation materials. More specifically, the embodiments of this disclosure relate to microelectronic devices, related electronic devices, and related methods that include features such as transistors having channel materials and passivation materials in contact with the channel materials. Background Technology

[0004] The fabrication of microelectronic devices includes forming transistors that can be accessed, such as memory components of memory cells in a microelectronic device. A transistor includes a channel region comprising a semiconductor material configured to conduct current in response to an applied threshold voltage and to prevent current flow in the absence of a threshold voltage.

[0005] A persistent goal of the semiconductor industry is to increase the memory density of memory devices (e.g., the number of memory cells per memory die). While the footprint of memory cells (containing transistors) continues to shrink to increase memory density, reducing the size of one or more components of a memory cell can adversely affect its performance. For example, for a conventional transistor containing a channel region formed of semiconductor material (e.g., silicon, polysilicon), reducing the thickness of the gate dielectric material between the channel region and the gate electrode can initially reduce the transistor's turn-off current (I0). off However, as the thickness of the gate dielectric material decreases, reaching the minimum thickness limit, the turn-off current begins to increase unnecessarily due to the interband tunneling and relatively low bandgap of conventional semiconductor materials. Furthermore, a reduction in the channel size leads to a decrease in the contact area between the channel region and the conductive contacts. This reduced contact area causes an increase in resistance between the channel region and the conductive contacts. Increased resistance results in a decrease in the on-state current, which ultimately reduces the speed of the transistor and associated memory cells.

[0006] In microelectronic devices containing vertical memory cells, the transistors associated with the vertical memory cells can be vertical. Forming such transistors involves forming a stack of materials that ultimately forms the transistor of the vertical memory cell, the materials including source and drain contacts, channel regions, and gate electrode materials. The stacked materials are patterned to form pillars containing the material stack.

[0007] The channel region of a vertical transistor contains semiconductor material. Traps and defects in the channel region of a conventional microelectronic device containing a vertical transistor can increase the turn-off current of the vertical transistor. In some cases, traps and defects can cause the presentation of so-called “sub-bandgap” states (also referred to herein as “sub-gap” states). As an example, deep traps and deep donors can alter the turn-off leakage of the transistor. Therefore, defects and traps in the channel region can cause an increase in the turn-off current of the transistor, thereby reducing the transistor’s charge retention capability, for example, by allowing charge leakage through the transistor in the turn-off state. The increased leakage due to the increased turn-off current leakage causes storage charge leakage through the transistor, forcing more frequent refreshes of the memory bits associated with the transistor. Summary of the Invention

[0008] In some embodiments, the microelectronic device includes a transistor adjacent to a conductive line. The transistor includes a channel material extending into and contacting the conductive line, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further includes a conductive contact adjacent to the channel material, the conductive contact comprising a portion extending between opposing portions of the channel material.

[0009] In other embodiments, the microelectronic device includes a transistor comprising a channel material extending into a conductive line, a passivation material located between different portions of the channel material, a dielectric material adjacent to the channel material, and a conductive material adjacent to the dielectric material, the dielectric material being situated between the channel material and the conductive material.

[0010] In yet another embodiment, the method of forming a microelectronic device includes removing sacrificial material between adjacent portions of a dielectric material to form an opening and exposing a conductive wire through the opening, removing a portion of the conductive wire through the opening, forming a channel material in contact with the conductive wire within the opening, forming a passivation material adjacent to the channel material, and forming a conductive contact adjacent to the channel material and the passivation material.

[0011] In another embodiment, the microelectronic device includes a conductive line, a passivation material adjacent to the conductive line, a channel material including an oxide semiconductor adjacent to and in contact with the opposite side of the passivation material, a dielectric material in contact with the channel material, and a conductive material adjacent to the dielectric material.

[0012] In some embodiments, the electronic device includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device. The memory device includes a channel material extending along a conductive line, a passivation material within an adjacent portion of the channel material, a dielectric material adjacent to the channel material, and a conductive material adjacent to the dielectric material. Attached Figure Description

[0013] Figure 1A and Figure 1B This is a simplified cross-sectional view of a transistor-included microelectronic device according to an embodiment of the present disclosure;

[0014] Figure 2 This is a simplified planar cross-sectional view of a transistor in a microelectronic device according to an embodiment of the present disclosure;

[0015] Figures 3A to 3F This is a simplified cross-sectional view illustrating a method of forming a microelectronic device according to an embodiment of the present disclosure;

[0016] Figure 4 This is a block diagram of an electronic system according to embodiments of the present disclosure; and

[0017] Figure 5 It is a processor-based system according to embodiments of the present disclosure. Detailed Implementation

[0018] The illustrations contained herein are not intended to be actual views of any particular system, microelectronic structure, microelectronic device, or its integrated circuit, but are merely idealized representations for describing the embodiments herein. Elements and features shared between the figures may retain the same numerical designations, but for ease of description below, the reference numerals begin with the designation of the figure on which the element is introduced or most fully described.

[0019] The following description provides specific details, such as material type, material thickness, and processing conditions, to provide a full description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein can be practiced without these specific details. In fact, the embodiments can be practiced in conjunction with conventional manufacturing techniques used in the semiconductor industry. Furthermore, the description provided herein does not constitute a complete description of a transistor, a microelectronic device containing a transistor, or a complete description of the process flow for manufacturing a transistor or a microelectronic device containing a transistor. The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding the embodiments described herein are described in detail below. Additional actions for forming a complete microelectronic device containing transistors can be performed using conventional manufacturing techniques.

[0020] The materials described herein can be formed using conventional techniques, including but not limited to spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Alternatively, the materials can be grown in situ. Depending on the specific material to be formed, the technique used for depositing or growing the material can be selected by those skilled in the art. Unless the context otherwise indicates, material removal can be achieved by any suitable technique including but not limited to etching, planarization (e.g., chemical-mechanical planarization), or other known methods.

[0021] As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” refer to the principal plane of a substrate (e.g., substrate material, substrate structure, substrate configuration, etc.) on which one or more structures and / or features are formed and are not necessarily defined by the Earth’s gravitational field. A “lateral” or “horizontal” direction is a direction generally parallel to the principal plane of the substrate, while a “longitudinal” or “vertical” direction is a direction generally perpendicular to the principal plane of the substrate. The principal plane of the substrate is defined by the surface of the substrate, which has a relatively large area compared to the other surfaces of the substrate.

[0022] As used herein, the term "generally" with respect to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition conforms to deviations (such as within acceptable tolerances) as would be understood by one of ordinary skill in the art. As an example, depending on the specific parameter, property, or condition that is substantially satisfied, it may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0023] As used herein, the term "about" or "approximately" when referring to a value for a particular parameter includes the value, and those skilled in the art will understand that the deviation from the value is within acceptable tolerances for the particular parameter. For example, "about" or "approximately" with respect to a value may include additional values ​​that are in the range of 90.0% to 110.0% of the value, such as in the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0024] As used herein, spatial relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and similar spatial relative terms are used to conveniently describe the relationship of one element or feature to another, as illustrated in the figures. Unless otherwise specified, spatial relative terms are intended to cover different orientations of material other than those depicted in the figures. For example, if the material in the figures is inverted, then an element described as “below,” “under,” “below,” or “bottom” of other elements or features will be oriented “above” or “top” of said other elements or features. Thus, the term “below” may encompass both above and below orientations, depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptors used herein may be interpreted accordingly.

[0025] As used herein, “conductive material” means one or more of the following: metals, such as tungsten, titanium, niobium, vanadium, hafnium, tantalum, chromium, zirconium, iron, osmium, cobalt, nickel, iridium, platinum, palladium, ruthenium, rhodium, aluminum, copper, molybdenum, and gold; metal alloys; metal-containing materials (e.g., metal nitrides (titanium nitride, tantalum nitride, tungsten nitride, aluminum titanium nitride), metal silicides (tantalum silicide, tungsten silicide, nickel silicide, titanium silicide), metal carbides, and metal oxides (iridium oxide and ruthenium oxide)); conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.); polycrystalline silicon; other materials exhibiting conductivity; or combinations thereof. The conductive material may include at least one of the following: titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), elemental titanium (Ti), elemental platinum (Pt), elemental rhodium (Rh), elemental ruthenium (Ru), elemental molybdenum (Mo), elemental iridium (Ir), iridium oxide (IrO). x ), element ruthenium (Ru), ruthenium oxide (RuO) x ), element tungsten (W), element aluminum (Al), element copper (Cu), element gold (Au), element silver (Ag), polycrystalline silicon, their alloys, or combinations thereof. The terms "conductive material" and "conductive material" are used interchangeably herein.

[0026] According to embodiments described herein, a microelectronic device includes an array of vertical transistors. The vertical transistors may be located between conductive lines (e.g., bit lines, data lines). At least one of the vertical transistors includes a vertically oriented channel region comprising a channel material and a passivation material located between portions of the channel material. The channel material may extend at least partially into one of the conductive lines. A portion of the channel material may directly contact the conductive line such that the channel material contacts the conductive line in three dimensions. In some embodiments, the channel material contacts the conductive line (e.g., along its vertical sidewalls) and along its lateral surface. A dielectric material (e.g., a gate dielectric material) may surround at least a portion of the channel material. A conductive material (e.g., a gate electrode material) may be adjacent to and in contact with the dielectric material. The passivation material may be located within the channel material and between different portions of the channel material (e.g., sidewalls). In some embodiments, the channel material includes openings partially filled with the passivation material. The channel material may include interfaces with the dielectric material and the passivation material. Therefore, a transistor may include a channel region having a channel material and a passivation material, and may include a so-called "double-layer" structure having a channel material and a passivation material. Conductive contacts (e.g., electrodes) may at least partially fill the opening and be located between different portions of the channel material. In some such embodiments, the conductive contacts contact the channel material in three dimensions, such as along the vertical direction (e.g., on its sidewalls) and along the lateral direction, such as along its lateral surface (e.g., the top surface).

[0027] Forming channel material extending into (e.g., partially extending into) the conductive lines and forming conductive contacts within and along the channel material (e.g., along the sidewalls of the channel material) helps improve transistor performance. Forming channel material that contacts the conductive lines in three dimensions increases the contact area between the channel material and the conductive lines. Similarly, forming conductive contacts that are at least partially within the channel material and contact the channel material in three dimensions increases the contact area between the channel material and the conductive contacts. The increased contact area between the channel material and each of the conductive lines and conductive contacts reduces the contact resistance, which helps increase the on-state current and improve the transistor's operating speed (e.g., a reduced RC value). Therefore, the lateral footprint of the transistor can be reduced while improving transistor performance.

[0028] Passivation materials can promote a reduction in the turn-off current of transistors. Passivation materials can be formulated and configured to passivate deep donor states (e.g., states within the bandgap of the channel material that have energy states between the valence and conduction bands and have a relatively high density of states) and other defects in the channel material. Passivation of deep donor states and defects in the channel material reduces the transistor's turn-off current, thereby reducing leakage through the transistor. Additionally, passivation materials can lower the transistor's threshold voltage (Vth). t Stress-induced degradation of ).

[0029] Figure 1A and Figure 1B This is a simplified cross-sectional view of a microelectronic device 100 including a transistor 150 according to an embodiment of the present disclosure. The transistor 150 may be adjacent to (e.g., overlaid on) a substrate material 102. The substrate material 102 may include a substrate or structure on which additional material may be formed. The substrate material 102 may be a semiconductor substrate, a substrate semiconductor layer on a support structure, a metal electrode, or a metal electrode on a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate material 102 may be a conventional silicon substrate or other bulk substrate including a layer of semiconducting material. As used herein, the term "bulk substrate" means and includes not only silicon wafers but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") and silicon-on-glass ("SOG") substrates, silicon epitaxial layers on a substrate semiconductor basis, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate material 102 may be doped or undoped.

[0030] Conductive wire 104 may be adjacent to (e.g., overlaid on) substrate material 102. Conductive wire 104 may comprise conductive materials such as tungsten, titanium, niobium, vanadium, hafnium, tantalum, chromium, zirconium, iron, osmium, cobalt, nickel, iridium, platinum, palladium, ruthenium, rhodium, aluminum, copper, molybdenum, gold, metal alloys, metallic materials (e.g., metal nitrides (titanium nitride, tantalum nitride, tungsten nitride, aluminum titanium nitride), metal silicides (tantalum silicide, tungsten silicide, nickel silicide, titanium silicide), metal carbides, metal oxides (iridium oxide, ruthenium oxide)), conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.), polycrystalline silicon, other materials exhibiting conductivity, or combinations thereof. In some embodiments, conductive wire 104 comprises tungsten.

[0031] Transistor 150 includes channel material 106 that extends at least partially into conductive line 104. Channel material 106 may, for example, be vertical (along the z-direction); Figure 1A and Figure 1B The dielectric material 108 (e.g., a gate dielectric material) extends into the conductive line 104 from top to bottom in the view. The dielectric material 108 may be adjacent to at least a portion of the channel material 106 (e.g., on its sidewalls). The dielectric material 108 may also include a portion adjacent to (e.g., covering) the conductive line 104. The dielectric material 108 may extend along the sidewalls of the channel material 106. In some embodiments, the upper portion of the dielectric material 108 is coplanar with the upper portion of the channel material 106.

[0032] The dielectric material 108 may comprise one or more electrically insulating materials, such as phosphosilicate glass (PSG), borosilicate glass, borosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride materials (e.g., silicon nitride (Si3N4)), oxynitrides (e.g., silicon oxynitride), another gate dielectric material, dielectric carbonitride material (e.g., silicon carbonitride (SiCN)), dielectric carbonoxynitride material (e.g., silicon carbonoxynitride (SiOCN)), or combinations thereof, another material, or combinations thereof. In some embodiments, the dielectric material 108 comprises silicon dioxide.

[0033] Conductive material 110 (e.g., gate electrode) Figure 1A The conductive material 110 may be adjacent to a portion of the dielectric material 108 (e.g., on its sidewalls). The conductive material 110 may be in direct contact with the dielectric material 108 (e.g., in direct contact with its sidewalls). In some embodiments, the dielectric material 108 extends further from the conductive line 104 than the conductive material 110. In other embodiments, the conductive material 110 extends substantially at the same level as the dielectric material 108. Reference Figure 1A and Figure 1B The conductive material 110 may be located on both sides of the transistor 150. In some such embodiments, the transistor 150 may include a so-called "dual-gate" transistor. However, this disclosure is not limited thereto, and the conductive material 110 may be located on only one side of the transistor 150. In some such embodiments, the transistor 150 may include a so-called "single-gate" transistor.

[0034] The conductive material 110 may include conductive materials such as tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, gold, metal alloys, and metallic materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides), including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and iridium oxide (IrO). x ), Ruthenium oxide (RuO) x Materials comprising at least one of the following alloys: conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.), polycrystalline silicon, other materials exhibiting conductivity, or combinations thereof.

[0035] As described above, the channel material 106 can extend along the sidewalls of the dielectric material 108 into a portion of the conductive line 104. Figure 1A and Figure 1BIn the cross-sectional view illustrated herein, the channel material 106 may have a generally U-shaped cross-section. In some embodiments, the channel material 106 includes sidewalls extending along the dielectric material 108, the sidewalls defining openings. In some such embodiments, the sidewalls of the channel material 106 may be separated from each other (e.g., spaced apart). As will be described herein, the openings between the sidewalls of the channel material 106 may include a passivation material 112. In other words, the passivation material 112 may separate different portions of the channel material 106 from each other (e.g., spaced apart).

[0036] The channel material 106 can contact the conductive line 104 in three dimensions. For example, the channel material 106 can contact the conductive line 104 along its lateral surface (e.g., in the xy plane) and along its vertical surface (sidewalls) (e.g., in the xz and yz planes). In contrast, the channel material of a conventional microelectronic device only contacts the conductive line or conductive contact along its lateral surface.

[0037] The channel material 106 may extend a distance D1 within the conductive line 104. The distance D1 can be customized to adjust the contact area between the channel material 106 and the conductive line 104. For example, for a given area of ​​the channel material 106 in the xy plane, increasing the distance D1 increases the contact area between the channel material 106 and the conductive line 104. The distance D1 may range from about 0.5 nm to about 40 nm, for example, from about 0.5 nm to about 1 nm, from about 1 nm to about 5 nm, from about 5 nm to about 10 nm, from about 10 nm to about 15 nm, from about 15 nm to about 20 nm, from about 20 nm to about 30 nm, or from about 30 nm to about 40 nm. However, this disclosure is not limited thereto, and the distance D1 may differ from those examples described. In some embodiments, the distance D1 is in the range of about 10 nm to about 30 nm. In some embodiments, the distance D1 is 0, and the lower portion of the channel material 106 is coplanar with the upper portion of the conductive line 104.

[0038] The distance D3 between the relatively outer sidewalls of the channel material 106 along the x-direction is approximately... Up to about 20nm, for example from about To date From the agreement The distance is within the range of about 2 nm, from about 2 nm to about 5 nm, from about 5 nm to about 10 nm, from about 10 nm to about 15 nm, or from about 15 nm to about 20 nm. In some embodiments, the distance D3 corresponds to the diameter of the channel material 106 from one sidewall in contact with the dielectric material 108 to the opposite sidewall in contact with the dielectric material 108. In some embodiments, the distance D3 corresponds to the distance between the opposite sidewalls of the dielectric material 108.

[0039] The channel material 106 may include a material configured to conduct current in response to a suitable voltage (e.g., threshold voltage, bias voltage set, read bias voltage) applied to the vertical transistor 150.

[0040] In some embodiments, the channel material 106 comprises a semiconducting material having a larger band gap (e.g., a band gap greater than about 1.65 electron volts (eV)) compared to polycrystalline silicon, and may be referred to herein as a so-called "large band gap material". For example, the channel material 106 may comprise an oxide semiconductor material, such as one or more of the following: zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO) x Indium gallium zinc oxide (IGZO), indium gallium silicon oxide (IGSO), indium oxide (InO) x In2O3), tin oxide (SnO2), titanium oxide (TiO2) x ), Zinc oxide (Zn) x O y N z ), magnesium zinc oxide (Mg x Zn y O z Indium zinc oxide (In) x Zn y O z Indium gallium zinc oxide (In) x Ga y Zn z O a Zirconia indium zinc (Zr) x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a ), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum tin indium zinc (Al x Sn y In z Zn a O d ), silicon indium zinc (Si) x In y Zn z O a ), Zinc tin oxide (Zn) x Sn y O z ), aluminum oxide zinc tin (Al x Zn y Snz O a Gallium zinc tin oxide (Ga) x Zn y Sn z O a Zirconia zinc tin (Zr) x Zn y Sn z O a Indium gallium silicon oxide (InGaSiO), indium tungsten oxide (IWO), combinations thereof, and other similar materials. In some embodiments, the channel material 106 comprises IGZO. The channel material 106 may, for example, comprise a ternary oxide containing atoms of two different elements and an oxygen atom. In other embodiments, the channel material 106 comprises a quaternary oxide containing atoms of three different elements and an oxygen atom.

[0041] In other embodiments, the channel material 106 includes silicon, n-doped silicon (e.g., silicon doped with one or more of arsenic ions, phosphorus ions, and antimony ions), p-doped silicon (e.g., silicon doped with a p-type dopant such as boron), polycrystalline silicon, n-doped polycrystalline silicon, and p-doped polycrystalline silicon.

[0042] In yet another embodiment, the channel material 106 includes a so-called "2D channel material". By way of non-limiting examples, the 2D channel material may comprise one or more of the following: a transition metal dichalcogenide (TMDC) having the general chemical formula Mx2, wherein M is a transition metal (e.g., molybdenum (Mo), tungsten (W), niobium (Nb), zirconium (Zr), hafnium (Hf), rhenium (Re), platinum (Pt), titanium (Ti), tantalum (Ta), vanadium (V), cobalt (Co), cadmium (Cd), chromium (Cr)) and X is a chalcogenide (e.g., sulfur (S), selenium (Se), tellurium (Te)); having the general chemical formula Mx2; n+1 X n(Also known as "MXene") and contains carbides or carbonitrides terminated by oxygen (-O) hydroxyl (-OH) or fluorine (-F) surfaces, where M is a transition metal from group IV or V of the periodic table (e.g., Ti, Hf, Zr, V, Nb, Ta) and X is selected from carbon (C) and nitrogen (N); graphene; graphene oxide; stanine; phosphorene; hexagonal boron nitride (h-BN); borographene; silicene; graphene; germanene; germanane; 2D supracrystal; and monolayer semiconducting materials. In some embodiments, the channel material 106 comprises one or more TMDC monolayers, such as one or more monolayers of the following: tungsten sulfide (WS2), tungsten selenide (WSe2), tungsten telluride (WTe2), molybdenum sulfide (MoS2), molybdenum selenide (MoSe2), molybdenum telluride (MoTe2), niobium sulfide (NbS2), niobium selenide (NbSe2), niobium telluride (NbTe2), zirconium sulfide (ZrS2), zirconium selenide (ZrSe2), zirconium telluride (ZrTe2), hafnium sulfide (HfS2), hafnium selenide (HfSe2), hafnium telluride (ZrTe2), rhenium sulfide (ReS2), rhenium selenide (ReSe2), and rhenium telluride (ReTe2). By way of non-limiting examples, the channel material 106 may include one or more of WS2, WSe2, MoS2, and MoSe2. In some embodiments, the channel material 106 is WSe2. In additional embodiments, the channel material 106 is WS2. In yet another embodiment, the channel material 106 is MoSe2.

[0043] Refer again Figure 1A and Figure 1B The passivation material 112 may be located between portions of the channel material 106. In some embodiments, the interface between the passivation material 112 and the channel material 106 is below the interface between the conductive line 104 and the dielectric material 108 (e.g., located closer to the substrate material 102). The passivation material 112 and the channel material 106 may extend into the conductive line 104.

[0044] Passivation material 112 can be formulated and configured to alter the energy of the trap states of channel material 106 and reduce the off-state current of channel material 106. Without being bound by any specific theory, passivation material 112 can passivate the deep donor states of channel material 106 by reducing the concentration of such states, thereby promoting improvements in the off-state current of transistor 150 and reducing off-state current leakage of transistor 150.

[0045] Passivation material 112 may comprise dielectric materials such as yttrium oxide, silicon dioxide, aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HfO2), and silicon nitride (Si). x N y The passivation material 112 comprises one or more of silicon oxynitride (SiON) and silicon oxycarbide (SiOC). In some embodiments, the passivation material 112 comprises yttrium oxide (Y2O3). In some such embodiments, the channel material 106 may comprise an oxide semiconductor, such as IGZO. In other embodiments, the channel material 106 comprises polycrystalline silicon and the passivation material 112 comprises one or more of, for example, silicon dioxide, aluminum oxide, zirconium oxide, hafnium oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide.

[0046] A conductive contact 114 (also referred to as an electrode) may be adjacent to the channel material 106. The conductive contact 114 may overlay on and contact the channel material 106. The conductive contact 114 may include a first portion 116 located between two laterally adjacent portions of the channel material 106 and a second portion 118 located above the first portion 116, the channel material 106, the dielectric material 108, and the passivation material 112. The first portion 116 may extend along and contact the opposing sidewalls of the channel material 106. In other words, the first portion 116 may separate the opposing sidewalls of the channel material 106 from each other. In other words, the first portion 116 may extend vertically (e.g., along the z-direction) and contact the sidewalls of the channel material 106 between opposing sidewalls. The conductive contact 114 may contact the channel material 106 in three dimensions. For example, conductive contact 114 may contact channel material 106 along the transverse surface (e.g., in the xy plane) and along the vertical surface (sidewall) (e.g., in the xz and yz planes) of channel material 106. In some embodiments, first portion 116 contacts channel material 106 and passivation material 112.

[0047] The first portion 116 may extend into the channel material 106 to a distance D2. The distance D2 may range from about 0.5 nm to about 40 nm, for example, from about 0.5 nm to about 1 nm, from about 1 nm to about 5 nm, from about 5 nm to about 10 nm, from about 10 nm to about 15 nm, from about 15 nm to about 20 nm, from about 20 nm to about 30 nm, or from about 30 nm to about 40 nm. However, this disclosure is not so limited and the distance D2 may differ from those examples described. In some embodiments, the distance D2 is in the range of about 10 nm to about 30 nm. In some embodiments, the distance D2 is approximately equal to the distance D1. In other embodiments, the distance D2 is greater than the distance D1. In still other embodiments, the distance D2 is less than the distance D1. In some embodiments, the distance D2 is 0 and the conductive contact 114 does not include the first portion 116 extending into the channel material 106.

[0048] The second portion 118 may be adjacent to (e.g., overlaid on) the first portion 116 and may be located at a distance from the conductive line 104 relative to the first portion 116. The second portion 118 may contact each of the first portion 116, the channel material 106, and the dielectric material 108.

[0049] The conductive contact 114 (e.g., the first portion 116 and the second portion 118) may comprise a conductive material. For example, the conductive contact 114 may comprise tungsten, titanium, niobium, vanadium, hafnium, tantalum, chromium, zirconium, iron, osmium, cobalt, nickel, iridium, platinum, palladium, ruthenium, rhodium, aluminum, copper, molybdenum, gold, metal alloys, metallic materials (e.g., metal nitrides (titanium nitride, tantalum nitride, tungsten nitride, aluminum titanium nitride), metal silicides (tantalum silicide, tungsten silicide, nickel silicide, titanium silicide), metal carbides, metal oxides (iridium oxide, ruthenium oxide), conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.), polycrystalline silicon, other materials exhibiting conductivity, or combinations thereof. In some embodiments, the conductive contact 114 and the conductive wire 104 comprise the same material composition. In some embodiments, the conductive contact 114 comprises tungsten.

[0050] Channel material 106 may include a semiconductor material formulated and configured to respond to a suitable voltage (e.g., a threshold voltage V). t Conductivity is exhibited by applying a conductive material 106 (e.g., between the conductive material 110 and the source region (e.g., conductive line 104)) to the transistor 150. In some embodiments, the channel material 106 is electrically connected to the conductive line 104 and the conductive contact 114. In some embodiments, the conductive line 104 and the conductive contact 114 may each be referred to herein as a so-called source contact or a so-called drain contact, respectively. In some such embodiments, the channel material 106 is electrically connected to each of the source and drain regions of the transistor 150.

[0051] Electrically insulating material 122 may surround transistor 150 and electrically isolate adjacent transistors 150 from each other. Electrically insulating material 122 may comprise, for example, phosphosilicate glass, borosilicate glass, borosilicate-phosphosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, nitride materials (e.g., silicon nitride (Si3N4)), oxynitrides (e.g., silicon oxynitride, another dielectric material, dielectric carbonitride material (e.g., silicon carbonitride (SiCN)), dielectric carbonoxynitride material (e.g., silicon carbonoxynitride (SiOCN)) or combinations thereof. In some embodiments, electrically insulating material 122 comprises silicon dioxide. In some embodiments, electrically insulating material 122 and dielectric material 108 comprise the same material.

[0052] In use and operation, passivation material 112 helps reduce the turn-off current of transistor 150. Passivation material 112 can passivate defects (e.g., deep traps, deep donors) within channel material 106 and reduce the concentration of subgap states within channel material 106 and reduce or prevent subgap states and leakage in channel material 106.

[0053] Forming a channel material 106 that is at least partially surrounded by conductive lines 104 and forming a first portion 116 of conductive contacts 114 within the channel material 106 can promote a reduction in contact resistance between the channel material 106 and corresponding portions of the conductive lines 104 and conductive contacts 114. Therefore, the lateral footprint of the transistor 150 can be reduced while increasing or maintaining the contact area between the channel material 106 and the conductive material adjacent to the channel material 106. Increased contact area reduces the contact resistance between the channel material 106 and the conductive material, thereby improving the speed and performance of the transistor.

[0054] Although Figure 1A and Figure 1B It has been described and illustrated as including conductive material 110 on both sides of transistor 150, but this disclosure is not limited thereto. Figure 2 This is a simplified planar cross-sectional view of transistor 250. Transistor 250 may include a conductive material 110 that substantially surrounds (e.g., encircles) all its sides. Transistor 250 may include a channel material 106 surrounding a passivation material 112, a dielectric material 108 surrounding the channel material 106, and a conductive material 110 surrounding the dielectric material 108. Because the conductive material 110 substantially surrounds all of the dielectric material 108, transistor 350 includes a so-called "gate-all-around" (GAA) transistor.

[0055] In other embodiments, the conductive material 110 may be located on three sides of the dielectric material 108. In some such embodiments, the transistor may include a so-called "triple-gate" or "tri-gate" transistor. In yet another embodiment, the conductive material 110 may be located on only one side of the transistor 150 and the transistor 150 may include a single-gate transistor.

[0056] Therefore, in at least some embodiments, the microelectronic device includes a transistor adjacent to a conductive line. The transistor includes a channel material extending into and contacting the conductive line, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further includes conductive contacts adjacent to the channel material, the conductive contacts comprising portions extending between opposing portions of the channel material.

[0057] Therefore, in some embodiments, the microelectronic device includes a transistor comprising a channel material extending into a conductive line, a passivation material located between different portions of the channel material, a dielectric material adjacent to the channel material, and a conductive material adjacent to the dielectric material, the dielectric material being situated between the channel material and the conductive material.

[0058] Therefore, in some embodiments, the microelectronic device includes a conductive line, a passivation material adjacent to the conductive line, a channel material including an oxide semiconductor adjacent to and in contact with the opposite side of the passivation material, a dielectric material in contact with the channel material, and a conductive material adjacent to the dielectric material.

[0059] Figures 3A to 3F Explanation of the formation of embodiments according to this disclosure Figure 1A and Figure 1B Method for a microelectronic device 100. (See reference) Figure 3A The microelectronic device 300 may include a structure 350 adjacent to (e.g., above) the substrate material 302. The substrate material 302 may contain the same material described above with reference to substrate material 102.

[0060] Structure 350 may include a dielectric material 308, a conductive material 310, and an electrically insulating material 322 adjacent to (e.g., above) the conductive line 304. The conductive line 304 may include one or more of the materials described above with reference to conductive line 104, and the dielectric material 308 may include one or more of the materials described above with reference to dielectric material 108. The conductive material 310 may be adjacent to the dielectric material 308. The conductive material 310 may include one or more of the materials described above with reference to conductive material 110. The electrically insulating material 322 may include one or more of the materials described above with reference to electrically insulating material 122 and may electrically isolate adjacent structures 350 from each other. In some embodiments, structure 350 is formed using conventional techniques.

[0061] Sacrificial material 305 may be formed between portions of dielectric material 308, such as between opposing sidewalls of dielectric material 308. Sacrificial material 305 may comprise one or more of, for example, polysilicon, silicon nitride, silicon oxynitride, and polymeric materials (e.g., poly(p-xylene) polymers, such as poly(p-xylene)). In some embodiments, sacrificial material 305 comprises polysilicon.

[0062] refer to Figure 3B Removable (e.g., etching, excavation) sacrificial material 305 ( Figure 3A An opening 307 is formed, exposing a portion of the conductive line 304 and the sidewalls of the dielectric material 308. The opening 307 may be defined by the sidewalls of the dielectric material 308 and the upper surface of the conductive line 304. By means of a non-limiting example, the sacrificial material 305 may be exposed to one or more of nitric acid, hydrofluoric acid, water, and tetramethylammonium hydroxide (TMAH) to remove the sacrificial material 305 and form the opening 307. In other embodiments, the sacrificial material 305 is removed by dry etching, for example by exposing the sacrificial material 305 to one or more of a plasma comprising chlorine, hydrobromic acid, oxygen, and sulfur hexafluoride (SF6).

[0063] refer to Figure 3C A portion of the conductive wire 304 can be removed to extend the opening 307 into the conductive wire 304. Removing a portion of the conductive wire 304 allows the opening 307 to extend a distance D1 from the interface 311 between the conductive wire 304 and the dielectric material 308. The extended opening 307 can be defined by the sidewalls of the dielectric material 308, the exposed sidewalls of the conductive wire 304, and the exposed upper surface of the conductive wire 304.

[0064] A portion of the conductive line 304 may be removed by, for example, dry etching (e.g., reactive ion etching (RIE)), wet etching, or by another method. By way of non-limiting examples, a portion of the conductive line 304 may be removed by exposing the exposed portion of the conductive line 304 to one or more of hydrofluoric acid, nitric acid, ammonium hydroxide and hydrogen peroxide, sulfuric acid, and hydrochloric acid. In other embodiments, a portion of the conductive line 304 may be removed by exposing the exposed portion of the conductive line 304 to one or more of sulfur hexafluoride, carbon tetrafluoride (CF4), bromotrifluoromethane (CBrF3), trifluoromethane (CHF3), oxygen, and nitrogen trifluoride (NF3). However, this disclosure is not limited thereto, and portions of the conductive line 304 may be removed by methods other than those described.

[0065] In some embodiments, after a portion of the conductive line 304 is removed, the microelectronic device 300 may be exposed to cleaning chemicals to remove conductive material that may have been re-sputtered onto the surface (e.g., sidewalls) of the dielectric material 308 during the removal of the portion of the conductive line 304. A portion of the dielectric material 308 may also be removed by cleaning chemicals, and additional portions of the dielectric material 308 may be reformed to promote a generally clean dielectric material 308.

[0066] refer to Figure 3D The channel material 306 may be formed within the opening 307, for example, along the sidewall of the opening 307 and above the exposed surface of the conductive line 304. Forming the channel material 306 within the opening 307 may not significantly fill the opening 307. In other words, portions of the channel material 306 on opposite sidewalls of the opening 307 may be separated from each other (e.g., spaced apart) so that the channel material 306 has a generally U-shaped cross-section. The channel material 306 may be formed by one or more of ALD, CVD, PEALD, PVD, PECVD, and LPCVD.

[0067] The channel material 306 may comprise one or more of the materials described above with reference to channel material 106. In some embodiments, the channel material 306 comprises an oxide semiconductor material, such as IGZO.

[0068] The channel material 306 can contact the conductive line 304 in three dimensions. For example, the channel material 306 can contact the vertical sidewalls of the conductive line 304 and also along the interface 311 between the dielectric material 308 and the conductive line 304. Figure 3C The generally parallel surface contacts the conductive lines 304. In some embodiments, the channel material 306 contacts the conductive lines 304 in three dimensions.

[0069] refer to Figure 3E After the channel material 306 is formed, the passivation material 312 can be formed inside the channel material 306 and the opening 307. Figure 3D The passivation material 312 may at least partially fill the opening 307. In some embodiments, the passivation material 312 may substantially fill the opening 307 and may include an upper surface coplanar with the upper surface of the channel material 306, which may also be coplanar with the upper surface of the insulating material 322, as indicated by the dashed line 313. The passivation material 312 may be formed by one or more of ALD, CVD, PEALD, PVD, PECVD, and LPCVD.

[0070] The passivation material 312 may comprise one or more of the materials described above with reference to passivation material 112. In some embodiments, the passivation material 312 comprises yttrium oxide.

[0071] After the passivation material 312 is formed, the upper portion of the passivation material 312 can be removed to make the passivation material 312 recessed and to form an opening 309 between the opposing sidewalls of the channel material 306. Recessing the passivation material 312 leaves an exposed surface of the passivation material 312 between the opposing sidewalls of the channel material 306 within the opening 309. The passivation material 312 can be recessed a distance D2 from the main surface of the electrical insulating material 322.

[0072] The upper portion of the passivation material 312 can be removed, for example, by exposing the passivation material 312 to one or more plasmas including carbon tetrafluoride and oxygen, boron trichloride (BCl3), hydrobromic acid gas, and chlorine. In other embodiments, the upper portion of the passivation material 312 can be removed, for example, by exposing the passivation material 312 to one or more of hydrochloric acid, nitric acid, and sulfuric acid. However, this disclosure is not limited thereto, and the upper portion of the passivation material 312 can be removed by methods other than those described above.

[0073] refer to Figure 3F In some embodiments, additional electrical insulating material 322 may be formed and patterned over the microelectronic device 300, for example over an exposed portion of the electrical insulating material 322.

[0074] Conductive contacts 314 may be formed over the recessed passivation material 312, channel material 306, and dielectric material 308 of the microelectronic device 300 to form a transistor 360. In some embodiments, the conductive contact 314 includes a substantially filled opening 309. Figure 3E The first portion 316 and the second portion 318 located above the first portion 316 and above the opening 309. The conductive contact 314 may be formed by one or more of ALD, CVD, PEALD, PVD, PECVD and LPCVD.

[0075] The conductive contact 314 may comprise one or more of the materials described above with reference to the conductive contact 114. In some embodiments, the conductive contact 314 comprises tungsten.

[0076] After the conductive contact 314 is formed over the microelectronic device 300, the microelectronic device 300 may be exposed to a chemical mechanical planarization process to planarize the upper surface of the electrically insulating material 322 and the conductive contact 314 (e.g., the upper surface of the second portion 318).

[0077] A microelectronic device 300 comprising a channel material 306 extending (e.g., vertically) into the conductive line 304 and including a first portion 316 extending (e.g., vertically) along the sidewalls of the channel material 306 and containing conductive contacts 314, helps to increase the contact area between the channel material 306 and each of the conductive line 304 and conductive contacts 314. For example, the channel material 306 may exhibit an increased contact area with the conductive line 304, as indicated by dashed circle 315, and an increased contact area with the conductive contacts 314, as indicated by dashed circle 317. Compared to the contact area of ​​a conventional transistor formed with the same spacing and footprint, the microelectronic device 300 according to embodiments of the present disclosure may exhibit approximately three times the increased contact area. Of course, the contact area may depend on depths D1 and D2. The increased contact area can facilitate an improvement (e.g., a reduction) in the contact resistance between the channel material 306 and each of the conductive line 304 and conductive contacts 314. Reducing contact resistance can improve the operating speed of a transistor.

[0078] Furthermore, forming a passivation material 312 between opposing portions of the U-shaped channel material 306 can reduce the transistor's turn-off current. Without any theoretical limitations, it is believed that the passivation material 312 passivates defects (e.g., deep traps, deep donors) within the channel material 306 and reduces the concentration of subgap states within the channel material 306, thereby reducing or preventing subgap states and leakage in the channel material 306.

[0079] After the conductive contact 314 is formed, the microelectronic device 300 can be further processed, for example, by forming a memory element electrically connected to the conductive contact 314. As just one example, a capacitor structure (not shown) may be formed above and electrically connected to the conductive contact 314. In some such embodiments, the conductive contact 314 may be electrically connected to, for example, an electrode of the capacitor structure. A dielectric material may be formed adjacent to an electrode, and another electrode may be formed adjacent to the dielectric material. However, this disclosure is not limited thereto, and structures other than or in conjunction with the capacitor structure may be formed electrically connected to the conductive contact 314.

[0080] Therefore, in at least some embodiments, the method of forming a microelectronic device includes removing sacrificial material between adjacent portions of dielectric material to form an opening and exposing conductive lines through the opening, removing a portion of the conductive lines through the opening, forming a channel material in contact with the conductive lines within the opening, forming a passivation material adjacent to the channel material, and forming conductive contacts adjacent to the channel material and the passivation material.

[0081] Microelectronic devices (e.g., microelectronic devices 100, 300) including transistors (e.g., transistors 150, 250, 350) according to embodiments of the present disclosure can be used in embodiments of the electronic systems of the present disclosure. For example, Figure 4This is a block diagram of an illustrative electronic system 403 according to embodiments of the present disclosure. Electronic system 403 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, Wi-Fi, or a cellular-enabled tablet computer (e.g.,...). or Tablet computers, e-books, navigation devices, etc. Electronic system 403 includes at least one memory device 405. Memory device 405 may include embodiments of microelectronic devices (e.g., microelectronic devices 100, 300) previously described herein, comprising a channel material (e.g., channel material 106, 306) and a passivation material adjacent to the channel material (e.g., passivation material 112, 312).

[0082] Electronic system 403 may additionally include at least one electronic signal processor device 407 (generally referred to as a “microprocessor”). Electronic signal processor device 407 may optionally include embodiments of the microelectronic devices (e.g., microelectronic devices 100, 300) previously described herein. Electronic system 403 may additionally include one or more input devices 409 for inputting information into electronic system 403 by a user, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. Electronic system 403 may additionally include one or more output devices 411 for outputting information (e.g., visual or audio output) to a user, such as a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, input device 409 and output device 411 may include a single touchscreen device available for inputting information into electronic system 403 and outputting visual information to a user. Input device 409 and output device 411 may be electrically connected to one or more of memory device 405 and electronic signal processor device 407.

[0083] refer to Figure 5 The present invention describes a processor-based system 500. The processor-based system 500 may include various electronic devices (e.g., microelectronic devices 100, 300) manufactured according to embodiments of the present disclosure. The processor-based system 500 may be any of a variety of types, such as a computer, pager, cellular phone, personal assistant, control circuitry, or other electronic device. The processor-based system 500 may include one or more processors 502, such as microprocessors, to control system functions and request processing within the processor-based system 500. The processor 502 and other sub-components of the processor-based system 500 may include microelectronic devices (e.g., microelectronic devices 100, 300) manufactured according to embodiments of the present disclosure.

[0084] The processor-based system 500 may include a power supply 504 operatively connected to the processor 502. For example, if the processor-based system 500 is a portable system, the power supply 504 may include one or more of a fuel cell, a power harvesting device, a permanent battery, a replaceable battery, and a rechargeable battery. For example, the power supply 504 may also include an AC adapter; thus, the processor-based system 500 can be plugged into a wall outlet. For example, the power supply 504 may also include a DC adapter, allowing the processor-based system 500 to be plugged into a vehicle cigarette lighter or a vehicle power port.

[0085] Various other devices may be coupled to processor 502 depending on the functions performed by processor-based system 500. For example, user interface 506 may be coupled to processor 502. User interface 506 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. Display 508 may also be coupled to processor 502. Display 508 may include LCD displays, SED displays, CRT displays, DLP displays, plasma displays, OLED displays, LED displays, 3D projections, audio displays, or combinations thereof. Furthermore, RF subsystem / baseband processor 510 may also be coupled to processor 502. RF subsystem / baseband processor 510 may include antennas coupled to RF receivers and RF transmitters (not shown). Communication port 512 or more may also be coupled to processor 502. For example, communication port 512 may be adapted to couple to one or more peripheral devices 514 (e.g., modem, printer, computer, scanner, or camera) or to a network (e.g., local area network, remote area network, corporate intranet, or Internet).

[0086] Processor 502 can control processor-based system 500 by implementing software programs stored in memory. For example, the software programs may include operating systems, database software, graphics software, word processing software, media editing software, or media playback software. Memory is operatively coupled to processor 502 to store and facilitate the execution of various programs. For example, processor 502 may be coupled to system memory 516, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, and other known memory types. System memory 516 may include volatile memory, non-volatile memory, or combinations thereof. System memory 516 is typically large enough to dynamically store loaded application programs and data. In some embodiments, system memory 516 may include semiconductor devices, such as the microelectronic devices described above (e.g., microelectronic devices 100, 300), or combinations thereof.

[0087] Processor 502 may also be coupled to non-volatile memory 518, which does not imply that system memory 516 is necessarily volatile. Non-volatile memory 518 may include one or more of the following: STT-MRAM, MRAM, read-only memory (ROM) such as EPROM, resistive read-only memory (RROM), and flash memory to be used in conjunction with system memory 516. The size of non-volatile memory 518 is typically chosen to be sufficient to store only the necessary operating system, applications, and fixed data. Furthermore, for example, non-volatile memory 518 may include mass storage such as disk drive memory, such as a hybrid drive containing resistive memory, or other types of non-volatile solid-state memory. Non-volatile memory 518 may include microelectronic devices, such as the microelectronic devices described above (e.g., microelectronic devices 100, 300), or combinations thereof.

[0088] Therefore, in some embodiments, the electronic device includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device. The memory device includes a channel material extending along a conductive line, a passivation material within an adjacent portion of the channel material, a dielectric material adjacent to the channel material, and a conductive material adjacent to the dielectric material.

[0089] Additional non-limiting example embodiments of this disclosure are described below.

[0090] Example 1: A microelectronic device comprising: a transistor adjacent to a conductive line, the transistor including: a channel material extending into and in contact with the conductive line; a dielectric material adjacent to the channel material; a conductive material adjacent to the dielectric material; a passivation material adjacent to the channel material; and a conductive contact adjacent to the channel material, the conductive contact comprising a portion extending between opposing portions of the channel material.

[0091] Example 2: The microelectronic device according to Example 1, wherein the passivation material is located between the opposing portions of the channel material.

[0092] Example 3: The microelectronic device according to Example 1 or Example 2, wherein the channel material is located between the passivation material and the dielectric material.

[0093] Example 4: A microelectronic device according to any one of Examples 1 to 3, wherein the passivation material comprises yttrium oxide.

[0094] Example 5: A microelectronic device according to any one of Examples 1 to 4, wherein the channel material comprises an oxide semiconductor material.

[0095] Example 6: A microelectronic device according to any one of Examples 1 to 5, wherein the conductive contact is in contact with the passivation material.

[0096] Example 7: A microelectronic device according to any one of Examples 1 to 6, wherein the channel material extends into the conductive line to a depth ranging from about 10 nm to about 30 nm.

[0097] Example 8: A microelectronic device according to any one of Examples 1 to 7, wherein the portion of the conductive line extending between opposite portions of the channel material extends into the channel material to a depth ranging from about 10 nm to about 30 nm.

[0098] Example 9: A microelectronic device according to any one of Examples 1 to 8, wherein the interface between the passivation material and the channel material is lower than the interface between the conductive line and the dielectric material.

[0099] Example 10: A microelectronic device comprising: a transistor including a channel material extending into a conductive line; a passivation material located between different portions of the channel material; a dielectric material adjacent to the channel material; and a conductive material adjacent to the dielectric material, the dielectric material being located between the channel material and the conductive material.

[0100] Example 11: The microelectronic device according to Example 10 further includes conductive contacts adjacent to the channel material.

[0101] Example 12: A microelectronic device according to Example 10 or Example 11, wherein the conductive material includes at least two interfaces with the channel material.

[0102] Example 13: A microelectronic device according to any one of Examples 10 to 12, wherein the passivation material comprises yttrium oxide.

[0103] Example 14: A microelectronic device according to any one of Examples 10 to 13, wherein the conductive material surrounds the dielectric material.

[0104] Example 15: A microelectronic device according to any one of Examples 10 to 14, wherein the channel material contacts the conductive wire in a first plane and a second plane intersecting the first plane.

[0105] Example 16: A method of forming a microelectronic device, the method comprising: removing sacrificial material between adjacent portions of a dielectric material to form an opening and exposing a conductive wire through the opening; removing a portion of the conductive wire through the opening; forming a channel material in contact with the conductive wire within the opening; forming a passivation material adjacent to the channel material; and forming a conductive contact adjacent to the channel material and the passivation material.

[0106] Example 17: According to the method of Example 16, forming a conductive contact adjacent to the channel material includes forming the conductive contact in contact with the sidewall of the channel material.

[0107] Example 18: The method according to Example 16 or Example 17 further includes recessing a portion of the passivation material before forming the conductive contact adjacent to the channel material and the passivation material.

[0108] Example 19: The method according to Example 18, wherein recessing a portion of the passivation material includes removing a portion of the passivation material relative to the channel material.

[0109] Example 20: The method according to any one of Examples 16 to 19, wherein: forming the channel material includes forming a channel material comprising an oxide semiconductor; and forming the passivation material includes forming yttrium oxide.

[0110] Example 21: The method according to any of Examples 16 to 20, wherein forming a passivation material adjacent to the channel material includes forming the passivation material between opposite portions of the channel material.

[0111] Example 22: The method according to any of Examples 16 to 21, wherein forming a conductive contact adjacent to the channel material and the passivation material includes forming a first portion of the conductive contact between opposing portions of the channel material and a second portion of the conductive contact above the channel material.

[0112] Example 23: A microelectronic device comprising: a conductive line; a passivation material adjacent to the conductive line; a channel material comprising an oxide semiconductor adjacent to and in contact with opposite sides of the passivation material; a dielectric material in contact with the channel material; and a conductive material adjacent to the dielectric material.

[0113] Example 24: The microelectronic device according to Example 23, wherein the passivation material comprises yttrium oxide.

[0114] Example 25: A microelectronic device according to Example 23 or Example 24, wherein the channel material extends into the conductive line and contacts the conductive line in at least two planes.

[0115] Example 26: An electronic device comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising: a channel material extending along a conductive line; a passivation material located in an adjacent portion of the channel material; a dielectric material adjacent to the channel material; and a conductive material adjacent to the dielectric material.

[0116] Example 27: The electronic device according to Example 26 further includes a conductive contact that contacts the sidewall of the adjacent portion of the channel material.

[0117] While certain illustrative embodiments have been described in conjunction with the drawings, those skilled in the art will recognize and understand that the embodiments included in this disclosure are not limited to those explicitly shown and described herein. Rather, various additions, deletions, and modifications can be made to the embodiments described herein without departing from the scope of the embodiments encompassed by this disclosure (such as those claimed herein, including legal equivalents). Furthermore, features of one disclosed embodiment may be combined with features of another disclosed embodiment while still being included within the scope of this disclosure.

Claims

1. A microelectronic device comprising: The transistor adjacent to the conductive line, the transistor comprising: A channel material extending into the conductive wire, the channel material being in direct contact with the conductive wire in three dimensions; Dielectric material adjacent to the channel material; A conductive material adjacent to the dielectric material; and Passivation material adjacent to the channel material; and A conductive contact adjacent to the channel material, the conductive contact being included in a portion extending between opposing portions of the channel material.

2. The microelectronic device of claim 1, wherein the passivation material is located between the opposing portions of the channel material.

3. The microelectronic device of claim 1, wherein the channel material is located between the passivation material and the dielectric material.

4. The microelectronic device according to claim 1, wherein the passivation material comprises yttrium oxide.

5. The microelectronic device of claim 4, wherein the channel material comprises an oxide semiconductor material.

6. The microelectronic device according to any one of claims 1 to 5, wherein the conductive contact is in contact with the passivation material.

7. The microelectronic device according to any one of claims 1 to 5, wherein the channel material extends into the conductive line to a depth ranging from 10 nm to 30 nm.

8. The microelectronic device according to any one of claims 1 to 5, wherein the portion of the conductive line extending between opposite portions of the channel material extends into the channel material to a depth ranging from 10 nm to 30 nm.

9. The microelectronic device according to any one of claims 1 to 5, wherein the interface between the passivation material and the channel material is lower than the interface between the conductive line and the dielectric material.

10. A microelectronic device comprising: Transistor, comprising: A channel material extending into the conductive wire, the channel material directly contacting the conductive wire in a first plane and a second plane intersecting the first plane; Passivation material located between different portions of the channel material; Dielectric material adjacent to the channel material; and A conductive material adjacent to the dielectric material, wherein the dielectric material is located between the channel material and the conductive material.

11. The microelectronic device of claim 10, further comprising a conductive contact adjacent to the channel material.

12. The microelectronic device of claim 10, wherein the conductive material comprises at least two interfaces with the channel material.

13. The microelectronic device of claim 10, wherein the passivation material comprises yttrium oxide.

14. The microelectronic device of claim 10, wherein the conductive material surrounds the dielectric material.

15. A method of forming a microelectronic device, the method comprising: Sacrificial material between adjacent portions of dielectric material is removed to form an opening and the conductive wire is exposed through the opening; A portion of the conductive wire is removed through the opening; A channel material is formed within the opening, the channel material extending into the conductive wire and directly contacting the conductive wire in three dimensions; A passivation material is formed adjacent to the channel material; and A conductive contact is formed adjacent to the channel material and the passivation material.

16. The method of claim 15, wherein forming a conductive contact adjacent to the channel material includes forming the conductive contact in contact with a sidewall of the channel material.

17. The method of claim 15, further comprising recessing a portion of the passivation material prior to forming the conductive contact adjacent to the channel material and the passivation material.

18. The method of claim 17, wherein recessing a portion of the passivation material comprises removing a portion of the passivation material relative to the channel material.

19. The method of claim 15, wherein: Forming a channel material includes forming a channel material comprising an oxide semiconductor; and The formation of passivating materials includes the formation of yttrium oxide.

20. The method according to any one of claims 15 to 19, wherein forming a passivation material adjacent to the channel material comprises forming the passivation material between opposing portions of the channel material.

21. The method according to any one of claims 15 to 19, wherein forming a conductive contact adjacent to the channel material and the passivation material comprises forming a first portion of the conductive contact between opposing portions of the channel material and a second portion of the conductive contact above the channel material.

22. A microelectronic device comprising: Conductive wire; Passivation material adjacent to the conductive line; A channel material adjacent to the opposite side of the passivation material, the channel material extending into the conductive line and directly contacting the conductive line in at least two planes, the channel material comprising an oxide semiconductor; Dielectric material in contact with the channel material; and A conductive material adjacent to the dielectric material.

23. The microelectronic device of claim 22, wherein the passivation material comprises yttrium oxide.

24. An electronic device comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; and A memory device operatively coupled to the processor device and comprising: A channel material extending into the conductive wire, the channel material being in direct contact with the conductive wire in three dimensions; Passivating material located in adjacent portions of the channel material; Dielectric material adjacent to the channel material; and A conductive material adjacent to the dielectric material.

25. The electronic device of claim 24, further comprising a conductive contact in contact with a sidewall of the adjacent portion of the channel material.

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