Task mapping, task processing method and processing core, electronic equipment

Abstract

The present disclosure provides a task mapping method, comprising: determining multiple layers of second matrices based on a first matrix, wherein each layer of the second matrix is ​​divided into at least one second sub-matrix; wherein the elements in the second matrix of the N+1th layer correspond one-to-one to multiple second sub-matrices of the Nth layer, and the second sub-matrix of the 1st layer is a sub-matrix of the first matrix; determining the operation instructions corresponding to each second sub-matrix; mapping at least one second sub-matrix in each layer of the second matrix and the operation instructions corresponding to the second sub-matrix to multiple processing cores in a many-core system, wherein each processing core corresponds to a second sub-matrix and a corresponding operation instruction, so that the processing core calculates the transpose of its corresponding second sub-matrix according to its corresponding operation instruction and stores the calculation result; wherein N is a positive integer. The present disclosure also provides a task processing method, a processing core, and an electronic device.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a task mapping method, a task processing method, a processing core, and an electronic device. Background Art

[0002] A sparse matrix is ​​one in which the number of zero elements far outnumbers the number of nonzero elements, and the nonzero elements are distributed irregularly. Sparse matrices are widely used in real life, particularly in high-performance computing and machine learning. For example, sparse matrices are used to encode data containing counts, map categories, and in subfields of machine learning such as natural language processing (NLP).

[0003] When performing operations such as transposition on a sparse matrix and storing the sparse matrix, it is necessary to store the values ​​of each element in the sparse matrix and its coordinates in the sparse matrix. However, in some related technologies, when the sparse matrix is ​​large, the sparse matrix requires more storage space and the computation is large, resulting in low efficiency of operations involving sparse matrices. Summary of the Invention

[0004] The present disclosure provides a task mapping method, a task processing method, a processing core, and an electronic device.

[0005] In a first aspect, the present disclosure provides a task mapping method, comprising:

[0006] Determining multiple layers of second matrices based on the first matrix, wherein each layer of the second matrix is ​​divided into at least one second sub-matrix; wherein elements in the second matrix of the N+1th layer correspond one-to-one to multiple second sub-matrices of the Nth layer, and the second sub-matrix of the first layer is a sub-matrix of the first matrix;

[0007] Determine the operation instructions corresponding to each second sub-matrix;

[0008] Mapping at least one second submatrix in each layer of the second matrix and a corresponding operation instruction of the second submatrix to multiple processing cores in the many-core system, each of the processing cores corresponding to one second submatrix and a corresponding budget instruction, so that the processing core calculates the transpose of the corresponding second submatrix according to the corresponding operation instruction and stores the calculation result;

[0009] Wherein, N is a positive integer.

[0010] In some embodiments, at least one second submatrix of each layer of the second matrix includes at least one non-zero second submatrix; and the step of mapping the at least one second submatrix in each layer of the second matrix and the operation instruction to multiple processing cores in the many-core system includes:

[0011] transmitting each non-zero second sub-matrix in each layer of the second matrix to the plurality of processing cores respectively;

[0012] The operation instructions corresponding to each non-zero second sub-matrix are configured into the plurality of processing cores.

[0013] In some embodiments, the processing core corresponding to the N-th layer second sub-matrix is ​​the N-th layer processing core; and the step of transmitting each non-zero second sub-matrix in each layer of the second matrix to the plurality of processing cores includes:

[0014] Transmitting the first-layer non-zero second submatrix in the first-layer second matrix to the first-layer processing core, so that the first-layer processing core calculates the transpose of its corresponding first-layer non-zero second submatrix;

[0015] The first correspondence between the N-th layer processing core and the first coordinate is transmitted to the N+1-th layer processing core, so that the N+1-th layer processing core determines the second correspondence between the N-th layer processing core and the second coordinate based on the first correspondence; the first coordinate is the coordinate of the element in the N+1-th layer second matrix corresponding to the N-th layer non-zero second submatrix in the N+1-th layer second matrix; the second coordinate is the coordinate of the element in the N+1-th layer second matrix corresponding to the N-th layer non-zero second submatrix in the transposed matrix of the N+1-th layer second matrix.

[0016] In some embodiments, the task mapping method further includes:

[0017] Determining the address of the storage space of each target calculation result in the off-chip storage according to the second corresponding relationship stored in each layer of processing cores; the target calculation result is the calculation result of calculating the transpose of the corresponding first-layer non-zero second submatrix calculated by the first-layer processing core and stored;

[0018] Control each first-layer processing core to write the target calculation result stored by the first-layer processing core into the off-chip storage according to the address of the storage space of the target calculation result stored by the first-layer processing core in the off-chip storage, wherein each of the target calculation results is spliced ​​into a transposed matrix of the first matrix in the off-chip storage.

[0019] In some embodiments, the step of determining the multi-layer second matrix according to the first matrix includes:

[0020] Determine a target size according to the size of the first matrix, where the target size is the size of the second sub-matrix of each layer;

[0021] A multi-layer second matrix is ​​determined according to the first matrix and the target size.

[0022] In some embodiments, the second sub-matrix of each layer is a square matrix.

[0023] In some embodiments, after the step of mapping at least one second sub-matrix in each layer of the second matrix and the operation instruction to multiple processing cores in the many-core system, the task mapping method further includes:

[0024] Determining a target processing core based on a mapping relationship between at least one second submatrix in the multi-layer second matrix and multiple processing cores in the many-core system; the target processing core is at least one of the multiple processing cores storing target data; the target data is a transposed matrix of a submatrix of the first matrix corresponding to task data of a task to be processed;

[0025] The task data is transmitted to the target processing core, so that the target processing core reads the target data and performs operations corresponding to the task data.

[0026] In some embodiments, at least one second submatrix of each layer of the second matrix includes at least one non-zero second submatrix; the mapping relationship between at least one second submatrix in the multi-layer second matrix and the multiple processing cores in the many-core system is the mapping relationship between each non-zero second submatrix in each layer of the second matrix and the multiple processing cores; the processing core corresponding to the N-th layer second submatrix is ​​the N-th layer processing core; the 1st layer processing core stores a calculation result obtained by calculating the transpose of its corresponding 1st layer non-zero second submatrix; the N+1th layer processing core stores a second correspondence between the N-th layer processing core and the second coordinate determined based on the first correspondence between the N-th layer processing core and the first coordinate; the first coordinate is the coordinate of the element in the N+1th layer second matrix corresponding to the N-th layer non-zero second submatrix in the N+1th layer second matrix; the second coordinate is the coordinate of the element in the N+1th layer second matrix corresponding to the N-th layer non-zero second submatrix in the transposed matrix of the N+1th layer second matrix; the target processing core is one of the at least one 1st layer processing core; and the step of determining the target processing core based on the mapping relationship between at least one second submatrix in the multi-layer second matrix and the multiple processing cores in the many-core system includes:

[0027] When N is greater than 1, determining the N-1th layer processing core corresponding to the target data according to the second corresponding relationship stored in the Nth layer processing core corresponding to the target data;

[0028] When N is equal to 1, the first-layer processing core storing the target data is used as the target processing core.

[0029] In a second aspect, an embodiment of the present disclosure provides a task processing method, including:

[0030] receiving a computing instruction and a first correspondence between an Nth layer processing core and a first coordinate in a multi-layer second matrix;

[0031] Determine a second correspondence between the Nth layer processing core and the second coordinate according to the operation instruction and the first correspondence;

[0032] In which, each layer of the second matrix in the multi-layer second matrix is ​​divided into at least one second sub-matrix; the elements in the N+1-th layer second matrix correspond one-to-one to multiple N-th layer second sub-matrices; each of the multiple processing cores in the many-core system corresponds to a second sub-matrix; the first coordinates are the coordinates of the elements in the N+1-th layer second matrix corresponding to the N-th layer second sub-matrix in the N+1-th layer second matrix; the second coordinates are the coordinates of the elements in the N+1-th layer second matrix corresponding to the N-th layer second sub-matrix in the transposed matrix of the N+1-th layer second matrix; N is a positive integer.

[0033] In a third aspect, an embodiment of the present disclosure provides a processing core, including:

[0034] Includes computing units and cache;

[0035] The computing unit can implement the task mapping method described in the first aspect of the embodiment of the present disclosure; and / or the task processing method described in the second aspect of the embodiment of the present disclosure.

[0036] In a fourth aspect, an embodiment of the present disclosure provides an electronic device, including:

[0037] multiple processing cores; and

[0038] an on-chip network configured to exchange data between the plurality of processing cores and external data;

[0039] One or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can perform the task mapping method described in the first aspect; and / or

[0040] The task processing method described in the second aspect of the embodiment of the present disclosure.

[0041] In the disclosed embodiment, a control core in a many-core system determines multiple layers of second matrices and operation instructions based on a first matrix that performs a transposition operation as needed, and the size of the second submatrix of each layer of the second matrix is ​​much smaller than the size of the first matrix; the second submatrices and operation instructions of each layer of the second matrix are mapped to multiple processing cores in the many-core system to perform the transposition operation, and finally the transposition operation result of the first matrix is ​​obtained, thereby achieving a high compression rate for the coordinate dimension of the elements in the matrix and greatly reducing memory overhead; the calculation results of the transposition operation are stored in each processing core of the many-core system, without having to be written to off-chip storage such as memory, and also avoiding repeated data movement, thereby improving the efficiency of ultra-large-scale sparse matrix transposition operations.

[0042] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings. In the accompanying drawings:

[0044] Figure 1 is a flowchart of a task mapping method according to an embodiment of the present disclosure;

[0045] Figure 2 is a schematic diagram of mapping a multi-layer second matrix to a processing core in an embodiment of the present disclosure;

[0046] Figure 3 is a flowchart of some steps in another task mapping method in an embodiment of the present disclosure;

[0047] Figure 4 is a flowchart of some steps in another task mapping method in an embodiment of the present disclosure;

[0048] Figure 5 This is a flowchart of some steps in another task mapping method according to an embodiment of the present disclosure;

[0049] Figure 6 This is a flowchart of some steps in another task mapping method according to an embodiment of the present disclosure;

[0050] Figure 7 This is a flowchart of some steps in another task mapping method according to an embodiment of the present disclosure;

[0051] Figure 8 is a flowchart of a task processing method in an embodiment of the present disclosure;

[0052] Figure 9 This is a block diagram of a processing core provided by an embodiment of the present disclosure;

[0053] Figure 10 This is a block diagram of the composition of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0054] To enable those skilled in the art to better understand the technical solutions of the present disclosure, exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0055] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0056] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0057] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0058] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined as such herein.

[0059] The inventors of the present disclosure have found that in some related technologies, the larger the scale of the sparse matrix, the more bits are required to store the coordinates of each element in the sparse matrix. For example, storing the coordinates of elements in a 10 billion-dimensional matrix requires 35 bits (bit) for each row and column. For ultra-large-scale sparse matrices, not only does it take up a large amount of storage space to store the coordinates of the elements, but the speed of performing operations involving sparse matrices is also slow. In addition, in some related technologies, after performing the transposition operation of the sparse matrix, it is necessary to transfer the result of the transposition operation to the memory (such as double data rate synchronous dynamic random access memory (DDR, Double Data Rate)), and splice out the transposed matrix of the complete sparse matrix in the memory; when performing subsequent operations, it is necessary to read the transposed matrix of the sparse matrix from the memory. The above-mentioned process of repeatedly moving data further reduces the efficiency of operations involving sparse matrices.

[0060] In view of this, firstly, referring to Figure 1 , the present disclosure provides a task mapping method, comprising:

[0061] In step S110, multiple layers of second matrices are determined based on the first matrix, and each layer of the second matrix is ​​divided into at least one second sub-matrix; wherein the elements in the second matrix of the N+1th layer correspond one-to-one to the multiple second sub-matrices of the Nth layer, and the second sub-matrix of the first layer is a sub-matrix of the first matrix;

[0062] In step S120, the operation instructions corresponding to each second sub-matrix are determined;

[0063] In step S130, at least one second sub-matrix in each layer of the second matrix and the operation instructions corresponding to the second sub-matrix are mapped to multiple processing cores in the many-core system, each of the processing cores corresponds to a second sub-matrix and a corresponding operation instruction, so that the processing core calculates the transpose of the corresponding second sub-matrix according to the corresponding operation instruction and stores the calculation result; wherein N is a positive integer.

[0064] The present embodiment provides a solution for performing sparse matrix transpose operations using a many-core system. In the present embodiment, the many-core system can be composed of a single chip with multiple processing cores. A processing core is the smallest computing unit in the many-core system that can be independently scheduled and has complete computing power. The many-core system can also be composed of multiple chips, each of which can have multiple processing cores. This embodiment is not particularly limited to this.

[0065] It should be noted that, in the disclosed embodiments, the multiple processing cores in the many-core system can independently execute program instructions or work together to leverage parallel computing capabilities to accelerate program execution and provide multitasking capabilities. It should also be noted that, in the disclosed embodiments, each processing core in the many-core system has an independent cache capable of storing data such as computational results obtained by the processing core.

[0066] In the embodiment of the present disclosure, steps S110 to S130 are executed by the control core of the many-core system. The control core may be any processing core in the many-core system. For example, the control core may be any processing core other than the multiple processing cores in step S130, or may be one of the multiple processing cores in step S130. Specifically, if there are M layers of second matrices in total, and the first-layer second matrix is ​​the first matrix, the M-layer processing core corresponding to the M-layer second matrix is ​​the control core. This embodiment of the present disclosure does not impose any special limitation on this.

[0067] In the disclosed embodiment, steps S110 to S130 are intended to calculate the transpose of a first matrix, where the first matrix is ​​a sparse matrix. In the multi-layer second matrix determined by step S110, the first-layer second matrix is ​​the first matrix. The multiple first-layer second sub-matrices obtained by dividing the first-layer second matrix are sub-matrices of the first matrix obtained by dividing the first matrix according to the same rule.

[0068] As an optional implementation, each layer of the second matrix is ​​a real number matrix, wherein all elements in the second matrix are real numbers. For example, if the second sub-matrix of the Nth layer corresponding to the element in the second matrix of the N+1th layer is a non-zero matrix, then the element is 1; if the second sub-matrix of the Nth layer corresponding to the element in the second matrix of the N+1th layer is a zero matrix, then the element is 0. Other numerical values ​​can also be used as elements in the second matrix, and this embodiment of the present disclosure does not impose any special limitation on this.

[0069] like Figure 2 As shown, the first matrix is ​​divided into 16 4*4 sub-matrices, corresponding to the first-level second matrix; the second-level second matrix includes 16 elements, corresponding one-to-one to the 16 sub-matrices of the first matrix. It should be noted that the sub-matrices obtained by dividing the first matrix can be non-zero matrices or zero matrices. When the first matrix, which is a sparse matrix, is relatively sparse, the number of zero matrices obtained by dividing the first matrix can be greater than the number of non-zero matrices. The second sub-matrix obtained by dividing the second matrix at each level can be either a non-zero matrix or a zero matrix.

[0070] It should be noted that, in step S110, when there are a total of M layers of second matrices and the first layer of second matrix is ​​the first matrix, the first layer of second matrix, the second layer of second matrix, ..., the M-1th layer of second matrix are divided into multiple second sub-matrices; the Mth layer of second matrix is ​​divided into one second sub-matrix, that is, the Mth layer of second sub-matrix is ​​the Mth layer of second matrix itself.

[0071] In the disclosed embodiment, the control core determines the operation instructions corresponding to each second sub-matrix by executing step S120. The operation instructions include the operators and parameters required for the processing core to calculate the transpose of the second sub-matrix. For example, the operation instructions instruct the processing core on how large a transpose operation to calculate. In the disclosed embodiment, the control core dynamically determines the processing core that performs the transpose operation based on the first matrix and determines the operation instructions for each processing core. The size of the first matrix can be arbitrary.

[0072] In the disclosed embodiment, the control core executes step S130 to map the multiple layers of second submatrices and the operation instructions to the multiple processing cores of the many-core system. The processing cores then calculate the transpose of the corresponding second submatrices and store the calculation results. Matrix operation rules indicate that in the disclosed embodiment, the multiple processing cores in the many-core system calculate the transpose of the second submatrix at each layer to obtain the transpose of the first matrix.

[0073] It should be noted that, in the disclosed embodiment, the size of the second sub-matrix of each layer is smaller than the size of the first matrix. In the multi-core system, the storage space required to store the second sub-matrix of each layer and the result of the transposition operation is much smaller than the storage space required to store the first matrix and the result of the transposition operation. Moreover, the amount of calculation required by each processing core when performing the transposition operation of the second sub-matrix is ​​also much smaller than the amount of calculation required when performing the transposition operation of the first matrix. For example, Figure 2 As shown, the 16*16 first matrix is ​​divided into 16 4*4 sub-matrices, corresponding to the first-layer second matrix; the second-layer second matrix is ​​also a 4*4 matrix. Storing the coordinates of the elements in the 16*16 first matrix requires 4 bits per row and column, while the processing core requires 2 bits per row and column to store the coordinates of the elements in a 4*4 sub-matrix. The layered matrix transposition scheme of the disclosed embodiment, in which multiple first processing cores calculate the transpose of the sub-matrix and a second processing core calculates the transpose of the block matrix, can achieve a high compression rate for the coordinate dimensions of the elements in the matrix and can significantly reduce memory overhead.

[0074] In the task mapping method provided by the embodiment of the present disclosure, the control core in the many-core system determines multiple layers of second matrices and operation instructions based on the first matrix that needs to perform a transposition operation, and the scale of the second submatrix of each layer of the second matrix is ​​much smaller than the scale of the first matrix; the second submatrices and operation instructions of each layer of the second matrix are mapped to multiple processing cores in the many-core system to perform the transposition operation, and finally the transposition operation result of the first matrix is ​​obtained, thereby achieving a high compression rate for the coordinate dimension of the elements in the matrix and greatly reducing memory overhead; the calculation results of the transposition operation are stored in each processing core of the many-core system, without having to be written to off-chip storage such as memory, and also avoiding repeated data movement, thereby improving the efficiency of ultra-large-scale sparse matrix transposition operations.

[0075] In an embodiment of the present disclosure, when mapping at least one second submatrix and operation instructions in each layer of the second matrix to multiple processing cores in the many-core system through step S130, all second submatrices in each layer of the second matrix can be mapped to multiple processing cores in the many-core system; or non-zero second submatrices in each layer of the second matrix can be mapped to multiple processing cores in the many-core system. It should be noted that when the first matrix is ​​a sparse matrix, the submatrices of the first matrix include multiple zero matrices; when determining a multi-layer second matrix, if the second submatrix of the Nth layer corresponding to an element in the second matrix of the N+1th layer is a non-zero matrix, then the element is 1; if the second submatrix of the Nth layer corresponding to an element in the second matrix of the N+1th layer is a zero matrix, then the element is 0. Therefore, the second submatrix of each layer of the second matrix may include a zero matrix. In step S130, mapping the non-zero second submatrix in each layer of the second matrix to multiple processing cores in the many-core system can further reduce the occupation of storage resources and computing resources. Figure 2 An optional implementation of mapping the non-zero second sub-matrix in each layer of the second matrix to multiple processing cores in a many-core system is shown.

[0076] Accordingly, in some embodiments, reference Figure 3 , at least one second sub-matrix of each layer of the second matrix includes at least one non-zero second sub-matrix; step S130 includes:

[0077] In step S131, each non-zero second sub-matrix in each layer of the second matrix is ​​transmitted to the plurality of processing cores respectively;

[0078] In step S132 , the operation instructions corresponding to each non-zero second sub-matrix are allocated to the plurality of processing cores.

[0079] In the embodiment of the present disclosure, the processing core corresponding to the second submatrix of the Nth layer is the Nth layer processing core. The second submatrix of the first layer is a submatrix of the first matrix. The first layer processing core calculates the submatrix of the first matrix and stores the transposed matrix of the submatrix of the first matrix; the N+1 layer processing core determines the coordinates in the transposed matrix of the second matrix of the N+1 layer corresponding to the Nth layer processing core after transposition based on the coordinates in the second matrix of the N+1 layer corresponding to the Nth layer processing core before transposition. When subsequent operations require the transposed operation result of the first matrix, the first layer processing core that stores the transposed matrix of the second submatrix of the first layer, that is, the transposed matrix of the submatrix of the first matrix, can be determined layer by layer based on the correspondence between the processing cores and the coordinates stored in each layer of processing cores.

[0080] Accordingly, in some embodiments, the processing core corresponding to the second sub-matrix of the Nth layer is the Nth layer processing core; Figure 4 , step S131 includes:

[0081] In step S131a, the first-layer non-zero second submatrix in the first-layer second matrix is ​​transmitted to the first-layer processing core, so that the first-layer processing core calculates the transpose of its corresponding first-layer non-zero second submatrix;

[0082] In step S131b, the first correspondence between the N-th layer processing core and the first coordinate is transmitted to the N+1-th layer processing core, so that the N+1-th layer processing core determines the second correspondence between the N-th layer processing core and the second coordinate based on the first correspondence; the first coordinate is the coordinate of the element in the N+1-th layer second matrix corresponding to the N-th layer non-zero second submatrix in the N+1-th layer second matrix; the second coordinate is the coordinate of the element in the N+1-th layer second matrix corresponding to the N-th layer non-zero second submatrix in the transposed matrix of the N+1-th layer second matrix.

[0083] In the disclosed embodiment, the control core may further control the multiple processing cores to output the results of the transpose operations in the multiple processing cores to an off-chip storage device such as a memory. In subsequent calculations, the transposed result of the first matrix may be obtained from the off-chip storage device. It should be noted that when the results of the transpose operations in the multiple processing cores are output to an off-chip storage device such as a memory device, they are directly stored as the transposed matrix of the first matrix.

[0084] It should also be noted that when the non-zero second submatrices in each layer of the second matrix are mapped to multiple processing cores in a many-core system, it is necessary to supplement the zero matrices in the submatrices of each first matrix when outputting the results of the transpose operations in the multiple processing cores to off-chip storage such as memory. The control core determines the address of the off-chip storage for the results of the transpose operations stored in each processing core, thereby ensuring that after each processing core writes the stored results of the transposed elements to the off-chip storage, they can be spliced ​​into the transposed matrix of the first matrix.

[0085] Accordingly, in some embodiments, reference Figure 5 , the task mapping method further includes:

[0086] In step S141, based on the second correspondence stored in each layer of processing cores, the address of the storage space of each target calculation result in the off-chip storage is determined; the target calculation result is the calculation result of the first layer processing core calculating the transpose of its corresponding first layer non-zero second submatrix and storing it;

[0087] In step S142, each first-layer processing core is controlled to write the target calculation result stored by the first-layer processing core into the off-chip storage according to the address of the storage space of the target calculation result stored by the first-layer processing core in the off-chip storage, wherein each of the target calculation results is spliced ​​into a transposed matrix of the first matrix in the off-chip storage.

[0088] In the embodiment of the present disclosure, the sizes of the second sub-matrices of each layer may be the same or different, and the embodiment of the present disclosure does not impose any special limitation on this.

[0089] Accordingly, in some embodiments, reference Figure 5 , step S110 includes:

[0090] In step S111, a target size is determined according to the size of the first matrix, where the target size is the size of the second sub-matrix of each layer;

[0091] In step S112, a multi-layer second matrix is ​​determined according to the first matrix and the target size.

[0092] In the embodiment of the present disclosure, there is no special limitation on the size of the second sub-matrix, and the size of the second sub-matrix can be determined based on the computing power, storage size, and computational efficiency requirements of the many-core system.

[0093] The embodiment of the present disclosure does not impose any special limitation on the second sub-matrix. In some embodiments, each layer of the second sub-matrix is ​​a square matrix.

[0094] In the disclosed embodiment, the calculation result of the transpose operation is stored in each processing core of the many-core system. When a subsequent operation involving the result of the transpose operation needs to be performed, the data of the subsequent operation is transmitted to the corresponding processing core, and the subsequent operation is performed by the processing core. There is no need to first transmit the transpose matrix of the sub-matrix of the first matrix calculated by each processing core to an off-chip storage such as a memory, and then read the transpose result of the first matrix from the off-chip storage, thereby avoiding repeated data transportation and improving the efficiency of ultra-large-scale sparse matrix transpose operations.

[0095] Accordingly, in some embodiments, reference Figure 6After step S130, the task mapping method further includes:

[0096] In step S161, a target processing core is determined based on a mapping relationship between at least one second submatrix in the multi-layer second matrix and multiple processing cores in the many-core system; the target processing core is at least one of the multiple processing cores storing target data; the target data is a transposed matrix of a submatrix of the first matrix corresponding to task data of a task to be processed;

[0097] In step S162 , the task data is transmitted to the target processing core, so that the target processing core reads the target data and performs operations corresponding to the task data.

[0098] In some embodiments, at least one second submatrix of each layer of the second matrix includes at least one non-zero second submatrix; the mapping relationship between at least one second submatrix in the multi-layer second matrix and the multiple processing cores in the many-core system is the mapping relationship between each non-zero second submatrix in each layer of the second matrix and the multiple processing cores; the processing core corresponding to the N-th layer second submatrix is ​​the N-th layer processing core; the 1st layer processing core stores the calculation result obtained by calculating the transpose of its corresponding 1st layer non-zero second submatrix; the N+1th layer processing core stores the second correspondence between the N-th layer processing core and the second coordinate determined according to the first correspondence between the N-th layer processing core and the first coordinate; the first coordinate is the coordinate of the element in the N+1th layer second matrix corresponding to the N-th layer non-zero second submatrix in the N+1th layer second matrix; the second coordinate is the coordinate of the element in the N+1th layer second matrix corresponding to the N-th layer non-zero second submatrix in the transposed matrix of the N+1th layer second matrix; the target processing core is one of the at least one 1st layer processing core; refer to Figure 7 , step S161 includes:

[0099] In step S161a, when N is greater than 1, determining the N-1th layer processing core corresponding to the target data according to the second corresponding relationship stored in the Nth layer processing core corresponding to the target data;

[0100] In step S161b, when N is equal to 1, the first-layer processing core storing the target data is used as the target processing core.

[0101] It should be noted that, when there are a total of M layers of second matrices and the first layer of second matrices is the first matrix, starting from the Mth layer of processing cores, when N is greater than 1, the processing cores corresponding to the target data in each layer are determined layer by layer by iterative execution of step 161a until N is equal to 1, and the first layer of processing cores storing the target data is used as the target processing core. That is, when N is greater than 1, step S161a is executed once, and N is decremented by 1; if N is still greater than 1 after the decrement, step S161a is continued; if N is equal to 1 after the decrement, step S161b is executed.

[0102] Secondly, refer to Figure 8 , an embodiment of the present disclosure provides a task processing method, including:

[0103] In step S210, an operation instruction and a first correspondence between an N-th layer processing core and a first coordinate in a multi-layer second matrix are received;

[0104] In step S220, a second correspondence between the Nth layer processing core and the second coordinate is determined according to the operation instruction and the first correspondence;

[0105] In which, each layer of the second matrix in the multi-layer second matrix is ​​divided into at least one second sub-matrix; the elements in the N+1-th layer second matrix correspond one-to-one to multiple N-th layer second sub-matrices; each of the multiple processing cores in the many-core system corresponds to a second sub-matrix; the first coordinates are the coordinates of the elements in the N+1-th layer second matrix corresponding to the N-th layer second sub-matrix in the N+1-th layer second matrix; the second coordinates are the coordinates of the elements in the N+1-th layer second matrix corresponding to the N-th layer second sub-matrix in the transposed matrix of the N+1-th layer second matrix; N is a positive integer.

[0106] In the task processing method provided by the embodiment of the present disclosure, the processing core of the many-core system can determine the coordinates in the transposed matrix of the second matrix of the N+1th layer corresponding to the processing core of the Nth layer after transposition based on the operation instruction and the coordinates in the second matrix of the N+1th layer corresponding to the processing core of the Nth layer before transposition, so that the many-core system can determine multiple layers of second matrices according to the first matrix on which the transposition operation is performed as needed, and map the second sub-matrices of the second matrices of each layer to multiple processing cores in the many-core system to perform the transposition operation, and finally obtain the transposition operation result of the first matrix, thereby achieving a higher compression rate for the coordinate dimension of the elements in the matrix and greatly reducing the memory overhead; the calculation result of the transposition operation is stored in the processing core of the many-core system, without having to be written to off-chip storage such as memory, and also avoids repeated data movement, thereby improving the efficiency of ultra-large-scale sparse matrix transposition operations.

[0107] Thirdly, refer to Figure 9 , an embodiment of the present disclosure provides a processing core, including:

[0108] It includes a computing unit 101 and a cache 102;

[0109] The computing unit 101 can implement the task mapping method described in the first aspect of the embodiment of the present disclosure; and / or

[0110] The task processing method described in the second aspect of the embodiment of the present disclosure.

[0111] Fourthly, refer to Figure 10 , an embodiment of the present disclosure provides an electronic device, including:

[0112] multiple processing cores 201; and

[0113] An on-chip network 202 configured to exchange data between the plurality of processing cores 201 and external data;

[0114] One or more instructions are stored in one or more of the processing cores 201, and one or more of the instructions are executed by one or more of the processing cores 201, so that one or more of the processing cores 201 can perform the task mapping method described in the first aspect; and / or

[0115] The task processing method described in the second aspect of the embodiment of the present disclosure.

[0116] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0117] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A task mapping method, comprising: Determining multiple layers of second matrices based on the first matrix, wherein, when there are a total of M layers of second matrices and the first layer of second matrix is ​​the first matrix, the first to M-1th layer of second matrices are divided into multiple second sub-matrices, the Mth layer of second matrix is ​​divided into one second sub-matrix, and the Mth layer of second sub-matrix is ​​the Mth layer of second matrix; elements in the N+1th layer of second matrix have a one-to-one correspondence with the multiple Nth layer of second sub-matrices, and the first layer of second sub-matrix is ​​a sub-matrix of the first matrix; Determine the operation instructions corresponding to each second sub-matrix; Mapping at least one second sub-matrix in each layer of the second matrix and a corresponding operation instruction of the second sub-matrix to multiple processing cores in the many-core system, each of the processing cores corresponding to one second sub-matrix and a corresponding operation instruction, so that the processing core calculates the transpose of the corresponding second sub-matrix according to the corresponding operation instruction and stores the calculation result; Wherein, M and N are positive integers.

2. The task mapping method according to claim 1, wherein: At least one second sub-matrix of each layer of the second matrix includes at least one non-zero second sub-matrix; The step of mapping at least one second sub-matrix in each layer of the second matrix and the operation instruction to multiple processing cores in the many-core system includes: transmitting each non-zero second sub-matrix in each layer of the second matrix to the plurality of processing cores respectively; The operation instructions corresponding to each non-zero second sub-matrix are configured into the plurality of processing cores.

3. The task mapping method according to claim 2, wherein: The processing core corresponding to the second sub-matrix of the Nth layer is the Nth layer processing core; The step of transmitting each non-zero second sub-matrix in each layer of the second matrix to the plurality of processing cores comprises: Transmitting the first-layer non-zero second submatrix in the first-layer second matrix to the first-layer processing core, so that the first-layer processing core calculates the transpose of its corresponding first-layer non-zero second submatrix; The first correspondence between the N-th layer processing core and the first coordinate is transmitted to the N+1-th layer processing core, so that the N+1-th layer processing core determines the second correspondence between the N-th layer processing core and the second coordinate based on the first correspondence; the first coordinate is the coordinate of the element in the N+1-th layer second matrix corresponding to the N-th layer non-zero second submatrix in the N+1-th layer second matrix; the second coordinate is the coordinate of the element in the N+1-th layer second matrix corresponding to the N-th layer non-zero second submatrix in the transposed matrix of the N+1-th layer second matrix.

4. The task mapping method according to claim 3, wherein: The task mapping method further includes: Determining the address of the storage space of each target calculation result in the off-chip storage according to the second corresponding relationship stored in each layer of processing cores; the target calculation result is the calculation result of calculating the transpose of the corresponding first-layer non-zero second submatrix calculated by the first-layer processing core and stored; Control each first-layer processing core to write the target calculation result stored by the first-layer processing core into the off-chip storage according to the address of the storage space of the target calculation result stored by the first-layer processing core in the off-chip storage, wherein each of the target calculation results is spliced ​​into a transposed matrix of the first matrix in the off-chip storage.

5. The task mapping method according to any one of claims 1 to 4, wherein: The step of determining a multi-layer second matrix according to the first matrix comprises: Determine a target size according to the size of the first matrix, where the target size is the size of the second sub-matrix of each layer; A multi-layer second matrix is ​​determined according to the first matrix and the target size.

6. The task mapping method according to any one of claims 1 to 4, wherein: The second sub-matrix of each layer is a square matrix.

7. The task mapping method according to any one of claims 1 to 3, wherein: After the step of mapping at least one second sub-matrix in each layer of the second matrix and the operation instruction to multiple processing cores in the many-core system, the task mapping method further includes: Determining a target processing core based on a mapping relationship between at least one second submatrix in the multi-layer second matrix and multiple processing cores in the many-core system; the target processing core is at least one of the multiple processing cores storing target data; the target data is a transposed matrix of a submatrix of the first matrix corresponding to task data of a task to be processed; The task data is transmitted to the target processing core, so that the target processing core reads the target data and performs operations corresponding to the task data.

8. The task mapping method according to claim 7, wherein: At least one second submatrix of each layer of the second matrix includes at least one non-zero second submatrix; the mapping relationship between the at least one second submatrix in the multi-layer second matrix and the multiple processing cores in the many-core system is the mapping relationship between each non-zero second submatrix in each layer of the second matrix and the multiple processing cores; The processing core corresponding to the second submatrix of the Nth layer is the Nth layer processing core; the 1st layer processing core stores the calculation result obtained by calculating the transpose of the corresponding 1st layer non-zero second submatrix; the N+1th layer processing core stores the second correspondence between the Nth layer processing core and the second coordinate determined based on the first correspondence between the Nth layer processing core and the first coordinate; The first coordinates are coordinates of elements in the second matrix of the N+1th layer corresponding to the non-zero second submatrix of the Nth layer in the second matrix of the N+1th layer; the second coordinates are coordinates of elements in the second matrix of the N+1th layer corresponding to the non-zero second submatrix of the Nth layer in the transposed matrix of the second matrix of the N+1th layer; the target processing core is one of the at least one processing core of the first layer; The step of determining a target processing core according to a mapping relationship between at least one second sub-matrix in the multi-layer second matrix and a plurality of processing cores in the many-core system includes: When N is greater than 1, determining the N-1th layer processing core corresponding to the target data according to the second corresponding relationship stored in the Nth layer processing core corresponding to the target data; When N is equal to 1, the first-layer processing core storing the target data is used as the target processing core.

9. A task processing method, comprising: receiving a computing instruction and a first correspondence between an Nth layer processing core and a first coordinate in a multi-layer second matrix; Determine a second correspondence between the Nth layer processing core and the second coordinate according to the operation instruction and the first correspondence; The multi-layer second matrix is ​​determined based on the first matrix. When there are a total of M layers of second matrices and the first-layer second matrix is ​​the first matrix, the first to M-1-th layer second matrices are divided into multiple second sub-matrices, the M-th layer second matrix is ​​divided into one second sub-matrix, and the M-th layer second sub-matrix is ​​the M-th layer second matrix. The elements in the second matrix of the N+1th layer correspond one-to-one to the multiple second sub-matrices of the Nth layer; each of the multiple processing cores in the many-core system corresponds to a second sub-matrix, and the Nth layer processing core represents the processing core corresponding to the Nth layer second sub-matrix; The first coordinates are the coordinates of the elements in the second matrix of the N+1th layer corresponding to the second submatrix of the Nth layer in the second matrix of the N+1th layer; the second coordinates are the coordinates of the elements in the second matrix of the N+1th layer corresponding to the second submatrix of the Nth layer in the transposed matrix of the second matrix of the N+1th layer; M and N are positive integers.

10. A processing core comprising: Includes computing units and cache; The computing unit is capable of implementing the task mapping method according to any one of claims 1 to 8; and / or The task processing method according to claim 9.

11. An electronic device comprising: Multiple processing cores; as well as an on-chip network configured to exchange data between the plurality of processing cores and external data; One or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can perform the task mapping method according to any one of claims 1 to 8; and / or The task processing method according to claim 9.

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